1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7280.h> 13#include <dt-bindings/interconnect/qcom,sc7280.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/reset/qcom,sdm845-aoss.h> 18#include <dt-bindings/reset/qcom,sdm845-pdc.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/thermal/thermal.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 chosen { }; 29 30 aliases { 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 i2c5 = &i2c5; 37 i2c6 = &i2c6; 38 i2c7 = &i2c7; 39 i2c8 = &i2c8; 40 i2c9 = &i2c9; 41 i2c10 = &i2c10; 42 i2c11 = &i2c11; 43 i2c12 = &i2c12; 44 i2c13 = &i2c13; 45 i2c14 = &i2c14; 46 i2c15 = &i2c15; 47 mmc1 = &sdhc_1; 48 mmc2 = &sdhc_2; 49 spi0 = &spi0; 50 spi1 = &spi1; 51 spi2 = &spi2; 52 spi3 = &spi3; 53 spi4 = &spi4; 54 spi5 = &spi5; 55 spi6 = &spi6; 56 spi7 = &spi7; 57 spi8 = &spi8; 58 spi9 = &spi9; 59 spi10 = &spi10; 60 spi11 = &spi11; 61 spi12 = &spi12; 62 spi13 = &spi13; 63 spi14 = &spi14; 64 spi15 = &spi15; 65 }; 66 67 clocks { 68 xo_board: xo-board { 69 compatible = "fixed-clock"; 70 clock-frequency = <76800000>; 71 #clock-cells = <0>; 72 }; 73 74 sleep_clk: sleep-clk { 75 compatible = "fixed-clock"; 76 clock-frequency = <32000>; 77 #clock-cells = <0>; 78 }; 79 }; 80 81 reserved-memory { 82 #address-cells = <2>; 83 #size-cells = <2>; 84 ranges; 85 86 aop_mem: memory@80800000 { 87 reg = <0x0 0x80800000 0x0 0x60000>; 88 no-map; 89 }; 90 91 aop_cmd_db_mem: memory@80860000 { 92 reg = <0x0 0x80860000 0x0 0x20000>; 93 compatible = "qcom,cmd-db"; 94 no-map; 95 }; 96 97 smem_mem: memory@80900000 { 98 reg = <0x0 0x80900000 0x0 0x200000>; 99 no-map; 100 }; 101 102 cpucp_mem: memory@80b00000 { 103 no-map; 104 reg = <0x0 0x80b00000 0x0 0x100000>; 105 }; 106 107 ipa_fw_mem: memory@8b700000 { 108 reg = <0 0x8b700000 0 0x10000>; 109 no-map; 110 }; 111 }; 112 113 cpus { 114 #address-cells = <2>; 115 #size-cells = <0>; 116 117 CPU0: cpu@0 { 118 device_type = "cpu"; 119 compatible = "arm,kryo"; 120 reg = <0x0 0x0>; 121 enable-method = "psci"; 122 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 123 &LITTLE_CPU_SLEEP_1 124 &CLUSTER_SLEEP_0>; 125 next-level-cache = <&L2_0>; 126 qcom,freq-domain = <&cpufreq_hw 0>; 127 #cooling-cells = <2>; 128 L2_0: l2-cache { 129 compatible = "cache"; 130 next-level-cache = <&L3_0>; 131 L3_0: l3-cache { 132 compatible = "cache"; 133 }; 134 }; 135 }; 136 137 CPU1: cpu@100 { 138 device_type = "cpu"; 139 compatible = "arm,kryo"; 140 reg = <0x0 0x100>; 141 enable-method = "psci"; 142 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 143 &LITTLE_CPU_SLEEP_1 144 &CLUSTER_SLEEP_0>; 145 next-level-cache = <&L2_100>; 146 qcom,freq-domain = <&cpufreq_hw 0>; 147 #cooling-cells = <2>; 148 L2_100: l2-cache { 149 compatible = "cache"; 150 next-level-cache = <&L3_0>; 151 }; 152 }; 153 154 CPU2: cpu@200 { 155 device_type = "cpu"; 156 compatible = "arm,kryo"; 157 reg = <0x0 0x200>; 158 enable-method = "psci"; 159 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 160 &LITTLE_CPU_SLEEP_1 161 &CLUSTER_SLEEP_0>; 162 next-level-cache = <&L2_200>; 163 qcom,freq-domain = <&cpufreq_hw 0>; 164 #cooling-cells = <2>; 165 L2_200: l2-cache { 166 compatible = "cache"; 167 next-level-cache = <&L3_0>; 168 }; 169 }; 170 171 CPU3: cpu@300 { 172 device_type = "cpu"; 173 compatible = "arm,kryo"; 174 reg = <0x0 0x300>; 175 enable-method = "psci"; 176 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 177 &LITTLE_CPU_SLEEP_1 178 &CLUSTER_SLEEP_0>; 179 next-level-cache = <&L2_300>; 180 qcom,freq-domain = <&cpufreq_hw 0>; 181 #cooling-cells = <2>; 182 L2_300: l2-cache { 183 compatible = "cache"; 184 next-level-cache = <&L3_0>; 185 }; 186 }; 187 188 CPU4: cpu@400 { 189 device_type = "cpu"; 190 compatible = "arm,kryo"; 191 reg = <0x0 0x400>; 192 enable-method = "psci"; 193 cpu-idle-states = <&BIG_CPU_SLEEP_0 194 &BIG_CPU_SLEEP_1 195 &CLUSTER_SLEEP_0>; 196 next-level-cache = <&L2_400>; 197 qcom,freq-domain = <&cpufreq_hw 1>; 198 #cooling-cells = <2>; 199 L2_400: l2-cache { 200 compatible = "cache"; 201 next-level-cache = <&L3_0>; 202 }; 203 }; 204 205 CPU5: cpu@500 { 206 device_type = "cpu"; 207 compatible = "arm,kryo"; 208 reg = <0x0 0x500>; 209 enable-method = "psci"; 210 cpu-idle-states = <&BIG_CPU_SLEEP_0 211 &BIG_CPU_SLEEP_1 212 &CLUSTER_SLEEP_0>; 213 next-level-cache = <&L2_500>; 214 qcom,freq-domain = <&cpufreq_hw 1>; 215 #cooling-cells = <2>; 216 L2_500: l2-cache { 217 compatible = "cache"; 218 next-level-cache = <&L3_0>; 219 }; 220 }; 221 222 CPU6: cpu@600 { 223 device_type = "cpu"; 224 compatible = "arm,kryo"; 225 reg = <0x0 0x600>; 226 enable-method = "psci"; 227 cpu-idle-states = <&BIG_CPU_SLEEP_0 228 &BIG_CPU_SLEEP_1 229 &CLUSTER_SLEEP_0>; 230 next-level-cache = <&L2_600>; 231 qcom,freq-domain = <&cpufreq_hw 1>; 232 #cooling-cells = <2>; 233 L2_600: l2-cache { 234 compatible = "cache"; 235 next-level-cache = <&L3_0>; 236 }; 237 }; 238 239 CPU7: cpu@700 { 240 device_type = "cpu"; 241 compatible = "arm,kryo"; 242 reg = <0x0 0x700>; 243 enable-method = "psci"; 244 cpu-idle-states = <&BIG_CPU_SLEEP_0 245 &BIG_CPU_SLEEP_1 246 &CLUSTER_SLEEP_0>; 247 next-level-cache = <&L2_700>; 248 qcom,freq-domain = <&cpufreq_hw 2>; 249 #cooling-cells = <2>; 250 L2_700: l2-cache { 251 compatible = "cache"; 252 next-level-cache = <&L3_0>; 253 }; 254 }; 255 256 cpu-map { 257 cluster0 { 258 core0 { 259 cpu = <&CPU0>; 260 }; 261 262 core1 { 263 cpu = <&CPU1>; 264 }; 265 266 core2 { 267 cpu = <&CPU2>; 268 }; 269 270 core3 { 271 cpu = <&CPU3>; 272 }; 273 274 core4 { 275 cpu = <&CPU4>; 276 }; 277 278 core5 { 279 cpu = <&CPU5>; 280 }; 281 282 core6 { 283 cpu = <&CPU6>; 284 }; 285 286 core7 { 287 cpu = <&CPU7>; 288 }; 289 }; 290 }; 291 292 idle-states { 293 entry-method = "psci"; 294 295 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 296 compatible = "arm,idle-state"; 297 idle-state-name = "little-power-down"; 298 arm,psci-suspend-param = <0x40000003>; 299 entry-latency-us = <549>; 300 exit-latency-us = <901>; 301 min-residency-us = <1774>; 302 local-timer-stop; 303 }; 304 305 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 306 compatible = "arm,idle-state"; 307 idle-state-name = "little-rail-power-down"; 308 arm,psci-suspend-param = <0x40000004>; 309 entry-latency-us = <702>; 310 exit-latency-us = <915>; 311 min-residency-us = <4001>; 312 local-timer-stop; 313 }; 314 315 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 316 compatible = "arm,idle-state"; 317 idle-state-name = "big-power-down"; 318 arm,psci-suspend-param = <0x40000003>; 319 entry-latency-us = <523>; 320 exit-latency-us = <1244>; 321 min-residency-us = <2207>; 322 local-timer-stop; 323 }; 324 325 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 326 compatible = "arm,idle-state"; 327 idle-state-name = "big-rail-power-down"; 328 arm,psci-suspend-param = <0x40000004>; 329 entry-latency-us = <526>; 330 exit-latency-us = <1854>; 331 min-residency-us = <5555>; 332 local-timer-stop; 333 }; 334 335 CLUSTER_SLEEP_0: cluster-sleep-0 { 336 compatible = "arm,idle-state"; 337 idle-state-name = "cluster-power-down"; 338 arm,psci-suspend-param = <0x40003444>; 339 entry-latency-us = <3263>; 340 exit-latency-us = <6562>; 341 min-residency-us = <9926>; 342 local-timer-stop; 343 }; 344 }; 345 }; 346 347 memory@80000000 { 348 device_type = "memory"; 349 /* We expect the bootloader to fill in the size */ 350 reg = <0 0x80000000 0 0>; 351 }; 352 353 firmware { 354 scm { 355 compatible = "qcom,scm-sc7280", "qcom,scm"; 356 }; 357 }; 358 359 clk_virt: interconnect { 360 compatible = "qcom,sc7280-clk-virt"; 361 #interconnect-cells = <2>; 362 qcom,bcm-voters = <&apps_bcm_voter>; 363 }; 364 365 smem { 366 compatible = "qcom,smem"; 367 memory-region = <&smem_mem>; 368 hwlocks = <&tcsr_mutex 3>; 369 }; 370 371 smp2p-adsp { 372 compatible = "qcom,smp2p"; 373 qcom,smem = <443>, <429>; 374 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 375 IPCC_MPROC_SIGNAL_SMP2P 376 IRQ_TYPE_EDGE_RISING>; 377 mboxes = <&ipcc IPCC_CLIENT_LPASS 378 IPCC_MPROC_SIGNAL_SMP2P>; 379 380 qcom,local-pid = <0>; 381 qcom,remote-pid = <2>; 382 383 adsp_smp2p_out: master-kernel { 384 qcom,entry-name = "master-kernel"; 385 #qcom,smem-state-cells = <1>; 386 }; 387 388 adsp_smp2p_in: slave-kernel { 389 qcom,entry-name = "slave-kernel"; 390 interrupt-controller; 391 #interrupt-cells = <2>; 392 }; 393 }; 394 395 smp2p-cdsp { 396 compatible = "qcom,smp2p"; 397 qcom,smem = <94>, <432>; 398 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 399 IPCC_MPROC_SIGNAL_SMP2P 400 IRQ_TYPE_EDGE_RISING>; 401 mboxes = <&ipcc IPCC_CLIENT_CDSP 402 IPCC_MPROC_SIGNAL_SMP2P>; 403 404 qcom,local-pid = <0>; 405 qcom,remote-pid = <5>; 406 407 cdsp_smp2p_out: master-kernel { 408 qcom,entry-name = "master-kernel"; 409 #qcom,smem-state-cells = <1>; 410 }; 411 412 cdsp_smp2p_in: slave-kernel { 413 qcom,entry-name = "slave-kernel"; 414 interrupt-controller; 415 #interrupt-cells = <2>; 416 }; 417 }; 418 419 smp2p-mpss { 420 compatible = "qcom,smp2p"; 421 qcom,smem = <435>, <428>; 422 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 423 IPCC_MPROC_SIGNAL_SMP2P 424 IRQ_TYPE_EDGE_RISING>; 425 mboxes = <&ipcc IPCC_CLIENT_MPSS 426 IPCC_MPROC_SIGNAL_SMP2P>; 427 428 qcom,local-pid = <0>; 429 qcom,remote-pid = <1>; 430 431 modem_smp2p_out: master-kernel { 432 qcom,entry-name = "master-kernel"; 433 #qcom,smem-state-cells = <1>; 434 }; 435 436 modem_smp2p_in: slave-kernel { 437 qcom,entry-name = "slave-kernel"; 438 interrupt-controller; 439 #interrupt-cells = <2>; 440 }; 441 442 ipa_smp2p_out: ipa-ap-to-modem { 443 qcom,entry-name = "ipa"; 444 #qcom,smem-state-cells = <1>; 445 }; 446 447 ipa_smp2p_in: ipa-modem-to-ap { 448 qcom,entry-name = "ipa"; 449 interrupt-controller; 450 #interrupt-cells = <2>; 451 }; 452 }; 453 454 smp2p-wpss { 455 compatible = "qcom,smp2p"; 456 qcom,smem = <617>, <616>; 457 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 458 IPCC_MPROC_SIGNAL_SMP2P 459 IRQ_TYPE_EDGE_RISING>; 460 mboxes = <&ipcc IPCC_CLIENT_WPSS 461 IPCC_MPROC_SIGNAL_SMP2P>; 462 463 qcom,local-pid = <0>; 464 qcom,remote-pid = <13>; 465 466 wpss_smp2p_out: master-kernel { 467 qcom,entry-name = "master-kernel"; 468 #qcom,smem-state-cells = <1>; 469 }; 470 471 wpss_smp2p_in: slave-kernel { 472 qcom,entry-name = "slave-kernel"; 473 interrupt-controller; 474 #interrupt-cells = <2>; 475 }; 476 }; 477 478 pmu { 479 compatible = "arm,armv8-pmuv3"; 480 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 481 }; 482 483 psci { 484 compatible = "arm,psci-1.0"; 485 method = "smc"; 486 }; 487 488 qspi_opp_table: qspi-opp-table { 489 compatible = "operating-points-v2"; 490 491 opp-75000000 { 492 opp-hz = /bits/ 64 <75000000>; 493 required-opps = <&rpmhpd_opp_low_svs>; 494 }; 495 496 opp-150000000 { 497 opp-hz = /bits/ 64 <150000000>; 498 required-opps = <&rpmhpd_opp_svs>; 499 }; 500 501 opp-300000000 { 502 opp-hz = /bits/ 64 <300000000>; 503 required-opps = <&rpmhpd_opp_nom>; 504 }; 505 }; 506 507 qup_opp_table: qup-opp-table { 508 compatible = "operating-points-v2"; 509 510 opp-75000000 { 511 opp-hz = /bits/ 64 <75000000>; 512 required-opps = <&rpmhpd_opp_low_svs>; 513 }; 514 515 opp-100000000 { 516 opp-hz = /bits/ 64 <100000000>; 517 required-opps = <&rpmhpd_opp_svs>; 518 }; 519 520 opp-128000000 { 521 opp-hz = /bits/ 64 <128000000>; 522 required-opps = <&rpmhpd_opp_nom>; 523 }; 524 }; 525 526 soc: soc@0 { 527 #address-cells = <2>; 528 #size-cells = <2>; 529 ranges = <0 0 0 0 0x10 0>; 530 dma-ranges = <0 0 0 0 0x10 0>; 531 compatible = "simple-bus"; 532 533 gcc: clock-controller@100000 { 534 compatible = "qcom,gcc-sc7280"; 535 reg = <0 0x00100000 0 0x1f0000>; 536 clocks = <&rpmhcc RPMH_CXO_CLK>, 537 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 538 <0>, <0>, <0>, <0>, <0>, <0>; 539 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 540 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 541 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 542 "ufs_phy_tx_symbol_0_clk", 543 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 544 #clock-cells = <1>; 545 #reset-cells = <1>; 546 #power-domain-cells = <1>; 547 }; 548 549 ipcc: mailbox@408000 { 550 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 551 reg = <0 0x00408000 0 0x1000>; 552 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 553 interrupt-controller; 554 #interrupt-cells = <3>; 555 #mbox-cells = <2>; 556 }; 557 558 qfprom: efuse@784000 { 559 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 560 reg = <0 0x00784000 0 0xa20>, 561 <0 0x00780000 0 0xa20>, 562 <0 0x00782000 0 0x120>, 563 <0 0x00786000 0 0x1fff>; 564 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 565 clock-names = "core"; 566 power-domains = <&rpmhpd SC7280_MX>; 567 #address-cells = <1>; 568 #size-cells = <1>; 569 }; 570 571 sdhc_1: sdhci@7c4000 { 572 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 573 status = "disabled"; 574 575 reg = <0 0x007c4000 0 0x1000>, 576 <0 0x007c5000 0 0x1000>; 577 reg-names = "hc", "cqhci"; 578 579 iommus = <&apps_smmu 0xc0 0x0>; 580 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 582 interrupt-names = "hc_irq", "pwr_irq"; 583 584 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 585 <&gcc GCC_SDCC1_AHB_CLK>, 586 <&rpmhcc RPMH_CXO_CLK>; 587 clock-names = "core", "iface", "xo"; 588 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 589 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 590 interconnect-names = "sdhc-ddr","cpu-sdhc"; 591 power-domains = <&rpmhpd SC7280_CX>; 592 operating-points-v2 = <&sdhc1_opp_table>; 593 594 bus-width = <8>; 595 supports-cqe; 596 597 qcom,dll-config = <0x0007642c>; 598 qcom,ddr-config = <0x80040868>; 599 600 mmc-ddr-1_8v; 601 mmc-hs200-1_8v; 602 mmc-hs400-1_8v; 603 mmc-hs400-enhanced-strobe; 604 605 sdhc1_opp_table: opp-table { 606 compatible = "operating-points-v2"; 607 608 opp-100000000 { 609 opp-hz = /bits/ 64 <100000000>; 610 required-opps = <&rpmhpd_opp_low_svs>; 611 opp-peak-kBps = <1800000 400000>; 612 opp-avg-kBps = <100000 0>; 613 }; 614 615 opp-384000000 { 616 opp-hz = /bits/ 64 <384000000>; 617 required-opps = <&rpmhpd_opp_nom>; 618 opp-peak-kBps = <5400000 1600000>; 619 opp-avg-kBps = <390000 0>; 620 }; 621 }; 622 623 }; 624 625 qupv3_id_0: geniqup@9c0000 { 626 compatible = "qcom,geni-se-qup"; 627 reg = <0 0x009c0000 0 0x2000>; 628 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 629 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 630 clock-names = "m-ahb", "s-ahb"; 631 #address-cells = <2>; 632 #size-cells = <2>; 633 ranges; 634 iommus = <&apps_smmu 0x123 0x0>; 635 status = "disabled"; 636 637 i2c0: i2c@980000 { 638 compatible = "qcom,geni-i2c"; 639 reg = <0 0x00980000 0 0x4000>; 640 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 641 clock-names = "se"; 642 pinctrl-names = "default"; 643 pinctrl-0 = <&qup_i2c0_data_clk>; 644 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 648 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 649 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 650 interconnect-names = "qup-core", "qup-config", 651 "qup-memory"; 652 status = "disabled"; 653 }; 654 655 spi0: spi@980000 { 656 compatible = "qcom,geni-spi"; 657 reg = <0 0x00980000 0 0x4000>; 658 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 659 clock-names = "se"; 660 pinctrl-names = "default"; 661 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 662 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 663 #address-cells = <1>; 664 #size-cells = <0>; 665 power-domains = <&rpmhpd SC7280_CX>; 666 operating-points-v2 = <&qup_opp_table>; 667 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 668 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 669 interconnect-names = "qup-core", "qup-config"; 670 status = "disabled"; 671 }; 672 673 uart0: serial@980000 { 674 compatible = "qcom,geni-uart"; 675 reg = <0 0x00980000 0 0x4000>; 676 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 677 clock-names = "se"; 678 pinctrl-names = "default"; 679 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 680 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 681 power-domains = <&rpmhpd SC7280_CX>; 682 operating-points-v2 = <&qup_opp_table>; 683 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 684 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 685 interconnect-names = "qup-core", "qup-config"; 686 status = "disabled"; 687 }; 688 689 i2c1: i2c@984000 { 690 compatible = "qcom,geni-i2c"; 691 reg = <0 0x00984000 0 0x4000>; 692 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 693 clock-names = "se"; 694 pinctrl-names = "default"; 695 pinctrl-0 = <&qup_i2c1_data_clk>; 696 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 697 #address-cells = <1>; 698 #size-cells = <0>; 699 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 700 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 701 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 702 interconnect-names = "qup-core", "qup-config", 703 "qup-memory"; 704 status = "disabled"; 705 }; 706 707 spi1: spi@984000 { 708 compatible = "qcom,geni-spi"; 709 reg = <0 0x00984000 0 0x4000>; 710 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 711 clock-names = "se"; 712 pinctrl-names = "default"; 713 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 714 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 715 #address-cells = <1>; 716 #size-cells = <0>; 717 power-domains = <&rpmhpd SC7280_CX>; 718 operating-points-v2 = <&qup_opp_table>; 719 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 720 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 721 interconnect-names = "qup-core", "qup-config"; 722 status = "disabled"; 723 }; 724 725 uart1: serial@984000 { 726 compatible = "qcom,geni-uart"; 727 reg = <0 0x00984000 0 0x4000>; 728 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 729 clock-names = "se"; 730 pinctrl-names = "default"; 731 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 732 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 733 power-domains = <&rpmhpd SC7280_CX>; 734 operating-points-v2 = <&qup_opp_table>; 735 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 736 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 737 interconnect-names = "qup-core", "qup-config"; 738 status = "disabled"; 739 }; 740 741 i2c2: i2c@988000 { 742 compatible = "qcom,geni-i2c"; 743 reg = <0 0x00988000 0 0x4000>; 744 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 745 clock-names = "se"; 746 pinctrl-names = "default"; 747 pinctrl-0 = <&qup_i2c2_data_clk>; 748 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 749 #address-cells = <1>; 750 #size-cells = <0>; 751 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 752 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 753 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 754 interconnect-names = "qup-core", "qup-config", 755 "qup-memory"; 756 status = "disabled"; 757 }; 758 759 spi2: spi@988000 { 760 compatible = "qcom,geni-spi"; 761 reg = <0 0x00988000 0 0x4000>; 762 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 763 clock-names = "se"; 764 pinctrl-names = "default"; 765 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 766 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 767 #address-cells = <1>; 768 #size-cells = <0>; 769 power-domains = <&rpmhpd SC7280_CX>; 770 operating-points-v2 = <&qup_opp_table>; 771 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 772 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 773 interconnect-names = "qup-core", "qup-config"; 774 status = "disabled"; 775 }; 776 777 uart2: serial@988000 { 778 compatible = "qcom,geni-uart"; 779 reg = <0 0x00988000 0 0x4000>; 780 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 781 clock-names = "se"; 782 pinctrl-names = "default"; 783 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 784 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 785 power-domains = <&rpmhpd SC7280_CX>; 786 operating-points-v2 = <&qup_opp_table>; 787 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 788 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 789 interconnect-names = "qup-core", "qup-config"; 790 status = "disabled"; 791 }; 792 793 i2c3: i2c@98c000 { 794 compatible = "qcom,geni-i2c"; 795 reg = <0 0x0098c000 0 0x4000>; 796 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 797 clock-names = "se"; 798 pinctrl-names = "default"; 799 pinctrl-0 = <&qup_i2c3_data_clk>; 800 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 804 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 805 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 806 interconnect-names = "qup-core", "qup-config", 807 "qup-memory"; 808 status = "disabled"; 809 }; 810 811 spi3: spi@98c000 { 812 compatible = "qcom,geni-spi"; 813 reg = <0 0x0098c000 0 0x4000>; 814 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 815 clock-names = "se"; 816 pinctrl-names = "default"; 817 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 818 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 819 #address-cells = <1>; 820 #size-cells = <0>; 821 power-domains = <&rpmhpd SC7280_CX>; 822 operating-points-v2 = <&qup_opp_table>; 823 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 824 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 825 interconnect-names = "qup-core", "qup-config"; 826 status = "disabled"; 827 }; 828 829 uart3: serial@98c000 { 830 compatible = "qcom,geni-uart"; 831 reg = <0 0x0098c000 0 0x4000>; 832 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 833 clock-names = "se"; 834 pinctrl-names = "default"; 835 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 836 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 837 power-domains = <&rpmhpd SC7280_CX>; 838 operating-points-v2 = <&qup_opp_table>; 839 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 840 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 841 interconnect-names = "qup-core", "qup-config"; 842 status = "disabled"; 843 }; 844 845 i2c4: i2c@990000 { 846 compatible = "qcom,geni-i2c"; 847 reg = <0 0x00990000 0 0x4000>; 848 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 849 clock-names = "se"; 850 pinctrl-names = "default"; 851 pinctrl-0 = <&qup_i2c4_data_clk>; 852 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 853 #address-cells = <1>; 854 #size-cells = <0>; 855 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 856 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 857 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 858 interconnect-names = "qup-core", "qup-config", 859 "qup-memory"; 860 status = "disabled"; 861 }; 862 863 spi4: spi@990000 { 864 compatible = "qcom,geni-spi"; 865 reg = <0 0x00990000 0 0x4000>; 866 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 867 clock-names = "se"; 868 pinctrl-names = "default"; 869 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 870 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 871 #address-cells = <1>; 872 #size-cells = <0>; 873 power-domains = <&rpmhpd SC7280_CX>; 874 operating-points-v2 = <&qup_opp_table>; 875 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 876 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 877 interconnect-names = "qup-core", "qup-config"; 878 status = "disabled"; 879 }; 880 881 uart4: serial@990000 { 882 compatible = "qcom,geni-uart"; 883 reg = <0 0x00990000 0 0x4000>; 884 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 885 clock-names = "se"; 886 pinctrl-names = "default"; 887 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 888 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 889 power-domains = <&rpmhpd SC7280_CX>; 890 operating-points-v2 = <&qup_opp_table>; 891 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 892 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 893 interconnect-names = "qup-core", "qup-config"; 894 status = "disabled"; 895 }; 896 897 i2c5: i2c@994000 { 898 compatible = "qcom,geni-i2c"; 899 reg = <0 0x00994000 0 0x4000>; 900 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 901 clock-names = "se"; 902 pinctrl-names = "default"; 903 pinctrl-0 = <&qup_i2c5_data_clk>; 904 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 908 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 909 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 910 interconnect-names = "qup-core", "qup-config", 911 "qup-memory"; 912 status = "disabled"; 913 }; 914 915 spi5: spi@994000 { 916 compatible = "qcom,geni-spi"; 917 reg = <0 0x00994000 0 0x4000>; 918 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 919 clock-names = "se"; 920 pinctrl-names = "default"; 921 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 922 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 923 #address-cells = <1>; 924 #size-cells = <0>; 925 power-domains = <&rpmhpd SC7280_CX>; 926 operating-points-v2 = <&qup_opp_table>; 927 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 928 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 929 interconnect-names = "qup-core", "qup-config"; 930 status = "disabled"; 931 }; 932 933 uart5: serial@994000 { 934 compatible = "qcom,geni-uart"; 935 reg = <0 0x00994000 0 0x4000>; 936 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 937 clock-names = "se"; 938 pinctrl-names = "default"; 939 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 940 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 941 power-domains = <&rpmhpd SC7280_CX>; 942 operating-points-v2 = <&qup_opp_table>; 943 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 944 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 945 interconnect-names = "qup-core", "qup-config"; 946 status = "disabled"; 947 }; 948 949 i2c6: i2c@998000 { 950 compatible = "qcom,geni-i2c"; 951 reg = <0 0x00998000 0 0x4000>; 952 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 953 clock-names = "se"; 954 pinctrl-names = "default"; 955 pinctrl-0 = <&qup_i2c6_data_clk>; 956 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 957 #address-cells = <1>; 958 #size-cells = <0>; 959 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 960 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 961 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 962 interconnect-names = "qup-core", "qup-config", 963 "qup-memory"; 964 status = "disabled"; 965 }; 966 967 spi6: spi@998000 { 968 compatible = "qcom,geni-spi"; 969 reg = <0 0x00998000 0 0x4000>; 970 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 971 clock-names = "se"; 972 pinctrl-names = "default"; 973 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 974 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 975 #address-cells = <1>; 976 #size-cells = <0>; 977 power-domains = <&rpmhpd SC7280_CX>; 978 operating-points-v2 = <&qup_opp_table>; 979 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 980 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 981 interconnect-names = "qup-core", "qup-config"; 982 status = "disabled"; 983 }; 984 985 uart6: serial@998000 { 986 compatible = "qcom,geni-uart"; 987 reg = <0 0x00998000 0 0x4000>; 988 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 989 clock-names = "se"; 990 pinctrl-names = "default"; 991 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 992 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 993 power-domains = <&rpmhpd SC7280_CX>; 994 operating-points-v2 = <&qup_opp_table>; 995 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 996 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 997 interconnect-names = "qup-core", "qup-config"; 998 status = "disabled"; 999 }; 1000 1001 i2c7: i2c@99c000 { 1002 compatible = "qcom,geni-i2c"; 1003 reg = <0 0x0099c000 0 0x4000>; 1004 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1005 clock-names = "se"; 1006 pinctrl-names = "default"; 1007 pinctrl-0 = <&qup_i2c7_data_clk>; 1008 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1009 #address-cells = <1>; 1010 #size-cells = <0>; 1011 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1012 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1013 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1014 interconnect-names = "qup-core", "qup-config", 1015 "qup-memory"; 1016 status = "disabled"; 1017 }; 1018 1019 spi7: spi@99c000 { 1020 compatible = "qcom,geni-spi"; 1021 reg = <0 0x0099c000 0 0x4000>; 1022 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1023 clock-names = "se"; 1024 pinctrl-names = "default"; 1025 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1026 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 power-domains = <&rpmhpd SC7280_CX>; 1030 operating-points-v2 = <&qup_opp_table>; 1031 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1032 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1033 interconnect-names = "qup-core", "qup-config"; 1034 status = "disabled"; 1035 }; 1036 1037 uart7: serial@99c000 { 1038 compatible = "qcom,geni-uart"; 1039 reg = <0 0x0099c000 0 0x4000>; 1040 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1041 clock-names = "se"; 1042 pinctrl-names = "default"; 1043 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1044 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1045 power-domains = <&rpmhpd SC7280_CX>; 1046 operating-points-v2 = <&qup_opp_table>; 1047 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1048 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1049 interconnect-names = "qup-core", "qup-config"; 1050 status = "disabled"; 1051 }; 1052 }; 1053 1054 qupv3_id_1: geniqup@ac0000 { 1055 compatible = "qcom,geni-se-qup"; 1056 reg = <0 0x00ac0000 0 0x2000>; 1057 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1058 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1059 clock-names = "m-ahb", "s-ahb"; 1060 #address-cells = <2>; 1061 #size-cells = <2>; 1062 ranges; 1063 iommus = <&apps_smmu 0x43 0x0>; 1064 status = "disabled"; 1065 1066 i2c8: i2c@a80000 { 1067 compatible = "qcom,geni-i2c"; 1068 reg = <0 0x00a80000 0 0x4000>; 1069 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1070 clock-names = "se"; 1071 pinctrl-names = "default"; 1072 pinctrl-0 = <&qup_i2c8_data_clk>; 1073 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1077 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1078 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1079 interconnect-names = "qup-core", "qup-config", 1080 "qup-memory"; 1081 status = "disabled"; 1082 }; 1083 1084 spi8: spi@a80000 { 1085 compatible = "qcom,geni-spi"; 1086 reg = <0 0x00a80000 0 0x4000>; 1087 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1088 clock-names = "se"; 1089 pinctrl-names = "default"; 1090 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1091 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1092 #address-cells = <1>; 1093 #size-cells = <0>; 1094 power-domains = <&rpmhpd SC7280_CX>; 1095 operating-points-v2 = <&qup_opp_table>; 1096 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1097 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1098 interconnect-names = "qup-core", "qup-config"; 1099 status = "disabled"; 1100 }; 1101 1102 uart8: serial@a80000 { 1103 compatible = "qcom,geni-uart"; 1104 reg = <0 0x00a80000 0 0x4000>; 1105 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1106 clock-names = "se"; 1107 pinctrl-names = "default"; 1108 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1109 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1110 power-domains = <&rpmhpd SC7280_CX>; 1111 operating-points-v2 = <&qup_opp_table>; 1112 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1113 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1114 interconnect-names = "qup-core", "qup-config"; 1115 status = "disabled"; 1116 }; 1117 1118 i2c9: i2c@a84000 { 1119 compatible = "qcom,geni-i2c"; 1120 reg = <0 0x00a84000 0 0x4000>; 1121 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1122 clock-names = "se"; 1123 pinctrl-names = "default"; 1124 pinctrl-0 = <&qup_i2c9_data_clk>; 1125 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1129 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1130 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1131 interconnect-names = "qup-core", "qup-config", 1132 "qup-memory"; 1133 status = "disabled"; 1134 }; 1135 1136 spi9: spi@a84000 { 1137 compatible = "qcom,geni-spi"; 1138 reg = <0 0x00a84000 0 0x4000>; 1139 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1140 clock-names = "se"; 1141 pinctrl-names = "default"; 1142 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1143 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 power-domains = <&rpmhpd SC7280_CX>; 1147 operating-points-v2 = <&qup_opp_table>; 1148 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1149 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1150 interconnect-names = "qup-core", "qup-config"; 1151 status = "disabled"; 1152 }; 1153 1154 uart9: serial@a84000 { 1155 compatible = "qcom,geni-uart"; 1156 reg = <0 0x00a84000 0 0x4000>; 1157 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1158 clock-names = "se"; 1159 pinctrl-names = "default"; 1160 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1161 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1162 power-domains = <&rpmhpd SC7280_CX>; 1163 operating-points-v2 = <&qup_opp_table>; 1164 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1165 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1166 interconnect-names = "qup-core", "qup-config"; 1167 status = "disabled"; 1168 }; 1169 1170 i2c10: i2c@a88000 { 1171 compatible = "qcom,geni-i2c"; 1172 reg = <0 0x00a88000 0 0x4000>; 1173 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1174 clock-names = "se"; 1175 pinctrl-names = "default"; 1176 pinctrl-0 = <&qup_i2c10_data_clk>; 1177 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1178 #address-cells = <1>; 1179 #size-cells = <0>; 1180 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1181 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1182 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1183 interconnect-names = "qup-core", "qup-config", 1184 "qup-memory"; 1185 status = "disabled"; 1186 }; 1187 1188 spi10: spi@a88000 { 1189 compatible = "qcom,geni-spi"; 1190 reg = <0 0x00a88000 0 0x4000>; 1191 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1192 clock-names = "se"; 1193 pinctrl-names = "default"; 1194 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1195 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1196 #address-cells = <1>; 1197 #size-cells = <0>; 1198 power-domains = <&rpmhpd SC7280_CX>; 1199 operating-points-v2 = <&qup_opp_table>; 1200 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1201 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1202 interconnect-names = "qup-core", "qup-config"; 1203 status = "disabled"; 1204 }; 1205 1206 uart10: serial@a88000 { 1207 compatible = "qcom,geni-uart"; 1208 reg = <0 0x00a88000 0 0x4000>; 1209 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1210 clock-names = "se"; 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1213 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1214 power-domains = <&rpmhpd SC7280_CX>; 1215 operating-points-v2 = <&qup_opp_table>; 1216 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1217 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1218 interconnect-names = "qup-core", "qup-config"; 1219 status = "disabled"; 1220 }; 1221 1222 i2c11: i2c@a8c000 { 1223 compatible = "qcom,geni-i2c"; 1224 reg = <0 0x00a8c000 0 0x4000>; 1225 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1226 clock-names = "se"; 1227 pinctrl-names = "default"; 1228 pinctrl-0 = <&qup_i2c11_data_clk>; 1229 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1230 #address-cells = <1>; 1231 #size-cells = <0>; 1232 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1233 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1234 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1235 interconnect-names = "qup-core", "qup-config", 1236 "qup-memory"; 1237 status = "disabled"; 1238 }; 1239 1240 spi11: spi@a8c000 { 1241 compatible = "qcom,geni-spi"; 1242 reg = <0 0x00a8c000 0 0x4000>; 1243 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1244 clock-names = "se"; 1245 pinctrl-names = "default"; 1246 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1247 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1248 #address-cells = <1>; 1249 #size-cells = <0>; 1250 power-domains = <&rpmhpd SC7280_CX>; 1251 operating-points-v2 = <&qup_opp_table>; 1252 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1253 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1254 interconnect-names = "qup-core", "qup-config"; 1255 status = "disabled"; 1256 }; 1257 1258 uart11: serial@a8c000 { 1259 compatible = "qcom,geni-uart"; 1260 reg = <0 0x00a8c000 0 0x4000>; 1261 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1262 clock-names = "se"; 1263 pinctrl-names = "default"; 1264 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1265 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1266 power-domains = <&rpmhpd SC7280_CX>; 1267 operating-points-v2 = <&qup_opp_table>; 1268 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1269 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1270 interconnect-names = "qup-core", "qup-config"; 1271 status = "disabled"; 1272 }; 1273 1274 i2c12: i2c@a90000 { 1275 compatible = "qcom,geni-i2c"; 1276 reg = <0 0x00a90000 0 0x4000>; 1277 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1278 clock-names = "se"; 1279 pinctrl-names = "default"; 1280 pinctrl-0 = <&qup_i2c12_data_clk>; 1281 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1285 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1286 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1287 interconnect-names = "qup-core", "qup-config", 1288 "qup-memory"; 1289 status = "disabled"; 1290 }; 1291 1292 spi12: spi@a90000 { 1293 compatible = "qcom,geni-spi"; 1294 reg = <0 0x00a90000 0 0x4000>; 1295 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1296 clock-names = "se"; 1297 pinctrl-names = "default"; 1298 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1299 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 power-domains = <&rpmhpd SC7280_CX>; 1303 operating-points-v2 = <&qup_opp_table>; 1304 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1305 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1306 interconnect-names = "qup-core", "qup-config"; 1307 status = "disabled"; 1308 }; 1309 1310 uart12: serial@a90000 { 1311 compatible = "qcom,geni-uart"; 1312 reg = <0 0x00a90000 0 0x4000>; 1313 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1314 clock-names = "se"; 1315 pinctrl-names = "default"; 1316 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1317 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1318 power-domains = <&rpmhpd SC7280_CX>; 1319 operating-points-v2 = <&qup_opp_table>; 1320 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1321 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1322 interconnect-names = "qup-core", "qup-config"; 1323 status = "disabled"; 1324 }; 1325 1326 i2c13: i2c@a94000 { 1327 compatible = "qcom,geni-i2c"; 1328 reg = <0 0x00a94000 0 0x4000>; 1329 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1330 clock-names = "se"; 1331 pinctrl-names = "default"; 1332 pinctrl-0 = <&qup_i2c13_data_clk>; 1333 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1334 #address-cells = <1>; 1335 #size-cells = <0>; 1336 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1337 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1338 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1339 interconnect-names = "qup-core", "qup-config", 1340 "qup-memory"; 1341 status = "disabled"; 1342 }; 1343 1344 spi13: spi@a94000 { 1345 compatible = "qcom,geni-spi"; 1346 reg = <0 0x00a94000 0 0x4000>; 1347 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1348 clock-names = "se"; 1349 pinctrl-names = "default"; 1350 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1351 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1352 #address-cells = <1>; 1353 #size-cells = <0>; 1354 power-domains = <&rpmhpd SC7280_CX>; 1355 operating-points-v2 = <&qup_opp_table>; 1356 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1357 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1358 interconnect-names = "qup-core", "qup-config"; 1359 status = "disabled"; 1360 }; 1361 1362 uart13: serial@a94000 { 1363 compatible = "qcom,geni-uart"; 1364 reg = <0 0x00a94000 0 0x4000>; 1365 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1366 clock-names = "se"; 1367 pinctrl-names = "default"; 1368 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1369 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1370 power-domains = <&rpmhpd SC7280_CX>; 1371 operating-points-v2 = <&qup_opp_table>; 1372 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1373 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1374 interconnect-names = "qup-core", "qup-config"; 1375 status = "disabled"; 1376 }; 1377 1378 i2c14: i2c@a98000 { 1379 compatible = "qcom,geni-i2c"; 1380 reg = <0 0x00a98000 0 0x4000>; 1381 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1382 clock-names = "se"; 1383 pinctrl-names = "default"; 1384 pinctrl-0 = <&qup_i2c14_data_clk>; 1385 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1386 #address-cells = <1>; 1387 #size-cells = <0>; 1388 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1389 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1390 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1391 interconnect-names = "qup-core", "qup-config", 1392 "qup-memory"; 1393 status = "disabled"; 1394 }; 1395 1396 spi14: spi@a98000 { 1397 compatible = "qcom,geni-spi"; 1398 reg = <0 0x00a98000 0 0x4000>; 1399 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1400 clock-names = "se"; 1401 pinctrl-names = "default"; 1402 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1403 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1404 #address-cells = <1>; 1405 #size-cells = <0>; 1406 power-domains = <&rpmhpd SC7280_CX>; 1407 operating-points-v2 = <&qup_opp_table>; 1408 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1409 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1410 interconnect-names = "qup-core", "qup-config"; 1411 status = "disabled"; 1412 }; 1413 1414 uart14: serial@a98000 { 1415 compatible = "qcom,geni-uart"; 1416 reg = <0 0x00a98000 0 0x4000>; 1417 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1418 clock-names = "se"; 1419 pinctrl-names = "default"; 1420 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1421 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1422 power-domains = <&rpmhpd SC7280_CX>; 1423 operating-points-v2 = <&qup_opp_table>; 1424 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1425 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1426 interconnect-names = "qup-core", "qup-config"; 1427 status = "disabled"; 1428 }; 1429 1430 i2c15: i2c@a9c000 { 1431 compatible = "qcom,geni-i2c"; 1432 reg = <0 0x00a9c000 0 0x4000>; 1433 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1434 clock-names = "se"; 1435 pinctrl-names = "default"; 1436 pinctrl-0 = <&qup_i2c15_data_clk>; 1437 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1438 #address-cells = <1>; 1439 #size-cells = <0>; 1440 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1441 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1442 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1443 interconnect-names = "qup-core", "qup-config", 1444 "qup-memory"; 1445 status = "disabled"; 1446 }; 1447 1448 spi15: spi@a9c000 { 1449 compatible = "qcom,geni-spi"; 1450 reg = <0 0x00a9c000 0 0x4000>; 1451 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1452 clock-names = "se"; 1453 pinctrl-names = "default"; 1454 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1455 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1456 #address-cells = <1>; 1457 #size-cells = <0>; 1458 power-domains = <&rpmhpd SC7280_CX>; 1459 operating-points-v2 = <&qup_opp_table>; 1460 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1461 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1462 interconnect-names = "qup-core", "qup-config"; 1463 status = "disabled"; 1464 }; 1465 1466 uart15: serial@a9c000 { 1467 compatible = "qcom,geni-uart"; 1468 reg = <0 0x00a9c000 0 0x4000>; 1469 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1470 clock-names = "se"; 1471 pinctrl-names = "default"; 1472 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1473 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1474 power-domains = <&rpmhpd SC7280_CX>; 1475 operating-points-v2 = <&qup_opp_table>; 1476 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1477 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1478 interconnect-names = "qup-core", "qup-config"; 1479 status = "disabled"; 1480 }; 1481 }; 1482 1483 cnoc2: interconnect@1500000 { 1484 reg = <0 0x01500000 0 0x1000>; 1485 compatible = "qcom,sc7280-cnoc2"; 1486 #interconnect-cells = <2>; 1487 qcom,bcm-voters = <&apps_bcm_voter>; 1488 }; 1489 1490 cnoc3: interconnect@1502000 { 1491 reg = <0 0x01502000 0 0x1000>; 1492 compatible = "qcom,sc7280-cnoc3"; 1493 #interconnect-cells = <2>; 1494 qcom,bcm-voters = <&apps_bcm_voter>; 1495 }; 1496 1497 mc_virt: interconnect@1580000 { 1498 reg = <0 0x01580000 0 0x4>; 1499 compatible = "qcom,sc7280-mc-virt"; 1500 #interconnect-cells = <2>; 1501 qcom,bcm-voters = <&apps_bcm_voter>; 1502 }; 1503 1504 system_noc: interconnect@1680000 { 1505 reg = <0 0x01680000 0 0x15480>; 1506 compatible = "qcom,sc7280-system-noc"; 1507 #interconnect-cells = <2>; 1508 qcom,bcm-voters = <&apps_bcm_voter>; 1509 }; 1510 1511 aggre1_noc: interconnect@16e0000 { 1512 compatible = "qcom,sc7280-aggre1-noc"; 1513 reg = <0 0x016e0000 0 0x1c080>; 1514 #interconnect-cells = <2>; 1515 qcom,bcm-voters = <&apps_bcm_voter>; 1516 }; 1517 1518 aggre2_noc: interconnect@1700000 { 1519 reg = <0 0x01700000 0 0x2b080>; 1520 compatible = "qcom,sc7280-aggre2-noc"; 1521 #interconnect-cells = <2>; 1522 qcom,bcm-voters = <&apps_bcm_voter>; 1523 }; 1524 1525 mmss_noc: interconnect@1740000 { 1526 reg = <0 0x01740000 0 0x1e080>; 1527 compatible = "qcom,sc7280-mmss-noc"; 1528 #interconnect-cells = <2>; 1529 qcom,bcm-voters = <&apps_bcm_voter>; 1530 }; 1531 1532 ipa: ipa@1e40000 { 1533 compatible = "qcom,sc7280-ipa"; 1534 1535 iommus = <&apps_smmu 0x480 0x0>, 1536 <&apps_smmu 0x482 0x0>; 1537 reg = <0 0x1e40000 0 0x8000>, 1538 <0 0x1e50000 0 0x4ad0>, 1539 <0 0x1e04000 0 0x23000>; 1540 reg-names = "ipa-reg", 1541 "ipa-shared", 1542 "gsi"; 1543 1544 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 1545 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1546 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1547 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1548 interrupt-names = "ipa", 1549 "gsi", 1550 "ipa-clock-query", 1551 "ipa-setup-ready"; 1552 1553 clocks = <&rpmhcc RPMH_IPA_CLK>; 1554 clock-names = "core"; 1555 1556 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1557 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 1558 interconnect-names = "memory", 1559 "config"; 1560 1561 qcom,smem-states = <&ipa_smp2p_out 0>, 1562 <&ipa_smp2p_out 1>; 1563 qcom,smem-state-names = "ipa-clock-enabled-valid", 1564 "ipa-clock-enabled"; 1565 1566 status = "disabled"; 1567 }; 1568 1569 tcsr_mutex: hwlock@1f40000 { 1570 compatible = "qcom,tcsr-mutex", "syscon"; 1571 reg = <0 0x01f40000 0 0x40000>; 1572 #hwlock-cells = <1>; 1573 }; 1574 1575 lpasscc: lpasscc@3000000 { 1576 compatible = "qcom,sc7280-lpasscc"; 1577 reg = <0 0x03000000 0 0x40>, 1578 <0 0x03c04000 0 0x4>, 1579 <0 0x03389000 0 0x24>; 1580 reg-names = "qdsp6ss", "top_cc", "cc"; 1581 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 1582 clock-names = "iface"; 1583 #clock-cells = <1>; 1584 }; 1585 1586 lpass_ag_noc: interconnect@3c40000 { 1587 reg = <0 0x03c40000 0 0xf080>; 1588 compatible = "qcom,sc7280-lpass-ag-noc"; 1589 #interconnect-cells = <2>; 1590 qcom,bcm-voters = <&apps_bcm_voter>; 1591 }; 1592 1593 gpu: gpu@3d00000 { 1594 compatible = "qcom,adreno-635.0", "qcom,adreno"; 1595 #stream-id-cells = <16>; 1596 reg = <0 0x03d00000 0 0x40000>, 1597 <0 0x03d9e000 0 0x1000>, 1598 <0 0x03d61000 0 0x800>; 1599 reg-names = "kgsl_3d0_reg_memory", 1600 "cx_mem", 1601 "cx_dbgc"; 1602 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1603 iommus = <&adreno_smmu 0 0x401>; 1604 operating-points-v2 = <&gpu_opp_table>; 1605 qcom,gmu = <&gmu>; 1606 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 1607 interconnect-names = "gfx-mem"; 1608 #cooling-cells = <2>; 1609 1610 gpu_opp_table: opp-table { 1611 compatible = "operating-points-v2"; 1612 1613 opp-315000000 { 1614 opp-hz = /bits/ 64 <315000000>; 1615 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1616 opp-peak-kBps = <1804000>; 1617 }; 1618 1619 opp-450000000 { 1620 opp-hz = /bits/ 64 <450000000>; 1621 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1622 opp-peak-kBps = <4068000>; 1623 }; 1624 1625 opp-550000000 { 1626 opp-hz = /bits/ 64 <550000000>; 1627 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1628 opp-peak-kBps = <6832000>; 1629 }; 1630 }; 1631 }; 1632 1633 gmu: gmu@3d69000 { 1634 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 1635 reg = <0 0x03d6a000 0 0x34000>, 1636 <0 0x3de0000 0 0x10000>, 1637 <0 0x0b290000 0 0x10000>; 1638 reg-names = "gmu", "rscc", "gmu_pdc"; 1639 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1641 interrupt-names = "hfi", "gmu"; 1642 clocks = <&gpucc 5>, 1643 <&gpucc 8>, 1644 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1645 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1646 <&gpucc 2>, 1647 <&gpucc 15>, 1648 <&gpucc 11>; 1649 clock-names = "gmu", 1650 "cxo", 1651 "axi", 1652 "memnoc", 1653 "ahb", 1654 "hub", 1655 "smmu_vote"; 1656 power-domains = <&gpucc 0>, 1657 <&gpucc 1>; 1658 power-domain-names = "cx", 1659 "gx"; 1660 iommus = <&adreno_smmu 5 0x400>; 1661 operating-points-v2 = <&gmu_opp_table>; 1662 1663 gmu_opp_table: opp-table { 1664 compatible = "operating-points-v2"; 1665 1666 opp-200000000 { 1667 opp-hz = /bits/ 64 <200000000>; 1668 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1669 }; 1670 }; 1671 }; 1672 1673 gpucc: clock-controller@3d90000 { 1674 compatible = "qcom,sc7280-gpucc"; 1675 reg = <0 0x03d90000 0 0x9000>; 1676 clocks = <&rpmhcc RPMH_CXO_CLK>, 1677 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1678 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1679 clock-names = "bi_tcxo", 1680 "gcc_gpu_gpll0_clk_src", 1681 "gcc_gpu_gpll0_div_clk_src"; 1682 #clock-cells = <1>; 1683 #reset-cells = <1>; 1684 #power-domain-cells = <1>; 1685 }; 1686 1687 adreno_smmu: iommu@3da0000 { 1688 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 1689 reg = <0 0x03da0000 0 0x20000>; 1690 #iommu-cells = <2>; 1691 #global-interrupts = <2>; 1692 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1693 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 1694 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1695 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1696 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1697 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1698 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1699 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1700 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1701 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1702 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1703 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1704 1705 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1706 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1707 <&gpucc 2>, 1708 <&gpucc 11>, 1709 <&gpucc 5>, 1710 <&gpucc 15>, 1711 <&gpucc 13>; 1712 clock-names = "gcc_gpu_memnoc_gfx_clk", 1713 "gcc_gpu_snoc_dvm_gfx_clk", 1714 "gpu_cc_ahb_clk", 1715 "gpu_cc_hlos1_vote_gpu_smmu_clk", 1716 "gpu_cc_cx_gmu_clk", 1717 "gpu_cc_hub_cx_int_clk", 1718 "gpu_cc_hub_aon_clk"; 1719 1720 power-domains = <&gpucc 0>; 1721 }; 1722 1723 stm@6002000 { 1724 compatible = "arm,coresight-stm", "arm,primecell"; 1725 reg = <0 0x06002000 0 0x1000>, 1726 <0 0x16280000 0 0x180000>; 1727 reg-names = "stm-base", "stm-stimulus-base"; 1728 1729 clocks = <&aoss_qmp>; 1730 clock-names = "apb_pclk"; 1731 1732 out-ports { 1733 port { 1734 stm_out: endpoint { 1735 remote-endpoint = <&funnel0_in7>; 1736 }; 1737 }; 1738 }; 1739 }; 1740 1741 funnel@6041000 { 1742 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1743 reg = <0 0x06041000 0 0x1000>; 1744 1745 clocks = <&aoss_qmp>; 1746 clock-names = "apb_pclk"; 1747 1748 out-ports { 1749 port { 1750 funnel0_out: endpoint { 1751 remote-endpoint = <&merge_funnel_in0>; 1752 }; 1753 }; 1754 }; 1755 1756 in-ports { 1757 #address-cells = <1>; 1758 #size-cells = <0>; 1759 1760 port@7 { 1761 reg = <7>; 1762 funnel0_in7: endpoint { 1763 remote-endpoint = <&stm_out>; 1764 }; 1765 }; 1766 }; 1767 }; 1768 1769 funnel@6042000 { 1770 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1771 reg = <0 0x06042000 0 0x1000>; 1772 1773 clocks = <&aoss_qmp>; 1774 clock-names = "apb_pclk"; 1775 1776 out-ports { 1777 port { 1778 funnel1_out: endpoint { 1779 remote-endpoint = <&merge_funnel_in1>; 1780 }; 1781 }; 1782 }; 1783 1784 in-ports { 1785 #address-cells = <1>; 1786 #size-cells = <0>; 1787 1788 port@4 { 1789 reg = <4>; 1790 funnel1_in4: endpoint { 1791 remote-endpoint = <&apss_merge_funnel_out>; 1792 }; 1793 }; 1794 }; 1795 }; 1796 1797 funnel@6045000 { 1798 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1799 reg = <0 0x06045000 0 0x1000>; 1800 1801 clocks = <&aoss_qmp>; 1802 clock-names = "apb_pclk"; 1803 1804 out-ports { 1805 port { 1806 merge_funnel_out: endpoint { 1807 remote-endpoint = <&swao_funnel_in>; 1808 }; 1809 }; 1810 }; 1811 1812 in-ports { 1813 #address-cells = <1>; 1814 #size-cells = <0>; 1815 1816 port@0 { 1817 reg = <0>; 1818 merge_funnel_in0: endpoint { 1819 remote-endpoint = <&funnel0_out>; 1820 }; 1821 }; 1822 1823 port@1 { 1824 reg = <1>; 1825 merge_funnel_in1: endpoint { 1826 remote-endpoint = <&funnel1_out>; 1827 }; 1828 }; 1829 }; 1830 }; 1831 1832 replicator@6046000 { 1833 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1834 reg = <0 0x06046000 0 0x1000>; 1835 1836 clocks = <&aoss_qmp>; 1837 clock-names = "apb_pclk"; 1838 1839 out-ports { 1840 port { 1841 replicator_out: endpoint { 1842 remote-endpoint = <&etr_in>; 1843 }; 1844 }; 1845 }; 1846 1847 in-ports { 1848 port { 1849 replicator_in: endpoint { 1850 remote-endpoint = <&swao_replicator_out>; 1851 }; 1852 }; 1853 }; 1854 }; 1855 1856 etr@6048000 { 1857 compatible = "arm,coresight-tmc", "arm,primecell"; 1858 reg = <0 0x06048000 0 0x1000>; 1859 iommus = <&apps_smmu 0x04c0 0>; 1860 1861 clocks = <&aoss_qmp>; 1862 clock-names = "apb_pclk"; 1863 arm,scatter-gather; 1864 1865 in-ports { 1866 port { 1867 etr_in: endpoint { 1868 remote-endpoint = <&replicator_out>; 1869 }; 1870 }; 1871 }; 1872 }; 1873 1874 funnel@6b04000 { 1875 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1876 reg = <0 0x06b04000 0 0x1000>; 1877 1878 clocks = <&aoss_qmp>; 1879 clock-names = "apb_pclk"; 1880 1881 out-ports { 1882 port { 1883 swao_funnel_out: endpoint { 1884 remote-endpoint = <&etf_in>; 1885 }; 1886 }; 1887 }; 1888 1889 in-ports { 1890 #address-cells = <1>; 1891 #size-cells = <0>; 1892 1893 port@7 { 1894 reg = <7>; 1895 swao_funnel_in: endpoint { 1896 remote-endpoint = <&merge_funnel_out>; 1897 }; 1898 }; 1899 }; 1900 }; 1901 1902 etf@6b05000 { 1903 compatible = "arm,coresight-tmc", "arm,primecell"; 1904 reg = <0 0x06b05000 0 0x1000>; 1905 1906 clocks = <&aoss_qmp>; 1907 clock-names = "apb_pclk"; 1908 1909 out-ports { 1910 port { 1911 etf_out: endpoint { 1912 remote-endpoint = <&swao_replicator_in>; 1913 }; 1914 }; 1915 }; 1916 1917 in-ports { 1918 port { 1919 etf_in: endpoint { 1920 remote-endpoint = <&swao_funnel_out>; 1921 }; 1922 }; 1923 }; 1924 }; 1925 1926 replicator@6b06000 { 1927 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1928 reg = <0 0x06b06000 0 0x1000>; 1929 1930 clocks = <&aoss_qmp>; 1931 clock-names = "apb_pclk"; 1932 qcom,replicator-loses-context; 1933 1934 out-ports { 1935 port { 1936 swao_replicator_out: endpoint { 1937 remote-endpoint = <&replicator_in>; 1938 }; 1939 }; 1940 }; 1941 1942 in-ports { 1943 port { 1944 swao_replicator_in: endpoint { 1945 remote-endpoint = <&etf_out>; 1946 }; 1947 }; 1948 }; 1949 }; 1950 1951 etm@7040000 { 1952 compatible = "arm,coresight-etm4x", "arm,primecell"; 1953 reg = <0 0x07040000 0 0x1000>; 1954 1955 cpu = <&CPU0>; 1956 1957 clocks = <&aoss_qmp>; 1958 clock-names = "apb_pclk"; 1959 arm,coresight-loses-context-with-cpu; 1960 qcom,skip-power-up; 1961 1962 out-ports { 1963 port { 1964 etm0_out: endpoint { 1965 remote-endpoint = <&apss_funnel_in0>; 1966 }; 1967 }; 1968 }; 1969 }; 1970 1971 etm@7140000 { 1972 compatible = "arm,coresight-etm4x", "arm,primecell"; 1973 reg = <0 0x07140000 0 0x1000>; 1974 1975 cpu = <&CPU1>; 1976 1977 clocks = <&aoss_qmp>; 1978 clock-names = "apb_pclk"; 1979 arm,coresight-loses-context-with-cpu; 1980 qcom,skip-power-up; 1981 1982 out-ports { 1983 port { 1984 etm1_out: endpoint { 1985 remote-endpoint = <&apss_funnel_in1>; 1986 }; 1987 }; 1988 }; 1989 }; 1990 1991 etm@7240000 { 1992 compatible = "arm,coresight-etm4x", "arm,primecell"; 1993 reg = <0 0x07240000 0 0x1000>; 1994 1995 cpu = <&CPU2>; 1996 1997 clocks = <&aoss_qmp>; 1998 clock-names = "apb_pclk"; 1999 arm,coresight-loses-context-with-cpu; 2000 qcom,skip-power-up; 2001 2002 out-ports { 2003 port { 2004 etm2_out: endpoint { 2005 remote-endpoint = <&apss_funnel_in2>; 2006 }; 2007 }; 2008 }; 2009 }; 2010 2011 etm@7340000 { 2012 compatible = "arm,coresight-etm4x", "arm,primecell"; 2013 reg = <0 0x07340000 0 0x1000>; 2014 2015 cpu = <&CPU3>; 2016 2017 clocks = <&aoss_qmp>; 2018 clock-names = "apb_pclk"; 2019 arm,coresight-loses-context-with-cpu; 2020 qcom,skip-power-up; 2021 2022 out-ports { 2023 port { 2024 etm3_out: endpoint { 2025 remote-endpoint = <&apss_funnel_in3>; 2026 }; 2027 }; 2028 }; 2029 }; 2030 2031 etm@7440000 { 2032 compatible = "arm,coresight-etm4x", "arm,primecell"; 2033 reg = <0 0x07440000 0 0x1000>; 2034 2035 cpu = <&CPU4>; 2036 2037 clocks = <&aoss_qmp>; 2038 clock-names = "apb_pclk"; 2039 arm,coresight-loses-context-with-cpu; 2040 qcom,skip-power-up; 2041 2042 out-ports { 2043 port { 2044 etm4_out: endpoint { 2045 remote-endpoint = <&apss_funnel_in4>; 2046 }; 2047 }; 2048 }; 2049 }; 2050 2051 etm@7540000 { 2052 compatible = "arm,coresight-etm4x", "arm,primecell"; 2053 reg = <0 0x07540000 0 0x1000>; 2054 2055 cpu = <&CPU5>; 2056 2057 clocks = <&aoss_qmp>; 2058 clock-names = "apb_pclk"; 2059 arm,coresight-loses-context-with-cpu; 2060 qcom,skip-power-up; 2061 2062 out-ports { 2063 port { 2064 etm5_out: endpoint { 2065 remote-endpoint = <&apss_funnel_in5>; 2066 }; 2067 }; 2068 }; 2069 }; 2070 2071 etm@7640000 { 2072 compatible = "arm,coresight-etm4x", "arm,primecell"; 2073 reg = <0 0x07640000 0 0x1000>; 2074 2075 cpu = <&CPU6>; 2076 2077 clocks = <&aoss_qmp>; 2078 clock-names = "apb_pclk"; 2079 arm,coresight-loses-context-with-cpu; 2080 qcom,skip-power-up; 2081 2082 out-ports { 2083 port { 2084 etm6_out: endpoint { 2085 remote-endpoint = <&apss_funnel_in6>; 2086 }; 2087 }; 2088 }; 2089 }; 2090 2091 etm@7740000 { 2092 compatible = "arm,coresight-etm4x", "arm,primecell"; 2093 reg = <0 0x07740000 0 0x1000>; 2094 2095 cpu = <&CPU7>; 2096 2097 clocks = <&aoss_qmp>; 2098 clock-names = "apb_pclk"; 2099 arm,coresight-loses-context-with-cpu; 2100 qcom,skip-power-up; 2101 2102 out-ports { 2103 port { 2104 etm7_out: endpoint { 2105 remote-endpoint = <&apss_funnel_in7>; 2106 }; 2107 }; 2108 }; 2109 }; 2110 2111 funnel@7800000 { /* APSS Funnel */ 2112 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2113 reg = <0 0x07800000 0 0x1000>; 2114 2115 clocks = <&aoss_qmp>; 2116 clock-names = "apb_pclk"; 2117 2118 out-ports { 2119 port { 2120 apss_funnel_out: endpoint { 2121 remote-endpoint = <&apss_merge_funnel_in>; 2122 }; 2123 }; 2124 }; 2125 2126 in-ports { 2127 #address-cells = <1>; 2128 #size-cells = <0>; 2129 2130 port@0 { 2131 reg = <0>; 2132 apss_funnel_in0: endpoint { 2133 remote-endpoint = <&etm0_out>; 2134 }; 2135 }; 2136 2137 port@1 { 2138 reg = <1>; 2139 apss_funnel_in1: endpoint { 2140 remote-endpoint = <&etm1_out>; 2141 }; 2142 }; 2143 2144 port@2 { 2145 reg = <2>; 2146 apss_funnel_in2: endpoint { 2147 remote-endpoint = <&etm2_out>; 2148 }; 2149 }; 2150 2151 port@3 { 2152 reg = <3>; 2153 apss_funnel_in3: endpoint { 2154 remote-endpoint = <&etm3_out>; 2155 }; 2156 }; 2157 2158 port@4 { 2159 reg = <4>; 2160 apss_funnel_in4: endpoint { 2161 remote-endpoint = <&etm4_out>; 2162 }; 2163 }; 2164 2165 port@5 { 2166 reg = <5>; 2167 apss_funnel_in5: endpoint { 2168 remote-endpoint = <&etm5_out>; 2169 }; 2170 }; 2171 2172 port@6 { 2173 reg = <6>; 2174 apss_funnel_in6: endpoint { 2175 remote-endpoint = <&etm6_out>; 2176 }; 2177 }; 2178 2179 port@7 { 2180 reg = <7>; 2181 apss_funnel_in7: endpoint { 2182 remote-endpoint = <&etm7_out>; 2183 }; 2184 }; 2185 }; 2186 }; 2187 2188 funnel@7810000 { 2189 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2190 reg = <0 0x07810000 0 0x1000>; 2191 2192 clocks = <&aoss_qmp>; 2193 clock-names = "apb_pclk"; 2194 2195 out-ports { 2196 port { 2197 apss_merge_funnel_out: endpoint { 2198 remote-endpoint = <&funnel1_in4>; 2199 }; 2200 }; 2201 }; 2202 2203 in-ports { 2204 port { 2205 apss_merge_funnel_in: endpoint { 2206 remote-endpoint = <&apss_funnel_out>; 2207 }; 2208 }; 2209 }; 2210 }; 2211 2212 sdhc_2: sdhci@8804000 { 2213 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 2214 status = "disabled"; 2215 2216 reg = <0 0x08804000 0 0x1000>; 2217 2218 iommus = <&apps_smmu 0x100 0x0>; 2219 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2220 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2221 interrupt-names = "hc_irq", "pwr_irq"; 2222 2223 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2224 <&gcc GCC_SDCC2_AHB_CLK>, 2225 <&rpmhcc RPMH_CXO_CLK>; 2226 clock-names = "core", "iface", "xo"; 2227 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2228 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 2229 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2230 power-domains = <&rpmhpd SC7280_CX>; 2231 operating-points-v2 = <&sdhc2_opp_table>; 2232 2233 bus-width = <4>; 2234 2235 qcom,dll-config = <0x0007642c>; 2236 2237 sdhc2_opp_table: opp-table { 2238 compatible = "operating-points-v2"; 2239 2240 opp-100000000 { 2241 opp-hz = /bits/ 64 <100000000>; 2242 required-opps = <&rpmhpd_opp_low_svs>; 2243 opp-peak-kBps = <1800000 400000>; 2244 opp-avg-kBps = <100000 0>; 2245 }; 2246 2247 opp-202000000 { 2248 opp-hz = /bits/ 64 <202000000>; 2249 required-opps = <&rpmhpd_opp_nom>; 2250 opp-peak-kBps = <5400000 1600000>; 2251 opp-avg-kBps = <200000 0>; 2252 }; 2253 }; 2254 2255 }; 2256 2257 usb_1_hsphy: phy@88e3000 { 2258 compatible = "qcom,sc7280-usb-hs-phy", 2259 "qcom,usb-snps-hs-7nm-phy"; 2260 reg = <0 0x088e3000 0 0x400>; 2261 status = "disabled"; 2262 #phy-cells = <0>; 2263 2264 clocks = <&rpmhcc RPMH_CXO_CLK>; 2265 clock-names = "ref"; 2266 2267 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2268 }; 2269 2270 usb_2_hsphy: phy@88e4000 { 2271 compatible = "qcom,sc7280-usb-hs-phy", 2272 "qcom,usb-snps-hs-7nm-phy"; 2273 reg = <0 0x088e4000 0 0x400>; 2274 status = "disabled"; 2275 #phy-cells = <0>; 2276 2277 clocks = <&rpmhcc RPMH_CXO_CLK>; 2278 clock-names = "ref"; 2279 2280 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2281 }; 2282 2283 usb_1_qmpphy: phy-wrapper@88e9000 { 2284 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 2285 "qcom,sm8250-qmp-usb3-dp-phy"; 2286 reg = <0 0x088e9000 0 0x200>, 2287 <0 0x088e8000 0 0x40>, 2288 <0 0x088ea000 0 0x200>; 2289 status = "disabled"; 2290 #address-cells = <2>; 2291 #size-cells = <2>; 2292 ranges; 2293 2294 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2295 <&rpmhcc RPMH_CXO_CLK>, 2296 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2297 clock-names = "aux", "ref_clk_src", "com_aux"; 2298 2299 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2300 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2301 reset-names = "phy", "common"; 2302 2303 usb_1_ssphy: usb3-phy@88e9200 { 2304 reg = <0 0x088e9200 0 0x200>, 2305 <0 0x088e9400 0 0x200>, 2306 <0 0x088e9c00 0 0x400>, 2307 <0 0x088e9600 0 0x200>, 2308 <0 0x088e9800 0 0x200>, 2309 <0 0x088e9a00 0 0x100>; 2310 #clock-cells = <0>; 2311 #phy-cells = <0>; 2312 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2313 clock-names = "pipe0"; 2314 clock-output-names = "usb3_phy_pipe_clk_src"; 2315 }; 2316 2317 dp_phy: dp-phy@88ea200 { 2318 reg = <0 0x088ea200 0 0x200>, 2319 <0 0x088ea400 0 0x200>, 2320 <0 0x088eaa00 0 0x200>, 2321 <0 0x088ea600 0 0x200>, 2322 <0 0x088ea800 0 0x200>; 2323 #phy-cells = <0>; 2324 #clock-cells = <1>; 2325 }; 2326 }; 2327 2328 usb_2: usb@8cf8800 { 2329 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2330 reg = <0 0x08cf8800 0 0x400>; 2331 status = "disabled"; 2332 #address-cells = <2>; 2333 #size-cells = <2>; 2334 ranges; 2335 dma-ranges; 2336 2337 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2338 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2339 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2340 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2341 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 2342 clock-names = "cfg_noc", "core", "iface","mock_utmi", 2343 "sleep"; 2344 2345 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2346 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2347 assigned-clock-rates = <19200000>, <200000000>; 2348 2349 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2350 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 2351 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 2352 interrupt-names = "hs_phy_irq", 2353 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2354 2355 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 2356 2357 resets = <&gcc GCC_USB30_SEC_BCR>; 2358 2359 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 2360 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 2361 interconnect-names = "usb-ddr", "apps-usb"; 2362 2363 usb_2_dwc3: usb@8c00000 { 2364 compatible = "snps,dwc3"; 2365 reg = <0 0x08c00000 0 0xe000>; 2366 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2367 iommus = <&apps_smmu 0xa0 0x0>; 2368 snps,dis_u2_susphy_quirk; 2369 snps,dis_enblslpm_quirk; 2370 phys = <&usb_2_hsphy>; 2371 phy-names = "usb2-phy"; 2372 maximum-speed = "high-speed"; 2373 }; 2374 }; 2375 2376 qspi: spi@88dc000 { 2377 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 2378 reg = <0 0x088dc000 0 0x1000>; 2379 #address-cells = <1>; 2380 #size-cells = <0>; 2381 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2382 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2383 <&gcc GCC_QSPI_CORE_CLK>; 2384 clock-names = "iface", "core"; 2385 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2386 &cnoc2 SLAVE_QSPI_0 0>; 2387 interconnect-names = "qspi-config"; 2388 power-domains = <&rpmhpd SC7280_CX>; 2389 operating-points-v2 = <&qspi_opp_table>; 2390 status = "disabled"; 2391 }; 2392 2393 dc_noc: interconnect@90e0000 { 2394 reg = <0 0x090e0000 0 0x5080>; 2395 compatible = "qcom,sc7280-dc-noc"; 2396 #interconnect-cells = <2>; 2397 qcom,bcm-voters = <&apps_bcm_voter>; 2398 }; 2399 2400 gem_noc: interconnect@9100000 { 2401 reg = <0 0x9100000 0 0xe2200>; 2402 compatible = "qcom,sc7280-gem-noc"; 2403 #interconnect-cells = <2>; 2404 qcom,bcm-voters = <&apps_bcm_voter>; 2405 }; 2406 2407 system-cache-controller@9200000 { 2408 compatible = "qcom,sc7280-llcc"; 2409 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 2410 reg-names = "llcc_base", "llcc_broadcast_base"; 2411 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2412 }; 2413 2414 nsp_noc: interconnect@a0c0000 { 2415 reg = <0 0x0a0c0000 0 0x10000>; 2416 compatible = "qcom,sc7280-nsp-noc"; 2417 #interconnect-cells = <2>; 2418 qcom,bcm-voters = <&apps_bcm_voter>; 2419 }; 2420 2421 usb_1: usb@a6f8800 { 2422 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2423 reg = <0 0x0a6f8800 0 0x400>; 2424 status = "disabled"; 2425 #address-cells = <2>; 2426 #size-cells = <2>; 2427 ranges; 2428 dma-ranges; 2429 2430 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2431 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2432 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2433 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2434 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2435 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2436 "sleep"; 2437 2438 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2439 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2440 assigned-clock-rates = <19200000>, <200000000>; 2441 2442 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2443 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2444 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2445 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2446 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2447 "dm_hs_phy_irq", "ss_phy_irq"; 2448 2449 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 2450 2451 resets = <&gcc GCC_USB30_PRIM_BCR>; 2452 2453 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2454 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 2455 interconnect-names = "usb-ddr", "apps-usb"; 2456 2457 usb_1_dwc3: usb@a600000 { 2458 compatible = "snps,dwc3"; 2459 reg = <0 0x0a600000 0 0xe000>; 2460 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2461 iommus = <&apps_smmu 0xe0 0x0>; 2462 snps,dis_u2_susphy_quirk; 2463 snps,dis_enblslpm_quirk; 2464 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2465 phy-names = "usb2-phy", "usb3-phy"; 2466 maximum-speed = "super-speed"; 2467 }; 2468 }; 2469 2470 videocc: clock-controller@aaf0000 { 2471 compatible = "qcom,sc7280-videocc"; 2472 reg = <0 0xaaf0000 0 0x10000>; 2473 clocks = <&rpmhcc RPMH_CXO_CLK>, 2474 <&rpmhcc RPMH_CXO_CLK_A>; 2475 clock-names = "bi_tcxo", "bi_tcxo_ao"; 2476 #clock-cells = <1>; 2477 #reset-cells = <1>; 2478 #power-domain-cells = <1>; 2479 }; 2480 2481 dispcc: clock-controller@af00000 { 2482 compatible = "qcom,sc7280-dispcc"; 2483 reg = <0 0xaf00000 0 0x20000>; 2484 clocks = <&rpmhcc RPMH_CXO_CLK>, 2485 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2486 <0>, <0>, <0>, <0>, <0>, <0>; 2487 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 2488 "dsi0_phy_pll_out_byteclk", 2489 "dsi0_phy_pll_out_dsiclk", 2490 "dp_phy_pll_link_clk", 2491 "dp_phy_pll_vco_div_clk", 2492 "edp_phy_pll_link_clk", 2493 "edp_phy_pll_vco_div_clk"; 2494 #clock-cells = <1>; 2495 #reset-cells = <1>; 2496 #power-domain-cells = <1>; 2497 }; 2498 2499 pdc: interrupt-controller@b220000 { 2500 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 2501 reg = <0 0x0b220000 0 0x30000>; 2502 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 2503 <55 306 4>, <59 312 3>, <62 374 2>, 2504 <64 434 2>, <66 438 3>, <69 86 1>, 2505 <70 520 54>, <124 609 31>, <155 63 1>, 2506 <156 716 12>; 2507 #interrupt-cells = <2>; 2508 interrupt-parent = <&intc>; 2509 interrupt-controller; 2510 }; 2511 2512 pdc_reset: reset-controller@b5e0000 { 2513 compatible = "qcom,sc7280-pdc-global"; 2514 reg = <0 0x0b5e0000 0 0x20000>; 2515 #reset-cells = <1>; 2516 }; 2517 2518 tsens0: thermal-sensor@c263000 { 2519 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 2520 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2521 <0 0x0c222000 0 0x1ff>; /* SROT */ 2522 #qcom,sensors = <15>; 2523 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2524 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2525 interrupt-names = "uplow","critical"; 2526 #thermal-sensor-cells = <1>; 2527 }; 2528 2529 tsens1: thermal-sensor@c265000 { 2530 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 2531 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2532 <0 0x0c223000 0 0x1ff>; /* SROT */ 2533 #qcom,sensors = <12>; 2534 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2535 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2536 interrupt-names = "uplow","critical"; 2537 #thermal-sensor-cells = <1>; 2538 }; 2539 2540 aoss_reset: reset-controller@c2a0000 { 2541 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 2542 reg = <0 0x0c2a0000 0 0x31000>; 2543 #reset-cells = <1>; 2544 }; 2545 2546 aoss_qmp: power-controller@c300000 { 2547 compatible = "qcom,sc7280-aoss-qmp"; 2548 reg = <0 0x0c300000 0 0x100000>; 2549 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 2550 IPCC_MPROC_SIGNAL_GLINK_QMP 2551 IRQ_TYPE_EDGE_RISING>; 2552 mboxes = <&ipcc IPCC_CLIENT_AOP 2553 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2554 2555 #clock-cells = <0>; 2556 }; 2557 2558 spmi_bus: spmi@c440000 { 2559 compatible = "qcom,spmi-pmic-arb"; 2560 reg = <0 0x0c440000 0 0x1100>, 2561 <0 0x0c600000 0 0x2000000>, 2562 <0 0x0e600000 0 0x100000>, 2563 <0 0x0e700000 0 0xa0000>, 2564 <0 0x0c40a000 0 0x26000>; 2565 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2566 interrupt-names = "periph_irq"; 2567 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2568 qcom,ee = <0>; 2569 qcom,channel = <0>; 2570 #address-cells = <1>; 2571 #size-cells = <1>; 2572 interrupt-controller; 2573 #interrupt-cells = <4>; 2574 }; 2575 2576 tlmm: pinctrl@f100000 { 2577 compatible = "qcom,sc7280-pinctrl"; 2578 reg = <0 0x0f100000 0 0x300000>; 2579 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2580 gpio-controller; 2581 #gpio-cells = <2>; 2582 interrupt-controller; 2583 #interrupt-cells = <2>; 2584 gpio-ranges = <&tlmm 0 0 175>; 2585 wakeup-parent = <&pdc>; 2586 2587 qspi_clk: qspi-clk { 2588 pins = "gpio14"; 2589 function = "qspi_clk"; 2590 }; 2591 2592 qspi_cs0: qspi-cs0 { 2593 pins = "gpio15"; 2594 function = "qspi_cs"; 2595 }; 2596 2597 qspi_cs1: qspi-cs1 { 2598 pins = "gpio19"; 2599 function = "qspi_cs"; 2600 }; 2601 2602 qspi_data01: qspi-data01 { 2603 pins = "gpio12", "gpio13"; 2604 function = "qspi_data"; 2605 }; 2606 2607 qspi_data12: qspi-data12 { 2608 pins = "gpio16", "gpio17"; 2609 function = "qspi_data"; 2610 }; 2611 2612 qup_i2c0_data_clk: qup-i2c0-data-clk { 2613 pins = "gpio0", "gpio1"; 2614 function = "qup00"; 2615 }; 2616 2617 qup_i2c1_data_clk: qup-i2c1-data-clk { 2618 pins = "gpio4", "gpio5"; 2619 function = "qup01"; 2620 }; 2621 2622 qup_i2c2_data_clk: qup-i2c2-data-clk { 2623 pins = "gpio8", "gpio9"; 2624 function = "qup02"; 2625 }; 2626 2627 qup_i2c3_data_clk: qup-i2c3-data-clk { 2628 pins = "gpio12", "gpio13"; 2629 function = "qup03"; 2630 }; 2631 2632 qup_i2c4_data_clk: qup-i2c4-data-clk { 2633 pins = "gpio16", "gpio17"; 2634 function = "qup04"; 2635 }; 2636 2637 qup_i2c5_data_clk: qup-i2c5-data-clk { 2638 pins = "gpio20", "gpio21"; 2639 function = "qup05"; 2640 }; 2641 2642 qup_i2c6_data_clk: qup-i2c6-data-clk { 2643 pins = "gpio24", "gpio25"; 2644 function = "qup06"; 2645 }; 2646 2647 qup_i2c7_data_clk: qup-i2c7-data-clk { 2648 pins = "gpio28", "gpio29"; 2649 function = "qup07"; 2650 }; 2651 2652 qup_i2c8_data_clk: qup-i2c8-data-clk { 2653 pins = "gpio32", "gpio33"; 2654 function = "qup10"; 2655 }; 2656 2657 qup_i2c9_data_clk: qup-i2c9-data-clk { 2658 pins = "gpio36", "gpio37"; 2659 function = "qup11"; 2660 }; 2661 2662 qup_i2c10_data_clk: qup-i2c10-data-clk { 2663 pins = "gpio40", "gpio41"; 2664 function = "qup12"; 2665 }; 2666 2667 qup_i2c11_data_clk: qup-i2c11-data-clk { 2668 pins = "gpio44", "gpio45"; 2669 function = "qup13"; 2670 }; 2671 2672 qup_i2c12_data_clk: qup-i2c12-data-clk { 2673 pins = "gpio48", "gpio49"; 2674 function = "qup14"; 2675 }; 2676 2677 qup_i2c13_data_clk: qup-i2c13-data-clk { 2678 pins = "gpio52", "gpio53"; 2679 function = "qup15"; 2680 }; 2681 2682 qup_i2c14_data_clk: qup-i2c14-data-clk { 2683 pins = "gpio56", "gpio57"; 2684 function = "qup16"; 2685 }; 2686 2687 qup_i2c15_data_clk: qup-i2c15-data-clk { 2688 pins = "gpio60", "gpio61"; 2689 function = "qup17"; 2690 }; 2691 2692 qup_spi0_data_clk: qup-spi0-data-clk { 2693 pins = "gpio0", "gpio1", "gpio2"; 2694 function = "qup00"; 2695 }; 2696 2697 qup_spi0_cs: qup-spi0-cs { 2698 pins = "gpio3"; 2699 function = "qup00"; 2700 }; 2701 2702 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 2703 pins = "gpio3"; 2704 function = "gpio"; 2705 }; 2706 2707 qup_spi1_data_clk: qup-spi1-data-clk { 2708 pins = "gpio4", "gpio5", "gpio6"; 2709 function = "qup01"; 2710 }; 2711 2712 qup_spi1_cs: qup-spi1-cs { 2713 pins = "gpio7"; 2714 function = "qup01"; 2715 }; 2716 2717 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 2718 pins = "gpio7"; 2719 function = "gpio"; 2720 }; 2721 2722 qup_spi2_data_clk: qup-spi2-data-clk { 2723 pins = "gpio8", "gpio9", "gpio10"; 2724 function = "qup02"; 2725 }; 2726 2727 qup_spi2_cs: qup-spi2-cs { 2728 pins = "gpio11"; 2729 function = "qup02"; 2730 }; 2731 2732 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 2733 pins = "gpio11"; 2734 function = "gpio"; 2735 }; 2736 2737 qup_spi3_data_clk: qup-spi3-data-clk { 2738 pins = "gpio12", "gpio13", "gpio14"; 2739 function = "qup03"; 2740 }; 2741 2742 qup_spi3_cs: qup-spi3-cs { 2743 pins = "gpio15"; 2744 function = "qup03"; 2745 }; 2746 2747 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 2748 pins = "gpio15"; 2749 function = "gpio"; 2750 }; 2751 2752 qup_spi4_data_clk: qup-spi4-data-clk { 2753 pins = "gpio16", "gpio17", "gpio18"; 2754 function = "qup04"; 2755 }; 2756 2757 qup_spi4_cs: qup-spi4-cs { 2758 pins = "gpio19"; 2759 function = "qup04"; 2760 }; 2761 2762 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 2763 pins = "gpio19"; 2764 function = "gpio"; 2765 }; 2766 2767 qup_spi5_data_clk: qup-spi5-data-clk { 2768 pins = "gpio20", "gpio21", "gpio22"; 2769 function = "qup05"; 2770 }; 2771 2772 qup_spi5_cs: qup-spi5-cs { 2773 pins = "gpio23"; 2774 function = "qup05"; 2775 }; 2776 2777 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 2778 pins = "gpio23"; 2779 function = "gpio"; 2780 }; 2781 2782 qup_spi6_data_clk: qup-spi6-data-clk { 2783 pins = "gpio24", "gpio25", "gpio26"; 2784 function = "qup06"; 2785 }; 2786 2787 qup_spi6_cs: qup-spi6-cs { 2788 pins = "gpio27"; 2789 function = "qup06"; 2790 }; 2791 2792 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 2793 pins = "gpio27"; 2794 function = "gpio"; 2795 }; 2796 2797 qup_spi7_data_clk: qup-spi7-data-clk { 2798 pins = "gpio28", "gpio29", "gpio30"; 2799 function = "qup07"; 2800 }; 2801 2802 qup_spi7_cs: qup-spi7-cs { 2803 pins = "gpio31"; 2804 function = "qup07"; 2805 }; 2806 2807 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 2808 pins = "gpio31"; 2809 function = "gpio"; 2810 }; 2811 2812 qup_spi8_data_clk: qup-spi8-data-clk { 2813 pins = "gpio32", "gpio33", "gpio34"; 2814 function = "qup10"; 2815 }; 2816 2817 qup_spi8_cs: qup-spi8-cs { 2818 pins = "gpio35"; 2819 function = "qup10"; 2820 }; 2821 2822 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 2823 pins = "gpio35"; 2824 function = "gpio"; 2825 }; 2826 2827 qup_spi9_data_clk: qup-spi9-data-clk { 2828 pins = "gpio36", "gpio37", "gpio38"; 2829 function = "qup11"; 2830 }; 2831 2832 qup_spi9_cs: qup-spi9-cs { 2833 pins = "gpio39"; 2834 function = "qup11"; 2835 }; 2836 2837 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 2838 pins = "gpio39"; 2839 function = "gpio"; 2840 }; 2841 2842 qup_spi10_data_clk: qup-spi10-data-clk { 2843 pins = "gpio40", "gpio41", "gpio42"; 2844 function = "qup12"; 2845 }; 2846 2847 qup_spi10_cs: qup-spi10-cs { 2848 pins = "gpio43"; 2849 function = "qup12"; 2850 }; 2851 2852 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 2853 pins = "gpio43"; 2854 function = "gpio"; 2855 }; 2856 2857 qup_spi11_data_clk: qup-spi11-data-clk { 2858 pins = "gpio44", "gpio45", "gpio46"; 2859 function = "qup13"; 2860 }; 2861 2862 qup_spi11_cs: qup-spi11-cs { 2863 pins = "gpio47"; 2864 function = "qup13"; 2865 }; 2866 2867 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 2868 pins = "gpio47"; 2869 function = "gpio"; 2870 }; 2871 2872 qup_spi12_data_clk: qup-spi12-data-clk { 2873 pins = "gpio48", "gpio49", "gpio50"; 2874 function = "qup14"; 2875 }; 2876 2877 qup_spi12_cs: qup-spi12-cs { 2878 pins = "gpio51"; 2879 function = "qup14"; 2880 }; 2881 2882 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 2883 pins = "gpio51"; 2884 function = "gpio"; 2885 }; 2886 2887 qup_spi13_data_clk: qup-spi13-data-clk { 2888 pins = "gpio52", "gpio53", "gpio54"; 2889 function = "qup15"; 2890 }; 2891 2892 qup_spi13_cs: qup-spi13-cs { 2893 pins = "gpio55"; 2894 function = "qup15"; 2895 }; 2896 2897 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 2898 pins = "gpio55"; 2899 function = "gpio"; 2900 }; 2901 2902 qup_spi14_data_clk: qup-spi14-data-clk { 2903 pins = "gpio56", "gpio57", "gpio58"; 2904 function = "qup16"; 2905 }; 2906 2907 qup_spi14_cs: qup-spi14-cs { 2908 pins = "gpio59"; 2909 function = "qup16"; 2910 }; 2911 2912 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 2913 pins = "gpio59"; 2914 function = "gpio"; 2915 }; 2916 2917 qup_spi15_data_clk: qup-spi15-data-clk { 2918 pins = "gpio60", "gpio61", "gpio62"; 2919 function = "qup17"; 2920 }; 2921 2922 qup_spi15_cs: qup-spi15-cs { 2923 pins = "gpio63"; 2924 function = "qup17"; 2925 }; 2926 2927 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 2928 pins = "gpio63"; 2929 function = "gpio"; 2930 }; 2931 2932 qup_uart0_cts: qup-uart0-cts { 2933 pins = "gpio0"; 2934 function = "qup00"; 2935 }; 2936 2937 qup_uart0_rts: qup-uart0-rts { 2938 pins = "gpio1"; 2939 function = "qup00"; 2940 }; 2941 2942 qup_uart0_tx: qup-uart0-tx { 2943 pins = "gpio2"; 2944 function = "qup00"; 2945 }; 2946 2947 qup_uart0_rx: qup-uart0-rx { 2948 pins = "gpio3"; 2949 function = "qup00"; 2950 }; 2951 2952 qup_uart1_cts: qup-uart1-cts { 2953 pins = "gpio4"; 2954 function = "qup01"; 2955 }; 2956 2957 qup_uart1_rts: qup-uart1-rts { 2958 pins = "gpio5"; 2959 function = "qup01"; 2960 }; 2961 2962 qup_uart1_tx: qup-uart1-tx { 2963 pins = "gpio6"; 2964 function = "qup01"; 2965 }; 2966 2967 qup_uart1_rx: qup-uart1-rx { 2968 pins = "gpio7"; 2969 function = "qup01"; 2970 }; 2971 2972 qup_uart2_cts: qup-uart2-cts { 2973 pins = "gpio8"; 2974 function = "qup02"; 2975 }; 2976 2977 qup_uart2_rts: qup-uart2-rts { 2978 pins = "gpio9"; 2979 function = "qup02"; 2980 }; 2981 2982 qup_uart2_tx: qup-uart2-tx { 2983 pins = "gpio10"; 2984 function = "qup02"; 2985 }; 2986 2987 qup_uart2_rx: qup-uart2-rx { 2988 pins = "gpio11"; 2989 function = "qup02"; 2990 }; 2991 2992 qup_uart3_cts: qup-uart3-cts { 2993 pins = "gpio12"; 2994 function = "qup03"; 2995 }; 2996 2997 qup_uart3_rts: qup-uart3-rts { 2998 pins = "gpio13"; 2999 function = "qup03"; 3000 }; 3001 3002 qup_uart3_tx: qup-uart3-tx { 3003 pins = "gpio14"; 3004 function = "qup03"; 3005 }; 3006 3007 qup_uart3_rx: qup-uart3-rx { 3008 pins = "gpio15"; 3009 function = "qup03"; 3010 }; 3011 3012 qup_uart4_cts: qup-uart4-cts { 3013 pins = "gpio16"; 3014 function = "qup04"; 3015 }; 3016 3017 qup_uart4_rts: qup-uart4-rts { 3018 pins = "gpio17"; 3019 function = "qup04"; 3020 }; 3021 3022 qup_uart4_tx: qup-uart4-tx { 3023 pins = "gpio18"; 3024 function = "qup04"; 3025 }; 3026 3027 qup_uart4_rx: qup-uart4-rx { 3028 pins = "gpio19"; 3029 function = "qup04"; 3030 }; 3031 3032 qup_uart5_cts: qup-uart5-cts { 3033 pins = "gpio20"; 3034 function = "qup05"; 3035 }; 3036 3037 qup_uart5_rts: qup-uart5-rts { 3038 pins = "gpio21"; 3039 function = "qup05"; 3040 }; 3041 3042 qup_uart5_tx: qup-uart5-tx { 3043 pins = "gpio22"; 3044 function = "qup05"; 3045 }; 3046 3047 qup_uart5_rx: qup-uart5-rx { 3048 pins = "gpio23"; 3049 function = "qup05"; 3050 }; 3051 3052 qup_uart6_cts: qup-uart6-cts { 3053 pins = "gpio24"; 3054 function = "qup06"; 3055 }; 3056 3057 qup_uart6_rts: qup-uart6-rts { 3058 pins = "gpio25"; 3059 function = "qup06"; 3060 }; 3061 3062 qup_uart6_tx: qup-uart6-tx { 3063 pins = "gpio26"; 3064 function = "qup06"; 3065 }; 3066 3067 qup_uart6_rx: qup-uart6-rx { 3068 pins = "gpio27"; 3069 function = "qup06"; 3070 }; 3071 3072 qup_uart7_cts: qup-uart7-cts { 3073 pins = "gpio28"; 3074 function = "qup07"; 3075 }; 3076 3077 qup_uart7_rts: qup-uart7-rts { 3078 pins = "gpio29"; 3079 function = "qup07"; 3080 }; 3081 3082 qup_uart7_tx: qup-uart7-tx { 3083 pins = "gpio30"; 3084 function = "qup07"; 3085 }; 3086 3087 qup_uart7_rx: qup-uart7-rx { 3088 pins = "gpio31"; 3089 function = "qup07"; 3090 }; 3091 3092 sdc1_on: sdc1-on { 3093 clk { 3094 pins = "sdc1_clk"; 3095 }; 3096 3097 cmd { 3098 pins = "sdc1_cmd"; 3099 }; 3100 3101 data { 3102 pins = "sdc1_data"; 3103 }; 3104 3105 rclk { 3106 pins = "sdc1_rclk"; 3107 }; 3108 }; 3109 3110 sdc1_off: sdc1-off { 3111 clk { 3112 pins = "sdc1_clk"; 3113 drive-strength = <2>; 3114 bias-bus-hold; 3115 }; 3116 3117 cmd { 3118 pins = "sdc1_cmd"; 3119 drive-strength = <2>; 3120 bias-bus-hold; 3121 }; 3122 3123 data { 3124 pins = "sdc1_data"; 3125 drive-strength = <2>; 3126 bias-bus-hold; 3127 }; 3128 3129 rclk { 3130 pins = "sdc1_rclk"; 3131 bias-bus-hold; 3132 }; 3133 }; 3134 3135 sdc2_on: sdc2-on { 3136 clk { 3137 pins = "sdc2_clk"; 3138 }; 3139 3140 cmd { 3141 pins = "sdc2_cmd"; 3142 }; 3143 3144 data { 3145 pins = "sdc2_data"; 3146 }; 3147 }; 3148 3149 sdc2_off: sdc2-off { 3150 clk { 3151 pins = "sdc2_clk"; 3152 drive-strength = <2>; 3153 bias-bus-hold; 3154 }; 3155 3156 cmd { 3157 pins ="sdc2_cmd"; 3158 drive-strength = <2>; 3159 bias-bus-hold; 3160 }; 3161 3162 data { 3163 pins ="sdc2_data"; 3164 drive-strength = <2>; 3165 bias-bus-hold; 3166 }; 3167 }; 3168 3169 qup_uart8_cts: qup-uart8-cts { 3170 pins = "gpio32"; 3171 function = "qup10"; 3172 }; 3173 3174 qup_uart8_rts: qup-uart8-rts { 3175 pins = "gpio33"; 3176 function = "qup10"; 3177 }; 3178 3179 qup_uart8_tx: qup-uart8-tx { 3180 pins = "gpio34"; 3181 function = "qup10"; 3182 }; 3183 3184 qup_uart8_rx: qup-uart8-rx { 3185 pins = "gpio35"; 3186 function = "qup10"; 3187 }; 3188 3189 qup_uart9_cts: qup-uart9-cts { 3190 pins = "gpio36"; 3191 function = "qup11"; 3192 }; 3193 3194 qup_uart9_rts: qup-uart9-rts { 3195 pins = "gpio37"; 3196 function = "qup11"; 3197 }; 3198 3199 qup_uart9_tx: qup-uart9-tx { 3200 pins = "gpio38"; 3201 function = "qup11"; 3202 }; 3203 3204 qup_uart9_rx: qup-uart9-rx { 3205 pins = "gpio39"; 3206 function = "qup11"; 3207 }; 3208 3209 qup_uart10_cts: qup-uart10-cts { 3210 pins = "gpio40"; 3211 function = "qup12"; 3212 }; 3213 3214 qup_uart10_rts: qup-uart10-rts { 3215 pins = "gpio41"; 3216 function = "qup12"; 3217 }; 3218 3219 qup_uart10_tx: qup-uart10-tx { 3220 pins = "gpio42"; 3221 function = "qup12"; 3222 }; 3223 3224 qup_uart10_rx: qup-uart10-rx { 3225 pins = "gpio43"; 3226 function = "qup12"; 3227 }; 3228 3229 qup_uart11_cts: qup-uart11-cts { 3230 pins = "gpio44"; 3231 function = "qup13"; 3232 }; 3233 3234 qup_uart11_rts: qup-uart11-rts { 3235 pins = "gpio45"; 3236 function = "qup13"; 3237 }; 3238 3239 qup_uart11_tx: qup-uart11-tx { 3240 pins = "gpio46"; 3241 function = "qup13"; 3242 }; 3243 3244 qup_uart11_rx: qup-uart11-rx { 3245 pins = "gpio47"; 3246 function = "qup13"; 3247 }; 3248 3249 qup_uart12_cts: qup-uart12-cts { 3250 pins = "gpio48"; 3251 function = "qup14"; 3252 }; 3253 3254 qup_uart12_rts: qup-uart12-rts { 3255 pins = "gpio49"; 3256 function = "qup14"; 3257 }; 3258 3259 qup_uart12_tx: qup-uart12-tx { 3260 pins = "gpio50"; 3261 function = "qup14"; 3262 }; 3263 3264 qup_uart12_rx: qup-uart12-rx { 3265 pins = "gpio51"; 3266 function = "qup14"; 3267 }; 3268 3269 qup_uart13_cts: qup-uart13-cts { 3270 pins = "gpio52"; 3271 function = "qup15"; 3272 }; 3273 3274 qup_uart13_rts: qup-uart13-rts { 3275 pins = "gpio53"; 3276 function = "qup15"; 3277 }; 3278 3279 qup_uart13_tx: qup-uart13-tx { 3280 pins = "gpio54"; 3281 function = "qup15"; 3282 }; 3283 3284 qup_uart13_rx: qup-uart13-rx { 3285 pins = "gpio55"; 3286 function = "qup15"; 3287 }; 3288 3289 qup_uart14_cts: qup-uart14-cts { 3290 pins = "gpio56"; 3291 function = "qup16"; 3292 }; 3293 3294 qup_uart14_rts: qup-uart14-rts { 3295 pins = "gpio57"; 3296 function = "qup16"; 3297 }; 3298 3299 qup_uart14_tx: qup-uart14-tx { 3300 pins = "gpio58"; 3301 function = "qup16"; 3302 }; 3303 3304 qup_uart14_rx: qup-uart14-rx { 3305 pins = "gpio59"; 3306 function = "qup16"; 3307 }; 3308 3309 qup_uart15_cts: qup-uart15-cts { 3310 pins = "gpio60"; 3311 function = "qup17"; 3312 }; 3313 3314 qup_uart15_rts: qup-uart15-rts { 3315 pins = "gpio61"; 3316 function = "qup17"; 3317 }; 3318 3319 qup_uart15_tx: qup-uart15-tx { 3320 pins = "gpio62"; 3321 function = "qup17"; 3322 }; 3323 3324 qup_uart15_rx: qup-uart15-rx { 3325 pins = "gpio63"; 3326 function = "qup17"; 3327 }; 3328 }; 3329 3330 apps_smmu: iommu@15000000 { 3331 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 3332 reg = <0 0x15000000 0 0x100000>; 3333 #iommu-cells = <2>; 3334 #global-interrupts = <1>; 3335 dma-coherent; 3336 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3337 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3338 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3339 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3340 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3341 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3342 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3343 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3344 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3345 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3346 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3347 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3348 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3349 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3350 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3351 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3352 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3353 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3354 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3355 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3356 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3357 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3358 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3359 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3360 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3361 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3362 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3363 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3364 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3365 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3366 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3367 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3368 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3369 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3370 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3371 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3372 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3373 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3374 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3375 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3377 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3378 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3379 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3380 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3381 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3382 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3383 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3384 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3385 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3386 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3387 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3388 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3389 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3390 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3391 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3392 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3393 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3394 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3395 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3396 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3397 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3398 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3399 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3400 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3401 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3402 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3403 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3404 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3405 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3406 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3407 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3408 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3409 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3410 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3411 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3412 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3413 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3414 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3415 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3416 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 3417 }; 3418 3419 intc: interrupt-controller@17a00000 { 3420 compatible = "arm,gic-v3"; 3421 #address-cells = <2>; 3422 #size-cells = <2>; 3423 ranges; 3424 #interrupt-cells = <3>; 3425 interrupt-controller; 3426 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3427 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3428 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 3429 3430 gic-its@17a40000 { 3431 compatible = "arm,gic-v3-its"; 3432 msi-controller; 3433 #msi-cells = <1>; 3434 reg = <0 0x17a40000 0 0x20000>; 3435 status = "disabled"; 3436 }; 3437 }; 3438 3439 watchdog@17c10000 { 3440 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 3441 reg = <0 0x17c10000 0 0x1000>; 3442 clocks = <&sleep_clk>; 3443 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3444 }; 3445 3446 timer@17c20000 { 3447 #address-cells = <2>; 3448 #size-cells = <2>; 3449 ranges; 3450 compatible = "arm,armv7-timer-mem"; 3451 reg = <0 0x17c20000 0 0x1000>; 3452 3453 frame@17c21000 { 3454 frame-number = <0>; 3455 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3456 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3457 reg = <0 0x17c21000 0 0x1000>, 3458 <0 0x17c22000 0 0x1000>; 3459 }; 3460 3461 frame@17c23000 { 3462 frame-number = <1>; 3463 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3464 reg = <0 0x17c23000 0 0x1000>; 3465 status = "disabled"; 3466 }; 3467 3468 frame@17c25000 { 3469 frame-number = <2>; 3470 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3471 reg = <0 0x17c25000 0 0x1000>; 3472 status = "disabled"; 3473 }; 3474 3475 frame@17c27000 { 3476 frame-number = <3>; 3477 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3478 reg = <0 0x17c27000 0 0x1000>; 3479 status = "disabled"; 3480 }; 3481 3482 frame@17c29000 { 3483 frame-number = <4>; 3484 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3485 reg = <0 0x17c29000 0 0x1000>; 3486 status = "disabled"; 3487 }; 3488 3489 frame@17c2b000 { 3490 frame-number = <5>; 3491 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3492 reg = <0 0x17c2b000 0 0x1000>; 3493 status = "disabled"; 3494 }; 3495 3496 frame@17c2d000 { 3497 frame-number = <6>; 3498 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3499 reg = <0 0x17c2d000 0 0x1000>; 3500 status = "disabled"; 3501 }; 3502 }; 3503 3504 apps_rsc: rsc@18200000 { 3505 compatible = "qcom,rpmh-rsc"; 3506 reg = <0 0x18200000 0 0x10000>, 3507 <0 0x18210000 0 0x10000>, 3508 <0 0x18220000 0 0x10000>; 3509 reg-names = "drv-0", "drv-1", "drv-2"; 3510 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3511 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3512 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3513 qcom,tcs-offset = <0xd00>; 3514 qcom,drv-id = <2>; 3515 qcom,tcs-config = <ACTIVE_TCS 2>, 3516 <SLEEP_TCS 3>, 3517 <WAKE_TCS 3>, 3518 <CONTROL_TCS 1>; 3519 3520 apps_bcm_voter: bcm-voter { 3521 compatible = "qcom,bcm-voter"; 3522 }; 3523 3524 rpmhpd: power-controller { 3525 compatible = "qcom,sc7280-rpmhpd"; 3526 #power-domain-cells = <1>; 3527 operating-points-v2 = <&rpmhpd_opp_table>; 3528 3529 rpmhpd_opp_table: opp-table { 3530 compatible = "operating-points-v2"; 3531 3532 rpmhpd_opp_ret: opp1 { 3533 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3534 }; 3535 3536 rpmhpd_opp_low_svs: opp2 { 3537 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3538 }; 3539 3540 rpmhpd_opp_svs: opp3 { 3541 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3542 }; 3543 3544 rpmhpd_opp_svs_l1: opp4 { 3545 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3546 }; 3547 3548 rpmhpd_opp_svs_l2: opp5 { 3549 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3550 }; 3551 3552 rpmhpd_opp_nom: opp6 { 3553 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3554 }; 3555 3556 rpmhpd_opp_nom_l1: opp7 { 3557 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3558 }; 3559 3560 rpmhpd_opp_turbo: opp8 { 3561 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3562 }; 3563 3564 rpmhpd_opp_turbo_l1: opp9 { 3565 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3566 }; 3567 }; 3568 }; 3569 3570 rpmhcc: clock-controller { 3571 compatible = "qcom,sc7280-rpmh-clk"; 3572 clocks = <&xo_board>; 3573 clock-names = "xo"; 3574 #clock-cells = <1>; 3575 }; 3576 }; 3577 3578 cpufreq_hw: cpufreq@18591000 { 3579 compatible = "qcom,cpufreq-epss"; 3580 reg = <0 0x18591100 0 0x900>, 3581 <0 0x18592100 0 0x900>, 3582 <0 0x18593100 0 0x900>; 3583 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3584 clock-names = "xo", "alternate"; 3585 #freq-domain-cells = <1>; 3586 }; 3587 }; 3588 3589 thermal_zones: thermal-zones { 3590 cpu0-thermal { 3591 polling-delay-passive = <250>; 3592 polling-delay = <0>; 3593 3594 thermal-sensors = <&tsens0 1>; 3595 3596 trips { 3597 cpu0_alert0: trip-point0 { 3598 temperature = <90000>; 3599 hysteresis = <2000>; 3600 type = "passive"; 3601 }; 3602 3603 cpu0_alert1: trip-point1 { 3604 temperature = <95000>; 3605 hysteresis = <2000>; 3606 type = "passive"; 3607 }; 3608 3609 cpu0_crit: cpu-crit { 3610 temperature = <110000>; 3611 hysteresis = <0>; 3612 type = "critical"; 3613 }; 3614 }; 3615 3616 cooling-maps { 3617 map0 { 3618 trip = <&cpu0_alert0>; 3619 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3620 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3621 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3622 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3623 }; 3624 map1 { 3625 trip = <&cpu0_alert1>; 3626 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3627 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3628 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3629 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3630 }; 3631 }; 3632 }; 3633 3634 cpu1-thermal { 3635 polling-delay-passive = <250>; 3636 polling-delay = <0>; 3637 3638 thermal-sensors = <&tsens0 2>; 3639 3640 trips { 3641 cpu1_alert0: trip-point0 { 3642 temperature = <90000>; 3643 hysteresis = <2000>; 3644 type = "passive"; 3645 }; 3646 3647 cpu1_alert1: trip-point1 { 3648 temperature = <95000>; 3649 hysteresis = <2000>; 3650 type = "passive"; 3651 }; 3652 3653 cpu1_crit: cpu-crit { 3654 temperature = <110000>; 3655 hysteresis = <0>; 3656 type = "critical"; 3657 }; 3658 }; 3659 3660 cooling-maps { 3661 map0 { 3662 trip = <&cpu1_alert0>; 3663 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3664 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3665 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3666 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3667 }; 3668 map1 { 3669 trip = <&cpu1_alert1>; 3670 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3671 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3672 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3673 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3674 }; 3675 }; 3676 }; 3677 3678 cpu2-thermal { 3679 polling-delay-passive = <250>; 3680 polling-delay = <0>; 3681 3682 thermal-sensors = <&tsens0 3>; 3683 3684 trips { 3685 cpu2_alert0: trip-point0 { 3686 temperature = <90000>; 3687 hysteresis = <2000>; 3688 type = "passive"; 3689 }; 3690 3691 cpu2_alert1: trip-point1 { 3692 temperature = <95000>; 3693 hysteresis = <2000>; 3694 type = "passive"; 3695 }; 3696 3697 cpu2_crit: cpu-crit { 3698 temperature = <110000>; 3699 hysteresis = <0>; 3700 type = "critical"; 3701 }; 3702 }; 3703 3704 cooling-maps { 3705 map0 { 3706 trip = <&cpu2_alert0>; 3707 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3708 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3709 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3710 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3711 }; 3712 map1 { 3713 trip = <&cpu2_alert1>; 3714 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3715 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3716 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3717 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3718 }; 3719 }; 3720 }; 3721 3722 cpu3-thermal { 3723 polling-delay-passive = <250>; 3724 polling-delay = <0>; 3725 3726 thermal-sensors = <&tsens0 4>; 3727 3728 trips { 3729 cpu3_alert0: trip-point0 { 3730 temperature = <90000>; 3731 hysteresis = <2000>; 3732 type = "passive"; 3733 }; 3734 3735 cpu3_alert1: trip-point1 { 3736 temperature = <95000>; 3737 hysteresis = <2000>; 3738 type = "passive"; 3739 }; 3740 3741 cpu3_crit: cpu-crit { 3742 temperature = <110000>; 3743 hysteresis = <0>; 3744 type = "critical"; 3745 }; 3746 }; 3747 3748 cooling-maps { 3749 map0 { 3750 trip = <&cpu3_alert0>; 3751 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3752 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3753 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3754 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3755 }; 3756 map1 { 3757 trip = <&cpu3_alert1>; 3758 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3759 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3760 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3761 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3762 }; 3763 }; 3764 }; 3765 3766 cpu4-thermal { 3767 polling-delay-passive = <250>; 3768 polling-delay = <0>; 3769 3770 thermal-sensors = <&tsens0 7>; 3771 3772 trips { 3773 cpu4_alert0: trip-point0 { 3774 temperature = <90000>; 3775 hysteresis = <2000>; 3776 type = "passive"; 3777 }; 3778 3779 cpu4_alert1: trip-point1 { 3780 temperature = <95000>; 3781 hysteresis = <2000>; 3782 type = "passive"; 3783 }; 3784 3785 cpu4_crit: cpu-crit { 3786 temperature = <110000>; 3787 hysteresis = <0>; 3788 type = "critical"; 3789 }; 3790 }; 3791 3792 cooling-maps { 3793 map0 { 3794 trip = <&cpu4_alert0>; 3795 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3796 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3797 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3798 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3799 }; 3800 map1 { 3801 trip = <&cpu4_alert1>; 3802 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3803 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3804 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3805 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3806 }; 3807 }; 3808 }; 3809 3810 cpu5-thermal { 3811 polling-delay-passive = <250>; 3812 polling-delay = <0>; 3813 3814 thermal-sensors = <&tsens0 8>; 3815 3816 trips { 3817 cpu5_alert0: trip-point0 { 3818 temperature = <90000>; 3819 hysteresis = <2000>; 3820 type = "passive"; 3821 }; 3822 3823 cpu5_alert1: trip-point1 { 3824 temperature = <95000>; 3825 hysteresis = <2000>; 3826 type = "passive"; 3827 }; 3828 3829 cpu5_crit: cpu-crit { 3830 temperature = <110000>; 3831 hysteresis = <0>; 3832 type = "critical"; 3833 }; 3834 }; 3835 3836 cooling-maps { 3837 map0 { 3838 trip = <&cpu5_alert0>; 3839 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3840 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3841 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3842 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3843 }; 3844 map1 { 3845 trip = <&cpu5_alert1>; 3846 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3847 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3848 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3849 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3850 }; 3851 }; 3852 }; 3853 3854 cpu6-thermal { 3855 polling-delay-passive = <250>; 3856 polling-delay = <0>; 3857 3858 thermal-sensors = <&tsens0 9>; 3859 3860 trips { 3861 cpu6_alert0: trip-point0 { 3862 temperature = <90000>; 3863 hysteresis = <2000>; 3864 type = "passive"; 3865 }; 3866 3867 cpu6_alert1: trip-point1 { 3868 temperature = <95000>; 3869 hysteresis = <2000>; 3870 type = "passive"; 3871 }; 3872 3873 cpu6_crit: cpu-crit { 3874 temperature = <110000>; 3875 hysteresis = <0>; 3876 type = "critical"; 3877 }; 3878 }; 3879 3880 cooling-maps { 3881 map0 { 3882 trip = <&cpu6_alert0>; 3883 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3884 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3885 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3886 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3887 }; 3888 map1 { 3889 trip = <&cpu6_alert1>; 3890 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3891 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3892 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3893 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3894 }; 3895 }; 3896 }; 3897 3898 cpu7-thermal { 3899 polling-delay-passive = <250>; 3900 polling-delay = <0>; 3901 3902 thermal-sensors = <&tsens0 10>; 3903 3904 trips { 3905 cpu7_alert0: trip-point0 { 3906 temperature = <90000>; 3907 hysteresis = <2000>; 3908 type = "passive"; 3909 }; 3910 3911 cpu7_alert1: trip-point1 { 3912 temperature = <95000>; 3913 hysteresis = <2000>; 3914 type = "passive"; 3915 }; 3916 3917 cpu7_crit: cpu-crit { 3918 temperature = <110000>; 3919 hysteresis = <0>; 3920 type = "critical"; 3921 }; 3922 }; 3923 3924 cooling-maps { 3925 map0 { 3926 trip = <&cpu7_alert0>; 3927 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3928 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3929 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3930 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3931 }; 3932 map1 { 3933 trip = <&cpu7_alert1>; 3934 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3935 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3936 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3937 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3938 }; 3939 }; 3940 }; 3941 3942 cpu8-thermal { 3943 polling-delay-passive = <250>; 3944 polling-delay = <0>; 3945 3946 thermal-sensors = <&tsens0 11>; 3947 3948 trips { 3949 cpu8_alert0: trip-point0 { 3950 temperature = <90000>; 3951 hysteresis = <2000>; 3952 type = "passive"; 3953 }; 3954 3955 cpu8_alert1: trip-point1 { 3956 temperature = <95000>; 3957 hysteresis = <2000>; 3958 type = "passive"; 3959 }; 3960 3961 cpu8_crit: cpu-crit { 3962 temperature = <110000>; 3963 hysteresis = <0>; 3964 type = "critical"; 3965 }; 3966 }; 3967 3968 cooling-maps { 3969 map0 { 3970 trip = <&cpu8_alert0>; 3971 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3972 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3973 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3974 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3975 }; 3976 map1 { 3977 trip = <&cpu8_alert1>; 3978 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3979 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3980 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3981 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3982 }; 3983 }; 3984 }; 3985 3986 cpu9-thermal { 3987 polling-delay-passive = <250>; 3988 polling-delay = <0>; 3989 3990 thermal-sensors = <&tsens0 12>; 3991 3992 trips { 3993 cpu9_alert0: trip-point0 { 3994 temperature = <90000>; 3995 hysteresis = <2000>; 3996 type = "passive"; 3997 }; 3998 3999 cpu9_alert1: trip-point1 { 4000 temperature = <95000>; 4001 hysteresis = <2000>; 4002 type = "passive"; 4003 }; 4004 4005 cpu9_crit: cpu-crit { 4006 temperature = <110000>; 4007 hysteresis = <0>; 4008 type = "critical"; 4009 }; 4010 }; 4011 4012 cooling-maps { 4013 map0 { 4014 trip = <&cpu9_alert0>; 4015 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4016 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4017 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4018 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4019 }; 4020 map1 { 4021 trip = <&cpu9_alert1>; 4022 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4023 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4024 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4025 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4026 }; 4027 }; 4028 }; 4029 4030 cpu10-thermal { 4031 polling-delay-passive = <250>; 4032 polling-delay = <0>; 4033 4034 thermal-sensors = <&tsens0 13>; 4035 4036 trips { 4037 cpu10_alert0: trip-point0 { 4038 temperature = <90000>; 4039 hysteresis = <2000>; 4040 type = "passive"; 4041 }; 4042 4043 cpu10_alert1: trip-point1 { 4044 temperature = <95000>; 4045 hysteresis = <2000>; 4046 type = "passive"; 4047 }; 4048 4049 cpu10_crit: cpu-crit { 4050 temperature = <110000>; 4051 hysteresis = <0>; 4052 type = "critical"; 4053 }; 4054 }; 4055 4056 cooling-maps { 4057 map0 { 4058 trip = <&cpu10_alert0>; 4059 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4060 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4061 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4062 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4063 }; 4064 map1 { 4065 trip = <&cpu10_alert1>; 4066 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4067 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4068 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4069 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4070 }; 4071 }; 4072 }; 4073 4074 cpu11-thermal { 4075 polling-delay-passive = <250>; 4076 polling-delay = <0>; 4077 4078 thermal-sensors = <&tsens0 14>; 4079 4080 trips { 4081 cpu11_alert0: trip-point0 { 4082 temperature = <90000>; 4083 hysteresis = <2000>; 4084 type = "passive"; 4085 }; 4086 4087 cpu11_alert1: trip-point1 { 4088 temperature = <95000>; 4089 hysteresis = <2000>; 4090 type = "passive"; 4091 }; 4092 4093 cpu11_crit: cpu-crit { 4094 temperature = <110000>; 4095 hysteresis = <0>; 4096 type = "critical"; 4097 }; 4098 }; 4099 4100 cooling-maps { 4101 map0 { 4102 trip = <&cpu11_alert0>; 4103 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4104 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4105 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4106 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4107 }; 4108 map1 { 4109 trip = <&cpu11_alert1>; 4110 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4111 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4112 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4113 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4114 }; 4115 }; 4116 }; 4117 4118 aoss0-thermal { 4119 polling-delay-passive = <0>; 4120 polling-delay = <0>; 4121 4122 thermal-sensors = <&tsens0 0>; 4123 4124 trips { 4125 aoss0_alert0: trip-point0 { 4126 temperature = <90000>; 4127 hysteresis = <2000>; 4128 type = "hot"; 4129 }; 4130 4131 aoss0_crit: aoss0-crit { 4132 temperature = <110000>; 4133 hysteresis = <0>; 4134 type = "critical"; 4135 }; 4136 }; 4137 }; 4138 4139 aoss1-thermal { 4140 polling-delay-passive = <0>; 4141 polling-delay = <0>; 4142 4143 thermal-sensors = <&tsens1 0>; 4144 4145 trips { 4146 aoss1_alert0: trip-point0 { 4147 temperature = <90000>; 4148 hysteresis = <2000>; 4149 type = "hot"; 4150 }; 4151 4152 aoss1_crit: aoss1-crit { 4153 temperature = <110000>; 4154 hysteresis = <0>; 4155 type = "critical"; 4156 }; 4157 }; 4158 }; 4159 4160 cpuss0-thermal { 4161 polling-delay-passive = <0>; 4162 polling-delay = <0>; 4163 4164 thermal-sensors = <&tsens0 5>; 4165 4166 trips { 4167 cpuss0_alert0: trip-point0 { 4168 temperature = <90000>; 4169 hysteresis = <2000>; 4170 type = "hot"; 4171 }; 4172 cpuss0_crit: cluster0-crit { 4173 temperature = <110000>; 4174 hysteresis = <0>; 4175 type = "critical"; 4176 }; 4177 }; 4178 }; 4179 4180 cpuss1-thermal { 4181 polling-delay-passive = <0>; 4182 polling-delay = <0>; 4183 4184 thermal-sensors = <&tsens0 6>; 4185 4186 trips { 4187 cpuss1_alert0: trip-point0 { 4188 temperature = <90000>; 4189 hysteresis = <2000>; 4190 type = "hot"; 4191 }; 4192 cpuss1_crit: cluster0-crit { 4193 temperature = <110000>; 4194 hysteresis = <0>; 4195 type = "critical"; 4196 }; 4197 }; 4198 }; 4199 4200 gpuss0-thermal { 4201 polling-delay-passive = <100>; 4202 polling-delay = <0>; 4203 4204 thermal-sensors = <&tsens1 1>; 4205 4206 trips { 4207 gpuss0_alert0: trip-point0 { 4208 temperature = <95000>; 4209 hysteresis = <2000>; 4210 type = "passive"; 4211 }; 4212 4213 gpuss0_crit: gpuss0-crit { 4214 temperature = <110000>; 4215 hysteresis = <0>; 4216 type = "critical"; 4217 }; 4218 }; 4219 4220 cooling-maps { 4221 map0 { 4222 trip = <&gpuss0_alert0>; 4223 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4224 }; 4225 }; 4226 }; 4227 4228 gpuss1-thermal { 4229 polling-delay-passive = <100>; 4230 polling-delay = <0>; 4231 4232 thermal-sensors = <&tsens1 2>; 4233 4234 trips { 4235 gpuss1_alert0: trip-point0 { 4236 temperature = <95000>; 4237 hysteresis = <2000>; 4238 type = "passive"; 4239 }; 4240 4241 gpuss1_crit: gpuss1-crit { 4242 temperature = <110000>; 4243 hysteresis = <0>; 4244 type = "critical"; 4245 }; 4246 }; 4247 4248 cooling-maps { 4249 map0 { 4250 trip = <&gpuss1_alert0>; 4251 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4252 }; 4253 }; 4254 }; 4255 4256 nspss0-thermal { 4257 polling-delay-passive = <0>; 4258 polling-delay = <0>; 4259 4260 thermal-sensors = <&tsens1 3>; 4261 4262 trips { 4263 nspss0_alert0: trip-point0 { 4264 temperature = <90000>; 4265 hysteresis = <2000>; 4266 type = "hot"; 4267 }; 4268 4269 nspss0_crit: nspss0-crit { 4270 temperature = <110000>; 4271 hysteresis = <0>; 4272 type = "critical"; 4273 }; 4274 }; 4275 }; 4276 4277 nspss1-thermal { 4278 polling-delay-passive = <0>; 4279 polling-delay = <0>; 4280 4281 thermal-sensors = <&tsens1 4>; 4282 4283 trips { 4284 nspss1_alert0: trip-point0 { 4285 temperature = <90000>; 4286 hysteresis = <2000>; 4287 type = "hot"; 4288 }; 4289 4290 nspss1_crit: nspss1-crit { 4291 temperature = <110000>; 4292 hysteresis = <0>; 4293 type = "critical"; 4294 }; 4295 }; 4296 }; 4297 4298 video-thermal { 4299 polling-delay-passive = <0>; 4300 polling-delay = <0>; 4301 4302 thermal-sensors = <&tsens1 5>; 4303 4304 trips { 4305 video_alert0: trip-point0 { 4306 temperature = <90000>; 4307 hysteresis = <2000>; 4308 type = "hot"; 4309 }; 4310 4311 video_crit: video-crit { 4312 temperature = <110000>; 4313 hysteresis = <0>; 4314 type = "critical"; 4315 }; 4316 }; 4317 }; 4318 4319 ddr-thermal { 4320 polling-delay-passive = <0>; 4321 polling-delay = <0>; 4322 4323 thermal-sensors = <&tsens1 6>; 4324 4325 trips { 4326 ddr_alert0: trip-point0 { 4327 temperature = <90000>; 4328 hysteresis = <2000>; 4329 type = "hot"; 4330 }; 4331 4332 ddr_crit: ddr-crit { 4333 temperature = <110000>; 4334 hysteresis = <0>; 4335 type = "critical"; 4336 }; 4337 }; 4338 }; 4339 4340 mdmss0-thermal { 4341 polling-delay-passive = <0>; 4342 polling-delay = <0>; 4343 4344 thermal-sensors = <&tsens1 7>; 4345 4346 trips { 4347 mdmss0_alert0: trip-point0 { 4348 temperature = <90000>; 4349 hysteresis = <2000>; 4350 type = "hot"; 4351 }; 4352 4353 mdmss0_crit: mdmss0-crit { 4354 temperature = <110000>; 4355 hysteresis = <0>; 4356 type = "critical"; 4357 }; 4358 }; 4359 }; 4360 4361 mdmss1-thermal { 4362 polling-delay-passive = <0>; 4363 polling-delay = <0>; 4364 4365 thermal-sensors = <&tsens1 8>; 4366 4367 trips { 4368 mdmss1_alert0: trip-point0 { 4369 temperature = <90000>; 4370 hysteresis = <2000>; 4371 type = "hot"; 4372 }; 4373 4374 mdmss1_crit: mdmss1-crit { 4375 temperature = <110000>; 4376 hysteresis = <0>; 4377 type = "critical"; 4378 }; 4379 }; 4380 }; 4381 4382 mdmss2-thermal { 4383 polling-delay-passive = <0>; 4384 polling-delay = <0>; 4385 4386 thermal-sensors = <&tsens1 9>; 4387 4388 trips { 4389 mdmss2_alert0: trip-point0 { 4390 temperature = <90000>; 4391 hysteresis = <2000>; 4392 type = "hot"; 4393 }; 4394 4395 mdmss2_crit: mdmss2-crit { 4396 temperature = <110000>; 4397 hysteresis = <0>; 4398 type = "critical"; 4399 }; 4400 }; 4401 }; 4402 4403 mdmss3-thermal { 4404 polling-delay-passive = <0>; 4405 polling-delay = <0>; 4406 4407 thermal-sensors = <&tsens1 10>; 4408 4409 trips { 4410 mdmss3_alert0: trip-point0 { 4411 temperature = <90000>; 4412 hysteresis = <2000>; 4413 type = "hot"; 4414 }; 4415 4416 mdmss3_crit: mdmss3-crit { 4417 temperature = <110000>; 4418 hysteresis = <0>; 4419 type = "critical"; 4420 }; 4421 }; 4422 }; 4423 4424 camera0-thermal { 4425 polling-delay-passive = <0>; 4426 polling-delay = <0>; 4427 4428 thermal-sensors = <&tsens1 11>; 4429 4430 trips { 4431 camera0_alert0: trip-point0 { 4432 temperature = <90000>; 4433 hysteresis = <2000>; 4434 type = "hot"; 4435 }; 4436 4437 camera0_crit: camera0-crit { 4438 temperature = <110000>; 4439 hysteresis = <0>; 4440 type = "critical"; 4441 }; 4442 }; 4443 }; 4444 }; 4445 4446 timer { 4447 compatible = "arm,armv8-timer"; 4448 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 4449 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 4450 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 4451 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 4452 }; 4453}; 4454