1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,lpass.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 mmc1 = &sdhc_1; 54 mmc2 = &sdhc_2; 55 spi0 = &spi0; 56 spi1 = &spi1; 57 spi2 = &spi2; 58 spi3 = &spi3; 59 spi4 = &spi4; 60 spi5 = &spi5; 61 spi6 = &spi6; 62 spi7 = &spi7; 63 spi8 = &spi8; 64 spi9 = &spi9; 65 spi10 = &spi10; 66 spi11 = &spi11; 67 spi12 = &spi12; 68 spi13 = &spi13; 69 spi14 = &spi14; 70 spi15 = &spi15; 71 }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 clock-frequency = <76800000>; 77 #clock-cells = <0>; 78 }; 79 80 sleep_clk: sleep-clk { 81 compatible = "fixed-clock"; 82 clock-frequency = <32000>; 83 #clock-cells = <0>; 84 }; 85 }; 86 87 reserved-memory { 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges; 91 92 wlan_ce_mem: memory@4cd000 { 93 no-map; 94 reg = <0x0 0x004cd000 0x0 0x1000>; 95 }; 96 97 hyp_mem: memory@80000000 { 98 reg = <0x0 0x80000000 0x0 0x600000>; 99 no-map; 100 }; 101 102 xbl_mem: memory@80600000 { 103 reg = <0x0 0x80600000 0x0 0x200000>; 104 no-map; 105 }; 106 107 aop_mem: memory@80800000 { 108 reg = <0x0 0x80800000 0x0 0x60000>; 109 no-map; 110 }; 111 112 aop_cmd_db_mem: memory@80860000 { 113 reg = <0x0 0x80860000 0x0 0x20000>; 114 compatible = "qcom,cmd-db"; 115 no-map; 116 }; 117 118 reserved_xbl_uefi_log: memory@80880000 { 119 reg = <0x0 0x80884000 0x0 0x10000>; 120 no-map; 121 }; 122 123 sec_apps_mem: memory@808ff000 { 124 reg = <0x0 0x808ff000 0x0 0x1000>; 125 no-map; 126 }; 127 128 smem_mem: memory@80900000 { 129 reg = <0x0 0x80900000 0x0 0x200000>; 130 no-map; 131 }; 132 133 cpucp_mem: memory@80b00000 { 134 no-map; 135 reg = <0x0 0x80b00000 0x0 0x100000>; 136 }; 137 138 wlan_fw_mem: memory@80c00000 { 139 reg = <0x0 0x80c00000 0x0 0xc00000>; 140 no-map; 141 }; 142 143 video_mem: memory@8b200000 { 144 reg = <0x0 0x8b200000 0x0 0x500000>; 145 no-map; 146 }; 147 148 ipa_fw_mem: memory@8b700000 { 149 reg = <0 0x8b700000 0 0x10000>; 150 no-map; 151 }; 152 153 rmtfs_mem: memory@9c900000 { 154 compatible = "qcom,rmtfs-mem"; 155 reg = <0x0 0x9c900000 0x0 0x280000>; 156 no-map; 157 158 qcom,client-id = <1>; 159 qcom,vmid = <15>; 160 }; 161 }; 162 163 cpus { 164 #address-cells = <2>; 165 #size-cells = <0>; 166 167 CPU0: cpu@0 { 168 device_type = "cpu"; 169 compatible = "qcom,kryo"; 170 reg = <0x0 0x0>; 171 clocks = <&cpufreq_hw 0>; 172 enable-method = "psci"; 173 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 174 &LITTLE_CPU_SLEEP_1 175 &CLUSTER_SLEEP_0>; 176 next-level-cache = <&L2_0>; 177 operating-points-v2 = <&cpu0_opp_table>; 178 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 179 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 180 qcom,freq-domain = <&cpufreq_hw 0>; 181 #cooling-cells = <2>; 182 L2_0: l2-cache { 183 compatible = "cache"; 184 cache-level = <2>; 185 next-level-cache = <&L3_0>; 186 L3_0: l3-cache { 187 compatible = "cache"; 188 cache-level = <3>; 189 }; 190 }; 191 }; 192 193 CPU1: cpu@100 { 194 device_type = "cpu"; 195 compatible = "qcom,kryo"; 196 reg = <0x0 0x100>; 197 clocks = <&cpufreq_hw 0>; 198 enable-method = "psci"; 199 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 200 &LITTLE_CPU_SLEEP_1 201 &CLUSTER_SLEEP_0>; 202 next-level-cache = <&L2_100>; 203 operating-points-v2 = <&cpu0_opp_table>; 204 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 205 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 206 qcom,freq-domain = <&cpufreq_hw 0>; 207 #cooling-cells = <2>; 208 L2_100: l2-cache { 209 compatible = "cache"; 210 cache-level = <2>; 211 next-level-cache = <&L3_0>; 212 }; 213 }; 214 215 CPU2: cpu@200 { 216 device_type = "cpu"; 217 compatible = "qcom,kryo"; 218 reg = <0x0 0x200>; 219 clocks = <&cpufreq_hw 0>; 220 enable-method = "psci"; 221 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 222 &LITTLE_CPU_SLEEP_1 223 &CLUSTER_SLEEP_0>; 224 next-level-cache = <&L2_200>; 225 operating-points-v2 = <&cpu0_opp_table>; 226 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 227 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 228 qcom,freq-domain = <&cpufreq_hw 0>; 229 #cooling-cells = <2>; 230 L2_200: l2-cache { 231 compatible = "cache"; 232 cache-level = <2>; 233 next-level-cache = <&L3_0>; 234 }; 235 }; 236 237 CPU3: cpu@300 { 238 device_type = "cpu"; 239 compatible = "qcom,kryo"; 240 reg = <0x0 0x300>; 241 clocks = <&cpufreq_hw 0>; 242 enable-method = "psci"; 243 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 244 &LITTLE_CPU_SLEEP_1 245 &CLUSTER_SLEEP_0>; 246 next-level-cache = <&L2_300>; 247 operating-points-v2 = <&cpu0_opp_table>; 248 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 249 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 250 qcom,freq-domain = <&cpufreq_hw 0>; 251 #cooling-cells = <2>; 252 L2_300: l2-cache { 253 compatible = "cache"; 254 cache-level = <2>; 255 next-level-cache = <&L3_0>; 256 }; 257 }; 258 259 CPU4: cpu@400 { 260 device_type = "cpu"; 261 compatible = "qcom,kryo"; 262 reg = <0x0 0x400>; 263 clocks = <&cpufreq_hw 1>; 264 enable-method = "psci"; 265 cpu-idle-states = <&BIG_CPU_SLEEP_0 266 &BIG_CPU_SLEEP_1 267 &CLUSTER_SLEEP_0>; 268 next-level-cache = <&L2_400>; 269 operating-points-v2 = <&cpu4_opp_table>; 270 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 271 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 272 qcom,freq-domain = <&cpufreq_hw 1>; 273 #cooling-cells = <2>; 274 L2_400: l2-cache { 275 compatible = "cache"; 276 cache-level = <2>; 277 next-level-cache = <&L3_0>; 278 }; 279 }; 280 281 CPU5: cpu@500 { 282 device_type = "cpu"; 283 compatible = "qcom,kryo"; 284 reg = <0x0 0x500>; 285 clocks = <&cpufreq_hw 1>; 286 enable-method = "psci"; 287 cpu-idle-states = <&BIG_CPU_SLEEP_0 288 &BIG_CPU_SLEEP_1 289 &CLUSTER_SLEEP_0>; 290 next-level-cache = <&L2_500>; 291 operating-points-v2 = <&cpu4_opp_table>; 292 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 293 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 294 qcom,freq-domain = <&cpufreq_hw 1>; 295 #cooling-cells = <2>; 296 L2_500: l2-cache { 297 compatible = "cache"; 298 cache-level = <2>; 299 next-level-cache = <&L3_0>; 300 }; 301 }; 302 303 CPU6: cpu@600 { 304 device_type = "cpu"; 305 compatible = "qcom,kryo"; 306 reg = <0x0 0x600>; 307 clocks = <&cpufreq_hw 1>; 308 enable-method = "psci"; 309 cpu-idle-states = <&BIG_CPU_SLEEP_0 310 &BIG_CPU_SLEEP_1 311 &CLUSTER_SLEEP_0>; 312 next-level-cache = <&L2_600>; 313 operating-points-v2 = <&cpu4_opp_table>; 314 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 315 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 316 qcom,freq-domain = <&cpufreq_hw 1>; 317 #cooling-cells = <2>; 318 L2_600: l2-cache { 319 compatible = "cache"; 320 cache-level = <2>; 321 next-level-cache = <&L3_0>; 322 }; 323 }; 324 325 CPU7: cpu@700 { 326 device_type = "cpu"; 327 compatible = "qcom,kryo"; 328 reg = <0x0 0x700>; 329 clocks = <&cpufreq_hw 2>; 330 enable-method = "psci"; 331 cpu-idle-states = <&BIG_CPU_SLEEP_0 332 &BIG_CPU_SLEEP_1 333 &CLUSTER_SLEEP_0>; 334 next-level-cache = <&L2_700>; 335 operating-points-v2 = <&cpu7_opp_table>; 336 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 337 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 338 qcom,freq-domain = <&cpufreq_hw 2>; 339 #cooling-cells = <2>; 340 L2_700: l2-cache { 341 compatible = "cache"; 342 cache-level = <2>; 343 next-level-cache = <&L3_0>; 344 }; 345 }; 346 347 cpu-map { 348 cluster0 { 349 core0 { 350 cpu = <&CPU0>; 351 }; 352 353 core1 { 354 cpu = <&CPU1>; 355 }; 356 357 core2 { 358 cpu = <&CPU2>; 359 }; 360 361 core3 { 362 cpu = <&CPU3>; 363 }; 364 365 core4 { 366 cpu = <&CPU4>; 367 }; 368 369 core5 { 370 cpu = <&CPU5>; 371 }; 372 373 core6 { 374 cpu = <&CPU6>; 375 }; 376 377 core7 { 378 cpu = <&CPU7>; 379 }; 380 }; 381 }; 382 383 idle-states { 384 entry-method = "psci"; 385 386 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 387 compatible = "arm,idle-state"; 388 idle-state-name = "little-power-down"; 389 arm,psci-suspend-param = <0x40000003>; 390 entry-latency-us = <549>; 391 exit-latency-us = <901>; 392 min-residency-us = <1774>; 393 local-timer-stop; 394 }; 395 396 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 397 compatible = "arm,idle-state"; 398 idle-state-name = "little-rail-power-down"; 399 arm,psci-suspend-param = <0x40000004>; 400 entry-latency-us = <702>; 401 exit-latency-us = <915>; 402 min-residency-us = <4001>; 403 local-timer-stop; 404 }; 405 406 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 407 compatible = "arm,idle-state"; 408 idle-state-name = "big-power-down"; 409 arm,psci-suspend-param = <0x40000003>; 410 entry-latency-us = <523>; 411 exit-latency-us = <1244>; 412 min-residency-us = <2207>; 413 local-timer-stop; 414 }; 415 416 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 417 compatible = "arm,idle-state"; 418 idle-state-name = "big-rail-power-down"; 419 arm,psci-suspend-param = <0x40000004>; 420 entry-latency-us = <526>; 421 exit-latency-us = <1854>; 422 min-residency-us = <5555>; 423 local-timer-stop; 424 }; 425 426 CLUSTER_SLEEP_0: cluster-sleep-0 { 427 compatible = "arm,idle-state"; 428 idle-state-name = "cluster-power-down"; 429 arm,psci-suspend-param = <0x40003444>; 430 entry-latency-us = <3263>; 431 exit-latency-us = <6562>; 432 min-residency-us = <9926>; 433 local-timer-stop; 434 }; 435 }; 436 }; 437 438 cpu0_opp_table: opp-table-cpu0 { 439 compatible = "operating-points-v2"; 440 opp-shared; 441 442 cpu0_opp_300mhz: opp-300000000 { 443 opp-hz = /bits/ 64 <300000000>; 444 opp-peak-kBps = <800000 9600000>; 445 }; 446 447 cpu0_opp_691mhz: opp-691200000 { 448 opp-hz = /bits/ 64 <691200000>; 449 opp-peak-kBps = <800000 17817600>; 450 }; 451 452 cpu0_opp_806mhz: opp-806400000 { 453 opp-hz = /bits/ 64 <806400000>; 454 opp-peak-kBps = <800000 20889600>; 455 }; 456 457 cpu0_opp_941mhz: opp-940800000 { 458 opp-hz = /bits/ 64 <940800000>; 459 opp-peak-kBps = <1804000 24576000>; 460 }; 461 462 cpu0_opp_1152mhz: opp-1152000000 { 463 opp-hz = /bits/ 64 <1152000000>; 464 opp-peak-kBps = <2188000 27033600>; 465 }; 466 467 cpu0_opp_1325mhz: opp-1324800000 { 468 opp-hz = /bits/ 64 <1324800000>; 469 opp-peak-kBps = <2188000 33792000>; 470 }; 471 472 cpu0_opp_1517mhz: opp-1516800000 { 473 opp-hz = /bits/ 64 <1516800000>; 474 opp-peak-kBps = <3072000 38092800>; 475 }; 476 477 cpu0_opp_1651mhz: opp-1651200000 { 478 opp-hz = /bits/ 64 <1651200000>; 479 opp-peak-kBps = <3072000 41779200>; 480 }; 481 482 cpu0_opp_1805mhz: opp-1804800000 { 483 opp-hz = /bits/ 64 <1804800000>; 484 opp-peak-kBps = <4068000 48537600>; 485 }; 486 487 cpu0_opp_1958mhz: opp-1958400000 { 488 opp-hz = /bits/ 64 <1958400000>; 489 opp-peak-kBps = <4068000 48537600>; 490 }; 491 492 cpu0_opp_2016mhz: opp-2016000000 { 493 opp-hz = /bits/ 64 <2016000000>; 494 opp-peak-kBps = <6220000 48537600>; 495 }; 496 }; 497 498 cpu4_opp_table: opp-table-cpu4 { 499 compatible = "operating-points-v2"; 500 opp-shared; 501 502 cpu4_opp_691mhz: opp-691200000 { 503 opp-hz = /bits/ 64 <691200000>; 504 opp-peak-kBps = <1804000 9600000>; 505 }; 506 507 cpu4_opp_941mhz: opp-940800000 { 508 opp-hz = /bits/ 64 <940800000>; 509 opp-peak-kBps = <2188000 17817600>; 510 }; 511 512 cpu4_opp_1229mhz: opp-1228800000 { 513 opp-hz = /bits/ 64 <1228800000>; 514 opp-peak-kBps = <4068000 24576000>; 515 }; 516 517 cpu4_opp_1344mhz: opp-1344000000 { 518 opp-hz = /bits/ 64 <1344000000>; 519 opp-peak-kBps = <4068000 24576000>; 520 }; 521 522 cpu4_opp_1517mhz: opp-1516800000 { 523 opp-hz = /bits/ 64 <1516800000>; 524 opp-peak-kBps = <4068000 24576000>; 525 }; 526 527 cpu4_opp_1651mhz: opp-1651200000 { 528 opp-hz = /bits/ 64 <1651200000>; 529 opp-peak-kBps = <6220000 38092800>; 530 }; 531 532 cpu4_opp_1901mhz: opp-1900800000 { 533 opp-hz = /bits/ 64 <1900800000>; 534 opp-peak-kBps = <6220000 44851200>; 535 }; 536 537 cpu4_opp_2054mhz: opp-2054400000 { 538 opp-hz = /bits/ 64 <2054400000>; 539 opp-peak-kBps = <6220000 44851200>; 540 }; 541 542 cpu4_opp_2112mhz: opp-2112000000 { 543 opp-hz = /bits/ 64 <2112000000>; 544 opp-peak-kBps = <6220000 44851200>; 545 }; 546 547 cpu4_opp_2131mhz: opp-2131200000 { 548 opp-hz = /bits/ 64 <2131200000>; 549 opp-peak-kBps = <6220000 44851200>; 550 }; 551 552 cpu4_opp_2208mhz: opp-2208000000 { 553 opp-hz = /bits/ 64 <2208000000>; 554 opp-peak-kBps = <6220000 44851200>; 555 }; 556 557 cpu4_opp_2400mhz: opp-2400000000 { 558 opp-hz = /bits/ 64 <2400000000>; 559 opp-peak-kBps = <8532000 48537600>; 560 }; 561 562 cpu4_opp_2611mhz: opp-2611200000 { 563 opp-hz = /bits/ 64 <2611200000>; 564 opp-peak-kBps = <8532000 48537600>; 565 }; 566 }; 567 568 cpu7_opp_table: opp-table-cpu7 { 569 compatible = "operating-points-v2"; 570 opp-shared; 571 572 cpu7_opp_806mhz: opp-806400000 { 573 opp-hz = /bits/ 64 <806400000>; 574 opp-peak-kBps = <1804000 9600000>; 575 }; 576 577 cpu7_opp_1056mhz: opp-1056000000 { 578 opp-hz = /bits/ 64 <1056000000>; 579 opp-peak-kBps = <2188000 17817600>; 580 }; 581 582 cpu7_opp_1325mhz: opp-1324800000 { 583 opp-hz = /bits/ 64 <1324800000>; 584 opp-peak-kBps = <4068000 24576000>; 585 }; 586 587 cpu7_opp_1517mhz: opp-1516800000 { 588 opp-hz = /bits/ 64 <1516800000>; 589 opp-peak-kBps = <4068000 24576000>; 590 }; 591 592 cpu7_opp_1766mhz: opp-1766400000 { 593 opp-hz = /bits/ 64 <1766400000>; 594 opp-peak-kBps = <6220000 38092800>; 595 }; 596 597 cpu7_opp_1862mhz: opp-1862400000 { 598 opp-hz = /bits/ 64 <1862400000>; 599 opp-peak-kBps = <6220000 38092800>; 600 }; 601 602 cpu7_opp_2035mhz: opp-2035200000 { 603 opp-hz = /bits/ 64 <2035200000>; 604 opp-peak-kBps = <6220000 38092800>; 605 }; 606 607 cpu7_opp_2112mhz: opp-2112000000 { 608 opp-hz = /bits/ 64 <2112000000>; 609 opp-peak-kBps = <6220000 44851200>; 610 }; 611 612 cpu7_opp_2208mhz: opp-2208000000 { 613 opp-hz = /bits/ 64 <2208000000>; 614 opp-peak-kBps = <6220000 44851200>; 615 }; 616 617 cpu7_opp_2381mhz: opp-2380800000 { 618 opp-hz = /bits/ 64 <2380800000>; 619 opp-peak-kBps = <6832000 44851200>; 620 }; 621 622 cpu7_opp_2400mhz: opp-2400000000 { 623 opp-hz = /bits/ 64 <2400000000>; 624 opp-peak-kBps = <8532000 48537600>; 625 }; 626 627 cpu7_opp_2515mhz: opp-2515200000 { 628 opp-hz = /bits/ 64 <2515200000>; 629 opp-peak-kBps = <8532000 48537600>; 630 }; 631 632 cpu7_opp_2707mhz: opp-2707200000 { 633 opp-hz = /bits/ 64 <2707200000>; 634 opp-peak-kBps = <8532000 48537600>; 635 }; 636 637 cpu7_opp_3014mhz: opp-3014400000 { 638 opp-hz = /bits/ 64 <3014400000>; 639 opp-peak-kBps = <8532000 48537600>; 640 }; 641 }; 642 643 memory@80000000 { 644 device_type = "memory"; 645 /* We expect the bootloader to fill in the size */ 646 reg = <0 0x80000000 0 0>; 647 }; 648 649 firmware { 650 scm { 651 compatible = "qcom,scm-sc7280", "qcom,scm"; 652 }; 653 }; 654 655 clk_virt: interconnect { 656 compatible = "qcom,sc7280-clk-virt"; 657 #interconnect-cells = <2>; 658 qcom,bcm-voters = <&apps_bcm_voter>; 659 }; 660 661 smem { 662 compatible = "qcom,smem"; 663 memory-region = <&smem_mem>; 664 hwlocks = <&tcsr_mutex 3>; 665 }; 666 667 smp2p-adsp { 668 compatible = "qcom,smp2p"; 669 qcom,smem = <443>, <429>; 670 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 671 IPCC_MPROC_SIGNAL_SMP2P 672 IRQ_TYPE_EDGE_RISING>; 673 mboxes = <&ipcc IPCC_CLIENT_LPASS 674 IPCC_MPROC_SIGNAL_SMP2P>; 675 676 qcom,local-pid = <0>; 677 qcom,remote-pid = <2>; 678 679 adsp_smp2p_out: master-kernel { 680 qcom,entry-name = "master-kernel"; 681 #qcom,smem-state-cells = <1>; 682 }; 683 684 adsp_smp2p_in: slave-kernel { 685 qcom,entry-name = "slave-kernel"; 686 interrupt-controller; 687 #interrupt-cells = <2>; 688 }; 689 }; 690 691 smp2p-cdsp { 692 compatible = "qcom,smp2p"; 693 qcom,smem = <94>, <432>; 694 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 695 IPCC_MPROC_SIGNAL_SMP2P 696 IRQ_TYPE_EDGE_RISING>; 697 mboxes = <&ipcc IPCC_CLIENT_CDSP 698 IPCC_MPROC_SIGNAL_SMP2P>; 699 700 qcom,local-pid = <0>; 701 qcom,remote-pid = <5>; 702 703 cdsp_smp2p_out: master-kernel { 704 qcom,entry-name = "master-kernel"; 705 #qcom,smem-state-cells = <1>; 706 }; 707 708 cdsp_smp2p_in: slave-kernel { 709 qcom,entry-name = "slave-kernel"; 710 interrupt-controller; 711 #interrupt-cells = <2>; 712 }; 713 }; 714 715 smp2p-mpss { 716 compatible = "qcom,smp2p"; 717 qcom,smem = <435>, <428>; 718 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 719 IPCC_MPROC_SIGNAL_SMP2P 720 IRQ_TYPE_EDGE_RISING>; 721 mboxes = <&ipcc IPCC_CLIENT_MPSS 722 IPCC_MPROC_SIGNAL_SMP2P>; 723 724 qcom,local-pid = <0>; 725 qcom,remote-pid = <1>; 726 727 modem_smp2p_out: master-kernel { 728 qcom,entry-name = "master-kernel"; 729 #qcom,smem-state-cells = <1>; 730 }; 731 732 modem_smp2p_in: slave-kernel { 733 qcom,entry-name = "slave-kernel"; 734 interrupt-controller; 735 #interrupt-cells = <2>; 736 }; 737 738 ipa_smp2p_out: ipa-ap-to-modem { 739 qcom,entry-name = "ipa"; 740 #qcom,smem-state-cells = <1>; 741 }; 742 743 ipa_smp2p_in: ipa-modem-to-ap { 744 qcom,entry-name = "ipa"; 745 interrupt-controller; 746 #interrupt-cells = <2>; 747 }; 748 }; 749 750 smp2p-wpss { 751 compatible = "qcom,smp2p"; 752 qcom,smem = <617>, <616>; 753 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 754 IPCC_MPROC_SIGNAL_SMP2P 755 IRQ_TYPE_EDGE_RISING>; 756 mboxes = <&ipcc IPCC_CLIENT_WPSS 757 IPCC_MPROC_SIGNAL_SMP2P>; 758 759 qcom,local-pid = <0>; 760 qcom,remote-pid = <13>; 761 762 wpss_smp2p_out: master-kernel { 763 qcom,entry-name = "master-kernel"; 764 #qcom,smem-state-cells = <1>; 765 }; 766 767 wpss_smp2p_in: slave-kernel { 768 qcom,entry-name = "slave-kernel"; 769 interrupt-controller; 770 #interrupt-cells = <2>; 771 }; 772 773 wlan_smp2p_out: wlan-ap-to-wpss { 774 qcom,entry-name = "wlan"; 775 #qcom,smem-state-cells = <1>; 776 }; 777 778 wlan_smp2p_in: wlan-wpss-to-ap { 779 qcom,entry-name = "wlan"; 780 interrupt-controller; 781 #interrupt-cells = <2>; 782 }; 783 }; 784 785 pmu { 786 compatible = "arm,armv8-pmuv3"; 787 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 788 }; 789 790 psci { 791 compatible = "arm,psci-1.0"; 792 method = "smc"; 793 }; 794 795 qspi_opp_table: opp-table-qspi { 796 compatible = "operating-points-v2"; 797 798 opp-75000000 { 799 opp-hz = /bits/ 64 <75000000>; 800 required-opps = <&rpmhpd_opp_low_svs>; 801 }; 802 803 opp-150000000 { 804 opp-hz = /bits/ 64 <150000000>; 805 required-opps = <&rpmhpd_opp_svs>; 806 }; 807 808 opp-200000000 { 809 opp-hz = /bits/ 64 <200000000>; 810 required-opps = <&rpmhpd_opp_svs_l1>; 811 }; 812 813 opp-300000000 { 814 opp-hz = /bits/ 64 <300000000>; 815 required-opps = <&rpmhpd_opp_nom>; 816 }; 817 }; 818 819 qup_opp_table: opp-table-qup { 820 compatible = "operating-points-v2"; 821 822 opp-75000000 { 823 opp-hz = /bits/ 64 <75000000>; 824 required-opps = <&rpmhpd_opp_low_svs>; 825 }; 826 827 opp-100000000 { 828 opp-hz = /bits/ 64 <100000000>; 829 required-opps = <&rpmhpd_opp_svs>; 830 }; 831 832 opp-128000000 { 833 opp-hz = /bits/ 64 <128000000>; 834 required-opps = <&rpmhpd_opp_nom>; 835 }; 836 }; 837 838 soc: soc@0 { 839 #address-cells = <2>; 840 #size-cells = <2>; 841 ranges = <0 0 0 0 0x10 0>; 842 dma-ranges = <0 0 0 0 0x10 0>; 843 compatible = "simple-bus"; 844 845 gcc: clock-controller@100000 { 846 compatible = "qcom,gcc-sc7280"; 847 reg = <0 0x00100000 0 0x1f0000>; 848 clocks = <&rpmhcc RPMH_CXO_CLK>, 849 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 850 <0>, <&pcie1_lane>, 851 <0>, <0>, <0>, <0>; 852 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 853 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 854 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 855 "ufs_phy_tx_symbol_0_clk", 856 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 857 #clock-cells = <1>; 858 #reset-cells = <1>; 859 #power-domain-cells = <1>; 860 power-domains = <&rpmhpd SC7280_CX>; 861 }; 862 863 ipcc: mailbox@408000 { 864 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 865 reg = <0 0x00408000 0 0x1000>; 866 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 867 interrupt-controller; 868 #interrupt-cells = <3>; 869 #mbox-cells = <2>; 870 }; 871 872 qfprom: efuse@784000 { 873 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 874 reg = <0 0x00784000 0 0xa20>, 875 <0 0x00780000 0 0xa20>, 876 <0 0x00782000 0 0x120>, 877 <0 0x00786000 0 0x1fff>; 878 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 879 clock-names = "core"; 880 power-domains = <&rpmhpd SC7280_MX>; 881 #address-cells = <1>; 882 #size-cells = <1>; 883 884 gpu_speed_bin: gpu_speed_bin@1e9 { 885 reg = <0x1e9 0x2>; 886 bits = <5 8>; 887 }; 888 }; 889 890 sdhc_1: mmc@7c4000 { 891 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 892 pinctrl-names = "default", "sleep"; 893 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 894 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 895 status = "disabled"; 896 897 reg = <0 0x007c4000 0 0x1000>, 898 <0 0x007c5000 0 0x1000>; 899 reg-names = "hc", "cqhci"; 900 901 iommus = <&apps_smmu 0xc0 0x0>; 902 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 904 interrupt-names = "hc_irq", "pwr_irq"; 905 906 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 907 <&gcc GCC_SDCC1_APPS_CLK>, 908 <&rpmhcc RPMH_CXO_CLK>; 909 clock-names = "iface", "core", "xo"; 910 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 911 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 912 interconnect-names = "sdhc-ddr","cpu-sdhc"; 913 power-domains = <&rpmhpd SC7280_CX>; 914 operating-points-v2 = <&sdhc1_opp_table>; 915 916 bus-width = <8>; 917 supports-cqe; 918 919 qcom,dll-config = <0x0007642c>; 920 qcom,ddr-config = <0x80040868>; 921 922 mmc-ddr-1_8v; 923 mmc-hs200-1_8v; 924 mmc-hs400-1_8v; 925 mmc-hs400-enhanced-strobe; 926 927 resets = <&gcc GCC_SDCC1_BCR>; 928 929 sdhc1_opp_table: opp-table { 930 compatible = "operating-points-v2"; 931 932 opp-100000000 { 933 opp-hz = /bits/ 64 <100000000>; 934 required-opps = <&rpmhpd_opp_low_svs>; 935 opp-peak-kBps = <1800000 400000>; 936 opp-avg-kBps = <100000 0>; 937 }; 938 939 opp-384000000 { 940 opp-hz = /bits/ 64 <384000000>; 941 required-opps = <&rpmhpd_opp_nom>; 942 opp-peak-kBps = <5400000 1600000>; 943 opp-avg-kBps = <390000 0>; 944 }; 945 }; 946 947 }; 948 949 gpi_dma0: dma-controller@900000 { 950 #dma-cells = <3>; 951 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 952 reg = <0 0x00900000 0 0x60000>; 953 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 965 dma-channels = <12>; 966 dma-channel-mask = <0x7f>; 967 iommus = <&apps_smmu 0x0136 0x0>; 968 status = "disabled"; 969 }; 970 971 qupv3_id_0: geniqup@9c0000 { 972 compatible = "qcom,geni-se-qup"; 973 reg = <0 0x009c0000 0 0x2000>; 974 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 975 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 976 clock-names = "m-ahb", "s-ahb"; 977 #address-cells = <2>; 978 #size-cells = <2>; 979 ranges; 980 iommus = <&apps_smmu 0x123 0x0>; 981 status = "disabled"; 982 983 i2c0: i2c@980000 { 984 compatible = "qcom,geni-i2c"; 985 reg = <0 0x00980000 0 0x4000>; 986 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 987 clock-names = "se"; 988 pinctrl-names = "default"; 989 pinctrl-0 = <&qup_i2c0_data_clk>; 990 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 991 #address-cells = <1>; 992 #size-cells = <0>; 993 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 994 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 995 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 996 interconnect-names = "qup-core", "qup-config", 997 "qup-memory"; 998 power-domains = <&rpmhpd SC7280_CX>; 999 required-opps = <&rpmhpd_opp_low_svs>; 1000 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1001 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1002 dma-names = "tx", "rx"; 1003 status = "disabled"; 1004 }; 1005 1006 spi0: spi@980000 { 1007 compatible = "qcom,geni-spi"; 1008 reg = <0 0x00980000 0 0x4000>; 1009 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1010 clock-names = "se"; 1011 pinctrl-names = "default"; 1012 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1013 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 power-domains = <&rpmhpd SC7280_CX>; 1017 operating-points-v2 = <&qup_opp_table>; 1018 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1019 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1020 interconnect-names = "qup-core", "qup-config"; 1021 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1022 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1023 dma-names = "tx", "rx"; 1024 status = "disabled"; 1025 }; 1026 1027 uart0: serial@980000 { 1028 compatible = "qcom,geni-uart"; 1029 reg = <0 0x00980000 0 0x4000>; 1030 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1031 clock-names = "se"; 1032 pinctrl-names = "default"; 1033 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1034 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1035 power-domains = <&rpmhpd SC7280_CX>; 1036 operating-points-v2 = <&qup_opp_table>; 1037 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1038 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1039 interconnect-names = "qup-core", "qup-config"; 1040 status = "disabled"; 1041 }; 1042 1043 i2c1: i2c@984000 { 1044 compatible = "qcom,geni-i2c"; 1045 reg = <0 0x00984000 0 0x4000>; 1046 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1047 clock-names = "se"; 1048 pinctrl-names = "default"; 1049 pinctrl-0 = <&qup_i2c1_data_clk>; 1050 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1054 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1055 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1056 interconnect-names = "qup-core", "qup-config", 1057 "qup-memory"; 1058 power-domains = <&rpmhpd SC7280_CX>; 1059 required-opps = <&rpmhpd_opp_low_svs>; 1060 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1061 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1062 dma-names = "tx", "rx"; 1063 status = "disabled"; 1064 }; 1065 1066 spi1: spi@984000 { 1067 compatible = "qcom,geni-spi"; 1068 reg = <0 0x00984000 0 0x4000>; 1069 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1070 clock-names = "se"; 1071 pinctrl-names = "default"; 1072 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1073 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 power-domains = <&rpmhpd SC7280_CX>; 1077 operating-points-v2 = <&qup_opp_table>; 1078 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1079 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1080 interconnect-names = "qup-core", "qup-config"; 1081 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1082 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1083 dma-names = "tx", "rx"; 1084 status = "disabled"; 1085 }; 1086 1087 uart1: serial@984000 { 1088 compatible = "qcom,geni-uart"; 1089 reg = <0 0x00984000 0 0x4000>; 1090 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1091 clock-names = "se"; 1092 pinctrl-names = "default"; 1093 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1094 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1095 power-domains = <&rpmhpd SC7280_CX>; 1096 operating-points-v2 = <&qup_opp_table>; 1097 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1098 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1099 interconnect-names = "qup-core", "qup-config"; 1100 status = "disabled"; 1101 }; 1102 1103 i2c2: i2c@988000 { 1104 compatible = "qcom,geni-i2c"; 1105 reg = <0 0x00988000 0 0x4000>; 1106 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1107 clock-names = "se"; 1108 pinctrl-names = "default"; 1109 pinctrl-0 = <&qup_i2c2_data_clk>; 1110 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1111 #address-cells = <1>; 1112 #size-cells = <0>; 1113 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1114 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1115 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1116 interconnect-names = "qup-core", "qup-config", 1117 "qup-memory"; 1118 power-domains = <&rpmhpd SC7280_CX>; 1119 required-opps = <&rpmhpd_opp_low_svs>; 1120 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1121 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1122 dma-names = "tx", "rx"; 1123 status = "disabled"; 1124 }; 1125 1126 spi2: spi@988000 { 1127 compatible = "qcom,geni-spi"; 1128 reg = <0 0x00988000 0 0x4000>; 1129 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1130 clock-names = "se"; 1131 pinctrl-names = "default"; 1132 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1133 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1134 #address-cells = <1>; 1135 #size-cells = <0>; 1136 power-domains = <&rpmhpd SC7280_CX>; 1137 operating-points-v2 = <&qup_opp_table>; 1138 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1139 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1140 interconnect-names = "qup-core", "qup-config"; 1141 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1142 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1143 dma-names = "tx", "rx"; 1144 status = "disabled"; 1145 }; 1146 1147 uart2: serial@988000 { 1148 compatible = "qcom,geni-uart"; 1149 reg = <0 0x00988000 0 0x4000>; 1150 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1151 clock-names = "se"; 1152 pinctrl-names = "default"; 1153 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1154 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1155 power-domains = <&rpmhpd SC7280_CX>; 1156 operating-points-v2 = <&qup_opp_table>; 1157 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1158 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1159 interconnect-names = "qup-core", "qup-config"; 1160 status = "disabled"; 1161 }; 1162 1163 i2c3: i2c@98c000 { 1164 compatible = "qcom,geni-i2c"; 1165 reg = <0 0x0098c000 0 0x4000>; 1166 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1167 clock-names = "se"; 1168 pinctrl-names = "default"; 1169 pinctrl-0 = <&qup_i2c3_data_clk>; 1170 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1171 #address-cells = <1>; 1172 #size-cells = <0>; 1173 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1174 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1175 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1176 interconnect-names = "qup-core", "qup-config", 1177 "qup-memory"; 1178 power-domains = <&rpmhpd SC7280_CX>; 1179 required-opps = <&rpmhpd_opp_low_svs>; 1180 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1181 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1182 dma-names = "tx", "rx"; 1183 status = "disabled"; 1184 }; 1185 1186 spi3: spi@98c000 { 1187 compatible = "qcom,geni-spi"; 1188 reg = <0 0x0098c000 0 0x4000>; 1189 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1190 clock-names = "se"; 1191 pinctrl-names = "default"; 1192 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1193 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1194 #address-cells = <1>; 1195 #size-cells = <0>; 1196 power-domains = <&rpmhpd SC7280_CX>; 1197 operating-points-v2 = <&qup_opp_table>; 1198 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1199 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1200 interconnect-names = "qup-core", "qup-config"; 1201 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1202 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1203 dma-names = "tx", "rx"; 1204 status = "disabled"; 1205 }; 1206 1207 uart3: serial@98c000 { 1208 compatible = "qcom,geni-uart"; 1209 reg = <0 0x0098c000 0 0x4000>; 1210 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1211 clock-names = "se"; 1212 pinctrl-names = "default"; 1213 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1214 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1215 power-domains = <&rpmhpd SC7280_CX>; 1216 operating-points-v2 = <&qup_opp_table>; 1217 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1218 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1219 interconnect-names = "qup-core", "qup-config"; 1220 status = "disabled"; 1221 }; 1222 1223 i2c4: i2c@990000 { 1224 compatible = "qcom,geni-i2c"; 1225 reg = <0 0x00990000 0 0x4000>; 1226 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1227 clock-names = "se"; 1228 pinctrl-names = "default"; 1229 pinctrl-0 = <&qup_i2c4_data_clk>; 1230 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1234 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1235 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1236 interconnect-names = "qup-core", "qup-config", 1237 "qup-memory"; 1238 power-domains = <&rpmhpd SC7280_CX>; 1239 required-opps = <&rpmhpd_opp_low_svs>; 1240 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1241 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1242 dma-names = "tx", "rx"; 1243 status = "disabled"; 1244 }; 1245 1246 spi4: spi@990000 { 1247 compatible = "qcom,geni-spi"; 1248 reg = <0 0x00990000 0 0x4000>; 1249 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1250 clock-names = "se"; 1251 pinctrl-names = "default"; 1252 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1253 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 power-domains = <&rpmhpd SC7280_CX>; 1257 operating-points-v2 = <&qup_opp_table>; 1258 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1259 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1260 interconnect-names = "qup-core", "qup-config"; 1261 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1262 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1263 dma-names = "tx", "rx"; 1264 status = "disabled"; 1265 }; 1266 1267 uart4: serial@990000 { 1268 compatible = "qcom,geni-uart"; 1269 reg = <0 0x00990000 0 0x4000>; 1270 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1271 clock-names = "se"; 1272 pinctrl-names = "default"; 1273 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1274 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1275 power-domains = <&rpmhpd SC7280_CX>; 1276 operating-points-v2 = <&qup_opp_table>; 1277 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1278 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1279 interconnect-names = "qup-core", "qup-config"; 1280 status = "disabled"; 1281 }; 1282 1283 i2c5: i2c@994000 { 1284 compatible = "qcom,geni-i2c"; 1285 reg = <0 0x00994000 0 0x4000>; 1286 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1287 clock-names = "se"; 1288 pinctrl-names = "default"; 1289 pinctrl-0 = <&qup_i2c5_data_clk>; 1290 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1291 #address-cells = <1>; 1292 #size-cells = <0>; 1293 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1294 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1295 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1296 interconnect-names = "qup-core", "qup-config", 1297 "qup-memory"; 1298 power-domains = <&rpmhpd SC7280_CX>; 1299 required-opps = <&rpmhpd_opp_low_svs>; 1300 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1301 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1302 dma-names = "tx", "rx"; 1303 status = "disabled"; 1304 }; 1305 1306 spi5: spi@994000 { 1307 compatible = "qcom,geni-spi"; 1308 reg = <0 0x00994000 0 0x4000>; 1309 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1310 clock-names = "se"; 1311 pinctrl-names = "default"; 1312 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1313 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 power-domains = <&rpmhpd SC7280_CX>; 1317 operating-points-v2 = <&qup_opp_table>; 1318 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1319 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1320 interconnect-names = "qup-core", "qup-config"; 1321 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1322 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1323 dma-names = "tx", "rx"; 1324 status = "disabled"; 1325 }; 1326 1327 uart5: serial@994000 { 1328 compatible = "qcom,geni-uart"; 1329 reg = <0 0x00994000 0 0x4000>; 1330 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1331 clock-names = "se"; 1332 pinctrl-names = "default"; 1333 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1334 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1335 power-domains = <&rpmhpd SC7280_CX>; 1336 operating-points-v2 = <&qup_opp_table>; 1337 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1338 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1339 interconnect-names = "qup-core", "qup-config"; 1340 status = "disabled"; 1341 }; 1342 1343 i2c6: i2c@998000 { 1344 compatible = "qcom,geni-i2c"; 1345 reg = <0 0x00998000 0 0x4000>; 1346 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1347 clock-names = "se"; 1348 pinctrl-names = "default"; 1349 pinctrl-0 = <&qup_i2c6_data_clk>; 1350 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1351 #address-cells = <1>; 1352 #size-cells = <0>; 1353 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1354 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1355 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1356 interconnect-names = "qup-core", "qup-config", 1357 "qup-memory"; 1358 power-domains = <&rpmhpd SC7280_CX>; 1359 required-opps = <&rpmhpd_opp_low_svs>; 1360 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1361 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1362 dma-names = "tx", "rx"; 1363 status = "disabled"; 1364 }; 1365 1366 spi6: spi@998000 { 1367 compatible = "qcom,geni-spi"; 1368 reg = <0 0x00998000 0 0x4000>; 1369 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1370 clock-names = "se"; 1371 pinctrl-names = "default"; 1372 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1373 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1374 #address-cells = <1>; 1375 #size-cells = <0>; 1376 power-domains = <&rpmhpd SC7280_CX>; 1377 operating-points-v2 = <&qup_opp_table>; 1378 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1379 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1380 interconnect-names = "qup-core", "qup-config"; 1381 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1382 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1383 dma-names = "tx", "rx"; 1384 status = "disabled"; 1385 }; 1386 1387 uart6: serial@998000 { 1388 compatible = "qcom,geni-uart"; 1389 reg = <0 0x00998000 0 0x4000>; 1390 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1391 clock-names = "se"; 1392 pinctrl-names = "default"; 1393 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1394 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1395 power-domains = <&rpmhpd SC7280_CX>; 1396 operating-points-v2 = <&qup_opp_table>; 1397 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1398 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1399 interconnect-names = "qup-core", "qup-config"; 1400 status = "disabled"; 1401 }; 1402 1403 i2c7: i2c@99c000 { 1404 compatible = "qcom,geni-i2c"; 1405 reg = <0 0x0099c000 0 0x4000>; 1406 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1407 clock-names = "se"; 1408 pinctrl-names = "default"; 1409 pinctrl-0 = <&qup_i2c7_data_clk>; 1410 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1411 #address-cells = <1>; 1412 #size-cells = <0>; 1413 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1414 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1415 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1416 interconnect-names = "qup-core", "qup-config", 1417 "qup-memory"; 1418 power-domains = <&rpmhpd SC7280_CX>; 1419 required-opps = <&rpmhpd_opp_low_svs>; 1420 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1421 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1422 dma-names = "tx", "rx"; 1423 status = "disabled"; 1424 }; 1425 1426 spi7: spi@99c000 { 1427 compatible = "qcom,geni-spi"; 1428 reg = <0 0x0099c000 0 0x4000>; 1429 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1430 clock-names = "se"; 1431 pinctrl-names = "default"; 1432 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1433 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1434 #address-cells = <1>; 1435 #size-cells = <0>; 1436 power-domains = <&rpmhpd SC7280_CX>; 1437 operating-points-v2 = <&qup_opp_table>; 1438 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1439 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1440 interconnect-names = "qup-core", "qup-config"; 1441 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1442 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1443 dma-names = "tx", "rx"; 1444 status = "disabled"; 1445 }; 1446 1447 uart7: serial@99c000 { 1448 compatible = "qcom,geni-uart"; 1449 reg = <0 0x0099c000 0 0x4000>; 1450 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1451 clock-names = "se"; 1452 pinctrl-names = "default"; 1453 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1454 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1455 power-domains = <&rpmhpd SC7280_CX>; 1456 operating-points-v2 = <&qup_opp_table>; 1457 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1458 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1459 interconnect-names = "qup-core", "qup-config"; 1460 status = "disabled"; 1461 }; 1462 }; 1463 1464 gpi_dma1: dma-controller@a00000 { 1465 #dma-cells = <3>; 1466 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1467 reg = <0 0x00a00000 0 0x60000>; 1468 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1480 dma-channels = <12>; 1481 dma-channel-mask = <0x1e>; 1482 iommus = <&apps_smmu 0x56 0x0>; 1483 status = "disabled"; 1484 }; 1485 1486 qupv3_id_1: geniqup@ac0000 { 1487 compatible = "qcom,geni-se-qup"; 1488 reg = <0 0x00ac0000 0 0x2000>; 1489 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1490 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1491 clock-names = "m-ahb", "s-ahb"; 1492 #address-cells = <2>; 1493 #size-cells = <2>; 1494 ranges; 1495 iommus = <&apps_smmu 0x43 0x0>; 1496 status = "disabled"; 1497 1498 i2c8: i2c@a80000 { 1499 compatible = "qcom,geni-i2c"; 1500 reg = <0 0x00a80000 0 0x4000>; 1501 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1502 clock-names = "se"; 1503 pinctrl-names = "default"; 1504 pinctrl-0 = <&qup_i2c8_data_clk>; 1505 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1506 #address-cells = <1>; 1507 #size-cells = <0>; 1508 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1509 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1510 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1511 interconnect-names = "qup-core", "qup-config", 1512 "qup-memory"; 1513 power-domains = <&rpmhpd SC7280_CX>; 1514 required-opps = <&rpmhpd_opp_low_svs>; 1515 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1516 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1517 dma-names = "tx", "rx"; 1518 status = "disabled"; 1519 }; 1520 1521 spi8: spi@a80000 { 1522 compatible = "qcom,geni-spi"; 1523 reg = <0 0x00a80000 0 0x4000>; 1524 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1525 clock-names = "se"; 1526 pinctrl-names = "default"; 1527 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1528 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1529 #address-cells = <1>; 1530 #size-cells = <0>; 1531 power-domains = <&rpmhpd SC7280_CX>; 1532 operating-points-v2 = <&qup_opp_table>; 1533 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1534 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1535 interconnect-names = "qup-core", "qup-config"; 1536 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1537 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1538 dma-names = "tx", "rx"; 1539 status = "disabled"; 1540 }; 1541 1542 uart8: serial@a80000 { 1543 compatible = "qcom,geni-uart"; 1544 reg = <0 0x00a80000 0 0x4000>; 1545 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1546 clock-names = "se"; 1547 pinctrl-names = "default"; 1548 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1549 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1550 power-domains = <&rpmhpd SC7280_CX>; 1551 operating-points-v2 = <&qup_opp_table>; 1552 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1553 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1554 interconnect-names = "qup-core", "qup-config"; 1555 status = "disabled"; 1556 }; 1557 1558 i2c9: i2c@a84000 { 1559 compatible = "qcom,geni-i2c"; 1560 reg = <0 0x00a84000 0 0x4000>; 1561 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1562 clock-names = "se"; 1563 pinctrl-names = "default"; 1564 pinctrl-0 = <&qup_i2c9_data_clk>; 1565 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1566 #address-cells = <1>; 1567 #size-cells = <0>; 1568 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1569 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1570 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1571 interconnect-names = "qup-core", "qup-config", 1572 "qup-memory"; 1573 power-domains = <&rpmhpd SC7280_CX>; 1574 required-opps = <&rpmhpd_opp_low_svs>; 1575 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1576 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1577 dma-names = "tx", "rx"; 1578 status = "disabled"; 1579 }; 1580 1581 spi9: spi@a84000 { 1582 compatible = "qcom,geni-spi"; 1583 reg = <0 0x00a84000 0 0x4000>; 1584 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1585 clock-names = "se"; 1586 pinctrl-names = "default"; 1587 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1588 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1589 #address-cells = <1>; 1590 #size-cells = <0>; 1591 power-domains = <&rpmhpd SC7280_CX>; 1592 operating-points-v2 = <&qup_opp_table>; 1593 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1594 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1595 interconnect-names = "qup-core", "qup-config"; 1596 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1597 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1598 dma-names = "tx", "rx"; 1599 status = "disabled"; 1600 }; 1601 1602 uart9: serial@a84000 { 1603 compatible = "qcom,geni-uart"; 1604 reg = <0 0x00a84000 0 0x4000>; 1605 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1606 clock-names = "se"; 1607 pinctrl-names = "default"; 1608 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1609 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1610 power-domains = <&rpmhpd SC7280_CX>; 1611 operating-points-v2 = <&qup_opp_table>; 1612 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1613 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1614 interconnect-names = "qup-core", "qup-config"; 1615 status = "disabled"; 1616 }; 1617 1618 i2c10: i2c@a88000 { 1619 compatible = "qcom,geni-i2c"; 1620 reg = <0 0x00a88000 0 0x4000>; 1621 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1622 clock-names = "se"; 1623 pinctrl-names = "default"; 1624 pinctrl-0 = <&qup_i2c10_data_clk>; 1625 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1626 #address-cells = <1>; 1627 #size-cells = <0>; 1628 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1629 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1630 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1631 interconnect-names = "qup-core", "qup-config", 1632 "qup-memory"; 1633 power-domains = <&rpmhpd SC7280_CX>; 1634 required-opps = <&rpmhpd_opp_low_svs>; 1635 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1636 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1637 dma-names = "tx", "rx"; 1638 status = "disabled"; 1639 }; 1640 1641 spi10: spi@a88000 { 1642 compatible = "qcom,geni-spi"; 1643 reg = <0 0x00a88000 0 0x4000>; 1644 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1645 clock-names = "se"; 1646 pinctrl-names = "default"; 1647 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1648 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1649 #address-cells = <1>; 1650 #size-cells = <0>; 1651 power-domains = <&rpmhpd SC7280_CX>; 1652 operating-points-v2 = <&qup_opp_table>; 1653 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1654 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1655 interconnect-names = "qup-core", "qup-config"; 1656 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1657 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1658 dma-names = "tx", "rx"; 1659 status = "disabled"; 1660 }; 1661 1662 uart10: serial@a88000 { 1663 compatible = "qcom,geni-uart"; 1664 reg = <0 0x00a88000 0 0x4000>; 1665 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1666 clock-names = "se"; 1667 pinctrl-names = "default"; 1668 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1669 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1670 power-domains = <&rpmhpd SC7280_CX>; 1671 operating-points-v2 = <&qup_opp_table>; 1672 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1673 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1674 interconnect-names = "qup-core", "qup-config"; 1675 status = "disabled"; 1676 }; 1677 1678 i2c11: i2c@a8c000 { 1679 compatible = "qcom,geni-i2c"; 1680 reg = <0 0x00a8c000 0 0x4000>; 1681 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1682 clock-names = "se"; 1683 pinctrl-names = "default"; 1684 pinctrl-0 = <&qup_i2c11_data_clk>; 1685 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1686 #address-cells = <1>; 1687 #size-cells = <0>; 1688 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1689 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1690 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1691 interconnect-names = "qup-core", "qup-config", 1692 "qup-memory"; 1693 power-domains = <&rpmhpd SC7280_CX>; 1694 required-opps = <&rpmhpd_opp_low_svs>; 1695 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1696 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1697 dma-names = "tx", "rx"; 1698 status = "disabled"; 1699 }; 1700 1701 spi11: spi@a8c000 { 1702 compatible = "qcom,geni-spi"; 1703 reg = <0 0x00a8c000 0 0x4000>; 1704 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1705 clock-names = "se"; 1706 pinctrl-names = "default"; 1707 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1708 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1709 #address-cells = <1>; 1710 #size-cells = <0>; 1711 power-domains = <&rpmhpd SC7280_CX>; 1712 operating-points-v2 = <&qup_opp_table>; 1713 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1714 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1715 interconnect-names = "qup-core", "qup-config"; 1716 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1717 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1718 dma-names = "tx", "rx"; 1719 status = "disabled"; 1720 }; 1721 1722 uart11: serial@a8c000 { 1723 compatible = "qcom,geni-uart"; 1724 reg = <0 0x00a8c000 0 0x4000>; 1725 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1726 clock-names = "se"; 1727 pinctrl-names = "default"; 1728 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1729 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1730 power-domains = <&rpmhpd SC7280_CX>; 1731 operating-points-v2 = <&qup_opp_table>; 1732 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1733 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1734 interconnect-names = "qup-core", "qup-config"; 1735 status = "disabled"; 1736 }; 1737 1738 i2c12: i2c@a90000 { 1739 compatible = "qcom,geni-i2c"; 1740 reg = <0 0x00a90000 0 0x4000>; 1741 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1742 clock-names = "se"; 1743 pinctrl-names = "default"; 1744 pinctrl-0 = <&qup_i2c12_data_clk>; 1745 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1746 #address-cells = <1>; 1747 #size-cells = <0>; 1748 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1749 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1750 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1751 interconnect-names = "qup-core", "qup-config", 1752 "qup-memory"; 1753 power-domains = <&rpmhpd SC7280_CX>; 1754 required-opps = <&rpmhpd_opp_low_svs>; 1755 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1756 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1757 dma-names = "tx", "rx"; 1758 status = "disabled"; 1759 }; 1760 1761 spi12: spi@a90000 { 1762 compatible = "qcom,geni-spi"; 1763 reg = <0 0x00a90000 0 0x4000>; 1764 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1765 clock-names = "se"; 1766 pinctrl-names = "default"; 1767 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1768 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1769 #address-cells = <1>; 1770 #size-cells = <0>; 1771 power-domains = <&rpmhpd SC7280_CX>; 1772 operating-points-v2 = <&qup_opp_table>; 1773 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1774 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1775 interconnect-names = "qup-core", "qup-config"; 1776 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1777 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1778 dma-names = "tx", "rx"; 1779 status = "disabled"; 1780 }; 1781 1782 uart12: serial@a90000 { 1783 compatible = "qcom,geni-uart"; 1784 reg = <0 0x00a90000 0 0x4000>; 1785 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1786 clock-names = "se"; 1787 pinctrl-names = "default"; 1788 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1789 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1790 power-domains = <&rpmhpd SC7280_CX>; 1791 operating-points-v2 = <&qup_opp_table>; 1792 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1793 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1794 interconnect-names = "qup-core", "qup-config"; 1795 status = "disabled"; 1796 }; 1797 1798 i2c13: i2c@a94000 { 1799 compatible = "qcom,geni-i2c"; 1800 reg = <0 0x00a94000 0 0x4000>; 1801 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1802 clock-names = "se"; 1803 pinctrl-names = "default"; 1804 pinctrl-0 = <&qup_i2c13_data_clk>; 1805 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1806 #address-cells = <1>; 1807 #size-cells = <0>; 1808 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1809 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1810 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1811 interconnect-names = "qup-core", "qup-config", 1812 "qup-memory"; 1813 power-domains = <&rpmhpd SC7280_CX>; 1814 required-opps = <&rpmhpd_opp_low_svs>; 1815 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1816 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1817 dma-names = "tx", "rx"; 1818 status = "disabled"; 1819 }; 1820 1821 spi13: spi@a94000 { 1822 compatible = "qcom,geni-spi"; 1823 reg = <0 0x00a94000 0 0x4000>; 1824 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1825 clock-names = "se"; 1826 pinctrl-names = "default"; 1827 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1828 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1829 #address-cells = <1>; 1830 #size-cells = <0>; 1831 power-domains = <&rpmhpd SC7280_CX>; 1832 operating-points-v2 = <&qup_opp_table>; 1833 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1834 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1835 interconnect-names = "qup-core", "qup-config"; 1836 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1837 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1838 dma-names = "tx", "rx"; 1839 status = "disabled"; 1840 }; 1841 1842 uart13: serial@a94000 { 1843 compatible = "qcom,geni-uart"; 1844 reg = <0 0x00a94000 0 0x4000>; 1845 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1846 clock-names = "se"; 1847 pinctrl-names = "default"; 1848 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1849 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1850 power-domains = <&rpmhpd SC7280_CX>; 1851 operating-points-v2 = <&qup_opp_table>; 1852 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1853 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1854 interconnect-names = "qup-core", "qup-config"; 1855 status = "disabled"; 1856 }; 1857 1858 i2c14: i2c@a98000 { 1859 compatible = "qcom,geni-i2c"; 1860 reg = <0 0x00a98000 0 0x4000>; 1861 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1862 clock-names = "se"; 1863 pinctrl-names = "default"; 1864 pinctrl-0 = <&qup_i2c14_data_clk>; 1865 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1866 #address-cells = <1>; 1867 #size-cells = <0>; 1868 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1869 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1870 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1871 interconnect-names = "qup-core", "qup-config", 1872 "qup-memory"; 1873 power-domains = <&rpmhpd SC7280_CX>; 1874 required-opps = <&rpmhpd_opp_low_svs>; 1875 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1876 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1877 dma-names = "tx", "rx"; 1878 status = "disabled"; 1879 }; 1880 1881 spi14: spi@a98000 { 1882 compatible = "qcom,geni-spi"; 1883 reg = <0 0x00a98000 0 0x4000>; 1884 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1885 clock-names = "se"; 1886 pinctrl-names = "default"; 1887 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1888 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1889 #address-cells = <1>; 1890 #size-cells = <0>; 1891 power-domains = <&rpmhpd SC7280_CX>; 1892 operating-points-v2 = <&qup_opp_table>; 1893 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1894 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1895 interconnect-names = "qup-core", "qup-config"; 1896 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1897 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1898 dma-names = "tx", "rx"; 1899 status = "disabled"; 1900 }; 1901 1902 uart14: serial@a98000 { 1903 compatible = "qcom,geni-uart"; 1904 reg = <0 0x00a98000 0 0x4000>; 1905 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1906 clock-names = "se"; 1907 pinctrl-names = "default"; 1908 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1909 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1910 power-domains = <&rpmhpd SC7280_CX>; 1911 operating-points-v2 = <&qup_opp_table>; 1912 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1913 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1914 interconnect-names = "qup-core", "qup-config"; 1915 status = "disabled"; 1916 }; 1917 1918 i2c15: i2c@a9c000 { 1919 compatible = "qcom,geni-i2c"; 1920 reg = <0 0x00a9c000 0 0x4000>; 1921 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1922 clock-names = "se"; 1923 pinctrl-names = "default"; 1924 pinctrl-0 = <&qup_i2c15_data_clk>; 1925 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1926 #address-cells = <1>; 1927 #size-cells = <0>; 1928 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1929 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1930 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1931 interconnect-names = "qup-core", "qup-config", 1932 "qup-memory"; 1933 power-domains = <&rpmhpd SC7280_CX>; 1934 required-opps = <&rpmhpd_opp_low_svs>; 1935 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1936 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1937 dma-names = "tx", "rx"; 1938 status = "disabled"; 1939 }; 1940 1941 spi15: spi@a9c000 { 1942 compatible = "qcom,geni-spi"; 1943 reg = <0 0x00a9c000 0 0x4000>; 1944 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1945 clock-names = "se"; 1946 pinctrl-names = "default"; 1947 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1948 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1949 #address-cells = <1>; 1950 #size-cells = <0>; 1951 power-domains = <&rpmhpd SC7280_CX>; 1952 operating-points-v2 = <&qup_opp_table>; 1953 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1954 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1955 interconnect-names = "qup-core", "qup-config"; 1956 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1957 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1958 dma-names = "tx", "rx"; 1959 status = "disabled"; 1960 }; 1961 1962 uart15: serial@a9c000 { 1963 compatible = "qcom,geni-uart"; 1964 reg = <0 0x00a9c000 0 0x4000>; 1965 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1966 clock-names = "se"; 1967 pinctrl-names = "default"; 1968 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1969 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1970 power-domains = <&rpmhpd SC7280_CX>; 1971 operating-points-v2 = <&qup_opp_table>; 1972 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1973 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1974 interconnect-names = "qup-core", "qup-config"; 1975 status = "disabled"; 1976 }; 1977 }; 1978 1979 cnoc2: interconnect@1500000 { 1980 reg = <0 0x01500000 0 0x1000>; 1981 compatible = "qcom,sc7280-cnoc2"; 1982 #interconnect-cells = <2>; 1983 qcom,bcm-voters = <&apps_bcm_voter>; 1984 }; 1985 1986 cnoc3: interconnect@1502000 { 1987 reg = <0 0x01502000 0 0x1000>; 1988 compatible = "qcom,sc7280-cnoc3"; 1989 #interconnect-cells = <2>; 1990 qcom,bcm-voters = <&apps_bcm_voter>; 1991 }; 1992 1993 mc_virt: interconnect@1580000 { 1994 reg = <0 0x01580000 0 0x4>; 1995 compatible = "qcom,sc7280-mc-virt"; 1996 #interconnect-cells = <2>; 1997 qcom,bcm-voters = <&apps_bcm_voter>; 1998 }; 1999 2000 system_noc: interconnect@1680000 { 2001 reg = <0 0x01680000 0 0x15480>; 2002 compatible = "qcom,sc7280-system-noc"; 2003 #interconnect-cells = <2>; 2004 qcom,bcm-voters = <&apps_bcm_voter>; 2005 }; 2006 2007 aggre1_noc: interconnect@16e0000 { 2008 compatible = "qcom,sc7280-aggre1-noc"; 2009 reg = <0 0x016e0000 0 0x1c080>; 2010 #interconnect-cells = <2>; 2011 qcom,bcm-voters = <&apps_bcm_voter>; 2012 }; 2013 2014 aggre2_noc: interconnect@1700000 { 2015 reg = <0 0x01700000 0 0x2b080>; 2016 compatible = "qcom,sc7280-aggre2-noc"; 2017 #interconnect-cells = <2>; 2018 qcom,bcm-voters = <&apps_bcm_voter>; 2019 }; 2020 2021 mmss_noc: interconnect@1740000 { 2022 reg = <0 0x01740000 0 0x1e080>; 2023 compatible = "qcom,sc7280-mmss-noc"; 2024 #interconnect-cells = <2>; 2025 qcom,bcm-voters = <&apps_bcm_voter>; 2026 }; 2027 2028 wifi: wifi@17a10040 { 2029 compatible = "qcom,wcn6750-wifi"; 2030 reg = <0 0x17a10040 0 0x0>; 2031 iommus = <&apps_smmu 0x1c00 0x1>; 2032 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2033 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2034 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2035 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2036 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2037 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2038 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2039 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2040 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2041 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2042 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2043 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2044 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2045 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2046 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2047 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2048 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2049 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2050 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2051 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2052 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2053 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2054 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2055 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2056 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2057 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2058 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2059 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2060 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2061 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2062 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2063 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2064 qcom,rproc = <&remoteproc_wpss>; 2065 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2066 status = "disabled"; 2067 qcom,smem-states = <&wlan_smp2p_out 0>; 2068 qcom,smem-state-names = "wlan-smp2p-out"; 2069 }; 2070 2071 pcie1: pci@1c08000 { 2072 compatible = "qcom,pcie-sc7280"; 2073 reg = <0 0x01c08000 0 0x3000>, 2074 <0 0x40000000 0 0xf1d>, 2075 <0 0x40000f20 0 0xa8>, 2076 <0 0x40001000 0 0x1000>, 2077 <0 0x40100000 0 0x100000>; 2078 2079 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2080 device_type = "pci"; 2081 linux,pci-domain = <1>; 2082 bus-range = <0x00 0xff>; 2083 num-lanes = <2>; 2084 2085 #address-cells = <3>; 2086 #size-cells = <2>; 2087 2088 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 2089 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2090 2091 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2092 interrupt-names = "msi"; 2093 #interrupt-cells = <1>; 2094 interrupt-map-mask = <0 0 0 0x7>; 2095 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2096 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2097 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2098 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2099 2100 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2101 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2102 <&pcie1_lane>, 2103 <&rpmhcc RPMH_CXO_CLK>, 2104 <&gcc GCC_PCIE_1_AUX_CLK>, 2105 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2106 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2107 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2108 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2109 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2110 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2111 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2112 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2113 2114 clock-names = "pipe", 2115 "pipe_mux", 2116 "phy_pipe", 2117 "ref", 2118 "aux", 2119 "cfg", 2120 "bus_master", 2121 "bus_slave", 2122 "slave_q2a", 2123 "tbu", 2124 "ddrss_sf_tbu", 2125 "aggre0", 2126 "aggre1"; 2127 2128 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2129 assigned-clock-rates = <19200000>; 2130 2131 resets = <&gcc GCC_PCIE_1_BCR>; 2132 reset-names = "pci"; 2133 2134 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2135 2136 phys = <&pcie1_lane>; 2137 phy-names = "pciephy"; 2138 2139 pinctrl-names = "default"; 2140 pinctrl-0 = <&pcie1_clkreq_n>; 2141 2142 iommus = <&apps_smmu 0x1c80 0x1>; 2143 2144 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2145 <0x100 &apps_smmu 0x1c81 0x1>; 2146 2147 status = "disabled"; 2148 }; 2149 2150 pcie1_phy: phy@1c0e000 { 2151 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2152 reg = <0 0x01c0e000 0 0x1c0>; 2153 #address-cells = <2>; 2154 #size-cells = <2>; 2155 ranges; 2156 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2157 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2158 <&gcc GCC_PCIE_CLKREF_EN>, 2159 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2160 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2161 2162 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2163 reset-names = "phy"; 2164 2165 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2166 assigned-clock-rates = <100000000>; 2167 2168 status = "disabled"; 2169 2170 pcie1_lane: phy@1c0e200 { 2171 reg = <0 0x01c0e200 0 0x170>, 2172 <0 0x01c0e400 0 0x200>, 2173 <0 0x01c0ea00 0 0x1f0>, 2174 <0 0x01c0e600 0 0x170>, 2175 <0 0x01c0e800 0 0x200>, 2176 <0 0x01c0ee00 0 0xf4>; 2177 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2178 clock-names = "pipe0"; 2179 2180 #phy-cells = <0>; 2181 #clock-cells = <0>; 2182 clock-output-names = "pcie_1_pipe_clk"; 2183 }; 2184 }; 2185 2186 ipa: ipa@1e40000 { 2187 compatible = "qcom,sc7280-ipa"; 2188 2189 iommus = <&apps_smmu 0x480 0x0>, 2190 <&apps_smmu 0x482 0x0>; 2191 reg = <0 0x01e40000 0 0x8000>, 2192 <0 0x01e50000 0 0x4ad0>, 2193 <0 0x01e04000 0 0x23000>; 2194 reg-names = "ipa-reg", 2195 "ipa-shared", 2196 "gsi"; 2197 2198 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2199 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2200 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2201 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2202 interrupt-names = "ipa", 2203 "gsi", 2204 "ipa-clock-query", 2205 "ipa-setup-ready"; 2206 2207 clocks = <&rpmhcc RPMH_IPA_CLK>; 2208 clock-names = "core"; 2209 2210 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2211 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2212 interconnect-names = "memory", 2213 "config"; 2214 2215 qcom,qmp = <&aoss_qmp>; 2216 2217 qcom,smem-states = <&ipa_smp2p_out 0>, 2218 <&ipa_smp2p_out 1>; 2219 qcom,smem-state-names = "ipa-clock-enabled-valid", 2220 "ipa-clock-enabled"; 2221 2222 status = "disabled"; 2223 }; 2224 2225 tcsr_mutex: hwlock@1f40000 { 2226 compatible = "qcom,tcsr-mutex"; 2227 reg = <0 0x01f40000 0 0x20000>; 2228 #hwlock-cells = <1>; 2229 }; 2230 2231 tcsr_1: syscon@1f60000 { 2232 compatible = "qcom,sc7280-tcsr", "syscon"; 2233 reg = <0 0x01f60000 0 0x20000>; 2234 }; 2235 2236 tcsr_2: syscon@1fc0000 { 2237 compatible = "qcom,sc7280-tcsr", "syscon"; 2238 reg = <0 0x01fc0000 0 0x30000>; 2239 }; 2240 2241 lpasscc: lpasscc@3000000 { 2242 compatible = "qcom,sc7280-lpasscc"; 2243 reg = <0 0x03000000 0 0x40>, 2244 <0 0x03c04000 0 0x4>; 2245 reg-names = "qdsp6ss", "top_cc"; 2246 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2247 clock-names = "iface"; 2248 #clock-cells = <1>; 2249 }; 2250 2251 lpass_rx_macro: codec@3200000 { 2252 compatible = "qcom,sc7280-lpass-rx-macro"; 2253 reg = <0 0x03200000 0 0x1000>; 2254 2255 pinctrl-names = "default"; 2256 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2257 2258 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2259 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2260 <&lpass_va_macro>; 2261 clock-names = "mclk", "npl", "fsgen"; 2262 2263 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2264 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2265 power-domain-names = "macro", "dcodec"; 2266 2267 #clock-cells = <0>; 2268 #sound-dai-cells = <1>; 2269 2270 status = "disabled"; 2271 }; 2272 2273 swr0: soundwire@3210000 { 2274 compatible = "qcom,soundwire-v1.6.0"; 2275 reg = <0 0x03210000 0 0x2000>; 2276 2277 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2278 clocks = <&lpass_rx_macro>; 2279 clock-names = "iface"; 2280 2281 qcom,din-ports = <0>; 2282 qcom,dout-ports = <5>; 2283 2284 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2285 reset-names = "swr_audio_cgcr"; 2286 2287 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2288 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2289 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2290 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2291 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2292 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2293 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2294 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2295 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2296 2297 #sound-dai-cells = <1>; 2298 #address-cells = <2>; 2299 #size-cells = <0>; 2300 2301 status = "disabled"; 2302 }; 2303 2304 lpass_tx_macro: codec@3220000 { 2305 compatible = "qcom,sc7280-lpass-tx-macro"; 2306 reg = <0 0x03220000 0 0x1000>; 2307 2308 pinctrl-names = "default"; 2309 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2310 2311 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2312 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2313 <&lpass_va_macro>; 2314 clock-names = "mclk", "npl", "fsgen"; 2315 2316 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2317 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2318 power-domain-names = "macro", "dcodec"; 2319 2320 #clock-cells = <0>; 2321 #sound-dai-cells = <1>; 2322 2323 status = "disabled"; 2324 }; 2325 2326 swr1: soundwire@3230000 { 2327 compatible = "qcom,soundwire-v1.6.0"; 2328 reg = <0 0x03230000 0 0x2000>; 2329 2330 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2331 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2332 clocks = <&lpass_tx_macro>; 2333 clock-names = "iface"; 2334 2335 qcom,din-ports = <3>; 2336 qcom,dout-ports = <0>; 2337 2338 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2339 reset-names = "swr_audio_cgcr"; 2340 2341 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2342 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2343 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2344 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2345 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2346 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2347 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2348 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2349 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2350 2351 #sound-dai-cells = <1>; 2352 #address-cells = <2>; 2353 #size-cells = <0>; 2354 2355 status = "disabled"; 2356 }; 2357 2358 lpass_audiocc: clock-controller@3300000 { 2359 compatible = "qcom,sc7280-lpassaudiocc"; 2360 reg = <0 0x03300000 0 0x30000>, 2361 <0 0x032a9000 0 0x1000>; 2362 clocks = <&rpmhcc RPMH_CXO_CLK>, 2363 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2364 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2365 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2366 #clock-cells = <1>; 2367 #power-domain-cells = <1>; 2368 #reset-cells = <1>; 2369 }; 2370 2371 lpass_va_macro: codec@3370000 { 2372 compatible = "qcom,sc7280-lpass-va-macro"; 2373 reg = <0 0x03370000 0 0x1000>; 2374 2375 pinctrl-names = "default"; 2376 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2377 2378 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2379 clock-names = "mclk"; 2380 2381 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2382 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2383 power-domain-names = "macro", "dcodec"; 2384 2385 #clock-cells = <0>; 2386 #sound-dai-cells = <1>; 2387 2388 status = "disabled"; 2389 }; 2390 2391 lpass_aon: clock-controller@3380000 { 2392 compatible = "qcom,sc7280-lpassaoncc"; 2393 reg = <0 0x03380000 0 0x30000>; 2394 clocks = <&rpmhcc RPMH_CXO_CLK>, 2395 <&rpmhcc RPMH_CXO_CLK_A>, 2396 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2397 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2398 #clock-cells = <1>; 2399 #power-domain-cells = <1>; 2400 }; 2401 2402 lpass_core: clock-controller@3900000 { 2403 compatible = "qcom,sc7280-lpasscorecc"; 2404 reg = <0 0x03900000 0 0x50000>; 2405 clocks = <&rpmhcc RPMH_CXO_CLK>; 2406 clock-names = "bi_tcxo"; 2407 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2408 #clock-cells = <1>; 2409 #power-domain-cells = <1>; 2410 }; 2411 2412 lpass_cpu: audio@3987000 { 2413 compatible = "qcom,sc7280-lpass-cpu"; 2414 2415 reg = <0 0x03987000 0 0x68000>, 2416 <0 0x03b00000 0 0x29000>, 2417 <0 0x03260000 0 0xc000>, 2418 <0 0x03280000 0 0x29000>, 2419 <0 0x03340000 0 0x29000>, 2420 <0 0x0336c000 0 0x3000>; 2421 reg-names = "lpass-hdmiif", 2422 "lpass-lpaif", 2423 "lpass-rxtx-cdc-dma-lpm", 2424 "lpass-rxtx-lpaif", 2425 "lpass-va-lpaif", 2426 "lpass-va-cdc-dma-lpm"; 2427 2428 iommus = <&apps_smmu 0x1820 0>, 2429 <&apps_smmu 0x1821 0>, 2430 <&apps_smmu 0x1832 0>; 2431 2432 power-domains = <&rpmhpd SC7280_LCX>; 2433 power-domain-names = "lcx"; 2434 required-opps = <&rpmhpd_opp_nom>; 2435 2436 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2437 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2438 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2439 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2440 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2441 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2442 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2443 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2444 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2445 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2446 clock-names = "aon_cc_audio_hm_h", 2447 "audio_cc_ext_mclk0", 2448 "core_cc_sysnoc_mport_core", 2449 "core_cc_ext_if0_ibit", 2450 "core_cc_ext_if1_ibit", 2451 "audio_cc_codec_mem", 2452 "audio_cc_codec_mem0", 2453 "audio_cc_codec_mem1", 2454 "audio_cc_codec_mem2", 2455 "aon_cc_va_mem0"; 2456 2457 #sound-dai-cells = <1>; 2458 #address-cells = <1>; 2459 #size-cells = <0>; 2460 2461 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2462 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2463 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2464 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2465 interrupt-names = "lpass-irq-lpaif", 2466 "lpass-irq-hdmi", 2467 "lpass-irq-vaif", 2468 "lpass-irq-rxtxif"; 2469 2470 status = "disabled"; 2471 }; 2472 2473 lpass_hm: clock-controller@3c00000 { 2474 compatible = "qcom,sc7280-lpasshm"; 2475 reg = <0 0x03c00000 0 0x28>; 2476 clocks = <&rpmhcc RPMH_CXO_CLK>; 2477 clock-names = "bi_tcxo"; 2478 #clock-cells = <1>; 2479 #power-domain-cells = <1>; 2480 }; 2481 2482 lpass_ag_noc: interconnect@3c40000 { 2483 reg = <0 0x03c40000 0 0xf080>; 2484 compatible = "qcom,sc7280-lpass-ag-noc"; 2485 #interconnect-cells = <2>; 2486 qcom,bcm-voters = <&apps_bcm_voter>; 2487 }; 2488 2489 lpass_tlmm: pinctrl@33c0000 { 2490 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2491 reg = <0 0x033c0000 0x0 0x20000>, 2492 <0 0x03550000 0x0 0x10000>; 2493 qcom,adsp-bypass-mode; 2494 gpio-controller; 2495 #gpio-cells = <2>; 2496 gpio-ranges = <&lpass_tlmm 0 0 15>; 2497 2498 lpass_dmic01_clk: dmic01-clk-state { 2499 pins = "gpio6"; 2500 function = "dmic1_clk"; 2501 }; 2502 2503 lpass_dmic01_data: dmic01-data-state { 2504 pins = "gpio7"; 2505 function = "dmic1_data"; 2506 }; 2507 2508 lpass_dmic23_clk: dmic23-clk-state { 2509 pins = "gpio8"; 2510 function = "dmic2_clk"; 2511 }; 2512 2513 lpass_dmic23_data: dmic23-data-state { 2514 pins = "gpio9"; 2515 function = "dmic2_data"; 2516 }; 2517 2518 lpass_rx_swr_clk: rx-swr-clk-state { 2519 pins = "gpio3"; 2520 function = "swr_rx_clk"; 2521 }; 2522 2523 lpass_rx_swr_data: rx-swr-data-state { 2524 pins = "gpio4", "gpio5"; 2525 function = "swr_rx_data"; 2526 }; 2527 2528 lpass_tx_swr_clk: tx-swr-clk-state { 2529 pins = "gpio0"; 2530 function = "swr_tx_clk"; 2531 }; 2532 2533 lpass_tx_swr_data: tx-swr-data-state { 2534 pins = "gpio1", "gpio2", "gpio14"; 2535 function = "swr_tx_data"; 2536 }; 2537 }; 2538 2539 gpu: gpu@3d00000 { 2540 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2541 reg = <0 0x03d00000 0 0x40000>, 2542 <0 0x03d9e000 0 0x1000>, 2543 <0 0x03d61000 0 0x800>; 2544 reg-names = "kgsl_3d0_reg_memory", 2545 "cx_mem", 2546 "cx_dbgc"; 2547 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2548 iommus = <&adreno_smmu 0 0x401>; 2549 operating-points-v2 = <&gpu_opp_table>; 2550 qcom,gmu = <&gmu>; 2551 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2552 interconnect-names = "gfx-mem"; 2553 #cooling-cells = <2>; 2554 2555 nvmem-cells = <&gpu_speed_bin>; 2556 nvmem-cell-names = "speed_bin"; 2557 2558 gpu_opp_table: opp-table { 2559 compatible = "operating-points-v2"; 2560 2561 opp-315000000 { 2562 opp-hz = /bits/ 64 <315000000>; 2563 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2564 opp-peak-kBps = <1804000>; 2565 opp-supported-hw = <0x03>; 2566 }; 2567 2568 opp-450000000 { 2569 opp-hz = /bits/ 64 <450000000>; 2570 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2571 opp-peak-kBps = <4068000>; 2572 opp-supported-hw = <0x03>; 2573 }; 2574 2575 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2576 opp-550000000-0 { 2577 opp-hz = /bits/ 64 <550000000>; 2578 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2579 opp-peak-kBps = <8368000>; 2580 opp-supported-hw = <0x01>; 2581 }; 2582 2583 opp-550000000-1 { 2584 opp-hz = /bits/ 64 <550000000>; 2585 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2586 opp-peak-kBps = <6832000>; 2587 opp-supported-hw = <0x02>; 2588 }; 2589 2590 opp-608000000 { 2591 opp-hz = /bits/ 64 <608000000>; 2592 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2593 opp-peak-kBps = <8368000>; 2594 opp-supported-hw = <0x02>; 2595 }; 2596 2597 opp-700000000 { 2598 opp-hz = /bits/ 64 <700000000>; 2599 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2600 opp-peak-kBps = <8532000>; 2601 opp-supported-hw = <0x02>; 2602 }; 2603 2604 opp-812000000 { 2605 opp-hz = /bits/ 64 <812000000>; 2606 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2607 opp-peak-kBps = <8532000>; 2608 opp-supported-hw = <0x02>; 2609 }; 2610 2611 opp-840000000 { 2612 opp-hz = /bits/ 64 <840000000>; 2613 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2614 opp-peak-kBps = <8532000>; 2615 opp-supported-hw = <0x02>; 2616 }; 2617 2618 opp-900000000 { 2619 opp-hz = /bits/ 64 <900000000>; 2620 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2621 opp-peak-kBps = <8532000>; 2622 opp-supported-hw = <0x02>; 2623 }; 2624 }; 2625 }; 2626 2627 gmu: gmu@3d6a000 { 2628 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2629 reg = <0 0x03d6a000 0 0x34000>, 2630 <0 0x3de0000 0 0x10000>, 2631 <0 0x0b290000 0 0x10000>; 2632 reg-names = "gmu", "rscc", "gmu_pdc"; 2633 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2634 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2635 interrupt-names = "hfi", "gmu"; 2636 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2637 <&gpucc GPU_CC_CXO_CLK>, 2638 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2639 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2640 <&gpucc GPU_CC_AHB_CLK>, 2641 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2642 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2643 clock-names = "gmu", 2644 "cxo", 2645 "axi", 2646 "memnoc", 2647 "ahb", 2648 "hub", 2649 "smmu_vote"; 2650 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2651 <&gpucc GPU_CC_GX_GDSC>; 2652 power-domain-names = "cx", 2653 "gx"; 2654 iommus = <&adreno_smmu 5 0x400>; 2655 operating-points-v2 = <&gmu_opp_table>; 2656 2657 gmu_opp_table: opp-table { 2658 compatible = "operating-points-v2"; 2659 2660 opp-200000000 { 2661 opp-hz = /bits/ 64 <200000000>; 2662 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2663 }; 2664 }; 2665 }; 2666 2667 gpucc: clock-controller@3d90000 { 2668 compatible = "qcom,sc7280-gpucc"; 2669 reg = <0 0x03d90000 0 0x9000>; 2670 clocks = <&rpmhcc RPMH_CXO_CLK>, 2671 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2672 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2673 clock-names = "bi_tcxo", 2674 "gcc_gpu_gpll0_clk_src", 2675 "gcc_gpu_gpll0_div_clk_src"; 2676 #clock-cells = <1>; 2677 #reset-cells = <1>; 2678 #power-domain-cells = <1>; 2679 }; 2680 2681 dma@117f000 { 2682 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 2683 reg = <0x0 0x0117f000 0x0 0x1000>, 2684 <0x0 0x01112000 0x0 0x6000>; 2685 }; 2686 2687 adreno_smmu: iommu@3da0000 { 2688 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2689 reg = <0 0x03da0000 0 0x20000>; 2690 #iommu-cells = <2>; 2691 #global-interrupts = <2>; 2692 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2693 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2694 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2695 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2696 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2697 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2698 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2699 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2700 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2701 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2702 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2703 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2704 2705 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2706 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2707 <&gpucc GPU_CC_AHB_CLK>, 2708 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2709 <&gpucc GPU_CC_CX_GMU_CLK>, 2710 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2711 <&gpucc GPU_CC_HUB_AON_CLK>; 2712 clock-names = "gcc_gpu_memnoc_gfx_clk", 2713 "gcc_gpu_snoc_dvm_gfx_clk", 2714 "gpu_cc_ahb_clk", 2715 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2716 "gpu_cc_cx_gmu_clk", 2717 "gpu_cc_hub_cx_int_clk", 2718 "gpu_cc_hub_aon_clk"; 2719 2720 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2721 }; 2722 2723 remoteproc_mpss: remoteproc@4080000 { 2724 compatible = "qcom,sc7280-mpss-pas"; 2725 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2726 reg-names = "qdsp6", "rmb"; 2727 2728 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2729 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2730 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2731 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2732 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2733 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2734 interrupt-names = "wdog", "fatal", "ready", "handover", 2735 "stop-ack", "shutdown-ack"; 2736 2737 clocks = <&rpmhcc RPMH_CXO_CLK>; 2738 clock-names = "xo"; 2739 2740 power-domains = <&rpmhpd SC7280_CX>, 2741 <&rpmhpd SC7280_MSS>; 2742 power-domain-names = "cx", "mss"; 2743 2744 memory-region = <&mpss_mem>; 2745 2746 qcom,qmp = <&aoss_qmp>; 2747 2748 qcom,smem-states = <&modem_smp2p_out 0>; 2749 qcom,smem-state-names = "stop"; 2750 2751 status = "disabled"; 2752 2753 glink-edge { 2754 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2755 IPCC_MPROC_SIGNAL_GLINK_QMP 2756 IRQ_TYPE_EDGE_RISING>; 2757 mboxes = <&ipcc IPCC_CLIENT_MPSS 2758 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2759 label = "modem"; 2760 qcom,remote-pid = <1>; 2761 }; 2762 }; 2763 2764 stm@6002000 { 2765 compatible = "arm,coresight-stm", "arm,primecell"; 2766 reg = <0 0x06002000 0 0x1000>, 2767 <0 0x16280000 0 0x180000>; 2768 reg-names = "stm-base", "stm-stimulus-base"; 2769 2770 clocks = <&aoss_qmp>; 2771 clock-names = "apb_pclk"; 2772 2773 out-ports { 2774 port { 2775 stm_out: endpoint { 2776 remote-endpoint = <&funnel0_in7>; 2777 }; 2778 }; 2779 }; 2780 }; 2781 2782 funnel@6041000 { 2783 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2784 reg = <0 0x06041000 0 0x1000>; 2785 2786 clocks = <&aoss_qmp>; 2787 clock-names = "apb_pclk"; 2788 2789 out-ports { 2790 port { 2791 funnel0_out: endpoint { 2792 remote-endpoint = <&merge_funnel_in0>; 2793 }; 2794 }; 2795 }; 2796 2797 in-ports { 2798 #address-cells = <1>; 2799 #size-cells = <0>; 2800 2801 port@7 { 2802 reg = <7>; 2803 funnel0_in7: endpoint { 2804 remote-endpoint = <&stm_out>; 2805 }; 2806 }; 2807 }; 2808 }; 2809 2810 funnel@6042000 { 2811 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2812 reg = <0 0x06042000 0 0x1000>; 2813 2814 clocks = <&aoss_qmp>; 2815 clock-names = "apb_pclk"; 2816 2817 out-ports { 2818 port { 2819 funnel1_out: endpoint { 2820 remote-endpoint = <&merge_funnel_in1>; 2821 }; 2822 }; 2823 }; 2824 2825 in-ports { 2826 #address-cells = <1>; 2827 #size-cells = <0>; 2828 2829 port@4 { 2830 reg = <4>; 2831 funnel1_in4: endpoint { 2832 remote-endpoint = <&apss_merge_funnel_out>; 2833 }; 2834 }; 2835 }; 2836 }; 2837 2838 funnel@6045000 { 2839 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2840 reg = <0 0x06045000 0 0x1000>; 2841 2842 clocks = <&aoss_qmp>; 2843 clock-names = "apb_pclk"; 2844 2845 out-ports { 2846 port { 2847 merge_funnel_out: endpoint { 2848 remote-endpoint = <&swao_funnel_in>; 2849 }; 2850 }; 2851 }; 2852 2853 in-ports { 2854 #address-cells = <1>; 2855 #size-cells = <0>; 2856 2857 port@0 { 2858 reg = <0>; 2859 merge_funnel_in0: endpoint { 2860 remote-endpoint = <&funnel0_out>; 2861 }; 2862 }; 2863 2864 port@1 { 2865 reg = <1>; 2866 merge_funnel_in1: endpoint { 2867 remote-endpoint = <&funnel1_out>; 2868 }; 2869 }; 2870 }; 2871 }; 2872 2873 replicator@6046000 { 2874 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2875 reg = <0 0x06046000 0 0x1000>; 2876 2877 clocks = <&aoss_qmp>; 2878 clock-names = "apb_pclk"; 2879 2880 out-ports { 2881 port { 2882 replicator_out: endpoint { 2883 remote-endpoint = <&etr_in>; 2884 }; 2885 }; 2886 }; 2887 2888 in-ports { 2889 port { 2890 replicator_in: endpoint { 2891 remote-endpoint = <&swao_replicator_out>; 2892 }; 2893 }; 2894 }; 2895 }; 2896 2897 etr@6048000 { 2898 compatible = "arm,coresight-tmc", "arm,primecell"; 2899 reg = <0 0x06048000 0 0x1000>; 2900 iommus = <&apps_smmu 0x04c0 0>; 2901 2902 clocks = <&aoss_qmp>; 2903 clock-names = "apb_pclk"; 2904 arm,scatter-gather; 2905 2906 in-ports { 2907 port { 2908 etr_in: endpoint { 2909 remote-endpoint = <&replicator_out>; 2910 }; 2911 }; 2912 }; 2913 }; 2914 2915 funnel@6b04000 { 2916 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2917 reg = <0 0x06b04000 0 0x1000>; 2918 2919 clocks = <&aoss_qmp>; 2920 clock-names = "apb_pclk"; 2921 2922 out-ports { 2923 port { 2924 swao_funnel_out: endpoint { 2925 remote-endpoint = <&etf_in>; 2926 }; 2927 }; 2928 }; 2929 2930 in-ports { 2931 #address-cells = <1>; 2932 #size-cells = <0>; 2933 2934 port@7 { 2935 reg = <7>; 2936 swao_funnel_in: endpoint { 2937 remote-endpoint = <&merge_funnel_out>; 2938 }; 2939 }; 2940 }; 2941 }; 2942 2943 etf@6b05000 { 2944 compatible = "arm,coresight-tmc", "arm,primecell"; 2945 reg = <0 0x06b05000 0 0x1000>; 2946 2947 clocks = <&aoss_qmp>; 2948 clock-names = "apb_pclk"; 2949 2950 out-ports { 2951 port { 2952 etf_out: endpoint { 2953 remote-endpoint = <&swao_replicator_in>; 2954 }; 2955 }; 2956 }; 2957 2958 in-ports { 2959 port { 2960 etf_in: endpoint { 2961 remote-endpoint = <&swao_funnel_out>; 2962 }; 2963 }; 2964 }; 2965 }; 2966 2967 replicator@6b06000 { 2968 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2969 reg = <0 0x06b06000 0 0x1000>; 2970 2971 clocks = <&aoss_qmp>; 2972 clock-names = "apb_pclk"; 2973 qcom,replicator-loses-context; 2974 2975 out-ports { 2976 port { 2977 swao_replicator_out: endpoint { 2978 remote-endpoint = <&replicator_in>; 2979 }; 2980 }; 2981 }; 2982 2983 in-ports { 2984 port { 2985 swao_replicator_in: endpoint { 2986 remote-endpoint = <&etf_out>; 2987 }; 2988 }; 2989 }; 2990 }; 2991 2992 etm@7040000 { 2993 compatible = "arm,coresight-etm4x", "arm,primecell"; 2994 reg = <0 0x07040000 0 0x1000>; 2995 2996 cpu = <&CPU0>; 2997 2998 clocks = <&aoss_qmp>; 2999 clock-names = "apb_pclk"; 3000 arm,coresight-loses-context-with-cpu; 3001 qcom,skip-power-up; 3002 3003 out-ports { 3004 port { 3005 etm0_out: endpoint { 3006 remote-endpoint = <&apss_funnel_in0>; 3007 }; 3008 }; 3009 }; 3010 }; 3011 3012 etm@7140000 { 3013 compatible = "arm,coresight-etm4x", "arm,primecell"; 3014 reg = <0 0x07140000 0 0x1000>; 3015 3016 cpu = <&CPU1>; 3017 3018 clocks = <&aoss_qmp>; 3019 clock-names = "apb_pclk"; 3020 arm,coresight-loses-context-with-cpu; 3021 qcom,skip-power-up; 3022 3023 out-ports { 3024 port { 3025 etm1_out: endpoint { 3026 remote-endpoint = <&apss_funnel_in1>; 3027 }; 3028 }; 3029 }; 3030 }; 3031 3032 etm@7240000 { 3033 compatible = "arm,coresight-etm4x", "arm,primecell"; 3034 reg = <0 0x07240000 0 0x1000>; 3035 3036 cpu = <&CPU2>; 3037 3038 clocks = <&aoss_qmp>; 3039 clock-names = "apb_pclk"; 3040 arm,coresight-loses-context-with-cpu; 3041 qcom,skip-power-up; 3042 3043 out-ports { 3044 port { 3045 etm2_out: endpoint { 3046 remote-endpoint = <&apss_funnel_in2>; 3047 }; 3048 }; 3049 }; 3050 }; 3051 3052 etm@7340000 { 3053 compatible = "arm,coresight-etm4x", "arm,primecell"; 3054 reg = <0 0x07340000 0 0x1000>; 3055 3056 cpu = <&CPU3>; 3057 3058 clocks = <&aoss_qmp>; 3059 clock-names = "apb_pclk"; 3060 arm,coresight-loses-context-with-cpu; 3061 qcom,skip-power-up; 3062 3063 out-ports { 3064 port { 3065 etm3_out: endpoint { 3066 remote-endpoint = <&apss_funnel_in3>; 3067 }; 3068 }; 3069 }; 3070 }; 3071 3072 etm@7440000 { 3073 compatible = "arm,coresight-etm4x", "arm,primecell"; 3074 reg = <0 0x07440000 0 0x1000>; 3075 3076 cpu = <&CPU4>; 3077 3078 clocks = <&aoss_qmp>; 3079 clock-names = "apb_pclk"; 3080 arm,coresight-loses-context-with-cpu; 3081 qcom,skip-power-up; 3082 3083 out-ports { 3084 port { 3085 etm4_out: endpoint { 3086 remote-endpoint = <&apss_funnel_in4>; 3087 }; 3088 }; 3089 }; 3090 }; 3091 3092 etm@7540000 { 3093 compatible = "arm,coresight-etm4x", "arm,primecell"; 3094 reg = <0 0x07540000 0 0x1000>; 3095 3096 cpu = <&CPU5>; 3097 3098 clocks = <&aoss_qmp>; 3099 clock-names = "apb_pclk"; 3100 arm,coresight-loses-context-with-cpu; 3101 qcom,skip-power-up; 3102 3103 out-ports { 3104 port { 3105 etm5_out: endpoint { 3106 remote-endpoint = <&apss_funnel_in5>; 3107 }; 3108 }; 3109 }; 3110 }; 3111 3112 etm@7640000 { 3113 compatible = "arm,coresight-etm4x", "arm,primecell"; 3114 reg = <0 0x07640000 0 0x1000>; 3115 3116 cpu = <&CPU6>; 3117 3118 clocks = <&aoss_qmp>; 3119 clock-names = "apb_pclk"; 3120 arm,coresight-loses-context-with-cpu; 3121 qcom,skip-power-up; 3122 3123 out-ports { 3124 port { 3125 etm6_out: endpoint { 3126 remote-endpoint = <&apss_funnel_in6>; 3127 }; 3128 }; 3129 }; 3130 }; 3131 3132 etm@7740000 { 3133 compatible = "arm,coresight-etm4x", "arm,primecell"; 3134 reg = <0 0x07740000 0 0x1000>; 3135 3136 cpu = <&CPU7>; 3137 3138 clocks = <&aoss_qmp>; 3139 clock-names = "apb_pclk"; 3140 arm,coresight-loses-context-with-cpu; 3141 qcom,skip-power-up; 3142 3143 out-ports { 3144 port { 3145 etm7_out: endpoint { 3146 remote-endpoint = <&apss_funnel_in7>; 3147 }; 3148 }; 3149 }; 3150 }; 3151 3152 funnel@7800000 { /* APSS Funnel */ 3153 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3154 reg = <0 0x07800000 0 0x1000>; 3155 3156 clocks = <&aoss_qmp>; 3157 clock-names = "apb_pclk"; 3158 3159 out-ports { 3160 port { 3161 apss_funnel_out: endpoint { 3162 remote-endpoint = <&apss_merge_funnel_in>; 3163 }; 3164 }; 3165 }; 3166 3167 in-ports { 3168 #address-cells = <1>; 3169 #size-cells = <0>; 3170 3171 port@0 { 3172 reg = <0>; 3173 apss_funnel_in0: endpoint { 3174 remote-endpoint = <&etm0_out>; 3175 }; 3176 }; 3177 3178 port@1 { 3179 reg = <1>; 3180 apss_funnel_in1: endpoint { 3181 remote-endpoint = <&etm1_out>; 3182 }; 3183 }; 3184 3185 port@2 { 3186 reg = <2>; 3187 apss_funnel_in2: endpoint { 3188 remote-endpoint = <&etm2_out>; 3189 }; 3190 }; 3191 3192 port@3 { 3193 reg = <3>; 3194 apss_funnel_in3: endpoint { 3195 remote-endpoint = <&etm3_out>; 3196 }; 3197 }; 3198 3199 port@4 { 3200 reg = <4>; 3201 apss_funnel_in4: endpoint { 3202 remote-endpoint = <&etm4_out>; 3203 }; 3204 }; 3205 3206 port@5 { 3207 reg = <5>; 3208 apss_funnel_in5: endpoint { 3209 remote-endpoint = <&etm5_out>; 3210 }; 3211 }; 3212 3213 port@6 { 3214 reg = <6>; 3215 apss_funnel_in6: endpoint { 3216 remote-endpoint = <&etm6_out>; 3217 }; 3218 }; 3219 3220 port@7 { 3221 reg = <7>; 3222 apss_funnel_in7: endpoint { 3223 remote-endpoint = <&etm7_out>; 3224 }; 3225 }; 3226 }; 3227 }; 3228 3229 funnel@7810000 { 3230 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3231 reg = <0 0x07810000 0 0x1000>; 3232 3233 clocks = <&aoss_qmp>; 3234 clock-names = "apb_pclk"; 3235 3236 out-ports { 3237 port { 3238 apss_merge_funnel_out: endpoint { 3239 remote-endpoint = <&funnel1_in4>; 3240 }; 3241 }; 3242 }; 3243 3244 in-ports { 3245 port { 3246 apss_merge_funnel_in: endpoint { 3247 remote-endpoint = <&apss_funnel_out>; 3248 }; 3249 }; 3250 }; 3251 }; 3252 3253 sdhc_2: mmc@8804000 { 3254 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3255 pinctrl-names = "default", "sleep"; 3256 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3257 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3258 status = "disabled"; 3259 3260 reg = <0 0x08804000 0 0x1000>; 3261 3262 iommus = <&apps_smmu 0x100 0x0>; 3263 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3264 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3265 interrupt-names = "hc_irq", "pwr_irq"; 3266 3267 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3268 <&gcc GCC_SDCC2_APPS_CLK>, 3269 <&rpmhcc RPMH_CXO_CLK>; 3270 clock-names = "iface", "core", "xo"; 3271 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3272 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3273 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3274 power-domains = <&rpmhpd SC7280_CX>; 3275 operating-points-v2 = <&sdhc2_opp_table>; 3276 3277 bus-width = <4>; 3278 3279 qcom,dll-config = <0x0007642c>; 3280 3281 resets = <&gcc GCC_SDCC2_BCR>; 3282 3283 sdhc2_opp_table: opp-table { 3284 compatible = "operating-points-v2"; 3285 3286 opp-100000000 { 3287 opp-hz = /bits/ 64 <100000000>; 3288 required-opps = <&rpmhpd_opp_low_svs>; 3289 opp-peak-kBps = <1800000 400000>; 3290 opp-avg-kBps = <100000 0>; 3291 }; 3292 3293 opp-202000000 { 3294 opp-hz = /bits/ 64 <202000000>; 3295 required-opps = <&rpmhpd_opp_nom>; 3296 opp-peak-kBps = <5400000 1600000>; 3297 opp-avg-kBps = <200000 0>; 3298 }; 3299 }; 3300 3301 }; 3302 3303 usb_1_hsphy: phy@88e3000 { 3304 compatible = "qcom,sc7280-usb-hs-phy", 3305 "qcom,usb-snps-hs-7nm-phy"; 3306 reg = <0 0x088e3000 0 0x400>; 3307 status = "disabled"; 3308 #phy-cells = <0>; 3309 3310 clocks = <&rpmhcc RPMH_CXO_CLK>; 3311 clock-names = "ref"; 3312 3313 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3314 }; 3315 3316 usb_2_hsphy: phy@88e4000 { 3317 compatible = "qcom,sc7280-usb-hs-phy", 3318 "qcom,usb-snps-hs-7nm-phy"; 3319 reg = <0 0x088e4000 0 0x400>; 3320 status = "disabled"; 3321 #phy-cells = <0>; 3322 3323 clocks = <&rpmhcc RPMH_CXO_CLK>; 3324 clock-names = "ref"; 3325 3326 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3327 }; 3328 3329 usb_1_qmpphy: phy-wrapper@88e9000 { 3330 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3331 "qcom,sm8250-qmp-usb3-dp-phy"; 3332 reg = <0 0x088e9000 0 0x200>, 3333 <0 0x088e8000 0 0x40>, 3334 <0 0x088ea000 0 0x200>; 3335 status = "disabled"; 3336 #address-cells = <2>; 3337 #size-cells = <2>; 3338 ranges; 3339 3340 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3341 <&rpmhcc RPMH_CXO_CLK>, 3342 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3343 clock-names = "aux", "ref_clk_src", "com_aux"; 3344 3345 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3346 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3347 reset-names = "phy", "common"; 3348 3349 usb_1_ssphy: usb3-phy@88e9200 { 3350 reg = <0 0x088e9200 0 0x200>, 3351 <0 0x088e9400 0 0x200>, 3352 <0 0x088e9c00 0 0x400>, 3353 <0 0x088e9600 0 0x200>, 3354 <0 0x088e9800 0 0x200>, 3355 <0 0x088e9a00 0 0x100>; 3356 #clock-cells = <0>; 3357 #phy-cells = <0>; 3358 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3359 clock-names = "pipe0"; 3360 clock-output-names = "usb3_phy_pipe_clk_src"; 3361 }; 3362 3363 dp_phy: dp-phy@88ea200 { 3364 reg = <0 0x088ea200 0 0x200>, 3365 <0 0x088ea400 0 0x200>, 3366 <0 0x088eaa00 0 0x200>, 3367 <0 0x088ea600 0 0x200>, 3368 <0 0x088ea800 0 0x200>; 3369 #phy-cells = <0>; 3370 #clock-cells = <1>; 3371 }; 3372 }; 3373 3374 usb_2: usb@8cf8800 { 3375 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3376 reg = <0 0x08cf8800 0 0x400>; 3377 status = "disabled"; 3378 #address-cells = <2>; 3379 #size-cells = <2>; 3380 ranges; 3381 dma-ranges; 3382 3383 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3384 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3385 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3386 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3387 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3388 clock-names = "cfg_noc", 3389 "core", 3390 "iface", 3391 "sleep", 3392 "mock_utmi"; 3393 3394 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3395 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3396 assigned-clock-rates = <19200000>, <200000000>; 3397 3398 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3399 <&pdc 12 IRQ_TYPE_EDGE_RISING>, 3400 <&pdc 13 IRQ_TYPE_EDGE_RISING>; 3401 interrupt-names = "hs_phy_irq", 3402 "dp_hs_phy_irq", 3403 "dm_hs_phy_irq"; 3404 3405 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3406 required-opps = <&rpmhpd_opp_nom>; 3407 3408 resets = <&gcc GCC_USB30_SEC_BCR>; 3409 3410 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3411 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3412 interconnect-names = "usb-ddr", "apps-usb"; 3413 3414 usb_2_dwc3: usb@8c00000 { 3415 compatible = "snps,dwc3"; 3416 reg = <0 0x08c00000 0 0xe000>; 3417 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3418 iommus = <&apps_smmu 0xa0 0x0>; 3419 snps,dis_u2_susphy_quirk; 3420 snps,dis_enblslpm_quirk; 3421 phys = <&usb_2_hsphy>; 3422 phy-names = "usb2-phy"; 3423 maximum-speed = "high-speed"; 3424 usb-role-switch; 3425 port { 3426 usb2_role_switch: endpoint { 3427 remote-endpoint = <&eud_ep>; 3428 }; 3429 }; 3430 }; 3431 }; 3432 3433 qspi: spi@88dc000 { 3434 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3435 reg = <0 0x088dc000 0 0x1000>; 3436 #address-cells = <1>; 3437 #size-cells = <0>; 3438 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3439 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3440 <&gcc GCC_QSPI_CORE_CLK>; 3441 clock-names = "iface", "core"; 3442 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3443 &cnoc2 SLAVE_QSPI_0 0>; 3444 interconnect-names = "qspi-config"; 3445 power-domains = <&rpmhpd SC7280_CX>; 3446 operating-points-v2 = <&qspi_opp_table>; 3447 status = "disabled"; 3448 }; 3449 3450 remoteproc_wpss: remoteproc@8a00000 { 3451 compatible = "qcom,sc7280-wpss-pil"; 3452 reg = <0 0x08a00000 0 0x10000>; 3453 3454 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3455 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3456 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3457 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3458 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3459 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3460 interrupt-names = "wdog", "fatal", "ready", "handover", 3461 "stop-ack", "shutdown-ack"; 3462 3463 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3464 <&gcc GCC_WPSS_AHB_CLK>, 3465 <&gcc GCC_WPSS_RSCP_CLK>, 3466 <&rpmhcc RPMH_CXO_CLK>; 3467 clock-names = "ahb_bdg", "ahb", 3468 "rscp", "xo"; 3469 3470 power-domains = <&rpmhpd SC7280_CX>, 3471 <&rpmhpd SC7280_MX>; 3472 power-domain-names = "cx", "mx"; 3473 3474 memory-region = <&wpss_mem>; 3475 3476 qcom,qmp = <&aoss_qmp>; 3477 3478 qcom,smem-states = <&wpss_smp2p_out 0>; 3479 qcom,smem-state-names = "stop"; 3480 3481 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3482 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3483 reset-names = "restart", "pdc_sync"; 3484 3485 qcom,halt-regs = <&tcsr_1 0x17000>; 3486 3487 status = "disabled"; 3488 3489 glink-edge { 3490 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3491 IPCC_MPROC_SIGNAL_GLINK_QMP 3492 IRQ_TYPE_EDGE_RISING>; 3493 mboxes = <&ipcc IPCC_CLIENT_WPSS 3494 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3495 3496 label = "wpss"; 3497 qcom,remote-pid = <13>; 3498 }; 3499 }; 3500 3501 pmu@9091000 { 3502 compatible = "qcom,sc7280-llcc-bwmon"; 3503 reg = <0 0x09091000 0 0x1000>; 3504 3505 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3506 3507 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3508 3509 operating-points-v2 = <&llcc_bwmon_opp_table>; 3510 3511 llcc_bwmon_opp_table: opp-table { 3512 compatible = "operating-points-v2"; 3513 3514 opp-0 { 3515 opp-peak-kBps = <800000>; 3516 }; 3517 opp-1 { 3518 opp-peak-kBps = <1804000>; 3519 }; 3520 opp-2 { 3521 opp-peak-kBps = <2188000>; 3522 }; 3523 opp-3 { 3524 opp-peak-kBps = <3072000>; 3525 }; 3526 opp-4 { 3527 opp-peak-kBps = <4068000>; 3528 }; 3529 opp-5 { 3530 opp-peak-kBps = <6220000>; 3531 }; 3532 opp-6 { 3533 opp-peak-kBps = <6832000>; 3534 }; 3535 opp-7 { 3536 opp-peak-kBps = <8532000>; 3537 }; 3538 }; 3539 }; 3540 3541 pmu@90b6400 { 3542 compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon"; 3543 reg = <0 0x090b6400 0 0x600>; 3544 3545 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3546 3547 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3548 operating-points-v2 = <&cpu_bwmon_opp_table>; 3549 3550 cpu_bwmon_opp_table: opp-table { 3551 compatible = "operating-points-v2"; 3552 3553 opp-0 { 3554 opp-peak-kBps = <2400000>; 3555 }; 3556 opp-1 { 3557 opp-peak-kBps = <4800000>; 3558 }; 3559 opp-2 { 3560 opp-peak-kBps = <7456000>; 3561 }; 3562 opp-3 { 3563 opp-peak-kBps = <9600000>; 3564 }; 3565 opp-4 { 3566 opp-peak-kBps = <12896000>; 3567 }; 3568 opp-5 { 3569 opp-peak-kBps = <14928000>; 3570 }; 3571 opp-6 { 3572 opp-peak-kBps = <17056000>; 3573 }; 3574 }; 3575 }; 3576 3577 dc_noc: interconnect@90e0000 { 3578 reg = <0 0x090e0000 0 0x5080>; 3579 compatible = "qcom,sc7280-dc-noc"; 3580 #interconnect-cells = <2>; 3581 qcom,bcm-voters = <&apps_bcm_voter>; 3582 }; 3583 3584 gem_noc: interconnect@9100000 { 3585 reg = <0 0x09100000 0 0xe2200>; 3586 compatible = "qcom,sc7280-gem-noc"; 3587 #interconnect-cells = <2>; 3588 qcom,bcm-voters = <&apps_bcm_voter>; 3589 }; 3590 3591 system-cache-controller@9200000 { 3592 compatible = "qcom,sc7280-llcc"; 3593 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 3594 reg-names = "llcc_base", "llcc_broadcast_base"; 3595 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3596 }; 3597 3598 eud: eud@88e0000 { 3599 compatible = "qcom,sc7280-eud","qcom,eud"; 3600 reg = <0 0x088e0000 0 0x2000>, 3601 <0 0x088e2000 0 0x1000>; 3602 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3603 ports { 3604 port@0 { 3605 eud_ep: endpoint { 3606 remote-endpoint = <&usb2_role_switch>; 3607 }; 3608 }; 3609 port@1 { 3610 eud_con: endpoint { 3611 remote-endpoint = <&con_eud>; 3612 }; 3613 }; 3614 }; 3615 }; 3616 3617 eud_typec: connector { 3618 compatible = "usb-c-connector"; 3619 ports { 3620 port@0 { 3621 con_eud: endpoint { 3622 remote-endpoint = <&eud_con>; 3623 }; 3624 }; 3625 }; 3626 }; 3627 3628 nsp_noc: interconnect@a0c0000 { 3629 reg = <0 0x0a0c0000 0 0x10000>; 3630 compatible = "qcom,sc7280-nsp-noc"; 3631 #interconnect-cells = <2>; 3632 qcom,bcm-voters = <&apps_bcm_voter>; 3633 }; 3634 3635 usb_1: usb@a6f8800 { 3636 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3637 reg = <0 0x0a6f8800 0 0x400>; 3638 status = "disabled"; 3639 #address-cells = <2>; 3640 #size-cells = <2>; 3641 ranges; 3642 dma-ranges; 3643 3644 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3645 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3646 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3647 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3648 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3649 clock-names = "cfg_noc", 3650 "core", 3651 "iface", 3652 "sleep", 3653 "mock_utmi"; 3654 3655 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3656 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3657 assigned-clock-rates = <19200000>, <200000000>; 3658 3659 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3660 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3661 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3662 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3663 interrupt-names = "hs_phy_irq", 3664 "dp_hs_phy_irq", 3665 "dm_hs_phy_irq", 3666 "ss_phy_irq"; 3667 3668 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3669 required-opps = <&rpmhpd_opp_nom>; 3670 3671 resets = <&gcc GCC_USB30_PRIM_BCR>; 3672 3673 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3674 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3675 interconnect-names = "usb-ddr", "apps-usb"; 3676 3677 wakeup-source; 3678 3679 usb_1_dwc3: usb@a600000 { 3680 compatible = "snps,dwc3"; 3681 reg = <0 0x0a600000 0 0xe000>; 3682 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3683 iommus = <&apps_smmu 0xe0 0x0>; 3684 snps,dis_u2_susphy_quirk; 3685 snps,dis_enblslpm_quirk; 3686 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3687 phy-names = "usb2-phy", "usb3-phy"; 3688 maximum-speed = "super-speed"; 3689 }; 3690 }; 3691 3692 venus: video-codec@aa00000 { 3693 compatible = "qcom,sc7280-venus"; 3694 reg = <0 0x0aa00000 0 0xd0600>; 3695 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3696 3697 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3698 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3699 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3700 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3701 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3702 clock-names = "core", "bus", "iface", 3703 "vcodec_core", "vcodec_bus"; 3704 3705 power-domains = <&videocc MVSC_GDSC>, 3706 <&videocc MVS0_GDSC>, 3707 <&rpmhpd SC7280_CX>; 3708 power-domain-names = "venus", "vcodec0", "cx"; 3709 operating-points-v2 = <&venus_opp_table>; 3710 3711 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3712 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3713 interconnect-names = "cpu-cfg", "video-mem"; 3714 3715 iommus = <&apps_smmu 0x2180 0x20>, 3716 <&apps_smmu 0x2184 0x20>; 3717 memory-region = <&video_mem>; 3718 3719 video-decoder { 3720 compatible = "venus-decoder"; 3721 }; 3722 3723 video-encoder { 3724 compatible = "venus-encoder"; 3725 }; 3726 3727 video-firmware { 3728 iommus = <&apps_smmu 0x21a2 0x0>; 3729 }; 3730 3731 venus_opp_table: opp-table { 3732 compatible = "operating-points-v2"; 3733 3734 opp-133330000 { 3735 opp-hz = /bits/ 64 <133330000>; 3736 required-opps = <&rpmhpd_opp_low_svs>; 3737 }; 3738 3739 opp-240000000 { 3740 opp-hz = /bits/ 64 <240000000>; 3741 required-opps = <&rpmhpd_opp_svs>; 3742 }; 3743 3744 opp-335000000 { 3745 opp-hz = /bits/ 64 <335000000>; 3746 required-opps = <&rpmhpd_opp_svs_l1>; 3747 }; 3748 3749 opp-424000000 { 3750 opp-hz = /bits/ 64 <424000000>; 3751 required-opps = <&rpmhpd_opp_nom>; 3752 }; 3753 3754 opp-460000048 { 3755 opp-hz = /bits/ 64 <460000048>; 3756 required-opps = <&rpmhpd_opp_turbo>; 3757 }; 3758 }; 3759 3760 }; 3761 3762 videocc: clock-controller@aaf0000 { 3763 compatible = "qcom,sc7280-videocc"; 3764 reg = <0 0x0aaf0000 0 0x10000>; 3765 clocks = <&rpmhcc RPMH_CXO_CLK>, 3766 <&rpmhcc RPMH_CXO_CLK_A>; 3767 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3768 #clock-cells = <1>; 3769 #reset-cells = <1>; 3770 #power-domain-cells = <1>; 3771 }; 3772 3773 camcc: clock-controller@ad00000 { 3774 compatible = "qcom,sc7280-camcc"; 3775 reg = <0 0x0ad00000 0 0x10000>; 3776 clocks = <&rpmhcc RPMH_CXO_CLK>, 3777 <&rpmhcc RPMH_CXO_CLK_A>, 3778 <&sleep_clk>; 3779 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3780 #clock-cells = <1>; 3781 #reset-cells = <1>; 3782 #power-domain-cells = <1>; 3783 }; 3784 3785 dispcc: clock-controller@af00000 { 3786 compatible = "qcom,sc7280-dispcc"; 3787 reg = <0 0x0af00000 0 0x20000>; 3788 clocks = <&rpmhcc RPMH_CXO_CLK>, 3789 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3790 <&mdss_dsi_phy 0>, 3791 <&mdss_dsi_phy 1>, 3792 <&dp_phy 0>, 3793 <&dp_phy 1>, 3794 <&mdss_edp_phy 0>, 3795 <&mdss_edp_phy 1>; 3796 clock-names = "bi_tcxo", 3797 "gcc_disp_gpll0_clk", 3798 "dsi0_phy_pll_out_byteclk", 3799 "dsi0_phy_pll_out_dsiclk", 3800 "dp_phy_pll_link_clk", 3801 "dp_phy_pll_vco_div_clk", 3802 "edp_phy_pll_link_clk", 3803 "edp_phy_pll_vco_div_clk"; 3804 #clock-cells = <1>; 3805 #reset-cells = <1>; 3806 #power-domain-cells = <1>; 3807 }; 3808 3809 mdss: display-subsystem@ae00000 { 3810 compatible = "qcom,sc7280-mdss"; 3811 reg = <0 0x0ae00000 0 0x1000>; 3812 reg-names = "mdss"; 3813 3814 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3815 3816 clocks = <&gcc GCC_DISP_AHB_CLK>, 3817 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3818 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3819 clock-names = "iface", 3820 "ahb", 3821 "core"; 3822 3823 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3824 interrupt-controller; 3825 #interrupt-cells = <1>; 3826 3827 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3828 interconnect-names = "mdp0-mem"; 3829 3830 iommus = <&apps_smmu 0x900 0x402>; 3831 3832 #address-cells = <2>; 3833 #size-cells = <2>; 3834 ranges; 3835 3836 status = "disabled"; 3837 3838 mdss_mdp: display-controller@ae01000 { 3839 compatible = "qcom,sc7280-dpu"; 3840 reg = <0 0x0ae01000 0 0x8f030>, 3841 <0 0x0aeb0000 0 0x2008>; 3842 reg-names = "mdp", "vbif"; 3843 3844 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3845 <&gcc GCC_DISP_SF_AXI_CLK>, 3846 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3847 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3848 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3849 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3850 clock-names = "bus", 3851 "nrt_bus", 3852 "iface", 3853 "lut", 3854 "core", 3855 "vsync"; 3856 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3857 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3858 assigned-clock-rates = <19200000>, 3859 <19200000>; 3860 operating-points-v2 = <&mdp_opp_table>; 3861 power-domains = <&rpmhpd SC7280_CX>; 3862 3863 interrupt-parent = <&mdss>; 3864 interrupts = <0>; 3865 3866 status = "disabled"; 3867 3868 ports { 3869 #address-cells = <1>; 3870 #size-cells = <0>; 3871 3872 port@0 { 3873 reg = <0>; 3874 dpu_intf1_out: endpoint { 3875 remote-endpoint = <&dsi0_in>; 3876 }; 3877 }; 3878 3879 port@1 { 3880 reg = <1>; 3881 dpu_intf5_out: endpoint { 3882 remote-endpoint = <&edp_in>; 3883 }; 3884 }; 3885 3886 port@2 { 3887 reg = <2>; 3888 dpu_intf0_out: endpoint { 3889 remote-endpoint = <&dp_in>; 3890 }; 3891 }; 3892 }; 3893 3894 mdp_opp_table: opp-table { 3895 compatible = "operating-points-v2"; 3896 3897 opp-200000000 { 3898 opp-hz = /bits/ 64 <200000000>; 3899 required-opps = <&rpmhpd_opp_low_svs>; 3900 }; 3901 3902 opp-300000000 { 3903 opp-hz = /bits/ 64 <300000000>; 3904 required-opps = <&rpmhpd_opp_svs>; 3905 }; 3906 3907 opp-380000000 { 3908 opp-hz = /bits/ 64 <380000000>; 3909 required-opps = <&rpmhpd_opp_svs_l1>; 3910 }; 3911 3912 opp-506666667 { 3913 opp-hz = /bits/ 64 <506666667>; 3914 required-opps = <&rpmhpd_opp_nom>; 3915 }; 3916 }; 3917 }; 3918 3919 mdss_dsi: dsi@ae94000 { 3920 compatible = "qcom,sc7280-dsi-ctrl", 3921 "qcom,mdss-dsi-ctrl"; 3922 reg = <0 0x0ae94000 0 0x400>; 3923 reg-names = "dsi_ctrl"; 3924 3925 interrupt-parent = <&mdss>; 3926 interrupts = <4>; 3927 3928 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3929 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3930 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3931 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3932 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3933 <&gcc GCC_DISP_HF_AXI_CLK>; 3934 clock-names = "byte", 3935 "byte_intf", 3936 "pixel", 3937 "core", 3938 "iface", 3939 "bus"; 3940 3941 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3942 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; 3943 3944 operating-points-v2 = <&dsi_opp_table>; 3945 power-domains = <&rpmhpd SC7280_CX>; 3946 3947 phys = <&mdss_dsi_phy>; 3948 3949 #address-cells = <1>; 3950 #size-cells = <0>; 3951 3952 status = "disabled"; 3953 3954 ports { 3955 #address-cells = <1>; 3956 #size-cells = <0>; 3957 3958 port@0 { 3959 reg = <0>; 3960 dsi0_in: endpoint { 3961 remote-endpoint = <&dpu_intf1_out>; 3962 }; 3963 }; 3964 3965 port@1 { 3966 reg = <1>; 3967 dsi0_out: endpoint { 3968 }; 3969 }; 3970 }; 3971 3972 dsi_opp_table: opp-table { 3973 compatible = "operating-points-v2"; 3974 3975 opp-187500000 { 3976 opp-hz = /bits/ 64 <187500000>; 3977 required-opps = <&rpmhpd_opp_low_svs>; 3978 }; 3979 3980 opp-300000000 { 3981 opp-hz = /bits/ 64 <300000000>; 3982 required-opps = <&rpmhpd_opp_svs>; 3983 }; 3984 3985 opp-358000000 { 3986 opp-hz = /bits/ 64 <358000000>; 3987 required-opps = <&rpmhpd_opp_svs_l1>; 3988 }; 3989 }; 3990 }; 3991 3992 mdss_dsi_phy: phy@ae94400 { 3993 compatible = "qcom,sc7280-dsi-phy-7nm"; 3994 reg = <0 0x0ae94400 0 0x200>, 3995 <0 0x0ae94600 0 0x280>, 3996 <0 0x0ae94900 0 0x280>; 3997 reg-names = "dsi_phy", 3998 "dsi_phy_lane", 3999 "dsi_pll"; 4000 4001 #clock-cells = <1>; 4002 #phy-cells = <0>; 4003 4004 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4005 <&rpmhcc RPMH_CXO_CLK>; 4006 clock-names = "iface", "ref"; 4007 4008 status = "disabled"; 4009 }; 4010 4011 mdss_edp: edp@aea0000 { 4012 compatible = "qcom,sc7280-edp"; 4013 pinctrl-names = "default"; 4014 pinctrl-0 = <&edp_hot_plug_det>; 4015 4016 reg = <0 0x0aea0000 0 0x200>, 4017 <0 0x0aea0200 0 0x200>, 4018 <0 0x0aea0400 0 0xc00>, 4019 <0 0x0aea1000 0 0x400>; 4020 4021 interrupt-parent = <&mdss>; 4022 interrupts = <14>; 4023 4024 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4025 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4026 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4027 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4028 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4029 clock-names = "core_iface", 4030 "core_aux", 4031 "ctrl_link", 4032 "ctrl_link_iface", 4033 "stream_pixel"; 4034 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4035 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4036 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4037 4038 phys = <&mdss_edp_phy>; 4039 phy-names = "dp"; 4040 4041 operating-points-v2 = <&edp_opp_table>; 4042 power-domains = <&rpmhpd SC7280_CX>; 4043 4044 status = "disabled"; 4045 4046 ports { 4047 #address-cells = <1>; 4048 #size-cells = <0>; 4049 4050 port@0 { 4051 reg = <0>; 4052 edp_in: endpoint { 4053 remote-endpoint = <&dpu_intf5_out>; 4054 }; 4055 }; 4056 4057 port@1 { 4058 reg = <1>; 4059 mdss_edp_out: endpoint { }; 4060 }; 4061 }; 4062 4063 edp_opp_table: opp-table { 4064 compatible = "operating-points-v2"; 4065 4066 opp-160000000 { 4067 opp-hz = /bits/ 64 <160000000>; 4068 required-opps = <&rpmhpd_opp_low_svs>; 4069 }; 4070 4071 opp-270000000 { 4072 opp-hz = /bits/ 64 <270000000>; 4073 required-opps = <&rpmhpd_opp_svs>; 4074 }; 4075 4076 opp-540000000 { 4077 opp-hz = /bits/ 64 <540000000>; 4078 required-opps = <&rpmhpd_opp_nom>; 4079 }; 4080 4081 opp-810000000 { 4082 opp-hz = /bits/ 64 <810000000>; 4083 required-opps = <&rpmhpd_opp_nom>; 4084 }; 4085 }; 4086 }; 4087 4088 mdss_edp_phy: phy@aec2a00 { 4089 compatible = "qcom,sc7280-edp-phy"; 4090 4091 reg = <0 0x0aec2a00 0 0x19c>, 4092 <0 0x0aec2200 0 0xa0>, 4093 <0 0x0aec2600 0 0xa0>, 4094 <0 0x0aec2000 0 0x1c0>; 4095 4096 clocks = <&rpmhcc RPMH_CXO_CLK>, 4097 <&gcc GCC_EDP_CLKREF_EN>; 4098 clock-names = "aux", 4099 "cfg_ahb"; 4100 4101 #clock-cells = <1>; 4102 #phy-cells = <0>; 4103 4104 status = "disabled"; 4105 }; 4106 4107 mdss_dp: displayport-controller@ae90000 { 4108 compatible = "qcom,sc7280-dp"; 4109 4110 reg = <0 0x0ae90000 0 0x200>, 4111 <0 0x0ae90200 0 0x200>, 4112 <0 0x0ae90400 0 0xc00>, 4113 <0 0x0ae91000 0 0x400>, 4114 <0 0x0ae91400 0 0x400>; 4115 4116 interrupt-parent = <&mdss>; 4117 interrupts = <12>; 4118 4119 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4120 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4121 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4122 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4123 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4124 clock-names = "core_iface", 4125 "core_aux", 4126 "ctrl_link", 4127 "ctrl_link_iface", 4128 "stream_pixel"; 4129 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4130 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4131 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4132 phys = <&dp_phy>; 4133 phy-names = "dp"; 4134 4135 operating-points-v2 = <&dp_opp_table>; 4136 power-domains = <&rpmhpd SC7280_CX>; 4137 4138 #sound-dai-cells = <0>; 4139 4140 status = "disabled"; 4141 4142 ports { 4143 #address-cells = <1>; 4144 #size-cells = <0>; 4145 4146 port@0 { 4147 reg = <0>; 4148 dp_in: endpoint { 4149 remote-endpoint = <&dpu_intf0_out>; 4150 }; 4151 }; 4152 4153 port@1 { 4154 reg = <1>; 4155 mdss_dp_out: endpoint { }; 4156 }; 4157 }; 4158 4159 dp_opp_table: opp-table { 4160 compatible = "operating-points-v2"; 4161 4162 opp-160000000 { 4163 opp-hz = /bits/ 64 <160000000>; 4164 required-opps = <&rpmhpd_opp_low_svs>; 4165 }; 4166 4167 opp-270000000 { 4168 opp-hz = /bits/ 64 <270000000>; 4169 required-opps = <&rpmhpd_opp_svs>; 4170 }; 4171 4172 opp-540000000 { 4173 opp-hz = /bits/ 64 <540000000>; 4174 required-opps = <&rpmhpd_opp_svs_l1>; 4175 }; 4176 4177 opp-810000000 { 4178 opp-hz = /bits/ 64 <810000000>; 4179 required-opps = <&rpmhpd_opp_nom>; 4180 }; 4181 }; 4182 }; 4183 }; 4184 4185 pdc: interrupt-controller@b220000 { 4186 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4187 reg = <0 0x0b220000 0 0x30000>; 4188 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4189 <55 306 4>, <59 312 3>, <62 374 2>, 4190 <64 434 2>, <66 438 3>, <69 86 1>, 4191 <70 520 54>, <124 609 31>, <155 63 1>, 4192 <156 716 12>; 4193 #interrupt-cells = <2>; 4194 interrupt-parent = <&intc>; 4195 interrupt-controller; 4196 }; 4197 4198 pdc_reset: reset-controller@b5e0000 { 4199 compatible = "qcom,sc7280-pdc-global"; 4200 reg = <0 0x0b5e0000 0 0x20000>; 4201 #reset-cells = <1>; 4202 }; 4203 4204 tsens0: thermal-sensor@c263000 { 4205 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4206 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4207 <0 0x0c222000 0 0x1ff>; /* SROT */ 4208 #qcom,sensors = <15>; 4209 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4210 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4211 interrupt-names = "uplow","critical"; 4212 #thermal-sensor-cells = <1>; 4213 }; 4214 4215 tsens1: thermal-sensor@c265000 { 4216 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4217 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4218 <0 0x0c223000 0 0x1ff>; /* SROT */ 4219 #qcom,sensors = <12>; 4220 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4221 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4222 interrupt-names = "uplow","critical"; 4223 #thermal-sensor-cells = <1>; 4224 }; 4225 4226 aoss_reset: reset-controller@c2a0000 { 4227 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4228 reg = <0 0x0c2a0000 0 0x31000>; 4229 #reset-cells = <1>; 4230 }; 4231 4232 aoss_qmp: power-management@c300000 { 4233 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4234 reg = <0 0x0c300000 0 0x400>; 4235 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4236 IPCC_MPROC_SIGNAL_GLINK_QMP 4237 IRQ_TYPE_EDGE_RISING>; 4238 mboxes = <&ipcc IPCC_CLIENT_AOP 4239 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4240 4241 #clock-cells = <0>; 4242 }; 4243 4244 sram@c3f0000 { 4245 compatible = "qcom,rpmh-stats"; 4246 reg = <0 0x0c3f0000 0 0x400>; 4247 }; 4248 4249 spmi_bus: spmi@c440000 { 4250 compatible = "qcom,spmi-pmic-arb"; 4251 reg = <0 0x0c440000 0 0x1100>, 4252 <0 0x0c600000 0 0x2000000>, 4253 <0 0x0e600000 0 0x100000>, 4254 <0 0x0e700000 0 0xa0000>, 4255 <0 0x0c40a000 0 0x26000>; 4256 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4257 interrupt-names = "periph_irq"; 4258 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4259 qcom,ee = <0>; 4260 qcom,channel = <0>; 4261 #address-cells = <2>; 4262 #size-cells = <0>; 4263 interrupt-controller; 4264 #interrupt-cells = <4>; 4265 }; 4266 4267 tlmm: pinctrl@f100000 { 4268 compatible = "qcom,sc7280-pinctrl"; 4269 reg = <0 0x0f100000 0 0x300000>; 4270 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4271 gpio-controller; 4272 #gpio-cells = <2>; 4273 interrupt-controller; 4274 #interrupt-cells = <2>; 4275 gpio-ranges = <&tlmm 0 0 175>; 4276 wakeup-parent = <&pdc>; 4277 4278 dp_hot_plug_det: dp-hot-plug-det-state { 4279 pins = "gpio47"; 4280 function = "dp_hot"; 4281 }; 4282 4283 edp_hot_plug_det: edp-hot-plug-det-state { 4284 pins = "gpio60"; 4285 function = "edp_hot"; 4286 }; 4287 4288 mi2s0_data0: mi2s0-data0-state { 4289 pins = "gpio98"; 4290 function = "mi2s0_data0"; 4291 }; 4292 4293 mi2s0_data1: mi2s0-data1-state { 4294 pins = "gpio99"; 4295 function = "mi2s0_data1"; 4296 }; 4297 4298 mi2s0_mclk: mi2s0-mclk-state { 4299 pins = "gpio96"; 4300 function = "pri_mi2s"; 4301 }; 4302 4303 mi2s0_sclk: mi2s0-sclk-state { 4304 pins = "gpio97"; 4305 function = "mi2s0_sck"; 4306 }; 4307 4308 mi2s0_ws: mi2s0-ws-state { 4309 pins = "gpio100"; 4310 function = "mi2s0_ws"; 4311 }; 4312 4313 mi2s1_data0: mi2s1-data0-state { 4314 pins = "gpio107"; 4315 function = "mi2s1_data0"; 4316 }; 4317 4318 mi2s1_sclk: mi2s1-sclk-state { 4319 pins = "gpio106"; 4320 function = "mi2s1_sck"; 4321 }; 4322 4323 mi2s1_ws: mi2s1-ws-state { 4324 pins = "gpio108"; 4325 function = "mi2s1_ws"; 4326 }; 4327 4328 pcie1_clkreq_n: pcie1-clkreq-n-state { 4329 pins = "gpio79"; 4330 function = "pcie1_clkreqn"; 4331 }; 4332 4333 qspi_clk: qspi-clk-state { 4334 pins = "gpio14"; 4335 function = "qspi_clk"; 4336 }; 4337 4338 qspi_cs0: qspi-cs0-state { 4339 pins = "gpio15"; 4340 function = "qspi_cs"; 4341 }; 4342 4343 qspi_cs1: qspi-cs1-state { 4344 pins = "gpio19"; 4345 function = "qspi_cs"; 4346 }; 4347 4348 qspi_data01: qspi-data01-state { 4349 pins = "gpio12", "gpio13"; 4350 function = "qspi_data"; 4351 }; 4352 4353 qspi_data12: qspi-data12-state { 4354 pins = "gpio16", "gpio17"; 4355 function = "qspi_data"; 4356 }; 4357 4358 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4359 pins = "gpio0", "gpio1"; 4360 function = "qup00"; 4361 }; 4362 4363 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4364 pins = "gpio4", "gpio5"; 4365 function = "qup01"; 4366 }; 4367 4368 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4369 pins = "gpio8", "gpio9"; 4370 function = "qup02"; 4371 }; 4372 4373 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4374 pins = "gpio12", "gpio13"; 4375 function = "qup03"; 4376 }; 4377 4378 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4379 pins = "gpio16", "gpio17"; 4380 function = "qup04"; 4381 }; 4382 4383 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4384 pins = "gpio20", "gpio21"; 4385 function = "qup05"; 4386 }; 4387 4388 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4389 pins = "gpio24", "gpio25"; 4390 function = "qup06"; 4391 }; 4392 4393 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4394 pins = "gpio28", "gpio29"; 4395 function = "qup07"; 4396 }; 4397 4398 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4399 pins = "gpio32", "gpio33"; 4400 function = "qup10"; 4401 }; 4402 4403 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4404 pins = "gpio36", "gpio37"; 4405 function = "qup11"; 4406 }; 4407 4408 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4409 pins = "gpio40", "gpio41"; 4410 function = "qup12"; 4411 }; 4412 4413 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4414 pins = "gpio44", "gpio45"; 4415 function = "qup13"; 4416 }; 4417 4418 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4419 pins = "gpio48", "gpio49"; 4420 function = "qup14"; 4421 }; 4422 4423 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4424 pins = "gpio52", "gpio53"; 4425 function = "qup15"; 4426 }; 4427 4428 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4429 pins = "gpio56", "gpio57"; 4430 function = "qup16"; 4431 }; 4432 4433 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4434 pins = "gpio60", "gpio61"; 4435 function = "qup17"; 4436 }; 4437 4438 qup_spi0_data_clk: qup-spi0-data-clk-state { 4439 pins = "gpio0", "gpio1", "gpio2"; 4440 function = "qup00"; 4441 }; 4442 4443 qup_spi0_cs: qup-spi0-cs-state { 4444 pins = "gpio3"; 4445 function = "qup00"; 4446 }; 4447 4448 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4449 pins = "gpio3"; 4450 function = "gpio"; 4451 }; 4452 4453 qup_spi1_data_clk: qup-spi1-data-clk-state { 4454 pins = "gpio4", "gpio5", "gpio6"; 4455 function = "qup01"; 4456 }; 4457 4458 qup_spi1_cs: qup-spi1-cs-state { 4459 pins = "gpio7"; 4460 function = "qup01"; 4461 }; 4462 4463 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4464 pins = "gpio7"; 4465 function = "gpio"; 4466 }; 4467 4468 qup_spi2_data_clk: qup-spi2-data-clk-state { 4469 pins = "gpio8", "gpio9", "gpio10"; 4470 function = "qup02"; 4471 }; 4472 4473 qup_spi2_cs: qup-spi2-cs-state { 4474 pins = "gpio11"; 4475 function = "qup02"; 4476 }; 4477 4478 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4479 pins = "gpio11"; 4480 function = "gpio"; 4481 }; 4482 4483 qup_spi3_data_clk: qup-spi3-data-clk-state { 4484 pins = "gpio12", "gpio13", "gpio14"; 4485 function = "qup03"; 4486 }; 4487 4488 qup_spi3_cs: qup-spi3-cs-state { 4489 pins = "gpio15"; 4490 function = "qup03"; 4491 }; 4492 4493 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4494 pins = "gpio15"; 4495 function = "gpio"; 4496 }; 4497 4498 qup_spi4_data_clk: qup-spi4-data-clk-state { 4499 pins = "gpio16", "gpio17", "gpio18"; 4500 function = "qup04"; 4501 }; 4502 4503 qup_spi4_cs: qup-spi4-cs-state { 4504 pins = "gpio19"; 4505 function = "qup04"; 4506 }; 4507 4508 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4509 pins = "gpio19"; 4510 function = "gpio"; 4511 }; 4512 4513 qup_spi5_data_clk: qup-spi5-data-clk-state { 4514 pins = "gpio20", "gpio21", "gpio22"; 4515 function = "qup05"; 4516 }; 4517 4518 qup_spi5_cs: qup-spi5-cs-state { 4519 pins = "gpio23"; 4520 function = "qup05"; 4521 }; 4522 4523 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4524 pins = "gpio23"; 4525 function = "gpio"; 4526 }; 4527 4528 qup_spi6_data_clk: qup-spi6-data-clk-state { 4529 pins = "gpio24", "gpio25", "gpio26"; 4530 function = "qup06"; 4531 }; 4532 4533 qup_spi6_cs: qup-spi6-cs-state { 4534 pins = "gpio27"; 4535 function = "qup06"; 4536 }; 4537 4538 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4539 pins = "gpio27"; 4540 function = "gpio"; 4541 }; 4542 4543 qup_spi7_data_clk: qup-spi7-data-clk-state { 4544 pins = "gpio28", "gpio29", "gpio30"; 4545 function = "qup07"; 4546 }; 4547 4548 qup_spi7_cs: qup-spi7-cs-state { 4549 pins = "gpio31"; 4550 function = "qup07"; 4551 }; 4552 4553 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4554 pins = "gpio31"; 4555 function = "gpio"; 4556 }; 4557 4558 qup_spi8_data_clk: qup-spi8-data-clk-state { 4559 pins = "gpio32", "gpio33", "gpio34"; 4560 function = "qup10"; 4561 }; 4562 4563 qup_spi8_cs: qup-spi8-cs-state { 4564 pins = "gpio35"; 4565 function = "qup10"; 4566 }; 4567 4568 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4569 pins = "gpio35"; 4570 function = "gpio"; 4571 }; 4572 4573 qup_spi9_data_clk: qup-spi9-data-clk-state { 4574 pins = "gpio36", "gpio37", "gpio38"; 4575 function = "qup11"; 4576 }; 4577 4578 qup_spi9_cs: qup-spi9-cs-state { 4579 pins = "gpio39"; 4580 function = "qup11"; 4581 }; 4582 4583 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4584 pins = "gpio39"; 4585 function = "gpio"; 4586 }; 4587 4588 qup_spi10_data_clk: qup-spi10-data-clk-state { 4589 pins = "gpio40", "gpio41", "gpio42"; 4590 function = "qup12"; 4591 }; 4592 4593 qup_spi10_cs: qup-spi10-cs-state { 4594 pins = "gpio43"; 4595 function = "qup12"; 4596 }; 4597 4598 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4599 pins = "gpio43"; 4600 function = "gpio"; 4601 }; 4602 4603 qup_spi11_data_clk: qup-spi11-data-clk-state { 4604 pins = "gpio44", "gpio45", "gpio46"; 4605 function = "qup13"; 4606 }; 4607 4608 qup_spi11_cs: qup-spi11-cs-state { 4609 pins = "gpio47"; 4610 function = "qup13"; 4611 }; 4612 4613 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 4614 pins = "gpio47"; 4615 function = "gpio"; 4616 }; 4617 4618 qup_spi12_data_clk: qup-spi12-data-clk-state { 4619 pins = "gpio48", "gpio49", "gpio50"; 4620 function = "qup14"; 4621 }; 4622 4623 qup_spi12_cs: qup-spi12-cs-state { 4624 pins = "gpio51"; 4625 function = "qup14"; 4626 }; 4627 4628 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4629 pins = "gpio51"; 4630 function = "gpio"; 4631 }; 4632 4633 qup_spi13_data_clk: qup-spi13-data-clk-state { 4634 pins = "gpio52", "gpio53", "gpio54"; 4635 function = "qup15"; 4636 }; 4637 4638 qup_spi13_cs: qup-spi13-cs-state { 4639 pins = "gpio55"; 4640 function = "qup15"; 4641 }; 4642 4643 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 4644 pins = "gpio55"; 4645 function = "gpio"; 4646 }; 4647 4648 qup_spi14_data_clk: qup-spi14-data-clk-state { 4649 pins = "gpio56", "gpio57", "gpio58"; 4650 function = "qup16"; 4651 }; 4652 4653 qup_spi14_cs: qup-spi14-cs-state { 4654 pins = "gpio59"; 4655 function = "qup16"; 4656 }; 4657 4658 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 4659 pins = "gpio59"; 4660 function = "gpio"; 4661 }; 4662 4663 qup_spi15_data_clk: qup-spi15-data-clk-state { 4664 pins = "gpio60", "gpio61", "gpio62"; 4665 function = "qup17"; 4666 }; 4667 4668 qup_spi15_cs: qup-spi15-cs-state { 4669 pins = "gpio63"; 4670 function = "qup17"; 4671 }; 4672 4673 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 4674 pins = "gpio63"; 4675 function = "gpio"; 4676 }; 4677 4678 qup_uart0_cts: qup-uart0-cts-state { 4679 pins = "gpio0"; 4680 function = "qup00"; 4681 }; 4682 4683 qup_uart0_rts: qup-uart0-rts-state { 4684 pins = "gpio1"; 4685 function = "qup00"; 4686 }; 4687 4688 qup_uart0_tx: qup-uart0-tx-state { 4689 pins = "gpio2"; 4690 function = "qup00"; 4691 }; 4692 4693 qup_uart0_rx: qup-uart0-rx-state { 4694 pins = "gpio3"; 4695 function = "qup00"; 4696 }; 4697 4698 qup_uart1_cts: qup-uart1-cts-state { 4699 pins = "gpio4"; 4700 function = "qup01"; 4701 }; 4702 4703 qup_uart1_rts: qup-uart1-rts-state { 4704 pins = "gpio5"; 4705 function = "qup01"; 4706 }; 4707 4708 qup_uart1_tx: qup-uart1-tx-state { 4709 pins = "gpio6"; 4710 function = "qup01"; 4711 }; 4712 4713 qup_uart1_rx: qup-uart1-rx-state { 4714 pins = "gpio7"; 4715 function = "qup01"; 4716 }; 4717 4718 qup_uart2_cts: qup-uart2-cts-state { 4719 pins = "gpio8"; 4720 function = "qup02"; 4721 }; 4722 4723 qup_uart2_rts: qup-uart2-rts-state { 4724 pins = "gpio9"; 4725 function = "qup02"; 4726 }; 4727 4728 qup_uart2_tx: qup-uart2-tx-state { 4729 pins = "gpio10"; 4730 function = "qup02"; 4731 }; 4732 4733 qup_uart2_rx: qup-uart2-rx-state { 4734 pins = "gpio11"; 4735 function = "qup02"; 4736 }; 4737 4738 qup_uart3_cts: qup-uart3-cts-state { 4739 pins = "gpio12"; 4740 function = "qup03"; 4741 }; 4742 4743 qup_uart3_rts: qup-uart3-rts-state { 4744 pins = "gpio13"; 4745 function = "qup03"; 4746 }; 4747 4748 qup_uart3_tx: qup-uart3-tx-state { 4749 pins = "gpio14"; 4750 function = "qup03"; 4751 }; 4752 4753 qup_uart3_rx: qup-uart3-rx-state { 4754 pins = "gpio15"; 4755 function = "qup03"; 4756 }; 4757 4758 qup_uart4_cts: qup-uart4-cts-state { 4759 pins = "gpio16"; 4760 function = "qup04"; 4761 }; 4762 4763 qup_uart4_rts: qup-uart4-rts-state { 4764 pins = "gpio17"; 4765 function = "qup04"; 4766 }; 4767 4768 qup_uart4_tx: qup-uart4-tx-state { 4769 pins = "gpio18"; 4770 function = "qup04"; 4771 }; 4772 4773 qup_uart4_rx: qup-uart4-rx-state { 4774 pins = "gpio19"; 4775 function = "qup04"; 4776 }; 4777 4778 qup_uart5_cts: qup-uart5-cts-state { 4779 pins = "gpio20"; 4780 function = "qup05"; 4781 }; 4782 4783 qup_uart5_rts: qup-uart5-rts-state { 4784 pins = "gpio21"; 4785 function = "qup05"; 4786 }; 4787 4788 qup_uart5_tx: qup-uart5-tx-state { 4789 pins = "gpio22"; 4790 function = "qup05"; 4791 }; 4792 4793 qup_uart5_rx: qup-uart5-rx-state { 4794 pins = "gpio23"; 4795 function = "qup05"; 4796 }; 4797 4798 qup_uart6_cts: qup-uart6-cts-state { 4799 pins = "gpio24"; 4800 function = "qup06"; 4801 }; 4802 4803 qup_uart6_rts: qup-uart6-rts-state { 4804 pins = "gpio25"; 4805 function = "qup06"; 4806 }; 4807 4808 qup_uart6_tx: qup-uart6-tx-state { 4809 pins = "gpio26"; 4810 function = "qup06"; 4811 }; 4812 4813 qup_uart6_rx: qup-uart6-rx-state { 4814 pins = "gpio27"; 4815 function = "qup06"; 4816 }; 4817 4818 qup_uart7_cts: qup-uart7-cts-state { 4819 pins = "gpio28"; 4820 function = "qup07"; 4821 }; 4822 4823 qup_uart7_rts: qup-uart7-rts-state { 4824 pins = "gpio29"; 4825 function = "qup07"; 4826 }; 4827 4828 qup_uart7_tx: qup-uart7-tx-state { 4829 pins = "gpio30"; 4830 function = "qup07"; 4831 }; 4832 4833 qup_uart7_rx: qup-uart7-rx-state { 4834 pins = "gpio31"; 4835 function = "qup07"; 4836 }; 4837 4838 qup_uart8_cts: qup-uart8-cts-state { 4839 pins = "gpio32"; 4840 function = "qup10"; 4841 }; 4842 4843 qup_uart8_rts: qup-uart8-rts-state { 4844 pins = "gpio33"; 4845 function = "qup10"; 4846 }; 4847 4848 qup_uart8_tx: qup-uart8-tx-state { 4849 pins = "gpio34"; 4850 function = "qup10"; 4851 }; 4852 4853 qup_uart8_rx: qup-uart8-rx-state { 4854 pins = "gpio35"; 4855 function = "qup10"; 4856 }; 4857 4858 qup_uart9_cts: qup-uart9-cts-state { 4859 pins = "gpio36"; 4860 function = "qup11"; 4861 }; 4862 4863 qup_uart9_rts: qup-uart9-rts-state { 4864 pins = "gpio37"; 4865 function = "qup11"; 4866 }; 4867 4868 qup_uart9_tx: qup-uart9-tx-state { 4869 pins = "gpio38"; 4870 function = "qup11"; 4871 }; 4872 4873 qup_uart9_rx: qup-uart9-rx-state { 4874 pins = "gpio39"; 4875 function = "qup11"; 4876 }; 4877 4878 qup_uart10_cts: qup-uart10-cts-state { 4879 pins = "gpio40"; 4880 function = "qup12"; 4881 }; 4882 4883 qup_uart10_rts: qup-uart10-rts-state { 4884 pins = "gpio41"; 4885 function = "qup12"; 4886 }; 4887 4888 qup_uart10_tx: qup-uart10-tx-state { 4889 pins = "gpio42"; 4890 function = "qup12"; 4891 }; 4892 4893 qup_uart10_rx: qup-uart10-rx-state { 4894 pins = "gpio43"; 4895 function = "qup12"; 4896 }; 4897 4898 qup_uart11_cts: qup-uart11-cts-state { 4899 pins = "gpio44"; 4900 function = "qup13"; 4901 }; 4902 4903 qup_uart11_rts: qup-uart11-rts-state { 4904 pins = "gpio45"; 4905 function = "qup13"; 4906 }; 4907 4908 qup_uart11_tx: qup-uart11-tx-state { 4909 pins = "gpio46"; 4910 function = "qup13"; 4911 }; 4912 4913 qup_uart11_rx: qup-uart11-rx-state { 4914 pins = "gpio47"; 4915 function = "qup13"; 4916 }; 4917 4918 qup_uart12_cts: qup-uart12-cts-state { 4919 pins = "gpio48"; 4920 function = "qup14"; 4921 }; 4922 4923 qup_uart12_rts: qup-uart12-rts-state { 4924 pins = "gpio49"; 4925 function = "qup14"; 4926 }; 4927 4928 qup_uart12_tx: qup-uart12-tx-state { 4929 pins = "gpio50"; 4930 function = "qup14"; 4931 }; 4932 4933 qup_uart12_rx: qup-uart12-rx-state { 4934 pins = "gpio51"; 4935 function = "qup14"; 4936 }; 4937 4938 qup_uart13_cts: qup-uart13-cts-state { 4939 pins = "gpio52"; 4940 function = "qup15"; 4941 }; 4942 4943 qup_uart13_rts: qup-uart13-rts-state { 4944 pins = "gpio53"; 4945 function = "qup15"; 4946 }; 4947 4948 qup_uart13_tx: qup-uart13-tx-state { 4949 pins = "gpio54"; 4950 function = "qup15"; 4951 }; 4952 4953 qup_uart13_rx: qup-uart13-rx-state { 4954 pins = "gpio55"; 4955 function = "qup15"; 4956 }; 4957 4958 qup_uart14_cts: qup-uart14-cts-state { 4959 pins = "gpio56"; 4960 function = "qup16"; 4961 }; 4962 4963 qup_uart14_rts: qup-uart14-rts-state { 4964 pins = "gpio57"; 4965 function = "qup16"; 4966 }; 4967 4968 qup_uart14_tx: qup-uart14-tx-state { 4969 pins = "gpio58"; 4970 function = "qup16"; 4971 }; 4972 4973 qup_uart14_rx: qup-uart14-rx-state { 4974 pins = "gpio59"; 4975 function = "qup16"; 4976 }; 4977 4978 qup_uart15_cts: qup-uart15-cts-state { 4979 pins = "gpio60"; 4980 function = "qup17"; 4981 }; 4982 4983 qup_uart15_rts: qup-uart15-rts-state { 4984 pins = "gpio61"; 4985 function = "qup17"; 4986 }; 4987 4988 qup_uart15_tx: qup-uart15-tx-state { 4989 pins = "gpio62"; 4990 function = "qup17"; 4991 }; 4992 4993 qup_uart15_rx: qup-uart15-rx-state { 4994 pins = "gpio63"; 4995 function = "qup17"; 4996 }; 4997 4998 sdc1_clk: sdc1-clk-state { 4999 pins = "sdc1_clk"; 5000 }; 5001 5002 sdc1_cmd: sdc1-cmd-state { 5003 pins = "sdc1_cmd"; 5004 }; 5005 5006 sdc1_data: sdc1-data-state { 5007 pins = "sdc1_data"; 5008 }; 5009 5010 sdc1_rclk: sdc1-rclk-state { 5011 pins = "sdc1_rclk"; 5012 }; 5013 5014 sdc1_clk_sleep: sdc1-clk-sleep-state { 5015 pins = "sdc1_clk"; 5016 drive-strength = <2>; 5017 bias-bus-hold; 5018 }; 5019 5020 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5021 pins = "sdc1_cmd"; 5022 drive-strength = <2>; 5023 bias-bus-hold; 5024 }; 5025 5026 sdc1_data_sleep: sdc1-data-sleep-state { 5027 pins = "sdc1_data"; 5028 drive-strength = <2>; 5029 bias-bus-hold; 5030 }; 5031 5032 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5033 pins = "sdc1_rclk"; 5034 drive-strength = <2>; 5035 bias-bus-hold; 5036 }; 5037 5038 sdc2_clk: sdc2-clk-state { 5039 pins = "sdc2_clk"; 5040 }; 5041 5042 sdc2_cmd: sdc2-cmd-state { 5043 pins = "sdc2_cmd"; 5044 }; 5045 5046 sdc2_data: sdc2-data-state { 5047 pins = "sdc2_data"; 5048 }; 5049 5050 sdc2_clk_sleep: sdc2-clk-sleep-state { 5051 pins = "sdc2_clk"; 5052 drive-strength = <2>; 5053 bias-bus-hold; 5054 }; 5055 5056 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 5057 pins = "sdc2_cmd"; 5058 drive-strength = <2>; 5059 bias-bus-hold; 5060 }; 5061 5062 sdc2_data_sleep: sdc2-data-sleep-state { 5063 pins = "sdc2_data"; 5064 drive-strength = <2>; 5065 bias-bus-hold; 5066 }; 5067 }; 5068 5069 sram@146a5000 { 5070 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5071 reg = <0 0x146a5000 0 0x6000>; 5072 5073 #address-cells = <1>; 5074 #size-cells = <1>; 5075 5076 ranges = <0 0 0x146a5000 0x6000>; 5077 5078 pil-reloc@594c { 5079 compatible = "qcom,pil-reloc-info"; 5080 reg = <0x594c 0xc8>; 5081 }; 5082 }; 5083 5084 apps_smmu: iommu@15000000 { 5085 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5086 reg = <0 0x15000000 0 0x100000>; 5087 #iommu-cells = <2>; 5088 #global-interrupts = <1>; 5089 dma-coherent; 5090 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5091 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5092 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5093 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5094 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5095 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5096 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5097 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5098 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5099 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5100 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5101 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5102 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5103 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5104 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5169 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5170 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5171 }; 5172 5173 intc: interrupt-controller@17a00000 { 5174 compatible = "arm,gic-v3"; 5175 #address-cells = <2>; 5176 #size-cells = <2>; 5177 ranges; 5178 #interrupt-cells = <3>; 5179 interrupt-controller; 5180 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5181 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5182 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5183 5184 gic-its@17a40000 { 5185 compatible = "arm,gic-v3-its"; 5186 msi-controller; 5187 #msi-cells = <1>; 5188 reg = <0 0x17a40000 0 0x20000>; 5189 status = "disabled"; 5190 }; 5191 }; 5192 5193 watchdog@17c10000 { 5194 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5195 reg = <0 0x17c10000 0 0x1000>; 5196 clocks = <&sleep_clk>; 5197 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5198 }; 5199 5200 timer@17c20000 { 5201 #address-cells = <1>; 5202 #size-cells = <1>; 5203 ranges = <0 0 0 0x20000000>; 5204 compatible = "arm,armv7-timer-mem"; 5205 reg = <0 0x17c20000 0 0x1000>; 5206 5207 frame@17c21000 { 5208 frame-number = <0>; 5209 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5210 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5211 reg = <0x17c21000 0x1000>, 5212 <0x17c22000 0x1000>; 5213 }; 5214 5215 frame@17c23000 { 5216 frame-number = <1>; 5217 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5218 reg = <0x17c23000 0x1000>; 5219 status = "disabled"; 5220 }; 5221 5222 frame@17c25000 { 5223 frame-number = <2>; 5224 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5225 reg = <0x17c25000 0x1000>; 5226 status = "disabled"; 5227 }; 5228 5229 frame@17c27000 { 5230 frame-number = <3>; 5231 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5232 reg = <0x17c27000 0x1000>; 5233 status = "disabled"; 5234 }; 5235 5236 frame@17c29000 { 5237 frame-number = <4>; 5238 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5239 reg = <0x17c29000 0x1000>; 5240 status = "disabled"; 5241 }; 5242 5243 frame@17c2b000 { 5244 frame-number = <5>; 5245 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5246 reg = <0x17c2b000 0x1000>; 5247 status = "disabled"; 5248 }; 5249 5250 frame@17c2d000 { 5251 frame-number = <6>; 5252 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5253 reg = <0x17c2d000 0x1000>; 5254 status = "disabled"; 5255 }; 5256 }; 5257 5258 apps_rsc: rsc@18200000 { 5259 compatible = "qcom,rpmh-rsc"; 5260 reg = <0 0x18200000 0 0x10000>, 5261 <0 0x18210000 0 0x10000>, 5262 <0 0x18220000 0 0x10000>; 5263 reg-names = "drv-0", "drv-1", "drv-2"; 5264 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5265 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5266 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5267 qcom,tcs-offset = <0xd00>; 5268 qcom,drv-id = <2>; 5269 qcom,tcs-config = <ACTIVE_TCS 2>, 5270 <SLEEP_TCS 3>, 5271 <WAKE_TCS 3>, 5272 <CONTROL_TCS 1>; 5273 5274 apps_bcm_voter: bcm-voter { 5275 compatible = "qcom,bcm-voter"; 5276 }; 5277 5278 rpmhpd: power-controller { 5279 compatible = "qcom,sc7280-rpmhpd"; 5280 #power-domain-cells = <1>; 5281 operating-points-v2 = <&rpmhpd_opp_table>; 5282 5283 rpmhpd_opp_table: opp-table { 5284 compatible = "operating-points-v2"; 5285 5286 rpmhpd_opp_ret: opp1 { 5287 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5288 }; 5289 5290 rpmhpd_opp_low_svs: opp2 { 5291 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5292 }; 5293 5294 rpmhpd_opp_svs: opp3 { 5295 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5296 }; 5297 5298 rpmhpd_opp_svs_l1: opp4 { 5299 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5300 }; 5301 5302 rpmhpd_opp_svs_l2: opp5 { 5303 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5304 }; 5305 5306 rpmhpd_opp_nom: opp6 { 5307 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5308 }; 5309 5310 rpmhpd_opp_nom_l1: opp7 { 5311 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5312 }; 5313 5314 rpmhpd_opp_turbo: opp8 { 5315 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5316 }; 5317 5318 rpmhpd_opp_turbo_l1: opp9 { 5319 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5320 }; 5321 }; 5322 }; 5323 5324 rpmhcc: clock-controller { 5325 compatible = "qcom,sc7280-rpmh-clk"; 5326 clocks = <&xo_board>; 5327 clock-names = "xo"; 5328 #clock-cells = <1>; 5329 }; 5330 }; 5331 5332 epss_l3: interconnect@18590000 { 5333 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 5334 reg = <0 0x18590000 0 0x1000>; 5335 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5336 clock-names = "xo", "alternate"; 5337 #interconnect-cells = <1>; 5338 }; 5339 5340 cpufreq_hw: cpufreq@18591000 { 5341 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 5342 reg = <0 0x18591000 0 0x1000>, 5343 <0 0x18592000 0 0x1000>, 5344 <0 0x18593000 0 0x1000>; 5345 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5346 clock-names = "xo", "alternate"; 5347 #freq-domain-cells = <1>; 5348 #clock-cells = <1>; 5349 }; 5350 }; 5351 5352 thermal_zones: thermal-zones { 5353 cpu0-thermal { 5354 polling-delay-passive = <250>; 5355 polling-delay = <0>; 5356 5357 thermal-sensors = <&tsens0 1>; 5358 5359 trips { 5360 cpu0_alert0: trip-point0 { 5361 temperature = <90000>; 5362 hysteresis = <2000>; 5363 type = "passive"; 5364 }; 5365 5366 cpu0_alert1: trip-point1 { 5367 temperature = <95000>; 5368 hysteresis = <2000>; 5369 type = "passive"; 5370 }; 5371 5372 cpu0_crit: cpu-crit { 5373 temperature = <110000>; 5374 hysteresis = <0>; 5375 type = "critical"; 5376 }; 5377 }; 5378 5379 cooling-maps { 5380 map0 { 5381 trip = <&cpu0_alert0>; 5382 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5383 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5384 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5385 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5386 }; 5387 map1 { 5388 trip = <&cpu0_alert1>; 5389 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5390 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5391 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5392 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5393 }; 5394 }; 5395 }; 5396 5397 cpu1-thermal { 5398 polling-delay-passive = <250>; 5399 polling-delay = <0>; 5400 5401 thermal-sensors = <&tsens0 2>; 5402 5403 trips { 5404 cpu1_alert0: trip-point0 { 5405 temperature = <90000>; 5406 hysteresis = <2000>; 5407 type = "passive"; 5408 }; 5409 5410 cpu1_alert1: trip-point1 { 5411 temperature = <95000>; 5412 hysteresis = <2000>; 5413 type = "passive"; 5414 }; 5415 5416 cpu1_crit: cpu-crit { 5417 temperature = <110000>; 5418 hysteresis = <0>; 5419 type = "critical"; 5420 }; 5421 }; 5422 5423 cooling-maps { 5424 map0 { 5425 trip = <&cpu1_alert0>; 5426 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5427 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5428 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5429 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5430 }; 5431 map1 { 5432 trip = <&cpu1_alert1>; 5433 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5434 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5435 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5436 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5437 }; 5438 }; 5439 }; 5440 5441 cpu2-thermal { 5442 polling-delay-passive = <250>; 5443 polling-delay = <0>; 5444 5445 thermal-sensors = <&tsens0 3>; 5446 5447 trips { 5448 cpu2_alert0: trip-point0 { 5449 temperature = <90000>; 5450 hysteresis = <2000>; 5451 type = "passive"; 5452 }; 5453 5454 cpu2_alert1: trip-point1 { 5455 temperature = <95000>; 5456 hysteresis = <2000>; 5457 type = "passive"; 5458 }; 5459 5460 cpu2_crit: cpu-crit { 5461 temperature = <110000>; 5462 hysteresis = <0>; 5463 type = "critical"; 5464 }; 5465 }; 5466 5467 cooling-maps { 5468 map0 { 5469 trip = <&cpu2_alert0>; 5470 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5471 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5472 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5473 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5474 }; 5475 map1 { 5476 trip = <&cpu2_alert1>; 5477 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5478 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5479 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5480 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5481 }; 5482 }; 5483 }; 5484 5485 cpu3-thermal { 5486 polling-delay-passive = <250>; 5487 polling-delay = <0>; 5488 5489 thermal-sensors = <&tsens0 4>; 5490 5491 trips { 5492 cpu3_alert0: trip-point0 { 5493 temperature = <90000>; 5494 hysteresis = <2000>; 5495 type = "passive"; 5496 }; 5497 5498 cpu3_alert1: trip-point1 { 5499 temperature = <95000>; 5500 hysteresis = <2000>; 5501 type = "passive"; 5502 }; 5503 5504 cpu3_crit: cpu-crit { 5505 temperature = <110000>; 5506 hysteresis = <0>; 5507 type = "critical"; 5508 }; 5509 }; 5510 5511 cooling-maps { 5512 map0 { 5513 trip = <&cpu3_alert0>; 5514 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5515 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5516 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5517 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5518 }; 5519 map1 { 5520 trip = <&cpu3_alert1>; 5521 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5522 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5523 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5524 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5525 }; 5526 }; 5527 }; 5528 5529 cpu4-thermal { 5530 polling-delay-passive = <250>; 5531 polling-delay = <0>; 5532 5533 thermal-sensors = <&tsens0 7>; 5534 5535 trips { 5536 cpu4_alert0: trip-point0 { 5537 temperature = <90000>; 5538 hysteresis = <2000>; 5539 type = "passive"; 5540 }; 5541 5542 cpu4_alert1: trip-point1 { 5543 temperature = <95000>; 5544 hysteresis = <2000>; 5545 type = "passive"; 5546 }; 5547 5548 cpu4_crit: cpu-crit { 5549 temperature = <110000>; 5550 hysteresis = <0>; 5551 type = "critical"; 5552 }; 5553 }; 5554 5555 cooling-maps { 5556 map0 { 5557 trip = <&cpu4_alert0>; 5558 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5559 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5560 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5561 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5562 }; 5563 map1 { 5564 trip = <&cpu4_alert1>; 5565 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5566 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5567 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5568 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5569 }; 5570 }; 5571 }; 5572 5573 cpu5-thermal { 5574 polling-delay-passive = <250>; 5575 polling-delay = <0>; 5576 5577 thermal-sensors = <&tsens0 8>; 5578 5579 trips { 5580 cpu5_alert0: trip-point0 { 5581 temperature = <90000>; 5582 hysteresis = <2000>; 5583 type = "passive"; 5584 }; 5585 5586 cpu5_alert1: trip-point1 { 5587 temperature = <95000>; 5588 hysteresis = <2000>; 5589 type = "passive"; 5590 }; 5591 5592 cpu5_crit: cpu-crit { 5593 temperature = <110000>; 5594 hysteresis = <0>; 5595 type = "critical"; 5596 }; 5597 }; 5598 5599 cooling-maps { 5600 map0 { 5601 trip = <&cpu5_alert0>; 5602 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5603 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5604 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5605 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5606 }; 5607 map1 { 5608 trip = <&cpu5_alert1>; 5609 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5610 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5611 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5612 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5613 }; 5614 }; 5615 }; 5616 5617 cpu6-thermal { 5618 polling-delay-passive = <250>; 5619 polling-delay = <0>; 5620 5621 thermal-sensors = <&tsens0 9>; 5622 5623 trips { 5624 cpu6_alert0: trip-point0 { 5625 temperature = <90000>; 5626 hysteresis = <2000>; 5627 type = "passive"; 5628 }; 5629 5630 cpu6_alert1: trip-point1 { 5631 temperature = <95000>; 5632 hysteresis = <2000>; 5633 type = "passive"; 5634 }; 5635 5636 cpu6_crit: cpu-crit { 5637 temperature = <110000>; 5638 hysteresis = <0>; 5639 type = "critical"; 5640 }; 5641 }; 5642 5643 cooling-maps { 5644 map0 { 5645 trip = <&cpu6_alert0>; 5646 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5647 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5648 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5649 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5650 }; 5651 map1 { 5652 trip = <&cpu6_alert1>; 5653 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5654 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5655 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5656 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5657 }; 5658 }; 5659 }; 5660 5661 cpu7-thermal { 5662 polling-delay-passive = <250>; 5663 polling-delay = <0>; 5664 5665 thermal-sensors = <&tsens0 10>; 5666 5667 trips { 5668 cpu7_alert0: trip-point0 { 5669 temperature = <90000>; 5670 hysteresis = <2000>; 5671 type = "passive"; 5672 }; 5673 5674 cpu7_alert1: trip-point1 { 5675 temperature = <95000>; 5676 hysteresis = <2000>; 5677 type = "passive"; 5678 }; 5679 5680 cpu7_crit: cpu-crit { 5681 temperature = <110000>; 5682 hysteresis = <0>; 5683 type = "critical"; 5684 }; 5685 }; 5686 5687 cooling-maps { 5688 map0 { 5689 trip = <&cpu7_alert0>; 5690 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5691 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5692 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5693 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5694 }; 5695 map1 { 5696 trip = <&cpu7_alert1>; 5697 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5698 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5699 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5700 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5701 }; 5702 }; 5703 }; 5704 5705 cpu8-thermal { 5706 polling-delay-passive = <250>; 5707 polling-delay = <0>; 5708 5709 thermal-sensors = <&tsens0 11>; 5710 5711 trips { 5712 cpu8_alert0: trip-point0 { 5713 temperature = <90000>; 5714 hysteresis = <2000>; 5715 type = "passive"; 5716 }; 5717 5718 cpu8_alert1: trip-point1 { 5719 temperature = <95000>; 5720 hysteresis = <2000>; 5721 type = "passive"; 5722 }; 5723 5724 cpu8_crit: cpu-crit { 5725 temperature = <110000>; 5726 hysteresis = <0>; 5727 type = "critical"; 5728 }; 5729 }; 5730 5731 cooling-maps { 5732 map0 { 5733 trip = <&cpu8_alert0>; 5734 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5735 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5736 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5737 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5738 }; 5739 map1 { 5740 trip = <&cpu8_alert1>; 5741 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5742 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5743 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5744 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5745 }; 5746 }; 5747 }; 5748 5749 cpu9-thermal { 5750 polling-delay-passive = <250>; 5751 polling-delay = <0>; 5752 5753 thermal-sensors = <&tsens0 12>; 5754 5755 trips { 5756 cpu9_alert0: trip-point0 { 5757 temperature = <90000>; 5758 hysteresis = <2000>; 5759 type = "passive"; 5760 }; 5761 5762 cpu9_alert1: trip-point1 { 5763 temperature = <95000>; 5764 hysteresis = <2000>; 5765 type = "passive"; 5766 }; 5767 5768 cpu9_crit: cpu-crit { 5769 temperature = <110000>; 5770 hysteresis = <0>; 5771 type = "critical"; 5772 }; 5773 }; 5774 5775 cooling-maps { 5776 map0 { 5777 trip = <&cpu9_alert0>; 5778 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5779 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5780 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5781 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5782 }; 5783 map1 { 5784 trip = <&cpu9_alert1>; 5785 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5786 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5787 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5788 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5789 }; 5790 }; 5791 }; 5792 5793 cpu10-thermal { 5794 polling-delay-passive = <250>; 5795 polling-delay = <0>; 5796 5797 thermal-sensors = <&tsens0 13>; 5798 5799 trips { 5800 cpu10_alert0: trip-point0 { 5801 temperature = <90000>; 5802 hysteresis = <2000>; 5803 type = "passive"; 5804 }; 5805 5806 cpu10_alert1: trip-point1 { 5807 temperature = <95000>; 5808 hysteresis = <2000>; 5809 type = "passive"; 5810 }; 5811 5812 cpu10_crit: cpu-crit { 5813 temperature = <110000>; 5814 hysteresis = <0>; 5815 type = "critical"; 5816 }; 5817 }; 5818 5819 cooling-maps { 5820 map0 { 5821 trip = <&cpu10_alert0>; 5822 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5823 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5824 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5825 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5826 }; 5827 map1 { 5828 trip = <&cpu10_alert1>; 5829 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5830 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5831 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5832 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5833 }; 5834 }; 5835 }; 5836 5837 cpu11-thermal { 5838 polling-delay-passive = <250>; 5839 polling-delay = <0>; 5840 5841 thermal-sensors = <&tsens0 14>; 5842 5843 trips { 5844 cpu11_alert0: trip-point0 { 5845 temperature = <90000>; 5846 hysteresis = <2000>; 5847 type = "passive"; 5848 }; 5849 5850 cpu11_alert1: trip-point1 { 5851 temperature = <95000>; 5852 hysteresis = <2000>; 5853 type = "passive"; 5854 }; 5855 5856 cpu11_crit: cpu-crit { 5857 temperature = <110000>; 5858 hysteresis = <0>; 5859 type = "critical"; 5860 }; 5861 }; 5862 5863 cooling-maps { 5864 map0 { 5865 trip = <&cpu11_alert0>; 5866 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5867 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5868 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5869 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5870 }; 5871 map1 { 5872 trip = <&cpu11_alert1>; 5873 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5874 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5875 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5876 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5877 }; 5878 }; 5879 }; 5880 5881 aoss0-thermal { 5882 polling-delay-passive = <0>; 5883 polling-delay = <0>; 5884 5885 thermal-sensors = <&tsens0 0>; 5886 5887 trips { 5888 aoss0_alert0: trip-point0 { 5889 temperature = <90000>; 5890 hysteresis = <2000>; 5891 type = "hot"; 5892 }; 5893 5894 aoss0_crit: aoss0-crit { 5895 temperature = <110000>; 5896 hysteresis = <0>; 5897 type = "critical"; 5898 }; 5899 }; 5900 }; 5901 5902 aoss1-thermal { 5903 polling-delay-passive = <0>; 5904 polling-delay = <0>; 5905 5906 thermal-sensors = <&tsens1 0>; 5907 5908 trips { 5909 aoss1_alert0: trip-point0 { 5910 temperature = <90000>; 5911 hysteresis = <2000>; 5912 type = "hot"; 5913 }; 5914 5915 aoss1_crit: aoss1-crit { 5916 temperature = <110000>; 5917 hysteresis = <0>; 5918 type = "critical"; 5919 }; 5920 }; 5921 }; 5922 5923 cpuss0-thermal { 5924 polling-delay-passive = <0>; 5925 polling-delay = <0>; 5926 5927 thermal-sensors = <&tsens0 5>; 5928 5929 trips { 5930 cpuss0_alert0: trip-point0 { 5931 temperature = <90000>; 5932 hysteresis = <2000>; 5933 type = "hot"; 5934 }; 5935 cpuss0_crit: cluster0-crit { 5936 temperature = <110000>; 5937 hysteresis = <0>; 5938 type = "critical"; 5939 }; 5940 }; 5941 }; 5942 5943 cpuss1-thermal { 5944 polling-delay-passive = <0>; 5945 polling-delay = <0>; 5946 5947 thermal-sensors = <&tsens0 6>; 5948 5949 trips { 5950 cpuss1_alert0: trip-point0 { 5951 temperature = <90000>; 5952 hysteresis = <2000>; 5953 type = "hot"; 5954 }; 5955 cpuss1_crit: cluster0-crit { 5956 temperature = <110000>; 5957 hysteresis = <0>; 5958 type = "critical"; 5959 }; 5960 }; 5961 }; 5962 5963 gpuss0-thermal { 5964 polling-delay-passive = <100>; 5965 polling-delay = <0>; 5966 5967 thermal-sensors = <&tsens1 1>; 5968 5969 trips { 5970 gpuss0_alert0: trip-point0 { 5971 temperature = <95000>; 5972 hysteresis = <2000>; 5973 type = "passive"; 5974 }; 5975 5976 gpuss0_crit: gpuss0-crit { 5977 temperature = <110000>; 5978 hysteresis = <0>; 5979 type = "critical"; 5980 }; 5981 }; 5982 5983 cooling-maps { 5984 map0 { 5985 trip = <&gpuss0_alert0>; 5986 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5987 }; 5988 }; 5989 }; 5990 5991 gpuss1-thermal { 5992 polling-delay-passive = <100>; 5993 polling-delay = <0>; 5994 5995 thermal-sensors = <&tsens1 2>; 5996 5997 trips { 5998 gpuss1_alert0: trip-point0 { 5999 temperature = <95000>; 6000 hysteresis = <2000>; 6001 type = "passive"; 6002 }; 6003 6004 gpuss1_crit: gpuss1-crit { 6005 temperature = <110000>; 6006 hysteresis = <0>; 6007 type = "critical"; 6008 }; 6009 }; 6010 6011 cooling-maps { 6012 map0 { 6013 trip = <&gpuss1_alert0>; 6014 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6015 }; 6016 }; 6017 }; 6018 6019 nspss0-thermal { 6020 polling-delay-passive = <0>; 6021 polling-delay = <0>; 6022 6023 thermal-sensors = <&tsens1 3>; 6024 6025 trips { 6026 nspss0_alert0: trip-point0 { 6027 temperature = <90000>; 6028 hysteresis = <2000>; 6029 type = "hot"; 6030 }; 6031 6032 nspss0_crit: nspss0-crit { 6033 temperature = <110000>; 6034 hysteresis = <0>; 6035 type = "critical"; 6036 }; 6037 }; 6038 }; 6039 6040 nspss1-thermal { 6041 polling-delay-passive = <0>; 6042 polling-delay = <0>; 6043 6044 thermal-sensors = <&tsens1 4>; 6045 6046 trips { 6047 nspss1_alert0: trip-point0 { 6048 temperature = <90000>; 6049 hysteresis = <2000>; 6050 type = "hot"; 6051 }; 6052 6053 nspss1_crit: nspss1-crit { 6054 temperature = <110000>; 6055 hysteresis = <0>; 6056 type = "critical"; 6057 }; 6058 }; 6059 }; 6060 6061 video-thermal { 6062 polling-delay-passive = <0>; 6063 polling-delay = <0>; 6064 6065 thermal-sensors = <&tsens1 5>; 6066 6067 trips { 6068 video_alert0: trip-point0 { 6069 temperature = <90000>; 6070 hysteresis = <2000>; 6071 type = "hot"; 6072 }; 6073 6074 video_crit: video-crit { 6075 temperature = <110000>; 6076 hysteresis = <0>; 6077 type = "critical"; 6078 }; 6079 }; 6080 }; 6081 6082 ddr-thermal { 6083 polling-delay-passive = <0>; 6084 polling-delay = <0>; 6085 6086 thermal-sensors = <&tsens1 6>; 6087 6088 trips { 6089 ddr_alert0: trip-point0 { 6090 temperature = <90000>; 6091 hysteresis = <2000>; 6092 type = "hot"; 6093 }; 6094 6095 ddr_crit: ddr-crit { 6096 temperature = <110000>; 6097 hysteresis = <0>; 6098 type = "critical"; 6099 }; 6100 }; 6101 }; 6102 6103 mdmss0-thermal { 6104 polling-delay-passive = <0>; 6105 polling-delay = <0>; 6106 6107 thermal-sensors = <&tsens1 7>; 6108 6109 trips { 6110 mdmss0_alert0: trip-point0 { 6111 temperature = <90000>; 6112 hysteresis = <2000>; 6113 type = "hot"; 6114 }; 6115 6116 mdmss0_crit: mdmss0-crit { 6117 temperature = <110000>; 6118 hysteresis = <0>; 6119 type = "critical"; 6120 }; 6121 }; 6122 }; 6123 6124 mdmss1-thermal { 6125 polling-delay-passive = <0>; 6126 polling-delay = <0>; 6127 6128 thermal-sensors = <&tsens1 8>; 6129 6130 trips { 6131 mdmss1_alert0: trip-point0 { 6132 temperature = <90000>; 6133 hysteresis = <2000>; 6134 type = "hot"; 6135 }; 6136 6137 mdmss1_crit: mdmss1-crit { 6138 temperature = <110000>; 6139 hysteresis = <0>; 6140 type = "critical"; 6141 }; 6142 }; 6143 }; 6144 6145 mdmss2-thermal { 6146 polling-delay-passive = <0>; 6147 polling-delay = <0>; 6148 6149 thermal-sensors = <&tsens1 9>; 6150 6151 trips { 6152 mdmss2_alert0: trip-point0 { 6153 temperature = <90000>; 6154 hysteresis = <2000>; 6155 type = "hot"; 6156 }; 6157 6158 mdmss2_crit: mdmss2-crit { 6159 temperature = <110000>; 6160 hysteresis = <0>; 6161 type = "critical"; 6162 }; 6163 }; 6164 }; 6165 6166 mdmss3-thermal { 6167 polling-delay-passive = <0>; 6168 polling-delay = <0>; 6169 6170 thermal-sensors = <&tsens1 10>; 6171 6172 trips { 6173 mdmss3_alert0: trip-point0 { 6174 temperature = <90000>; 6175 hysteresis = <2000>; 6176 type = "hot"; 6177 }; 6178 6179 mdmss3_crit: mdmss3-crit { 6180 temperature = <110000>; 6181 hysteresis = <0>; 6182 type = "critical"; 6183 }; 6184 }; 6185 }; 6186 6187 camera0-thermal { 6188 polling-delay-passive = <0>; 6189 polling-delay = <0>; 6190 6191 thermal-sensors = <&tsens1 11>; 6192 6193 trips { 6194 camera0_alert0: trip-point0 { 6195 temperature = <90000>; 6196 hysteresis = <2000>; 6197 type = "hot"; 6198 }; 6199 6200 camera0_crit: camera0-crit { 6201 temperature = <110000>; 6202 hysteresis = <0>; 6203 type = "critical"; 6204 }; 6205 }; 6206 }; 6207 }; 6208 6209 timer { 6210 compatible = "arm,armv8-timer"; 6211 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6212 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6213 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6214 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6215 }; 6216}; 6217