1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-sc7280.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/interconnect/qcom,sc7280.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/mailbox/qcom-ipcc.h> 13#include <dt-bindings/power/qcom-aoss-qmp.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/reset/qcom,sdm845-aoss.h> 16#include <dt-bindings/reset/qcom,sdm845-pdc.h> 17#include <dt-bindings/soc/qcom,rpmh-rsc.h> 18#include <dt-bindings/thermal/thermal.h> 19 20/ { 21 interrupt-parent = <&intc>; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 chosen { }; 27 28 aliases { 29 mmc1 = &sdhc_1; 30 mmc2 = &sdhc_2; 31 }; 32 33 clocks { 34 xo_board: xo-board { 35 compatible = "fixed-clock"; 36 clock-frequency = <76800000>; 37 #clock-cells = <0>; 38 }; 39 40 sleep_clk: sleep-clk { 41 compatible = "fixed-clock"; 42 clock-frequency = <32000>; 43 #clock-cells = <0>; 44 }; 45 }; 46 47 reserved-memory { 48 #address-cells = <2>; 49 #size-cells = <2>; 50 ranges; 51 52 aop_mem: memory@80800000 { 53 reg = <0x0 0x80800000 0x0 0x60000>; 54 no-map; 55 }; 56 57 aop_cmd_db_mem: memory@80860000 { 58 reg = <0x0 0x80860000 0x0 0x20000>; 59 compatible = "qcom,cmd-db"; 60 no-map; 61 }; 62 63 smem_mem: memory@80900000 { 64 reg = <0x0 0x80900000 0x0 0x200000>; 65 no-map; 66 }; 67 68 cpucp_mem: memory@80b00000 { 69 no-map; 70 reg = <0x0 0x80b00000 0x0 0x100000>; 71 }; 72 73 ipa_fw_mem: memory@8b700000 { 74 reg = <0 0x8b700000 0 0x10000>; 75 no-map; 76 }; 77 }; 78 79 cpus { 80 #address-cells = <2>; 81 #size-cells = <0>; 82 83 CPU0: cpu@0 { 84 device_type = "cpu"; 85 compatible = "arm,kryo"; 86 reg = <0x0 0x0>; 87 enable-method = "psci"; 88 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 89 &LITTLE_CPU_SLEEP_1 90 &CLUSTER_SLEEP_0>; 91 next-level-cache = <&L2_0>; 92 qcom,freq-domain = <&cpufreq_hw 0>; 93 #cooling-cells = <2>; 94 L2_0: l2-cache { 95 compatible = "cache"; 96 next-level-cache = <&L3_0>; 97 L3_0: l3-cache { 98 compatible = "cache"; 99 }; 100 }; 101 }; 102 103 CPU1: cpu@100 { 104 device_type = "cpu"; 105 compatible = "arm,kryo"; 106 reg = <0x0 0x100>; 107 enable-method = "psci"; 108 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 109 &LITTLE_CPU_SLEEP_1 110 &CLUSTER_SLEEP_0>; 111 next-level-cache = <&L2_100>; 112 qcom,freq-domain = <&cpufreq_hw 0>; 113 #cooling-cells = <2>; 114 L2_100: l2-cache { 115 compatible = "cache"; 116 next-level-cache = <&L3_0>; 117 }; 118 }; 119 120 CPU2: cpu@200 { 121 device_type = "cpu"; 122 compatible = "arm,kryo"; 123 reg = <0x0 0x200>; 124 enable-method = "psci"; 125 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 126 &LITTLE_CPU_SLEEP_1 127 &CLUSTER_SLEEP_0>; 128 next-level-cache = <&L2_200>; 129 qcom,freq-domain = <&cpufreq_hw 0>; 130 #cooling-cells = <2>; 131 L2_200: l2-cache { 132 compatible = "cache"; 133 next-level-cache = <&L3_0>; 134 }; 135 }; 136 137 CPU3: cpu@300 { 138 device_type = "cpu"; 139 compatible = "arm,kryo"; 140 reg = <0x0 0x300>; 141 enable-method = "psci"; 142 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 143 &LITTLE_CPU_SLEEP_1 144 &CLUSTER_SLEEP_0>; 145 next-level-cache = <&L2_300>; 146 qcom,freq-domain = <&cpufreq_hw 0>; 147 #cooling-cells = <2>; 148 L2_300: l2-cache { 149 compatible = "cache"; 150 next-level-cache = <&L3_0>; 151 }; 152 }; 153 154 CPU4: cpu@400 { 155 device_type = "cpu"; 156 compatible = "arm,kryo"; 157 reg = <0x0 0x400>; 158 enable-method = "psci"; 159 cpu-idle-states = <&BIG_CPU_SLEEP_0 160 &BIG_CPU_SLEEP_1 161 &CLUSTER_SLEEP_0>; 162 next-level-cache = <&L2_400>; 163 qcom,freq-domain = <&cpufreq_hw 1>; 164 #cooling-cells = <2>; 165 L2_400: l2-cache { 166 compatible = "cache"; 167 next-level-cache = <&L3_0>; 168 }; 169 }; 170 171 CPU5: cpu@500 { 172 device_type = "cpu"; 173 compatible = "arm,kryo"; 174 reg = <0x0 0x500>; 175 enable-method = "psci"; 176 cpu-idle-states = <&BIG_CPU_SLEEP_0 177 &BIG_CPU_SLEEP_1 178 &CLUSTER_SLEEP_0>; 179 next-level-cache = <&L2_500>; 180 qcom,freq-domain = <&cpufreq_hw 1>; 181 #cooling-cells = <2>; 182 L2_500: l2-cache { 183 compatible = "cache"; 184 next-level-cache = <&L3_0>; 185 }; 186 }; 187 188 CPU6: cpu@600 { 189 device_type = "cpu"; 190 compatible = "arm,kryo"; 191 reg = <0x0 0x600>; 192 enable-method = "psci"; 193 cpu-idle-states = <&BIG_CPU_SLEEP_0 194 &BIG_CPU_SLEEP_1 195 &CLUSTER_SLEEP_0>; 196 next-level-cache = <&L2_600>; 197 qcom,freq-domain = <&cpufreq_hw 1>; 198 #cooling-cells = <2>; 199 L2_600: l2-cache { 200 compatible = "cache"; 201 next-level-cache = <&L3_0>; 202 }; 203 }; 204 205 CPU7: cpu@700 { 206 device_type = "cpu"; 207 compatible = "arm,kryo"; 208 reg = <0x0 0x700>; 209 enable-method = "psci"; 210 cpu-idle-states = <&BIG_CPU_SLEEP_0 211 &BIG_CPU_SLEEP_1 212 &CLUSTER_SLEEP_0>; 213 next-level-cache = <&L2_700>; 214 qcom,freq-domain = <&cpufreq_hw 2>; 215 #cooling-cells = <2>; 216 L2_700: l2-cache { 217 compatible = "cache"; 218 next-level-cache = <&L3_0>; 219 }; 220 }; 221 222 cpu-map { 223 cluster0 { 224 core0 { 225 cpu = <&CPU0>; 226 }; 227 228 core1 { 229 cpu = <&CPU1>; 230 }; 231 232 core2 { 233 cpu = <&CPU2>; 234 }; 235 236 core3 { 237 cpu = <&CPU3>; 238 }; 239 240 core4 { 241 cpu = <&CPU4>; 242 }; 243 244 core5 { 245 cpu = <&CPU5>; 246 }; 247 248 core6 { 249 cpu = <&CPU6>; 250 }; 251 252 core7 { 253 cpu = <&CPU7>; 254 }; 255 }; 256 }; 257 258 idle-states { 259 entry-method = "psci"; 260 261 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 262 compatible = "arm,idle-state"; 263 idle-state-name = "little-power-down"; 264 arm,psci-suspend-param = <0x40000003>; 265 entry-latency-us = <549>; 266 exit-latency-us = <901>; 267 min-residency-us = <1774>; 268 local-timer-stop; 269 }; 270 271 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 272 compatible = "arm,idle-state"; 273 idle-state-name = "little-rail-power-down"; 274 arm,psci-suspend-param = <0x40000004>; 275 entry-latency-us = <702>; 276 exit-latency-us = <915>; 277 min-residency-us = <4001>; 278 local-timer-stop; 279 }; 280 281 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 282 compatible = "arm,idle-state"; 283 idle-state-name = "big-power-down"; 284 arm,psci-suspend-param = <0x40000003>; 285 entry-latency-us = <523>; 286 exit-latency-us = <1244>; 287 min-residency-us = <2207>; 288 local-timer-stop; 289 }; 290 291 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 292 compatible = "arm,idle-state"; 293 idle-state-name = "big-rail-power-down"; 294 arm,psci-suspend-param = <0x40000004>; 295 entry-latency-us = <526>; 296 exit-latency-us = <1854>; 297 min-residency-us = <5555>; 298 local-timer-stop; 299 }; 300 301 CLUSTER_SLEEP_0: cluster-sleep-0 { 302 compatible = "arm,idle-state"; 303 idle-state-name = "cluster-power-down"; 304 arm,psci-suspend-param = <0x40003444>; 305 entry-latency-us = <3263>; 306 exit-latency-us = <6562>; 307 min-residency-us = <9926>; 308 local-timer-stop; 309 }; 310 }; 311 }; 312 313 memory@80000000 { 314 device_type = "memory"; 315 /* We expect the bootloader to fill in the size */ 316 reg = <0 0x80000000 0 0>; 317 }; 318 319 firmware { 320 scm { 321 compatible = "qcom,scm-sc7280", "qcom,scm"; 322 }; 323 }; 324 325 clk_virt: interconnect { 326 compatible = "qcom,sc7280-clk-virt"; 327 #interconnect-cells = <2>; 328 qcom,bcm-voters = <&apps_bcm_voter>; 329 }; 330 331 smem { 332 compatible = "qcom,smem"; 333 memory-region = <&smem_mem>; 334 hwlocks = <&tcsr_mutex 3>; 335 }; 336 337 smp2p-adsp { 338 compatible = "qcom,smp2p"; 339 qcom,smem = <443>, <429>; 340 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 341 IPCC_MPROC_SIGNAL_SMP2P 342 IRQ_TYPE_EDGE_RISING>; 343 mboxes = <&ipcc IPCC_CLIENT_LPASS 344 IPCC_MPROC_SIGNAL_SMP2P>; 345 346 qcom,local-pid = <0>; 347 qcom,remote-pid = <2>; 348 349 adsp_smp2p_out: master-kernel { 350 qcom,entry-name = "master-kernel"; 351 #qcom,smem-state-cells = <1>; 352 }; 353 354 adsp_smp2p_in: slave-kernel { 355 qcom,entry-name = "slave-kernel"; 356 interrupt-controller; 357 #interrupt-cells = <2>; 358 }; 359 }; 360 361 smp2p-cdsp { 362 compatible = "qcom,smp2p"; 363 qcom,smem = <94>, <432>; 364 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 365 IPCC_MPROC_SIGNAL_SMP2P 366 IRQ_TYPE_EDGE_RISING>; 367 mboxes = <&ipcc IPCC_CLIENT_CDSP 368 IPCC_MPROC_SIGNAL_SMP2P>; 369 370 qcom,local-pid = <0>; 371 qcom,remote-pid = <5>; 372 373 cdsp_smp2p_out: master-kernel { 374 qcom,entry-name = "master-kernel"; 375 #qcom,smem-state-cells = <1>; 376 }; 377 378 cdsp_smp2p_in: slave-kernel { 379 qcom,entry-name = "slave-kernel"; 380 interrupt-controller; 381 #interrupt-cells = <2>; 382 }; 383 }; 384 385 smp2p-mpss { 386 compatible = "qcom,smp2p"; 387 qcom,smem = <435>, <428>; 388 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 389 IPCC_MPROC_SIGNAL_SMP2P 390 IRQ_TYPE_EDGE_RISING>; 391 mboxes = <&ipcc IPCC_CLIENT_MPSS 392 IPCC_MPROC_SIGNAL_SMP2P>; 393 394 qcom,local-pid = <0>; 395 qcom,remote-pid = <1>; 396 397 modem_smp2p_out: master-kernel { 398 qcom,entry-name = "master-kernel"; 399 #qcom,smem-state-cells = <1>; 400 }; 401 402 modem_smp2p_in: slave-kernel { 403 qcom,entry-name = "slave-kernel"; 404 interrupt-controller; 405 #interrupt-cells = <2>; 406 }; 407 408 ipa_smp2p_out: ipa-ap-to-modem { 409 qcom,entry-name = "ipa"; 410 #qcom,smem-state-cells = <1>; 411 }; 412 413 ipa_smp2p_in: ipa-modem-to-ap { 414 qcom,entry-name = "ipa"; 415 interrupt-controller; 416 #interrupt-cells = <2>; 417 }; 418 }; 419 420 smp2p-wpss { 421 compatible = "qcom,smp2p"; 422 qcom,smem = <617>, <616>; 423 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 424 IPCC_MPROC_SIGNAL_SMP2P 425 IRQ_TYPE_EDGE_RISING>; 426 mboxes = <&ipcc IPCC_CLIENT_WPSS 427 IPCC_MPROC_SIGNAL_SMP2P>; 428 429 qcom,local-pid = <0>; 430 qcom,remote-pid = <13>; 431 432 wpss_smp2p_out: master-kernel { 433 qcom,entry-name = "master-kernel"; 434 #qcom,smem-state-cells = <1>; 435 }; 436 437 wpss_smp2p_in: slave-kernel { 438 qcom,entry-name = "slave-kernel"; 439 interrupt-controller; 440 #interrupt-cells = <2>; 441 }; 442 }; 443 444 pmu { 445 compatible = "arm,armv8-pmuv3"; 446 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 447 }; 448 449 psci { 450 compatible = "arm,psci-1.0"; 451 method = "smc"; 452 }; 453 454 soc: soc@0 { 455 #address-cells = <2>; 456 #size-cells = <2>; 457 ranges = <0 0 0 0 0x10 0>; 458 dma-ranges = <0 0 0 0 0x10 0>; 459 compatible = "simple-bus"; 460 461 gcc: clock-controller@100000 { 462 compatible = "qcom,gcc-sc7280"; 463 reg = <0 0x00100000 0 0x1f0000>; 464 clocks = <&rpmhcc RPMH_CXO_CLK>, 465 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 466 <0>, <0>, <0>, <0>, <0>, <0>; 467 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 468 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 469 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 470 "ufs_phy_tx_symbol_0_clk", 471 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 472 #clock-cells = <1>; 473 #reset-cells = <1>; 474 #power-domain-cells = <1>; 475 }; 476 477 ipcc: mailbox@408000 { 478 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 479 reg = <0 0x00408000 0 0x1000>; 480 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 481 interrupt-controller; 482 #interrupt-cells = <3>; 483 #mbox-cells = <2>; 484 }; 485 486 qfprom: efuse@784000 { 487 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 488 reg = <0 0x00784000 0 0xa20>, 489 <0 0x00780000 0 0xa20>, 490 <0 0x00782000 0 0x120>, 491 <0 0x00786000 0 0x1fff>; 492 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 493 clock-names = "core"; 494 power-domains = <&rpmhpd SC7280_MX>; 495 #address-cells = <1>; 496 #size-cells = <1>; 497 }; 498 499 sdhc_1: sdhci@7c4000 { 500 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 501 status = "disabled"; 502 503 reg = <0 0x007c4000 0 0x1000>, 504 <0 0x007c5000 0 0x1000>; 505 reg-names = "hc", "cqhci"; 506 507 iommus = <&apps_smmu 0xc0 0x0>; 508 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 510 interrupt-names = "hc_irq", "pwr_irq"; 511 512 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 513 <&gcc GCC_SDCC1_AHB_CLK>, 514 <&rpmhcc RPMH_CXO_CLK>; 515 clock-names = "core", "iface", "xo"; 516 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 517 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 518 interconnect-names = "sdhc-ddr","cpu-sdhc"; 519 power-domains = <&rpmhpd SC7280_CX>; 520 operating-points-v2 = <&sdhc1_opp_table>; 521 522 bus-width = <8>; 523 supports-cqe; 524 525 qcom,dll-config = <0x0007642c>; 526 qcom,ddr-config = <0x80040868>; 527 528 mmc-ddr-1_8v; 529 mmc-hs200-1_8v; 530 mmc-hs400-1_8v; 531 mmc-hs400-enhanced-strobe; 532 533 sdhc1_opp_table: opp-table { 534 compatible = "operating-points-v2"; 535 536 opp-100000000 { 537 opp-hz = /bits/ 64 <100000000>; 538 required-opps = <&rpmhpd_opp_low_svs>; 539 opp-peak-kBps = <1800000 400000>; 540 opp-avg-kBps = <100000 0>; 541 }; 542 543 opp-384000000 { 544 opp-hz = /bits/ 64 <384000000>; 545 required-opps = <&rpmhpd_opp_nom>; 546 opp-peak-kBps = <5400000 1600000>; 547 opp-avg-kBps = <390000 0>; 548 }; 549 }; 550 551 }; 552 553 qupv3_id_0: geniqup@9c0000 { 554 compatible = "qcom,geni-se-qup"; 555 reg = <0 0x009c0000 0 0x2000>; 556 clock-names = "m-ahb", "s-ahb"; 557 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 558 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 559 #address-cells = <2>; 560 #size-cells = <2>; 561 ranges; 562 status = "disabled"; 563 564 uart5: serial@994000 { 565 compatible = "qcom,geni-debug-uart"; 566 reg = <0 0x00994000 0 0x4000>; 567 clock-names = "se"; 568 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 569 pinctrl-names = "default"; 570 pinctrl-0 = <&qup_uart5_default>; 571 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 572 status = "disabled"; 573 }; 574 }; 575 576 cnoc2: interconnect@1500000 { 577 reg = <0 0x01500000 0 0x1000>; 578 compatible = "qcom,sc7280-cnoc2"; 579 #interconnect-cells = <2>; 580 qcom,bcm-voters = <&apps_bcm_voter>; 581 }; 582 583 cnoc3: interconnect@1502000 { 584 reg = <0 0x01502000 0 0x1000>; 585 compatible = "qcom,sc7280-cnoc3"; 586 #interconnect-cells = <2>; 587 qcom,bcm-voters = <&apps_bcm_voter>; 588 }; 589 590 mc_virt: interconnect@1580000 { 591 reg = <0 0x01580000 0 0x4>; 592 compatible = "qcom,sc7280-mc-virt"; 593 #interconnect-cells = <2>; 594 qcom,bcm-voters = <&apps_bcm_voter>; 595 }; 596 597 system_noc: interconnect@1680000 { 598 reg = <0 0x01680000 0 0x15480>; 599 compatible = "qcom,sc7280-system-noc"; 600 #interconnect-cells = <2>; 601 qcom,bcm-voters = <&apps_bcm_voter>; 602 }; 603 604 aggre1_noc: interconnect@16e0000 { 605 compatible = "qcom,sc7280-aggre1-noc"; 606 reg = <0 0x016e0000 0 0x1c080>; 607 #interconnect-cells = <2>; 608 qcom,bcm-voters = <&apps_bcm_voter>; 609 }; 610 611 aggre2_noc: interconnect@1700000 { 612 reg = <0 0x01700000 0 0x2b080>; 613 compatible = "qcom,sc7280-aggre2-noc"; 614 #interconnect-cells = <2>; 615 qcom,bcm-voters = <&apps_bcm_voter>; 616 }; 617 618 mmss_noc: interconnect@1740000 { 619 reg = <0 0x01740000 0 0x1e080>; 620 compatible = "qcom,sc7280-mmss-noc"; 621 #interconnect-cells = <2>; 622 qcom,bcm-voters = <&apps_bcm_voter>; 623 }; 624 625 ipa: ipa@1e40000 { 626 compatible = "qcom,sc7280-ipa"; 627 628 iommus = <&apps_smmu 0x480 0x0>, 629 <&apps_smmu 0x482 0x0>; 630 reg = <0 0x1e40000 0 0x8000>, 631 <0 0x1e50000 0 0x4ad0>, 632 <0 0x1e04000 0 0x23000>; 633 reg-names = "ipa-reg", 634 "ipa-shared", 635 "gsi"; 636 637 interrupts-extended = <&intc 0 654 IRQ_TYPE_EDGE_RISING>, 638 <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, 639 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 640 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 641 interrupt-names = "ipa", 642 "gsi", 643 "ipa-clock-query", 644 "ipa-setup-ready"; 645 646 clocks = <&rpmhcc RPMH_IPA_CLK>; 647 clock-names = "core"; 648 649 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 650 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 651 interconnect-names = "memory", 652 "config"; 653 654 qcom,smem-states = <&ipa_smp2p_out 0>, 655 <&ipa_smp2p_out 1>; 656 qcom,smem-state-names = "ipa-clock-enabled-valid", 657 "ipa-clock-enabled"; 658 659 status = "disabled"; 660 }; 661 662 tcsr_mutex: hwlock@1f40000 { 663 compatible = "qcom,tcsr-mutex", "syscon"; 664 reg = <0 0x01f40000 0 0x40000>; 665 #hwlock-cells = <1>; 666 }; 667 668 lpasscc: lpasscc@3000000 { 669 compatible = "qcom,sc7280-lpasscc"; 670 reg = <0 0x03000000 0 0x40>, 671 <0 0x03c04000 0 0x4>, 672 <0 0x03389000 0 0x24>; 673 reg-names = "qdsp6ss", "top_cc", "cc"; 674 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 675 clock-names = "iface"; 676 #clock-cells = <1>; 677 }; 678 679 lpass_ag_noc: interconnect@3c40000 { 680 reg = <0 0x03c40000 0 0xf080>; 681 compatible = "qcom,sc7280-lpass-ag-noc"; 682 #interconnect-cells = <2>; 683 qcom,bcm-voters = <&apps_bcm_voter>; 684 }; 685 686 gpucc: clock-controller@3d90000 { 687 compatible = "qcom,sc7280-gpucc"; 688 reg = <0 0x03d90000 0 0x9000>; 689 clocks = <&rpmhcc RPMH_CXO_CLK>, 690 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 691 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 692 clock-names = "bi_tcxo", 693 "gcc_gpu_gpll0_clk_src", 694 "gcc_gpu_gpll0_div_clk_src"; 695 #clock-cells = <1>; 696 #reset-cells = <1>; 697 #power-domain-cells = <1>; 698 }; 699 700 stm@6002000 { 701 compatible = "arm,coresight-stm", "arm,primecell"; 702 reg = <0 0x06002000 0 0x1000>, 703 <0 0x16280000 0 0x180000>; 704 reg-names = "stm-base", "stm-stimulus-base"; 705 706 clocks = <&aoss_qmp>; 707 clock-names = "apb_pclk"; 708 709 out-ports { 710 port { 711 stm_out: endpoint { 712 remote-endpoint = <&funnel0_in7>; 713 }; 714 }; 715 }; 716 }; 717 718 funnel@6041000 { 719 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 720 reg = <0 0x06041000 0 0x1000>; 721 722 clocks = <&aoss_qmp>; 723 clock-names = "apb_pclk"; 724 725 out-ports { 726 port { 727 funnel0_out: endpoint { 728 remote-endpoint = <&merge_funnel_in0>; 729 }; 730 }; 731 }; 732 733 in-ports { 734 #address-cells = <1>; 735 #size-cells = <0>; 736 737 port@7 { 738 reg = <7>; 739 funnel0_in7: endpoint { 740 remote-endpoint = <&stm_out>; 741 }; 742 }; 743 }; 744 }; 745 746 funnel@6042000 { 747 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 748 reg = <0 0x06042000 0 0x1000>; 749 750 clocks = <&aoss_qmp>; 751 clock-names = "apb_pclk"; 752 753 out-ports { 754 port { 755 funnel1_out: endpoint { 756 remote-endpoint = <&merge_funnel_in1>; 757 }; 758 }; 759 }; 760 761 in-ports { 762 #address-cells = <1>; 763 #size-cells = <0>; 764 765 port@4 { 766 reg = <4>; 767 funnel1_in4: endpoint { 768 remote-endpoint = <&apss_merge_funnel_out>; 769 }; 770 }; 771 }; 772 }; 773 774 funnel@6045000 { 775 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 776 reg = <0 0x06045000 0 0x1000>; 777 778 clocks = <&aoss_qmp>; 779 clock-names = "apb_pclk"; 780 781 out-ports { 782 port { 783 merge_funnel_out: endpoint { 784 remote-endpoint = <&swao_funnel_in>; 785 }; 786 }; 787 }; 788 789 in-ports { 790 #address-cells = <1>; 791 #size-cells = <0>; 792 793 port@0 { 794 reg = <0>; 795 merge_funnel_in0: endpoint { 796 remote-endpoint = <&funnel0_out>; 797 }; 798 }; 799 800 port@1 { 801 reg = <1>; 802 merge_funnel_in1: endpoint { 803 remote-endpoint = <&funnel1_out>; 804 }; 805 }; 806 }; 807 }; 808 809 replicator@6046000 { 810 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 811 reg = <0 0x06046000 0 0x1000>; 812 813 clocks = <&aoss_qmp>; 814 clock-names = "apb_pclk"; 815 816 out-ports { 817 port { 818 replicator_out: endpoint { 819 remote-endpoint = <&etr_in>; 820 }; 821 }; 822 }; 823 824 in-ports { 825 port { 826 replicator_in: endpoint { 827 remote-endpoint = <&swao_replicator_out>; 828 }; 829 }; 830 }; 831 }; 832 833 etr@6048000 { 834 compatible = "arm,coresight-tmc", "arm,primecell"; 835 reg = <0 0x06048000 0 0x1000>; 836 iommus = <&apps_smmu 0x04c0 0>; 837 838 clocks = <&aoss_qmp>; 839 clock-names = "apb_pclk"; 840 arm,scatter-gather; 841 842 in-ports { 843 port { 844 etr_in: endpoint { 845 remote-endpoint = <&replicator_out>; 846 }; 847 }; 848 }; 849 }; 850 851 funnel@6b04000 { 852 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 853 reg = <0 0x06b04000 0 0x1000>; 854 855 clocks = <&aoss_qmp>; 856 clock-names = "apb_pclk"; 857 858 out-ports { 859 port { 860 swao_funnel_out: endpoint { 861 remote-endpoint = <&etf_in>; 862 }; 863 }; 864 }; 865 866 in-ports { 867 #address-cells = <1>; 868 #size-cells = <0>; 869 870 port@7 { 871 reg = <7>; 872 swao_funnel_in: endpoint { 873 remote-endpoint = <&merge_funnel_out>; 874 }; 875 }; 876 }; 877 }; 878 879 etf@6b05000 { 880 compatible = "arm,coresight-tmc", "arm,primecell"; 881 reg = <0 0x06b05000 0 0x1000>; 882 883 clocks = <&aoss_qmp>; 884 clock-names = "apb_pclk"; 885 886 out-ports { 887 port { 888 etf_out: endpoint { 889 remote-endpoint = <&swao_replicator_in>; 890 }; 891 }; 892 }; 893 894 in-ports { 895 port { 896 etf_in: endpoint { 897 remote-endpoint = <&swao_funnel_out>; 898 }; 899 }; 900 }; 901 }; 902 903 replicator@6b06000 { 904 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 905 reg = <0 0x06b06000 0 0x1000>; 906 907 clocks = <&aoss_qmp>; 908 clock-names = "apb_pclk"; 909 qcom,replicator-loses-context; 910 911 out-ports { 912 port { 913 swao_replicator_out: endpoint { 914 remote-endpoint = <&replicator_in>; 915 }; 916 }; 917 }; 918 919 in-ports { 920 port { 921 swao_replicator_in: endpoint { 922 remote-endpoint = <&etf_out>; 923 }; 924 }; 925 }; 926 }; 927 928 etm@7040000 { 929 compatible = "arm,coresight-etm4x", "arm,primecell"; 930 reg = <0 0x07040000 0 0x1000>; 931 932 cpu = <&CPU0>; 933 934 clocks = <&aoss_qmp>; 935 clock-names = "apb_pclk"; 936 arm,coresight-loses-context-with-cpu; 937 qcom,skip-power-up; 938 939 out-ports { 940 port { 941 etm0_out: endpoint { 942 remote-endpoint = <&apss_funnel_in0>; 943 }; 944 }; 945 }; 946 }; 947 948 etm@7140000 { 949 compatible = "arm,coresight-etm4x", "arm,primecell"; 950 reg = <0 0x07140000 0 0x1000>; 951 952 cpu = <&CPU1>; 953 954 clocks = <&aoss_qmp>; 955 clock-names = "apb_pclk"; 956 arm,coresight-loses-context-with-cpu; 957 qcom,skip-power-up; 958 959 out-ports { 960 port { 961 etm1_out: endpoint { 962 remote-endpoint = <&apss_funnel_in1>; 963 }; 964 }; 965 }; 966 }; 967 968 etm@7240000 { 969 compatible = "arm,coresight-etm4x", "arm,primecell"; 970 reg = <0 0x07240000 0 0x1000>; 971 972 cpu = <&CPU2>; 973 974 clocks = <&aoss_qmp>; 975 clock-names = "apb_pclk"; 976 arm,coresight-loses-context-with-cpu; 977 qcom,skip-power-up; 978 979 out-ports { 980 port { 981 etm2_out: endpoint { 982 remote-endpoint = <&apss_funnel_in2>; 983 }; 984 }; 985 }; 986 }; 987 988 etm@7340000 { 989 compatible = "arm,coresight-etm4x", "arm,primecell"; 990 reg = <0 0x07340000 0 0x1000>; 991 992 cpu = <&CPU3>; 993 994 clocks = <&aoss_qmp>; 995 clock-names = "apb_pclk"; 996 arm,coresight-loses-context-with-cpu; 997 qcom,skip-power-up; 998 999 out-ports { 1000 port { 1001 etm3_out: endpoint { 1002 remote-endpoint = <&apss_funnel_in3>; 1003 }; 1004 }; 1005 }; 1006 }; 1007 1008 etm@7440000 { 1009 compatible = "arm,coresight-etm4x", "arm,primecell"; 1010 reg = <0 0x07440000 0 0x1000>; 1011 1012 cpu = <&CPU4>; 1013 1014 clocks = <&aoss_qmp>; 1015 clock-names = "apb_pclk"; 1016 arm,coresight-loses-context-with-cpu; 1017 qcom,skip-power-up; 1018 1019 out-ports { 1020 port { 1021 etm4_out: endpoint { 1022 remote-endpoint = <&apss_funnel_in4>; 1023 }; 1024 }; 1025 }; 1026 }; 1027 1028 etm@7540000 { 1029 compatible = "arm,coresight-etm4x", "arm,primecell"; 1030 reg = <0 0x07540000 0 0x1000>; 1031 1032 cpu = <&CPU5>; 1033 1034 clocks = <&aoss_qmp>; 1035 clock-names = "apb_pclk"; 1036 arm,coresight-loses-context-with-cpu; 1037 qcom,skip-power-up; 1038 1039 out-ports { 1040 port { 1041 etm5_out: endpoint { 1042 remote-endpoint = <&apss_funnel_in5>; 1043 }; 1044 }; 1045 }; 1046 }; 1047 1048 etm@7640000 { 1049 compatible = "arm,coresight-etm4x", "arm,primecell"; 1050 reg = <0 0x07640000 0 0x1000>; 1051 1052 cpu = <&CPU6>; 1053 1054 clocks = <&aoss_qmp>; 1055 clock-names = "apb_pclk"; 1056 arm,coresight-loses-context-with-cpu; 1057 qcom,skip-power-up; 1058 1059 out-ports { 1060 port { 1061 etm6_out: endpoint { 1062 remote-endpoint = <&apss_funnel_in6>; 1063 }; 1064 }; 1065 }; 1066 }; 1067 1068 etm@7740000 { 1069 compatible = "arm,coresight-etm4x", "arm,primecell"; 1070 reg = <0 0x07740000 0 0x1000>; 1071 1072 cpu = <&CPU7>; 1073 1074 clocks = <&aoss_qmp>; 1075 clock-names = "apb_pclk"; 1076 arm,coresight-loses-context-with-cpu; 1077 qcom,skip-power-up; 1078 1079 out-ports { 1080 port { 1081 etm7_out: endpoint { 1082 remote-endpoint = <&apss_funnel_in7>; 1083 }; 1084 }; 1085 }; 1086 }; 1087 1088 funnel@7800000 { /* APSS Funnel */ 1089 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1090 reg = <0 0x07800000 0 0x1000>; 1091 1092 clocks = <&aoss_qmp>; 1093 clock-names = "apb_pclk"; 1094 1095 out-ports { 1096 port { 1097 apss_funnel_out: endpoint { 1098 remote-endpoint = <&apss_merge_funnel_in>; 1099 }; 1100 }; 1101 }; 1102 1103 in-ports { 1104 #address-cells = <1>; 1105 #size-cells = <0>; 1106 1107 port@0 { 1108 reg = <0>; 1109 apss_funnel_in0: endpoint { 1110 remote-endpoint = <&etm0_out>; 1111 }; 1112 }; 1113 1114 port@1 { 1115 reg = <1>; 1116 apss_funnel_in1: endpoint { 1117 remote-endpoint = <&etm1_out>; 1118 }; 1119 }; 1120 1121 port@2 { 1122 reg = <2>; 1123 apss_funnel_in2: endpoint { 1124 remote-endpoint = <&etm2_out>; 1125 }; 1126 }; 1127 1128 port@3 { 1129 reg = <3>; 1130 apss_funnel_in3: endpoint { 1131 remote-endpoint = <&etm3_out>; 1132 }; 1133 }; 1134 1135 port@4 { 1136 reg = <4>; 1137 apss_funnel_in4: endpoint { 1138 remote-endpoint = <&etm4_out>; 1139 }; 1140 }; 1141 1142 port@5 { 1143 reg = <5>; 1144 apss_funnel_in5: endpoint { 1145 remote-endpoint = <&etm5_out>; 1146 }; 1147 }; 1148 1149 port@6 { 1150 reg = <6>; 1151 apss_funnel_in6: endpoint { 1152 remote-endpoint = <&etm6_out>; 1153 }; 1154 }; 1155 1156 port@7 { 1157 reg = <7>; 1158 apss_funnel_in7: endpoint { 1159 remote-endpoint = <&etm7_out>; 1160 }; 1161 }; 1162 }; 1163 }; 1164 1165 funnel@7810000 { 1166 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1167 reg = <0 0x07810000 0 0x1000>; 1168 1169 clocks = <&aoss_qmp>; 1170 clock-names = "apb_pclk"; 1171 1172 out-ports { 1173 port { 1174 apss_merge_funnel_out: endpoint { 1175 remote-endpoint = <&funnel1_in4>; 1176 }; 1177 }; 1178 }; 1179 1180 in-ports { 1181 port { 1182 apss_merge_funnel_in: endpoint { 1183 remote-endpoint = <&apss_funnel_out>; 1184 }; 1185 }; 1186 }; 1187 }; 1188 1189 sdhc_2: sdhci@8804000 { 1190 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 1191 status = "disabled"; 1192 1193 reg = <0 0x08804000 0 0x1000>; 1194 1195 iommus = <&apps_smmu 0x100 0x0>; 1196 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1198 interrupt-names = "hc_irq", "pwr_irq"; 1199 1200 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 1201 <&gcc GCC_SDCC2_AHB_CLK>, 1202 <&rpmhcc RPMH_CXO_CLK>; 1203 clock-names = "core", "iface", "xo"; 1204 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 1205 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 1206 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1207 power-domains = <&rpmhpd SC7280_CX>; 1208 operating-points-v2 = <&sdhc2_opp_table>; 1209 1210 bus-width = <4>; 1211 1212 qcom,dll-config = <0x0007642c>; 1213 1214 sdhc2_opp_table: opp-table { 1215 compatible = "operating-points-v2"; 1216 1217 opp-100000000 { 1218 opp-hz = /bits/ 64 <100000000>; 1219 required-opps = <&rpmhpd_opp_low_svs>; 1220 opp-peak-kBps = <1800000 400000>; 1221 opp-avg-kBps = <100000 0>; 1222 }; 1223 1224 opp-202000000 { 1225 opp-hz = /bits/ 64 <202000000>; 1226 required-opps = <&rpmhpd_opp_nom>; 1227 opp-peak-kBps = <5400000 1600000>; 1228 opp-avg-kBps = <200000 0>; 1229 }; 1230 }; 1231 1232 }; 1233 1234 usb_1_hsphy: phy@88e3000 { 1235 compatible = "qcom,sc7280-usb-hs-phy", 1236 "qcom,usb-snps-hs-7nm-phy"; 1237 reg = <0 0x088e3000 0 0x400>; 1238 status = "disabled"; 1239 #phy-cells = <0>; 1240 1241 clocks = <&rpmhcc RPMH_CXO_CLK>; 1242 clock-names = "ref"; 1243 1244 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1245 }; 1246 1247 usb_2_hsphy: phy@88e4000 { 1248 compatible = "qcom,sc7280-usb-hs-phy", 1249 "qcom,usb-snps-hs-7nm-phy"; 1250 reg = <0 0x088e4000 0 0x400>; 1251 status = "disabled"; 1252 #phy-cells = <0>; 1253 1254 clocks = <&rpmhcc RPMH_CXO_CLK>; 1255 clock-names = "ref"; 1256 1257 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1258 }; 1259 1260 usb_1_qmpphy: phy-wrapper@88e9000 { 1261 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 1262 "qcom,sm8250-qmp-usb3-dp-phy"; 1263 reg = <0 0x088e9000 0 0x200>, 1264 <0 0x088e8000 0 0x40>, 1265 <0 0x088ea000 0 0x200>; 1266 status = "disabled"; 1267 #address-cells = <2>; 1268 #size-cells = <2>; 1269 ranges; 1270 1271 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1272 <&rpmhcc RPMH_CXO_CLK>, 1273 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1274 clock-names = "aux", "ref_clk_src", "com_aux"; 1275 1276 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 1277 <&gcc GCC_USB3_PHY_PRIM_BCR>; 1278 reset-names = "phy", "common"; 1279 1280 usb_1_ssphy: usb3-phy@88e9200 { 1281 reg = <0 0x088e9200 0 0x200>, 1282 <0 0x088e9400 0 0x200>, 1283 <0 0x088e9c00 0 0x400>, 1284 <0 0x088e9600 0 0x200>, 1285 <0 0x088e9800 0 0x200>, 1286 <0 0x088e9a00 0 0x100>; 1287 #clock-cells = <0>; 1288 #phy-cells = <0>; 1289 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1290 clock-names = "pipe0"; 1291 clock-output-names = "usb3_phy_pipe_clk_src"; 1292 }; 1293 1294 dp_phy: dp-phy@88ea200 { 1295 reg = <0 0x088ea200 0 0x200>, 1296 <0 0x088ea400 0 0x200>, 1297 <0 0x088eaa00 0 0x200>, 1298 <0 0x088ea600 0 0x200>, 1299 <0 0x088ea800 0 0x200>; 1300 #phy-cells = <0>; 1301 #clock-cells = <1>; 1302 }; 1303 }; 1304 1305 usb_2: usb@8cf8800 { 1306 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 1307 reg = <0 0x08cf8800 0 0x400>; 1308 status = "disabled"; 1309 #address-cells = <2>; 1310 #size-cells = <2>; 1311 ranges; 1312 dma-ranges; 1313 1314 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 1315 <&gcc GCC_USB30_SEC_MASTER_CLK>, 1316 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 1317 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1318 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 1319 clock-names = "cfg_noc", "core", "iface","mock_utmi", 1320 "sleep"; 1321 1322 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1323 <&gcc GCC_USB30_SEC_MASTER_CLK>; 1324 assigned-clock-rates = <19200000>, <200000000>; 1325 1326 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1327 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 1328 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 1329 interrupt-names = "hs_phy_irq", 1330 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1331 1332 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 1333 1334 resets = <&gcc GCC_USB30_SEC_BCR>; 1335 1336 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 1337 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 1338 interconnect-names = "usb-ddr", "apps-usb"; 1339 1340 usb_2_dwc3: usb@8c00000 { 1341 compatible = "snps,dwc3"; 1342 reg = <0 0x08c00000 0 0xe000>; 1343 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1344 iommus = <&apps_smmu 0xa0 0x0>; 1345 snps,dis_u2_susphy_quirk; 1346 snps,dis_enblslpm_quirk; 1347 phys = <&usb_2_hsphy>; 1348 phy-names = "usb2-phy"; 1349 maximum-speed = "high-speed"; 1350 }; 1351 }; 1352 1353 dc_noc: interconnect@90e0000 { 1354 reg = <0 0x090e0000 0 0x5080>; 1355 compatible = "qcom,sc7280-dc-noc"; 1356 #interconnect-cells = <2>; 1357 qcom,bcm-voters = <&apps_bcm_voter>; 1358 }; 1359 1360 gem_noc: interconnect@9100000 { 1361 reg = <0 0x9100000 0 0xe2200>; 1362 compatible = "qcom,sc7280-gem-noc"; 1363 #interconnect-cells = <2>; 1364 qcom,bcm-voters = <&apps_bcm_voter>; 1365 }; 1366 1367 system-cache-controller@9200000 { 1368 compatible = "qcom,sc7280-llcc"; 1369 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 1370 reg-names = "llcc_base", "llcc_broadcast_base"; 1371 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1372 }; 1373 1374 nsp_noc: interconnect@a0c0000 { 1375 reg = <0 0x0a0c0000 0 0x10000>; 1376 compatible = "qcom,sc7280-nsp-noc"; 1377 #interconnect-cells = <2>; 1378 qcom,bcm-voters = <&apps_bcm_voter>; 1379 }; 1380 1381 usb_1: usb@a6f8800 { 1382 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 1383 reg = <0 0x0a6f8800 0 0x400>; 1384 status = "disabled"; 1385 #address-cells = <2>; 1386 #size-cells = <2>; 1387 ranges; 1388 dma-ranges; 1389 1390 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1391 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1392 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1393 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1394 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 1395 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1396 "sleep"; 1397 1398 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1399 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1400 assigned-clock-rates = <19200000>, <200000000>; 1401 1402 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1403 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1404 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1405 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 1406 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 1407 "dm_hs_phy_irq", "ss_phy_irq"; 1408 1409 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1410 1411 resets = <&gcc GCC_USB30_PRIM_BCR>; 1412 1413 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 1414 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 1415 interconnect-names = "usb-ddr", "apps-usb"; 1416 1417 usb_1_dwc3: usb@a600000 { 1418 compatible = "snps,dwc3"; 1419 reg = <0 0x0a600000 0 0xe000>; 1420 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1421 iommus = <&apps_smmu 0xe0 0x0>; 1422 snps,dis_u2_susphy_quirk; 1423 snps,dis_enblslpm_quirk; 1424 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1425 phy-names = "usb2-phy", "usb3-phy"; 1426 maximum-speed = "super-speed"; 1427 }; 1428 }; 1429 1430 videocc: clock-controller@aaf0000 { 1431 compatible = "qcom,sc7280-videocc"; 1432 reg = <0 0xaaf0000 0 0x10000>; 1433 clocks = <&rpmhcc RPMH_CXO_CLK>, 1434 <&rpmhcc RPMH_CXO_CLK_A>; 1435 clock-names = "bi_tcxo", "bi_tcxo_ao"; 1436 #clock-cells = <1>; 1437 #reset-cells = <1>; 1438 #power-domain-cells = <1>; 1439 }; 1440 1441 dispcc: clock-controller@af00000 { 1442 compatible = "qcom,sc7280-dispcc"; 1443 reg = <0 0xaf00000 0 0x20000>; 1444 clocks = <&rpmhcc RPMH_CXO_CLK>, 1445 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 1446 <0>, <0>, <0>, <0>, <0>, <0>; 1447 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 1448 "dsi0_phy_pll_out_byteclk", 1449 "dsi0_phy_pll_out_dsiclk", 1450 "dp_phy_pll_link_clk", 1451 "dp_phy_pll_vco_div_clk", 1452 "edp_phy_pll_link_clk", 1453 "edp_phy_pll_vco_div_clk"; 1454 #clock-cells = <1>; 1455 #reset-cells = <1>; 1456 #power-domain-cells = <1>; 1457 }; 1458 1459 pdc: interrupt-controller@b220000 { 1460 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 1461 reg = <0 0x0b220000 0 0x30000>; 1462 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 1463 <55 306 4>, <59 312 3>, <62 374 2>, 1464 <64 434 2>, <66 438 3>, <69 86 1>, 1465 <70 520 54>, <124 609 31>, <155 63 1>, 1466 <156 716 12>; 1467 #interrupt-cells = <2>; 1468 interrupt-parent = <&intc>; 1469 interrupt-controller; 1470 }; 1471 1472 pdc_reset: reset-controller@b5e0000 { 1473 compatible = "qcom,sc7280-pdc-global"; 1474 reg = <0 0x0b5e0000 0 0x20000>; 1475 #reset-cells = <1>; 1476 }; 1477 1478 tsens0: thermal-sensor@c263000 { 1479 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 1480 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1481 <0 0x0c222000 0 0x1ff>; /* SROT */ 1482 #qcom,sensors = <15>; 1483 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1485 interrupt-names = "uplow","critical"; 1486 #thermal-sensor-cells = <1>; 1487 }; 1488 1489 tsens1: thermal-sensor@c265000 { 1490 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 1491 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1492 <0 0x0c223000 0 0x1ff>; /* SROT */ 1493 #qcom,sensors = <12>; 1494 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1496 interrupt-names = "uplow","critical"; 1497 #thermal-sensor-cells = <1>; 1498 }; 1499 1500 aoss_reset: reset-controller@c2a0000 { 1501 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 1502 reg = <0 0x0c2a0000 0 0x31000>; 1503 #reset-cells = <1>; 1504 }; 1505 1506 aoss_qmp: power-controller@c300000 { 1507 compatible = "qcom,sc7280-aoss-qmp"; 1508 reg = <0 0x0c300000 0 0x100000>; 1509 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 1510 IPCC_MPROC_SIGNAL_GLINK_QMP 1511 IRQ_TYPE_EDGE_RISING>; 1512 mboxes = <&ipcc IPCC_CLIENT_AOP 1513 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1514 1515 #clock-cells = <0>; 1516 #power-domain-cells = <1>; 1517 }; 1518 1519 spmi_bus: spmi@c440000 { 1520 compatible = "qcom,spmi-pmic-arb"; 1521 reg = <0 0x0c440000 0 0x1100>, 1522 <0 0x0c600000 0 0x2000000>, 1523 <0 0x0e600000 0 0x100000>, 1524 <0 0x0e700000 0 0xa0000>, 1525 <0 0x0c40a000 0 0x26000>; 1526 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1527 interrupt-names = "periph_irq"; 1528 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1529 qcom,ee = <0>; 1530 qcom,channel = <0>; 1531 #address-cells = <1>; 1532 #size-cells = <1>; 1533 interrupt-controller; 1534 #interrupt-cells = <4>; 1535 }; 1536 1537 tlmm: pinctrl@f100000 { 1538 compatible = "qcom,sc7280-pinctrl"; 1539 reg = <0 0x0f100000 0 0x300000>; 1540 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1541 gpio-controller; 1542 #gpio-cells = <2>; 1543 interrupt-controller; 1544 #interrupt-cells = <2>; 1545 gpio-ranges = <&tlmm 0 0 175>; 1546 wakeup-parent = <&pdc>; 1547 1548 qup_uart5_default: qup-uart5-default { 1549 pins = "gpio46", "gpio47"; 1550 function = "qup13"; 1551 }; 1552 1553 sdc1_on: sdc1-on { 1554 clk { 1555 pins = "sdc1_clk"; 1556 }; 1557 1558 cmd { 1559 pins = "sdc1_cmd"; 1560 }; 1561 1562 data { 1563 pins = "sdc1_data"; 1564 }; 1565 1566 rclk { 1567 pins = "sdc1_rclk"; 1568 }; 1569 }; 1570 1571 sdc1_off: sdc1-off { 1572 clk { 1573 pins = "sdc1_clk"; 1574 drive-strength = <2>; 1575 bias-bus-hold; 1576 }; 1577 1578 cmd { 1579 pins = "sdc1_cmd"; 1580 drive-strength = <2>; 1581 bias-bus-hold; 1582 }; 1583 1584 data { 1585 pins = "sdc1_data"; 1586 drive-strength = <2>; 1587 bias-bus-hold; 1588 }; 1589 1590 rclk { 1591 pins = "sdc1_rclk"; 1592 bias-bus-hold; 1593 }; 1594 }; 1595 1596 sdc2_on: sdc2-on { 1597 clk { 1598 pins = "sdc2_clk"; 1599 }; 1600 1601 cmd { 1602 pins = "sdc2_cmd"; 1603 }; 1604 1605 data { 1606 pins = "sdc2_data"; 1607 }; 1608 }; 1609 1610 sdc2_off: sdc2-off { 1611 clk { 1612 pins = "sdc2_clk"; 1613 drive-strength = <2>; 1614 bias-bus-hold; 1615 }; 1616 1617 cmd { 1618 pins ="sdc2_cmd"; 1619 drive-strength = <2>; 1620 bias-bus-hold; 1621 }; 1622 1623 data { 1624 pins ="sdc2_data"; 1625 drive-strength = <2>; 1626 bias-bus-hold; 1627 }; 1628 }; 1629 }; 1630 1631 apps_smmu: iommu@15000000 { 1632 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 1633 reg = <0 0x15000000 0 0x100000>; 1634 #iommu-cells = <2>; 1635 #global-interrupts = <1>; 1636 dma-coherent; 1637 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1651 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1652 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1655 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1656 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1657 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1658 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1659 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1660 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1661 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1662 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1663 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1665 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1666 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1667 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1668 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1669 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1670 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1672 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1673 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1674 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1675 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1676 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1677 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1680 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1681 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1682 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1683 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1684 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1685 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1686 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1688 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1690 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1691 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1692 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1693 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1694 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1695 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1696 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1697 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1698 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1699 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1700 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1701 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1702 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1703 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1704 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1705 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1706 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1707 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1708 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1709 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1710 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1711 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1712 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1713 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1714 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1715 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1716 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1717 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1718 }; 1719 1720 intc: interrupt-controller@17a00000 { 1721 compatible = "arm,gic-v3"; 1722 #address-cells = <2>; 1723 #size-cells = <2>; 1724 ranges; 1725 #interrupt-cells = <3>; 1726 interrupt-controller; 1727 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 1728 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 1729 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 1730 1731 gic-its@17a40000 { 1732 compatible = "arm,gic-v3-its"; 1733 msi-controller; 1734 #msi-cells = <1>; 1735 reg = <0 0x17a40000 0 0x20000>; 1736 status = "disabled"; 1737 }; 1738 }; 1739 1740 watchdog@17c10000 { 1741 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 1742 reg = <0 0x17c10000 0 0x1000>; 1743 clocks = <&sleep_clk>; 1744 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1745 }; 1746 1747 timer@17c20000 { 1748 #address-cells = <2>; 1749 #size-cells = <2>; 1750 ranges; 1751 compatible = "arm,armv7-timer-mem"; 1752 reg = <0 0x17c20000 0 0x1000>; 1753 1754 frame@17c21000 { 1755 frame-number = <0>; 1756 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1758 reg = <0 0x17c21000 0 0x1000>, 1759 <0 0x17c22000 0 0x1000>; 1760 }; 1761 1762 frame@17c23000 { 1763 frame-number = <1>; 1764 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1765 reg = <0 0x17c23000 0 0x1000>; 1766 status = "disabled"; 1767 }; 1768 1769 frame@17c25000 { 1770 frame-number = <2>; 1771 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1772 reg = <0 0x17c25000 0 0x1000>; 1773 status = "disabled"; 1774 }; 1775 1776 frame@17c27000 { 1777 frame-number = <3>; 1778 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1779 reg = <0 0x17c27000 0 0x1000>; 1780 status = "disabled"; 1781 }; 1782 1783 frame@17c29000 { 1784 frame-number = <4>; 1785 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1786 reg = <0 0x17c29000 0 0x1000>; 1787 status = "disabled"; 1788 }; 1789 1790 frame@17c2b000 { 1791 frame-number = <5>; 1792 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1793 reg = <0 0x17c2b000 0 0x1000>; 1794 status = "disabled"; 1795 }; 1796 1797 frame@17c2d000 { 1798 frame-number = <6>; 1799 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1800 reg = <0 0x17c2d000 0 0x1000>; 1801 status = "disabled"; 1802 }; 1803 }; 1804 1805 apps_rsc: rsc@18200000 { 1806 compatible = "qcom,rpmh-rsc"; 1807 reg = <0 0x18200000 0 0x10000>, 1808 <0 0x18210000 0 0x10000>, 1809 <0 0x18220000 0 0x10000>; 1810 reg-names = "drv-0", "drv-1", "drv-2"; 1811 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1814 qcom,tcs-offset = <0xd00>; 1815 qcom,drv-id = <2>; 1816 qcom,tcs-config = <ACTIVE_TCS 2>, 1817 <SLEEP_TCS 3>, 1818 <WAKE_TCS 3>, 1819 <CONTROL_TCS 1>; 1820 1821 apps_bcm_voter: bcm-voter { 1822 compatible = "qcom,bcm-voter"; 1823 }; 1824 1825 rpmhpd: power-controller { 1826 compatible = "qcom,sc7280-rpmhpd"; 1827 #power-domain-cells = <1>; 1828 operating-points-v2 = <&rpmhpd_opp_table>; 1829 1830 rpmhpd_opp_table: opp-table { 1831 compatible = "operating-points-v2"; 1832 1833 rpmhpd_opp_ret: opp1 { 1834 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1835 }; 1836 1837 rpmhpd_opp_low_svs: opp2 { 1838 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1839 }; 1840 1841 rpmhpd_opp_svs: opp3 { 1842 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1843 }; 1844 1845 rpmhpd_opp_svs_l1: opp4 { 1846 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1847 }; 1848 1849 rpmhpd_opp_svs_l2: opp5 { 1850 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1851 }; 1852 1853 rpmhpd_opp_nom: opp6 { 1854 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1855 }; 1856 1857 rpmhpd_opp_nom_l1: opp7 { 1858 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1859 }; 1860 1861 rpmhpd_opp_turbo: opp8 { 1862 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1863 }; 1864 1865 rpmhpd_opp_turbo_l1: opp9 { 1866 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1867 }; 1868 }; 1869 }; 1870 1871 rpmhcc: clock-controller { 1872 compatible = "qcom,sc7280-rpmh-clk"; 1873 clocks = <&xo_board>; 1874 clock-names = "xo"; 1875 #clock-cells = <1>; 1876 }; 1877 }; 1878 1879 cpufreq_hw: cpufreq@18591000 { 1880 compatible = "qcom,cpufreq-epss"; 1881 reg = <0 0x18591100 0 0x900>, 1882 <0 0x18592100 0 0x900>, 1883 <0 0x18593100 0 0x900>; 1884 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 1885 clock-names = "xo", "alternate"; 1886 #freq-domain-cells = <1>; 1887 }; 1888 }; 1889 1890 thermal_zones: thermal-zones { 1891 cpu0-thermal { 1892 polling-delay-passive = <250>; 1893 polling-delay = <0>; 1894 1895 thermal-sensors = <&tsens0 1>; 1896 1897 trips { 1898 cpu0_alert0: trip-point0 { 1899 temperature = <90000>; 1900 hysteresis = <2000>; 1901 type = "passive"; 1902 }; 1903 1904 cpu0_alert1: trip-point1 { 1905 temperature = <95000>; 1906 hysteresis = <2000>; 1907 type = "passive"; 1908 }; 1909 1910 cpu0_crit: cpu-crit { 1911 temperature = <110000>; 1912 hysteresis = <0>; 1913 type = "critical"; 1914 }; 1915 }; 1916 1917 cooling-maps { 1918 map0 { 1919 trip = <&cpu0_alert0>; 1920 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1921 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1922 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1923 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1924 }; 1925 map1 { 1926 trip = <&cpu0_alert1>; 1927 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1928 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1929 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1930 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1931 }; 1932 }; 1933 }; 1934 1935 cpu1-thermal { 1936 polling-delay-passive = <250>; 1937 polling-delay = <0>; 1938 1939 thermal-sensors = <&tsens0 2>; 1940 1941 trips { 1942 cpu1_alert0: trip-point0 { 1943 temperature = <90000>; 1944 hysteresis = <2000>; 1945 type = "passive"; 1946 }; 1947 1948 cpu1_alert1: trip-point1 { 1949 temperature = <95000>; 1950 hysteresis = <2000>; 1951 type = "passive"; 1952 }; 1953 1954 cpu1_crit: cpu-crit { 1955 temperature = <110000>; 1956 hysteresis = <0>; 1957 type = "critical"; 1958 }; 1959 }; 1960 1961 cooling-maps { 1962 map0 { 1963 trip = <&cpu1_alert0>; 1964 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1965 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1966 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1967 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1968 }; 1969 map1 { 1970 trip = <&cpu1_alert1>; 1971 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1972 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1973 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1974 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1975 }; 1976 }; 1977 }; 1978 1979 cpu2-thermal { 1980 polling-delay-passive = <250>; 1981 polling-delay = <0>; 1982 1983 thermal-sensors = <&tsens0 3>; 1984 1985 trips { 1986 cpu2_alert0: trip-point0 { 1987 temperature = <90000>; 1988 hysteresis = <2000>; 1989 type = "passive"; 1990 }; 1991 1992 cpu2_alert1: trip-point1 { 1993 temperature = <95000>; 1994 hysteresis = <2000>; 1995 type = "passive"; 1996 }; 1997 1998 cpu2_crit: cpu-crit { 1999 temperature = <110000>; 2000 hysteresis = <0>; 2001 type = "critical"; 2002 }; 2003 }; 2004 2005 cooling-maps { 2006 map0 { 2007 trip = <&cpu2_alert0>; 2008 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2009 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2010 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2011 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2012 }; 2013 map1 { 2014 trip = <&cpu2_alert1>; 2015 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2016 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2017 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2018 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2019 }; 2020 }; 2021 }; 2022 2023 cpu3-thermal { 2024 polling-delay-passive = <250>; 2025 polling-delay = <0>; 2026 2027 thermal-sensors = <&tsens0 4>; 2028 2029 trips { 2030 cpu3_alert0: trip-point0 { 2031 temperature = <90000>; 2032 hysteresis = <2000>; 2033 type = "passive"; 2034 }; 2035 2036 cpu3_alert1: trip-point1 { 2037 temperature = <95000>; 2038 hysteresis = <2000>; 2039 type = "passive"; 2040 }; 2041 2042 cpu3_crit: cpu-crit { 2043 temperature = <110000>; 2044 hysteresis = <0>; 2045 type = "critical"; 2046 }; 2047 }; 2048 2049 cooling-maps { 2050 map0 { 2051 trip = <&cpu3_alert0>; 2052 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2053 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2054 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2055 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2056 }; 2057 map1 { 2058 trip = <&cpu3_alert1>; 2059 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2060 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2061 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2062 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2063 }; 2064 }; 2065 }; 2066 2067 cpu4-thermal { 2068 polling-delay-passive = <250>; 2069 polling-delay = <0>; 2070 2071 thermal-sensors = <&tsens0 7>; 2072 2073 trips { 2074 cpu4_alert0: trip-point0 { 2075 temperature = <90000>; 2076 hysteresis = <2000>; 2077 type = "passive"; 2078 }; 2079 2080 cpu4_alert1: trip-point1 { 2081 temperature = <95000>; 2082 hysteresis = <2000>; 2083 type = "passive"; 2084 }; 2085 2086 cpu4_crit: cpu-crit { 2087 temperature = <110000>; 2088 hysteresis = <0>; 2089 type = "critical"; 2090 }; 2091 }; 2092 2093 cooling-maps { 2094 map0 { 2095 trip = <&cpu4_alert0>; 2096 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2097 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2098 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2099 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2100 }; 2101 map1 { 2102 trip = <&cpu4_alert1>; 2103 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2104 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2105 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2106 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2107 }; 2108 }; 2109 }; 2110 2111 cpu5-thermal { 2112 polling-delay-passive = <250>; 2113 polling-delay = <0>; 2114 2115 thermal-sensors = <&tsens0 8>; 2116 2117 trips { 2118 cpu5_alert0: trip-point0 { 2119 temperature = <90000>; 2120 hysteresis = <2000>; 2121 type = "passive"; 2122 }; 2123 2124 cpu5_alert1: trip-point1 { 2125 temperature = <95000>; 2126 hysteresis = <2000>; 2127 type = "passive"; 2128 }; 2129 2130 cpu5_crit: cpu-crit { 2131 temperature = <110000>; 2132 hysteresis = <0>; 2133 type = "critical"; 2134 }; 2135 }; 2136 2137 cooling-maps { 2138 map0 { 2139 trip = <&cpu5_alert0>; 2140 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2141 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2142 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2143 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2144 }; 2145 map1 { 2146 trip = <&cpu5_alert1>; 2147 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2148 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2149 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2150 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2151 }; 2152 }; 2153 }; 2154 2155 cpu6-thermal { 2156 polling-delay-passive = <250>; 2157 polling-delay = <0>; 2158 2159 thermal-sensors = <&tsens0 9>; 2160 2161 trips { 2162 cpu6_alert0: trip-point0 { 2163 temperature = <90000>; 2164 hysteresis = <2000>; 2165 type = "passive"; 2166 }; 2167 2168 cpu6_alert1: trip-point1 { 2169 temperature = <95000>; 2170 hysteresis = <2000>; 2171 type = "passive"; 2172 }; 2173 2174 cpu6_crit: cpu-crit { 2175 temperature = <110000>; 2176 hysteresis = <0>; 2177 type = "critical"; 2178 }; 2179 }; 2180 2181 cooling-maps { 2182 map0 { 2183 trip = <&cpu6_alert0>; 2184 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2185 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2186 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2187 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2188 }; 2189 map1 { 2190 trip = <&cpu6_alert1>; 2191 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2192 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2193 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2194 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2195 }; 2196 }; 2197 }; 2198 2199 cpu7-thermal { 2200 polling-delay-passive = <250>; 2201 polling-delay = <0>; 2202 2203 thermal-sensors = <&tsens0 10>; 2204 2205 trips { 2206 cpu7_alert0: trip-point0 { 2207 temperature = <90000>; 2208 hysteresis = <2000>; 2209 type = "passive"; 2210 }; 2211 2212 cpu7_alert1: trip-point1 { 2213 temperature = <95000>; 2214 hysteresis = <2000>; 2215 type = "passive"; 2216 }; 2217 2218 cpu7_crit: cpu-crit { 2219 temperature = <110000>; 2220 hysteresis = <0>; 2221 type = "critical"; 2222 }; 2223 }; 2224 2225 cooling-maps { 2226 map0 { 2227 trip = <&cpu7_alert0>; 2228 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2229 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2230 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2231 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2232 }; 2233 map1 { 2234 trip = <&cpu7_alert1>; 2235 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2236 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2237 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2238 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2239 }; 2240 }; 2241 }; 2242 2243 cpu8-thermal { 2244 polling-delay-passive = <250>; 2245 polling-delay = <0>; 2246 2247 thermal-sensors = <&tsens0 11>; 2248 2249 trips { 2250 cpu8_alert0: trip-point0 { 2251 temperature = <90000>; 2252 hysteresis = <2000>; 2253 type = "passive"; 2254 }; 2255 2256 cpu8_alert1: trip-point1 { 2257 temperature = <95000>; 2258 hysteresis = <2000>; 2259 type = "passive"; 2260 }; 2261 2262 cpu8_crit: cpu-crit { 2263 temperature = <110000>; 2264 hysteresis = <0>; 2265 type = "critical"; 2266 }; 2267 }; 2268 2269 cooling-maps { 2270 map0 { 2271 trip = <&cpu8_alert0>; 2272 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2273 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2274 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2275 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2276 }; 2277 map1 { 2278 trip = <&cpu8_alert1>; 2279 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2280 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2281 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2282 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2283 }; 2284 }; 2285 }; 2286 2287 cpu9-thermal { 2288 polling-delay-passive = <250>; 2289 polling-delay = <0>; 2290 2291 thermal-sensors = <&tsens0 12>; 2292 2293 trips { 2294 cpu9_alert0: trip-point0 { 2295 temperature = <90000>; 2296 hysteresis = <2000>; 2297 type = "passive"; 2298 }; 2299 2300 cpu9_alert1: trip-point1 { 2301 temperature = <95000>; 2302 hysteresis = <2000>; 2303 type = "passive"; 2304 }; 2305 2306 cpu9_crit: cpu-crit { 2307 temperature = <110000>; 2308 hysteresis = <0>; 2309 type = "critical"; 2310 }; 2311 }; 2312 2313 cooling-maps { 2314 map0 { 2315 trip = <&cpu9_alert0>; 2316 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2317 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2318 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2319 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2320 }; 2321 map1 { 2322 trip = <&cpu9_alert1>; 2323 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2324 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2325 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2326 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2327 }; 2328 }; 2329 }; 2330 2331 cpu10-thermal { 2332 polling-delay-passive = <250>; 2333 polling-delay = <0>; 2334 2335 thermal-sensors = <&tsens0 13>; 2336 2337 trips { 2338 cpu10_alert0: trip-point0 { 2339 temperature = <90000>; 2340 hysteresis = <2000>; 2341 type = "passive"; 2342 }; 2343 2344 cpu10_alert1: trip-point1 { 2345 temperature = <95000>; 2346 hysteresis = <2000>; 2347 type = "passive"; 2348 }; 2349 2350 cpu10_crit: cpu-crit { 2351 temperature = <110000>; 2352 hysteresis = <0>; 2353 type = "critical"; 2354 }; 2355 }; 2356 2357 cooling-maps { 2358 map0 { 2359 trip = <&cpu10_alert0>; 2360 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2361 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2362 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2363 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2364 }; 2365 map1 { 2366 trip = <&cpu10_alert1>; 2367 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2368 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2369 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2370 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2371 }; 2372 }; 2373 }; 2374 2375 cpu11-thermal { 2376 polling-delay-passive = <250>; 2377 polling-delay = <0>; 2378 2379 thermal-sensors = <&tsens0 14>; 2380 2381 trips { 2382 cpu11_alert0: trip-point0 { 2383 temperature = <90000>; 2384 hysteresis = <2000>; 2385 type = "passive"; 2386 }; 2387 2388 cpu11_alert1: trip-point1 { 2389 temperature = <95000>; 2390 hysteresis = <2000>; 2391 type = "passive"; 2392 }; 2393 2394 cpu11_crit: cpu-crit { 2395 temperature = <110000>; 2396 hysteresis = <0>; 2397 type = "critical"; 2398 }; 2399 }; 2400 2401 cooling-maps { 2402 map0 { 2403 trip = <&cpu11_alert0>; 2404 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2405 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2406 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2407 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2408 }; 2409 map1 { 2410 trip = <&cpu11_alert1>; 2411 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2412 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2413 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2414 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2415 }; 2416 }; 2417 }; 2418 2419 aoss0-thermal { 2420 polling-delay-passive = <0>; 2421 polling-delay = <0>; 2422 2423 thermal-sensors = <&tsens0 0>; 2424 2425 trips { 2426 aoss0_alert0: trip-point0 { 2427 temperature = <90000>; 2428 hysteresis = <2000>; 2429 type = "hot"; 2430 }; 2431 2432 aoss0_crit: aoss0-crit { 2433 temperature = <110000>; 2434 hysteresis = <0>; 2435 type = "critical"; 2436 }; 2437 }; 2438 }; 2439 2440 aoss1-thermal { 2441 polling-delay-passive = <0>; 2442 polling-delay = <0>; 2443 2444 thermal-sensors = <&tsens1 0>; 2445 2446 trips { 2447 aoss1_alert0: trip-point0 { 2448 temperature = <90000>; 2449 hysteresis = <2000>; 2450 type = "hot"; 2451 }; 2452 2453 aoss1_crit: aoss1-crit { 2454 temperature = <110000>; 2455 hysteresis = <0>; 2456 type = "critical"; 2457 }; 2458 }; 2459 }; 2460 2461 cpuss0-thermal { 2462 polling-delay-passive = <0>; 2463 polling-delay = <0>; 2464 2465 thermal-sensors = <&tsens0 5>; 2466 2467 trips { 2468 cpuss0_alert0: trip-point0 { 2469 temperature = <90000>; 2470 hysteresis = <2000>; 2471 type = "hot"; 2472 }; 2473 cpuss0_crit: cluster0-crit { 2474 temperature = <110000>; 2475 hysteresis = <0>; 2476 type = "critical"; 2477 }; 2478 }; 2479 }; 2480 2481 cpuss1-thermal { 2482 polling-delay-passive = <0>; 2483 polling-delay = <0>; 2484 2485 thermal-sensors = <&tsens0 6>; 2486 2487 trips { 2488 cpuss1_alert0: trip-point0 { 2489 temperature = <90000>; 2490 hysteresis = <2000>; 2491 type = "hot"; 2492 }; 2493 cpuss1_crit: cluster0-crit { 2494 temperature = <110000>; 2495 hysteresis = <0>; 2496 type = "critical"; 2497 }; 2498 }; 2499 }; 2500 2501 gpuss0-thermal { 2502 polling-delay-passive = <0>; 2503 polling-delay = <0>; 2504 2505 thermal-sensors = <&tsens1 1>; 2506 2507 trips { 2508 gpuss0_alert0: trip-point0 { 2509 temperature = <90000>; 2510 hysteresis = <2000>; 2511 type = "hot"; 2512 }; 2513 2514 gpuss0_crit: gpuss0-crit { 2515 temperature = <110000>; 2516 hysteresis = <0>; 2517 type = "critical"; 2518 }; 2519 }; 2520 }; 2521 2522 gpuss1-thermal { 2523 polling-delay-passive = <0>; 2524 polling-delay = <0>; 2525 2526 thermal-sensors = <&tsens1 2>; 2527 2528 trips { 2529 gpuss1_alert0: trip-point0 { 2530 temperature = <90000>; 2531 hysteresis = <2000>; 2532 type = "hot"; 2533 }; 2534 2535 gpuss1_crit: gpuss1-crit { 2536 temperature = <110000>; 2537 hysteresis = <0>; 2538 type = "critical"; 2539 }; 2540 }; 2541 }; 2542 2543 nspss0-thermal { 2544 polling-delay-passive = <0>; 2545 polling-delay = <0>; 2546 2547 thermal-sensors = <&tsens1 3>; 2548 2549 trips { 2550 nspss0_alert0: trip-point0 { 2551 temperature = <90000>; 2552 hysteresis = <2000>; 2553 type = "hot"; 2554 }; 2555 2556 nspss0_crit: nspss0-crit { 2557 temperature = <110000>; 2558 hysteresis = <0>; 2559 type = "critical"; 2560 }; 2561 }; 2562 }; 2563 2564 nspss1-thermal { 2565 polling-delay-passive = <0>; 2566 polling-delay = <0>; 2567 2568 thermal-sensors = <&tsens1 4>; 2569 2570 trips { 2571 nspss1_alert0: trip-point0 { 2572 temperature = <90000>; 2573 hysteresis = <2000>; 2574 type = "hot"; 2575 }; 2576 2577 nspss1_crit: nspss1-crit { 2578 temperature = <110000>; 2579 hysteresis = <0>; 2580 type = "critical"; 2581 }; 2582 }; 2583 }; 2584 2585 video-thermal { 2586 polling-delay-passive = <0>; 2587 polling-delay = <0>; 2588 2589 thermal-sensors = <&tsens1 5>; 2590 2591 trips { 2592 video_alert0: trip-point0 { 2593 temperature = <90000>; 2594 hysteresis = <2000>; 2595 type = "hot"; 2596 }; 2597 2598 video_crit: video-crit { 2599 temperature = <110000>; 2600 hysteresis = <0>; 2601 type = "critical"; 2602 }; 2603 }; 2604 }; 2605 2606 ddr-thermal { 2607 polling-delay-passive = <0>; 2608 polling-delay = <0>; 2609 2610 thermal-sensors = <&tsens1 6>; 2611 2612 trips { 2613 ddr_alert0: trip-point0 { 2614 temperature = <90000>; 2615 hysteresis = <2000>; 2616 type = "hot"; 2617 }; 2618 2619 ddr_crit: ddr-crit { 2620 temperature = <110000>; 2621 hysteresis = <0>; 2622 type = "critical"; 2623 }; 2624 }; 2625 }; 2626 2627 mdmss0-thermal { 2628 polling-delay-passive = <0>; 2629 polling-delay = <0>; 2630 2631 thermal-sensors = <&tsens1 7>; 2632 2633 trips { 2634 mdmss0_alert0: trip-point0 { 2635 temperature = <90000>; 2636 hysteresis = <2000>; 2637 type = "hot"; 2638 }; 2639 2640 mdmss0_crit: mdmss0-crit { 2641 temperature = <110000>; 2642 hysteresis = <0>; 2643 type = "critical"; 2644 }; 2645 }; 2646 }; 2647 2648 mdmss1-thermal { 2649 polling-delay-passive = <0>; 2650 polling-delay = <0>; 2651 2652 thermal-sensors = <&tsens1 8>; 2653 2654 trips { 2655 mdmss1_alert0: trip-point0 { 2656 temperature = <90000>; 2657 hysteresis = <2000>; 2658 type = "hot"; 2659 }; 2660 2661 mdmss1_crit: mdmss1-crit { 2662 temperature = <110000>; 2663 hysteresis = <0>; 2664 type = "critical"; 2665 }; 2666 }; 2667 }; 2668 2669 mdmss2-thermal { 2670 polling-delay-passive = <0>; 2671 polling-delay = <0>; 2672 2673 thermal-sensors = <&tsens1 9>; 2674 2675 trips { 2676 mdmss2_alert0: trip-point0 { 2677 temperature = <90000>; 2678 hysteresis = <2000>; 2679 type = "hot"; 2680 }; 2681 2682 mdmss2_crit: mdmss2-crit { 2683 temperature = <110000>; 2684 hysteresis = <0>; 2685 type = "critical"; 2686 }; 2687 }; 2688 }; 2689 2690 mdmss3-thermal { 2691 polling-delay-passive = <0>; 2692 polling-delay = <0>; 2693 2694 thermal-sensors = <&tsens1 10>; 2695 2696 trips { 2697 mdmss3_alert0: trip-point0 { 2698 temperature = <90000>; 2699 hysteresis = <2000>; 2700 type = "hot"; 2701 }; 2702 2703 mdmss3_crit: mdmss3-crit { 2704 temperature = <110000>; 2705 hysteresis = <0>; 2706 type = "critical"; 2707 }; 2708 }; 2709 }; 2710 2711 camera0-thermal { 2712 polling-delay-passive = <0>; 2713 polling-delay = <0>; 2714 2715 thermal-sensors = <&tsens1 11>; 2716 2717 trips { 2718 camera0_alert0: trip-point0 { 2719 temperature = <90000>; 2720 hysteresis = <2000>; 2721 type = "hot"; 2722 }; 2723 2724 camera0_crit: camera0-crit { 2725 temperature = <110000>; 2726 hysteresis = <0>; 2727 type = "critical"; 2728 }; 2729 }; 2730 }; 2731 }; 2732 2733 timer { 2734 compatible = "arm,armv8-timer"; 2735 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 2736 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 2737 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 2738 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 2739 }; 2740}; 2741