1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,lpass.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 mmc1 = &sdhc_1; 54 mmc2 = &sdhc_2; 55 spi0 = &spi0; 56 spi1 = &spi1; 57 spi2 = &spi2; 58 spi3 = &spi3; 59 spi4 = &spi4; 60 spi5 = &spi5; 61 spi6 = &spi6; 62 spi7 = &spi7; 63 spi8 = &spi8; 64 spi9 = &spi9; 65 spi10 = &spi10; 66 spi11 = &spi11; 67 spi12 = &spi12; 68 spi13 = &spi13; 69 spi14 = &spi14; 70 spi15 = &spi15; 71 }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 clock-frequency = <76800000>; 77 #clock-cells = <0>; 78 }; 79 80 sleep_clk: sleep-clk { 81 compatible = "fixed-clock"; 82 clock-frequency = <32000>; 83 #clock-cells = <0>; 84 }; 85 }; 86 87 reserved-memory { 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges; 91 92 wlan_ce_mem: memory@4cd000 { 93 no-map; 94 reg = <0x0 0x004cd000 0x0 0x1000>; 95 }; 96 97 hyp_mem: memory@80000000 { 98 reg = <0x0 0x80000000 0x0 0x600000>; 99 no-map; 100 }; 101 102 xbl_mem: memory@80600000 { 103 reg = <0x0 0x80600000 0x0 0x200000>; 104 no-map; 105 }; 106 107 aop_mem: memory@80800000 { 108 reg = <0x0 0x80800000 0x0 0x60000>; 109 no-map; 110 }; 111 112 aop_cmd_db_mem: memory@80860000 { 113 reg = <0x0 0x80860000 0x0 0x20000>; 114 compatible = "qcom,cmd-db"; 115 no-map; 116 }; 117 118 reserved_xbl_uefi_log: memory@80880000 { 119 reg = <0x0 0x80884000 0x0 0x10000>; 120 no-map; 121 }; 122 123 sec_apps_mem: memory@808ff000 { 124 reg = <0x0 0x808ff000 0x0 0x1000>; 125 no-map; 126 }; 127 128 smem_mem: memory@80900000 { 129 reg = <0x0 0x80900000 0x0 0x200000>; 130 no-map; 131 }; 132 133 cpucp_mem: memory@80b00000 { 134 no-map; 135 reg = <0x0 0x80b00000 0x0 0x100000>; 136 }; 137 138 wlan_fw_mem: memory@80c00000 { 139 reg = <0x0 0x80c00000 0x0 0xc00000>; 140 no-map; 141 }; 142 143 video_mem: memory@8b200000 { 144 reg = <0x0 0x8b200000 0x0 0x500000>; 145 no-map; 146 }; 147 148 ipa_fw_mem: memory@8b700000 { 149 reg = <0 0x8b700000 0 0x10000>; 150 no-map; 151 }; 152 153 rmtfs_mem: memory@9c900000 { 154 compatible = "qcom,rmtfs-mem"; 155 reg = <0x0 0x9c900000 0x0 0x280000>; 156 no-map; 157 158 qcom,client-id = <1>; 159 qcom,vmid = <15>; 160 }; 161 }; 162 163 cpus { 164 #address-cells = <2>; 165 #size-cells = <0>; 166 167 CPU0: cpu@0 { 168 device_type = "cpu"; 169 compatible = "qcom,kryo"; 170 reg = <0x0 0x0>; 171 clocks = <&cpufreq_hw 0>; 172 enable-method = "psci"; 173 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 174 &LITTLE_CPU_SLEEP_1 175 &CLUSTER_SLEEP_0>; 176 next-level-cache = <&L2_0>; 177 operating-points-v2 = <&cpu0_opp_table>; 178 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 179 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 180 qcom,freq-domain = <&cpufreq_hw 0>; 181 #cooling-cells = <2>; 182 L2_0: l2-cache { 183 compatible = "cache"; 184 cache-level = <2>; 185 next-level-cache = <&L3_0>; 186 L3_0: l3-cache { 187 compatible = "cache"; 188 cache-level = <3>; 189 }; 190 }; 191 }; 192 193 CPU1: cpu@100 { 194 device_type = "cpu"; 195 compatible = "qcom,kryo"; 196 reg = <0x0 0x100>; 197 clocks = <&cpufreq_hw 0>; 198 enable-method = "psci"; 199 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 200 &LITTLE_CPU_SLEEP_1 201 &CLUSTER_SLEEP_0>; 202 next-level-cache = <&L2_100>; 203 operating-points-v2 = <&cpu0_opp_table>; 204 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 205 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 206 qcom,freq-domain = <&cpufreq_hw 0>; 207 #cooling-cells = <2>; 208 L2_100: l2-cache { 209 compatible = "cache"; 210 cache-level = <2>; 211 next-level-cache = <&L3_0>; 212 }; 213 }; 214 215 CPU2: cpu@200 { 216 device_type = "cpu"; 217 compatible = "qcom,kryo"; 218 reg = <0x0 0x200>; 219 clocks = <&cpufreq_hw 0>; 220 enable-method = "psci"; 221 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 222 &LITTLE_CPU_SLEEP_1 223 &CLUSTER_SLEEP_0>; 224 next-level-cache = <&L2_200>; 225 operating-points-v2 = <&cpu0_opp_table>; 226 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 227 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 228 qcom,freq-domain = <&cpufreq_hw 0>; 229 #cooling-cells = <2>; 230 L2_200: l2-cache { 231 compatible = "cache"; 232 cache-level = <2>; 233 next-level-cache = <&L3_0>; 234 }; 235 }; 236 237 CPU3: cpu@300 { 238 device_type = "cpu"; 239 compatible = "qcom,kryo"; 240 reg = <0x0 0x300>; 241 clocks = <&cpufreq_hw 0>; 242 enable-method = "psci"; 243 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 244 &LITTLE_CPU_SLEEP_1 245 &CLUSTER_SLEEP_0>; 246 next-level-cache = <&L2_300>; 247 operating-points-v2 = <&cpu0_opp_table>; 248 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 249 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 250 qcom,freq-domain = <&cpufreq_hw 0>; 251 #cooling-cells = <2>; 252 L2_300: l2-cache { 253 compatible = "cache"; 254 cache-level = <2>; 255 next-level-cache = <&L3_0>; 256 }; 257 }; 258 259 CPU4: cpu@400 { 260 device_type = "cpu"; 261 compatible = "qcom,kryo"; 262 reg = <0x0 0x400>; 263 clocks = <&cpufreq_hw 1>; 264 enable-method = "psci"; 265 cpu-idle-states = <&BIG_CPU_SLEEP_0 266 &BIG_CPU_SLEEP_1 267 &CLUSTER_SLEEP_0>; 268 next-level-cache = <&L2_400>; 269 operating-points-v2 = <&cpu4_opp_table>; 270 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 271 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 272 qcom,freq-domain = <&cpufreq_hw 1>; 273 #cooling-cells = <2>; 274 L2_400: l2-cache { 275 compatible = "cache"; 276 cache-level = <2>; 277 next-level-cache = <&L3_0>; 278 }; 279 }; 280 281 CPU5: cpu@500 { 282 device_type = "cpu"; 283 compatible = "qcom,kryo"; 284 reg = <0x0 0x500>; 285 clocks = <&cpufreq_hw 1>; 286 enable-method = "psci"; 287 cpu-idle-states = <&BIG_CPU_SLEEP_0 288 &BIG_CPU_SLEEP_1 289 &CLUSTER_SLEEP_0>; 290 next-level-cache = <&L2_500>; 291 operating-points-v2 = <&cpu4_opp_table>; 292 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 293 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 294 qcom,freq-domain = <&cpufreq_hw 1>; 295 #cooling-cells = <2>; 296 L2_500: l2-cache { 297 compatible = "cache"; 298 cache-level = <2>; 299 next-level-cache = <&L3_0>; 300 }; 301 }; 302 303 CPU6: cpu@600 { 304 device_type = "cpu"; 305 compatible = "qcom,kryo"; 306 reg = <0x0 0x600>; 307 clocks = <&cpufreq_hw 1>; 308 enable-method = "psci"; 309 cpu-idle-states = <&BIG_CPU_SLEEP_0 310 &BIG_CPU_SLEEP_1 311 &CLUSTER_SLEEP_0>; 312 next-level-cache = <&L2_600>; 313 operating-points-v2 = <&cpu4_opp_table>; 314 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 315 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 316 qcom,freq-domain = <&cpufreq_hw 1>; 317 #cooling-cells = <2>; 318 L2_600: l2-cache { 319 compatible = "cache"; 320 cache-level = <2>; 321 next-level-cache = <&L3_0>; 322 }; 323 }; 324 325 CPU7: cpu@700 { 326 device_type = "cpu"; 327 compatible = "qcom,kryo"; 328 reg = <0x0 0x700>; 329 clocks = <&cpufreq_hw 2>; 330 enable-method = "psci"; 331 cpu-idle-states = <&BIG_CPU_SLEEP_0 332 &BIG_CPU_SLEEP_1 333 &CLUSTER_SLEEP_0>; 334 next-level-cache = <&L2_700>; 335 operating-points-v2 = <&cpu7_opp_table>; 336 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 337 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 338 qcom,freq-domain = <&cpufreq_hw 2>; 339 #cooling-cells = <2>; 340 L2_700: l2-cache { 341 compatible = "cache"; 342 cache-level = <2>; 343 next-level-cache = <&L3_0>; 344 }; 345 }; 346 347 cpu-map { 348 cluster0 { 349 core0 { 350 cpu = <&CPU0>; 351 }; 352 353 core1 { 354 cpu = <&CPU1>; 355 }; 356 357 core2 { 358 cpu = <&CPU2>; 359 }; 360 361 core3 { 362 cpu = <&CPU3>; 363 }; 364 365 core4 { 366 cpu = <&CPU4>; 367 }; 368 369 core5 { 370 cpu = <&CPU5>; 371 }; 372 373 core6 { 374 cpu = <&CPU6>; 375 }; 376 377 core7 { 378 cpu = <&CPU7>; 379 }; 380 }; 381 }; 382 383 idle-states { 384 entry-method = "psci"; 385 386 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 387 compatible = "arm,idle-state"; 388 idle-state-name = "little-power-down"; 389 arm,psci-suspend-param = <0x40000003>; 390 entry-latency-us = <549>; 391 exit-latency-us = <901>; 392 min-residency-us = <1774>; 393 local-timer-stop; 394 }; 395 396 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 397 compatible = "arm,idle-state"; 398 idle-state-name = "little-rail-power-down"; 399 arm,psci-suspend-param = <0x40000004>; 400 entry-latency-us = <702>; 401 exit-latency-us = <915>; 402 min-residency-us = <4001>; 403 local-timer-stop; 404 }; 405 406 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 407 compatible = "arm,idle-state"; 408 idle-state-name = "big-power-down"; 409 arm,psci-suspend-param = <0x40000003>; 410 entry-latency-us = <523>; 411 exit-latency-us = <1244>; 412 min-residency-us = <2207>; 413 local-timer-stop; 414 }; 415 416 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 417 compatible = "arm,idle-state"; 418 idle-state-name = "big-rail-power-down"; 419 arm,psci-suspend-param = <0x40000004>; 420 entry-latency-us = <526>; 421 exit-latency-us = <1854>; 422 min-residency-us = <5555>; 423 local-timer-stop; 424 }; 425 426 CLUSTER_SLEEP_0: cluster-sleep-0 { 427 compatible = "arm,idle-state"; 428 idle-state-name = "cluster-power-down"; 429 arm,psci-suspend-param = <0x40003444>; 430 entry-latency-us = <3263>; 431 exit-latency-us = <6562>; 432 min-residency-us = <9926>; 433 local-timer-stop; 434 }; 435 }; 436 }; 437 438 cpu0_opp_table: opp-table-cpu0 { 439 compatible = "operating-points-v2"; 440 opp-shared; 441 442 cpu0_opp_300mhz: opp-300000000 { 443 opp-hz = /bits/ 64 <300000000>; 444 opp-peak-kBps = <800000 9600000>; 445 }; 446 447 cpu0_opp_691mhz: opp-691200000 { 448 opp-hz = /bits/ 64 <691200000>; 449 opp-peak-kBps = <800000 17817600>; 450 }; 451 452 cpu0_opp_806mhz: opp-806400000 { 453 opp-hz = /bits/ 64 <806400000>; 454 opp-peak-kBps = <800000 20889600>; 455 }; 456 457 cpu0_opp_941mhz: opp-940800000 { 458 opp-hz = /bits/ 64 <940800000>; 459 opp-peak-kBps = <1804000 24576000>; 460 }; 461 462 cpu0_opp_1152mhz: opp-1152000000 { 463 opp-hz = /bits/ 64 <1152000000>; 464 opp-peak-kBps = <2188000 27033600>; 465 }; 466 467 cpu0_opp_1325mhz: opp-1324800000 { 468 opp-hz = /bits/ 64 <1324800000>; 469 opp-peak-kBps = <2188000 33792000>; 470 }; 471 472 cpu0_opp_1517mhz: opp-1516800000 { 473 opp-hz = /bits/ 64 <1516800000>; 474 opp-peak-kBps = <3072000 38092800>; 475 }; 476 477 cpu0_opp_1651mhz: opp-1651200000 { 478 opp-hz = /bits/ 64 <1651200000>; 479 opp-peak-kBps = <3072000 41779200>; 480 }; 481 482 cpu0_opp_1805mhz: opp-1804800000 { 483 opp-hz = /bits/ 64 <1804800000>; 484 opp-peak-kBps = <4068000 48537600>; 485 }; 486 487 cpu0_opp_1958mhz: opp-1958400000 { 488 opp-hz = /bits/ 64 <1958400000>; 489 opp-peak-kBps = <4068000 48537600>; 490 }; 491 492 cpu0_opp_2016mhz: opp-2016000000 { 493 opp-hz = /bits/ 64 <2016000000>; 494 opp-peak-kBps = <6220000 48537600>; 495 }; 496 }; 497 498 cpu4_opp_table: opp-table-cpu4 { 499 compatible = "operating-points-v2"; 500 opp-shared; 501 502 cpu4_opp_691mhz: opp-691200000 { 503 opp-hz = /bits/ 64 <691200000>; 504 opp-peak-kBps = <1804000 9600000>; 505 }; 506 507 cpu4_opp_941mhz: opp-940800000 { 508 opp-hz = /bits/ 64 <940800000>; 509 opp-peak-kBps = <2188000 17817600>; 510 }; 511 512 cpu4_opp_1229mhz: opp-1228800000 { 513 opp-hz = /bits/ 64 <1228800000>; 514 opp-peak-kBps = <4068000 24576000>; 515 }; 516 517 cpu4_opp_1344mhz: opp-1344000000 { 518 opp-hz = /bits/ 64 <1344000000>; 519 opp-peak-kBps = <4068000 24576000>; 520 }; 521 522 cpu4_opp_1517mhz: opp-1516800000 { 523 opp-hz = /bits/ 64 <1516800000>; 524 opp-peak-kBps = <4068000 24576000>; 525 }; 526 527 cpu4_opp_1651mhz: opp-1651200000 { 528 opp-hz = /bits/ 64 <1651200000>; 529 opp-peak-kBps = <6220000 38092800>; 530 }; 531 532 cpu4_opp_1901mhz: opp-1900800000 { 533 opp-hz = /bits/ 64 <1900800000>; 534 opp-peak-kBps = <6220000 44851200>; 535 }; 536 537 cpu4_opp_2054mhz: opp-2054400000 { 538 opp-hz = /bits/ 64 <2054400000>; 539 opp-peak-kBps = <6220000 44851200>; 540 }; 541 542 cpu4_opp_2112mhz: opp-2112000000 { 543 opp-hz = /bits/ 64 <2112000000>; 544 opp-peak-kBps = <6220000 44851200>; 545 }; 546 547 cpu4_opp_2131mhz: opp-2131200000 { 548 opp-hz = /bits/ 64 <2131200000>; 549 opp-peak-kBps = <6220000 44851200>; 550 }; 551 552 cpu4_opp_2208mhz: opp-2208000000 { 553 opp-hz = /bits/ 64 <2208000000>; 554 opp-peak-kBps = <6220000 44851200>; 555 }; 556 557 cpu4_opp_2400mhz: opp-2400000000 { 558 opp-hz = /bits/ 64 <2400000000>; 559 opp-peak-kBps = <8532000 48537600>; 560 }; 561 562 cpu4_opp_2611mhz: opp-2611200000 { 563 opp-hz = /bits/ 64 <2611200000>; 564 opp-peak-kBps = <8532000 48537600>; 565 }; 566 }; 567 568 cpu7_opp_table: opp-table-cpu7 { 569 compatible = "operating-points-v2"; 570 opp-shared; 571 572 cpu7_opp_806mhz: opp-806400000 { 573 opp-hz = /bits/ 64 <806400000>; 574 opp-peak-kBps = <1804000 9600000>; 575 }; 576 577 cpu7_opp_1056mhz: opp-1056000000 { 578 opp-hz = /bits/ 64 <1056000000>; 579 opp-peak-kBps = <2188000 17817600>; 580 }; 581 582 cpu7_opp_1325mhz: opp-1324800000 { 583 opp-hz = /bits/ 64 <1324800000>; 584 opp-peak-kBps = <4068000 24576000>; 585 }; 586 587 cpu7_opp_1517mhz: opp-1516800000 { 588 opp-hz = /bits/ 64 <1516800000>; 589 opp-peak-kBps = <4068000 24576000>; 590 }; 591 592 cpu7_opp_1766mhz: opp-1766400000 { 593 opp-hz = /bits/ 64 <1766400000>; 594 opp-peak-kBps = <6220000 38092800>; 595 }; 596 597 cpu7_opp_1862mhz: opp-1862400000 { 598 opp-hz = /bits/ 64 <1862400000>; 599 opp-peak-kBps = <6220000 38092800>; 600 }; 601 602 cpu7_opp_2035mhz: opp-2035200000 { 603 opp-hz = /bits/ 64 <2035200000>; 604 opp-peak-kBps = <6220000 38092800>; 605 }; 606 607 cpu7_opp_2112mhz: opp-2112000000 { 608 opp-hz = /bits/ 64 <2112000000>; 609 opp-peak-kBps = <6220000 44851200>; 610 }; 611 612 cpu7_opp_2208mhz: opp-2208000000 { 613 opp-hz = /bits/ 64 <2208000000>; 614 opp-peak-kBps = <6220000 44851200>; 615 }; 616 617 cpu7_opp_2381mhz: opp-2380800000 { 618 opp-hz = /bits/ 64 <2380800000>; 619 opp-peak-kBps = <6832000 44851200>; 620 }; 621 622 cpu7_opp_2400mhz: opp-2400000000 { 623 opp-hz = /bits/ 64 <2400000000>; 624 opp-peak-kBps = <8532000 48537600>; 625 }; 626 627 cpu7_opp_2515mhz: opp-2515200000 { 628 opp-hz = /bits/ 64 <2515200000>; 629 opp-peak-kBps = <8532000 48537600>; 630 }; 631 632 cpu7_opp_2707mhz: opp-2707200000 { 633 opp-hz = /bits/ 64 <2707200000>; 634 opp-peak-kBps = <8532000 48537600>; 635 }; 636 637 cpu7_opp_3014mhz: opp-3014400000 { 638 opp-hz = /bits/ 64 <3014400000>; 639 opp-peak-kBps = <8532000 48537600>; 640 }; 641 }; 642 643 memory@80000000 { 644 device_type = "memory"; 645 /* We expect the bootloader to fill in the size */ 646 reg = <0 0x80000000 0 0>; 647 }; 648 649 firmware { 650 scm { 651 compatible = "qcom,scm-sc7280", "qcom,scm"; 652 }; 653 }; 654 655 clk_virt: interconnect { 656 compatible = "qcom,sc7280-clk-virt"; 657 #interconnect-cells = <2>; 658 qcom,bcm-voters = <&apps_bcm_voter>; 659 }; 660 661 smem { 662 compatible = "qcom,smem"; 663 memory-region = <&smem_mem>; 664 hwlocks = <&tcsr_mutex 3>; 665 }; 666 667 smp2p-adsp { 668 compatible = "qcom,smp2p"; 669 qcom,smem = <443>, <429>; 670 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 671 IPCC_MPROC_SIGNAL_SMP2P 672 IRQ_TYPE_EDGE_RISING>; 673 mboxes = <&ipcc IPCC_CLIENT_LPASS 674 IPCC_MPROC_SIGNAL_SMP2P>; 675 676 qcom,local-pid = <0>; 677 qcom,remote-pid = <2>; 678 679 adsp_smp2p_out: master-kernel { 680 qcom,entry-name = "master-kernel"; 681 #qcom,smem-state-cells = <1>; 682 }; 683 684 adsp_smp2p_in: slave-kernel { 685 qcom,entry-name = "slave-kernel"; 686 interrupt-controller; 687 #interrupt-cells = <2>; 688 }; 689 }; 690 691 smp2p-cdsp { 692 compatible = "qcom,smp2p"; 693 qcom,smem = <94>, <432>; 694 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 695 IPCC_MPROC_SIGNAL_SMP2P 696 IRQ_TYPE_EDGE_RISING>; 697 mboxes = <&ipcc IPCC_CLIENT_CDSP 698 IPCC_MPROC_SIGNAL_SMP2P>; 699 700 qcom,local-pid = <0>; 701 qcom,remote-pid = <5>; 702 703 cdsp_smp2p_out: master-kernel { 704 qcom,entry-name = "master-kernel"; 705 #qcom,smem-state-cells = <1>; 706 }; 707 708 cdsp_smp2p_in: slave-kernel { 709 qcom,entry-name = "slave-kernel"; 710 interrupt-controller; 711 #interrupt-cells = <2>; 712 }; 713 }; 714 715 smp2p-mpss { 716 compatible = "qcom,smp2p"; 717 qcom,smem = <435>, <428>; 718 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 719 IPCC_MPROC_SIGNAL_SMP2P 720 IRQ_TYPE_EDGE_RISING>; 721 mboxes = <&ipcc IPCC_CLIENT_MPSS 722 IPCC_MPROC_SIGNAL_SMP2P>; 723 724 qcom,local-pid = <0>; 725 qcom,remote-pid = <1>; 726 727 modem_smp2p_out: master-kernel { 728 qcom,entry-name = "master-kernel"; 729 #qcom,smem-state-cells = <1>; 730 }; 731 732 modem_smp2p_in: slave-kernel { 733 qcom,entry-name = "slave-kernel"; 734 interrupt-controller; 735 #interrupt-cells = <2>; 736 }; 737 738 ipa_smp2p_out: ipa-ap-to-modem { 739 qcom,entry-name = "ipa"; 740 #qcom,smem-state-cells = <1>; 741 }; 742 743 ipa_smp2p_in: ipa-modem-to-ap { 744 qcom,entry-name = "ipa"; 745 interrupt-controller; 746 #interrupt-cells = <2>; 747 }; 748 }; 749 750 smp2p-wpss { 751 compatible = "qcom,smp2p"; 752 qcom,smem = <617>, <616>; 753 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 754 IPCC_MPROC_SIGNAL_SMP2P 755 IRQ_TYPE_EDGE_RISING>; 756 mboxes = <&ipcc IPCC_CLIENT_WPSS 757 IPCC_MPROC_SIGNAL_SMP2P>; 758 759 qcom,local-pid = <0>; 760 qcom,remote-pid = <13>; 761 762 wpss_smp2p_out: master-kernel { 763 qcom,entry-name = "master-kernel"; 764 #qcom,smem-state-cells = <1>; 765 }; 766 767 wpss_smp2p_in: slave-kernel { 768 qcom,entry-name = "slave-kernel"; 769 interrupt-controller; 770 #interrupt-cells = <2>; 771 }; 772 773 wlan_smp2p_out: wlan-ap-to-wpss { 774 qcom,entry-name = "wlan"; 775 #qcom,smem-state-cells = <1>; 776 }; 777 778 wlan_smp2p_in: wlan-wpss-to-ap { 779 qcom,entry-name = "wlan"; 780 interrupt-controller; 781 #interrupt-cells = <2>; 782 }; 783 }; 784 785 pmu { 786 compatible = "arm,armv8-pmuv3"; 787 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 788 }; 789 790 psci { 791 compatible = "arm,psci-1.0"; 792 method = "smc"; 793 }; 794 795 qspi_opp_table: opp-table-qspi { 796 compatible = "operating-points-v2"; 797 798 opp-75000000 { 799 opp-hz = /bits/ 64 <75000000>; 800 required-opps = <&rpmhpd_opp_low_svs>; 801 }; 802 803 opp-150000000 { 804 opp-hz = /bits/ 64 <150000000>; 805 required-opps = <&rpmhpd_opp_svs>; 806 }; 807 808 opp-200000000 { 809 opp-hz = /bits/ 64 <200000000>; 810 required-opps = <&rpmhpd_opp_svs_l1>; 811 }; 812 813 opp-300000000 { 814 opp-hz = /bits/ 64 <300000000>; 815 required-opps = <&rpmhpd_opp_nom>; 816 }; 817 }; 818 819 qup_opp_table: opp-table-qup { 820 compatible = "operating-points-v2"; 821 822 opp-75000000 { 823 opp-hz = /bits/ 64 <75000000>; 824 required-opps = <&rpmhpd_opp_low_svs>; 825 }; 826 827 opp-100000000 { 828 opp-hz = /bits/ 64 <100000000>; 829 required-opps = <&rpmhpd_opp_svs>; 830 }; 831 832 opp-128000000 { 833 opp-hz = /bits/ 64 <128000000>; 834 required-opps = <&rpmhpd_opp_nom>; 835 }; 836 }; 837 838 soc: soc@0 { 839 #address-cells = <2>; 840 #size-cells = <2>; 841 ranges = <0 0 0 0 0x10 0>; 842 dma-ranges = <0 0 0 0 0x10 0>; 843 compatible = "simple-bus"; 844 845 gcc: clock-controller@100000 { 846 compatible = "qcom,gcc-sc7280"; 847 reg = <0 0x00100000 0 0x1f0000>; 848 clocks = <&rpmhcc RPMH_CXO_CLK>, 849 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 850 <0>, <&pcie1_lane>, 851 <0>, <0>, <0>, <0>; 852 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 853 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 854 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 855 "ufs_phy_tx_symbol_0_clk", 856 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 857 #clock-cells = <1>; 858 #reset-cells = <1>; 859 #power-domain-cells = <1>; 860 power-domains = <&rpmhpd SC7280_CX>; 861 }; 862 863 ipcc: mailbox@408000 { 864 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 865 reg = <0 0x00408000 0 0x1000>; 866 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 867 interrupt-controller; 868 #interrupt-cells = <3>; 869 #mbox-cells = <2>; 870 }; 871 872 qfprom: efuse@784000 { 873 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 874 reg = <0 0x00784000 0 0xa20>, 875 <0 0x00780000 0 0xa20>, 876 <0 0x00782000 0 0x120>, 877 <0 0x00786000 0 0x1fff>; 878 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 879 clock-names = "core"; 880 power-domains = <&rpmhpd SC7280_MX>; 881 #address-cells = <1>; 882 #size-cells = <1>; 883 884 gpu_speed_bin: gpu_speed_bin@1e9 { 885 reg = <0x1e9 0x2>; 886 bits = <5 8>; 887 }; 888 }; 889 890 sdhc_1: mmc@7c4000 { 891 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 892 pinctrl-names = "default", "sleep"; 893 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 894 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 895 status = "disabled"; 896 897 reg = <0 0x007c4000 0 0x1000>, 898 <0 0x007c5000 0 0x1000>; 899 reg-names = "hc", "cqhci"; 900 901 iommus = <&apps_smmu 0xc0 0x0>; 902 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 904 interrupt-names = "hc_irq", "pwr_irq"; 905 906 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 907 <&gcc GCC_SDCC1_APPS_CLK>, 908 <&rpmhcc RPMH_CXO_CLK>; 909 clock-names = "iface", "core", "xo"; 910 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 911 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 912 interconnect-names = "sdhc-ddr","cpu-sdhc"; 913 power-domains = <&rpmhpd SC7280_CX>; 914 operating-points-v2 = <&sdhc1_opp_table>; 915 916 bus-width = <8>; 917 supports-cqe; 918 919 qcom,dll-config = <0x0007642c>; 920 qcom,ddr-config = <0x80040868>; 921 922 mmc-ddr-1_8v; 923 mmc-hs200-1_8v; 924 mmc-hs400-1_8v; 925 mmc-hs400-enhanced-strobe; 926 927 resets = <&gcc GCC_SDCC1_BCR>; 928 929 sdhc1_opp_table: opp-table { 930 compatible = "operating-points-v2"; 931 932 opp-100000000 { 933 opp-hz = /bits/ 64 <100000000>; 934 required-opps = <&rpmhpd_opp_low_svs>; 935 opp-peak-kBps = <1800000 400000>; 936 opp-avg-kBps = <100000 0>; 937 }; 938 939 opp-384000000 { 940 opp-hz = /bits/ 64 <384000000>; 941 required-opps = <&rpmhpd_opp_nom>; 942 opp-peak-kBps = <5400000 1600000>; 943 opp-avg-kBps = <390000 0>; 944 }; 945 }; 946 947 }; 948 949 gpi_dma0: dma-controller@900000 { 950 #dma-cells = <3>; 951 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 952 reg = <0 0x00900000 0 0x60000>; 953 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 965 dma-channels = <12>; 966 dma-channel-mask = <0x7f>; 967 iommus = <&apps_smmu 0x0136 0x0>; 968 status = "disabled"; 969 }; 970 971 qupv3_id_0: geniqup@9c0000 { 972 compatible = "qcom,geni-se-qup"; 973 reg = <0 0x009c0000 0 0x2000>; 974 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 975 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 976 clock-names = "m-ahb", "s-ahb"; 977 #address-cells = <2>; 978 #size-cells = <2>; 979 ranges; 980 iommus = <&apps_smmu 0x123 0x0>; 981 status = "disabled"; 982 983 i2c0: i2c@980000 { 984 compatible = "qcom,geni-i2c"; 985 reg = <0 0x00980000 0 0x4000>; 986 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 987 clock-names = "se"; 988 pinctrl-names = "default"; 989 pinctrl-0 = <&qup_i2c0_data_clk>; 990 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 991 #address-cells = <1>; 992 #size-cells = <0>; 993 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 994 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 995 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 996 interconnect-names = "qup-core", "qup-config", 997 "qup-memory"; 998 power-domains = <&rpmhpd SC7280_CX>; 999 required-opps = <&rpmhpd_opp_low_svs>; 1000 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1001 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1002 dma-names = "tx", "rx"; 1003 status = "disabled"; 1004 }; 1005 1006 spi0: spi@980000 { 1007 compatible = "qcom,geni-spi"; 1008 reg = <0 0x00980000 0 0x4000>; 1009 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1010 clock-names = "se"; 1011 pinctrl-names = "default"; 1012 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1013 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 power-domains = <&rpmhpd SC7280_CX>; 1017 operating-points-v2 = <&qup_opp_table>; 1018 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1019 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1020 interconnect-names = "qup-core", "qup-config"; 1021 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1022 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1023 dma-names = "tx", "rx"; 1024 status = "disabled"; 1025 }; 1026 1027 uart0: serial@980000 { 1028 compatible = "qcom,geni-uart"; 1029 reg = <0 0x00980000 0 0x4000>; 1030 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1031 clock-names = "se"; 1032 pinctrl-names = "default"; 1033 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1034 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1035 power-domains = <&rpmhpd SC7280_CX>; 1036 operating-points-v2 = <&qup_opp_table>; 1037 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1038 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1039 interconnect-names = "qup-core", "qup-config"; 1040 status = "disabled"; 1041 }; 1042 1043 i2c1: i2c@984000 { 1044 compatible = "qcom,geni-i2c"; 1045 reg = <0 0x00984000 0 0x4000>; 1046 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1047 clock-names = "se"; 1048 pinctrl-names = "default"; 1049 pinctrl-0 = <&qup_i2c1_data_clk>; 1050 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1054 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1055 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1056 interconnect-names = "qup-core", "qup-config", 1057 "qup-memory"; 1058 power-domains = <&rpmhpd SC7280_CX>; 1059 required-opps = <&rpmhpd_opp_low_svs>; 1060 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1061 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1062 dma-names = "tx", "rx"; 1063 status = "disabled"; 1064 }; 1065 1066 spi1: spi@984000 { 1067 compatible = "qcom,geni-spi"; 1068 reg = <0 0x00984000 0 0x4000>; 1069 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1070 clock-names = "se"; 1071 pinctrl-names = "default"; 1072 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1073 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 power-domains = <&rpmhpd SC7280_CX>; 1077 operating-points-v2 = <&qup_opp_table>; 1078 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1079 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1080 interconnect-names = "qup-core", "qup-config"; 1081 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1082 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1083 dma-names = "tx", "rx"; 1084 status = "disabled"; 1085 }; 1086 1087 uart1: serial@984000 { 1088 compatible = "qcom,geni-uart"; 1089 reg = <0 0x00984000 0 0x4000>; 1090 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1091 clock-names = "se"; 1092 pinctrl-names = "default"; 1093 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1094 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1095 power-domains = <&rpmhpd SC7280_CX>; 1096 operating-points-v2 = <&qup_opp_table>; 1097 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1098 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1099 interconnect-names = "qup-core", "qup-config"; 1100 status = "disabled"; 1101 }; 1102 1103 i2c2: i2c@988000 { 1104 compatible = "qcom,geni-i2c"; 1105 reg = <0 0x00988000 0 0x4000>; 1106 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1107 clock-names = "se"; 1108 pinctrl-names = "default"; 1109 pinctrl-0 = <&qup_i2c2_data_clk>; 1110 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1111 #address-cells = <1>; 1112 #size-cells = <0>; 1113 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1114 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1115 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1116 interconnect-names = "qup-core", "qup-config", 1117 "qup-memory"; 1118 power-domains = <&rpmhpd SC7280_CX>; 1119 required-opps = <&rpmhpd_opp_low_svs>; 1120 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1121 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1122 dma-names = "tx", "rx"; 1123 status = "disabled"; 1124 }; 1125 1126 spi2: spi@988000 { 1127 compatible = "qcom,geni-spi"; 1128 reg = <0 0x00988000 0 0x4000>; 1129 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1130 clock-names = "se"; 1131 pinctrl-names = "default"; 1132 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1133 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1134 #address-cells = <1>; 1135 #size-cells = <0>; 1136 power-domains = <&rpmhpd SC7280_CX>; 1137 operating-points-v2 = <&qup_opp_table>; 1138 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1139 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1140 interconnect-names = "qup-core", "qup-config"; 1141 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1142 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1143 dma-names = "tx", "rx"; 1144 status = "disabled"; 1145 }; 1146 1147 uart2: serial@988000 { 1148 compatible = "qcom,geni-uart"; 1149 reg = <0 0x00988000 0 0x4000>; 1150 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1151 clock-names = "se"; 1152 pinctrl-names = "default"; 1153 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1154 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1155 power-domains = <&rpmhpd SC7280_CX>; 1156 operating-points-v2 = <&qup_opp_table>; 1157 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1158 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1159 interconnect-names = "qup-core", "qup-config"; 1160 status = "disabled"; 1161 }; 1162 1163 i2c3: i2c@98c000 { 1164 compatible = "qcom,geni-i2c"; 1165 reg = <0 0x0098c000 0 0x4000>; 1166 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1167 clock-names = "se"; 1168 pinctrl-names = "default"; 1169 pinctrl-0 = <&qup_i2c3_data_clk>; 1170 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1171 #address-cells = <1>; 1172 #size-cells = <0>; 1173 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1174 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1175 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1176 interconnect-names = "qup-core", "qup-config", 1177 "qup-memory"; 1178 power-domains = <&rpmhpd SC7280_CX>; 1179 required-opps = <&rpmhpd_opp_low_svs>; 1180 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1181 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1182 dma-names = "tx", "rx"; 1183 status = "disabled"; 1184 }; 1185 1186 spi3: spi@98c000 { 1187 compatible = "qcom,geni-spi"; 1188 reg = <0 0x0098c000 0 0x4000>; 1189 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1190 clock-names = "se"; 1191 pinctrl-names = "default"; 1192 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1193 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1194 #address-cells = <1>; 1195 #size-cells = <0>; 1196 power-domains = <&rpmhpd SC7280_CX>; 1197 operating-points-v2 = <&qup_opp_table>; 1198 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1199 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1200 interconnect-names = "qup-core", "qup-config"; 1201 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1202 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1203 dma-names = "tx", "rx"; 1204 status = "disabled"; 1205 }; 1206 1207 uart3: serial@98c000 { 1208 compatible = "qcom,geni-uart"; 1209 reg = <0 0x0098c000 0 0x4000>; 1210 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1211 clock-names = "se"; 1212 pinctrl-names = "default"; 1213 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1214 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1215 power-domains = <&rpmhpd SC7280_CX>; 1216 operating-points-v2 = <&qup_opp_table>; 1217 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1218 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1219 interconnect-names = "qup-core", "qup-config"; 1220 status = "disabled"; 1221 }; 1222 1223 i2c4: i2c@990000 { 1224 compatible = "qcom,geni-i2c"; 1225 reg = <0 0x00990000 0 0x4000>; 1226 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1227 clock-names = "se"; 1228 pinctrl-names = "default"; 1229 pinctrl-0 = <&qup_i2c4_data_clk>; 1230 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1234 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1235 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1236 interconnect-names = "qup-core", "qup-config", 1237 "qup-memory"; 1238 power-domains = <&rpmhpd SC7280_CX>; 1239 required-opps = <&rpmhpd_opp_low_svs>; 1240 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1241 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1242 dma-names = "tx", "rx"; 1243 status = "disabled"; 1244 }; 1245 1246 spi4: spi@990000 { 1247 compatible = "qcom,geni-spi"; 1248 reg = <0 0x00990000 0 0x4000>; 1249 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1250 clock-names = "se"; 1251 pinctrl-names = "default"; 1252 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1253 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 power-domains = <&rpmhpd SC7280_CX>; 1257 operating-points-v2 = <&qup_opp_table>; 1258 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1259 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1260 interconnect-names = "qup-core", "qup-config"; 1261 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1262 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1263 dma-names = "tx", "rx"; 1264 status = "disabled"; 1265 }; 1266 1267 uart4: serial@990000 { 1268 compatible = "qcom,geni-uart"; 1269 reg = <0 0x00990000 0 0x4000>; 1270 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1271 clock-names = "se"; 1272 pinctrl-names = "default"; 1273 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1274 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1275 power-domains = <&rpmhpd SC7280_CX>; 1276 operating-points-v2 = <&qup_opp_table>; 1277 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1278 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1279 interconnect-names = "qup-core", "qup-config"; 1280 status = "disabled"; 1281 }; 1282 1283 i2c5: i2c@994000 { 1284 compatible = "qcom,geni-i2c"; 1285 reg = <0 0x00994000 0 0x4000>; 1286 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1287 clock-names = "se"; 1288 pinctrl-names = "default"; 1289 pinctrl-0 = <&qup_i2c5_data_clk>; 1290 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1291 #address-cells = <1>; 1292 #size-cells = <0>; 1293 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1294 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1295 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1296 interconnect-names = "qup-core", "qup-config", 1297 "qup-memory"; 1298 power-domains = <&rpmhpd SC7280_CX>; 1299 required-opps = <&rpmhpd_opp_low_svs>; 1300 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1301 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1302 dma-names = "tx", "rx"; 1303 status = "disabled"; 1304 }; 1305 1306 spi5: spi@994000 { 1307 compatible = "qcom,geni-spi"; 1308 reg = <0 0x00994000 0 0x4000>; 1309 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1310 clock-names = "se"; 1311 pinctrl-names = "default"; 1312 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1313 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 power-domains = <&rpmhpd SC7280_CX>; 1317 operating-points-v2 = <&qup_opp_table>; 1318 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1319 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1320 interconnect-names = "qup-core", "qup-config"; 1321 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1322 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1323 dma-names = "tx", "rx"; 1324 status = "disabled"; 1325 }; 1326 1327 uart5: serial@994000 { 1328 compatible = "qcom,geni-uart"; 1329 reg = <0 0x00994000 0 0x4000>; 1330 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1331 clock-names = "se"; 1332 pinctrl-names = "default"; 1333 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1334 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1335 power-domains = <&rpmhpd SC7280_CX>; 1336 operating-points-v2 = <&qup_opp_table>; 1337 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1338 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1339 interconnect-names = "qup-core", "qup-config"; 1340 status = "disabled"; 1341 }; 1342 1343 i2c6: i2c@998000 { 1344 compatible = "qcom,geni-i2c"; 1345 reg = <0 0x00998000 0 0x4000>; 1346 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1347 clock-names = "se"; 1348 pinctrl-names = "default"; 1349 pinctrl-0 = <&qup_i2c6_data_clk>; 1350 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1351 #address-cells = <1>; 1352 #size-cells = <0>; 1353 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1354 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1355 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1356 interconnect-names = "qup-core", "qup-config", 1357 "qup-memory"; 1358 power-domains = <&rpmhpd SC7280_CX>; 1359 required-opps = <&rpmhpd_opp_low_svs>; 1360 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1361 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1362 dma-names = "tx", "rx"; 1363 status = "disabled"; 1364 }; 1365 1366 spi6: spi@998000 { 1367 compatible = "qcom,geni-spi"; 1368 reg = <0 0x00998000 0 0x4000>; 1369 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1370 clock-names = "se"; 1371 pinctrl-names = "default"; 1372 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1373 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1374 #address-cells = <1>; 1375 #size-cells = <0>; 1376 power-domains = <&rpmhpd SC7280_CX>; 1377 operating-points-v2 = <&qup_opp_table>; 1378 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1379 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1380 interconnect-names = "qup-core", "qup-config"; 1381 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1382 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1383 dma-names = "tx", "rx"; 1384 status = "disabled"; 1385 }; 1386 1387 uart6: serial@998000 { 1388 compatible = "qcom,geni-uart"; 1389 reg = <0 0x00998000 0 0x4000>; 1390 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1391 clock-names = "se"; 1392 pinctrl-names = "default"; 1393 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1394 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1395 power-domains = <&rpmhpd SC7280_CX>; 1396 operating-points-v2 = <&qup_opp_table>; 1397 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1398 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1399 interconnect-names = "qup-core", "qup-config"; 1400 status = "disabled"; 1401 }; 1402 1403 i2c7: i2c@99c000 { 1404 compatible = "qcom,geni-i2c"; 1405 reg = <0 0x0099c000 0 0x4000>; 1406 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1407 clock-names = "se"; 1408 pinctrl-names = "default"; 1409 pinctrl-0 = <&qup_i2c7_data_clk>; 1410 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1411 #address-cells = <1>; 1412 #size-cells = <0>; 1413 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1414 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1415 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1416 interconnect-names = "qup-core", "qup-config", 1417 "qup-memory"; 1418 power-domains = <&rpmhpd SC7280_CX>; 1419 required-opps = <&rpmhpd_opp_low_svs>; 1420 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1421 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1422 dma-names = "tx", "rx"; 1423 status = "disabled"; 1424 }; 1425 1426 spi7: spi@99c000 { 1427 compatible = "qcom,geni-spi"; 1428 reg = <0 0x0099c000 0 0x4000>; 1429 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1430 clock-names = "se"; 1431 pinctrl-names = "default"; 1432 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1433 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1434 #address-cells = <1>; 1435 #size-cells = <0>; 1436 power-domains = <&rpmhpd SC7280_CX>; 1437 operating-points-v2 = <&qup_opp_table>; 1438 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1439 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1440 interconnect-names = "qup-core", "qup-config"; 1441 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1442 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1443 dma-names = "tx", "rx"; 1444 status = "disabled"; 1445 }; 1446 1447 uart7: serial@99c000 { 1448 compatible = "qcom,geni-uart"; 1449 reg = <0 0x0099c000 0 0x4000>; 1450 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1451 clock-names = "se"; 1452 pinctrl-names = "default"; 1453 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1454 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1455 power-domains = <&rpmhpd SC7280_CX>; 1456 operating-points-v2 = <&qup_opp_table>; 1457 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1458 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1459 interconnect-names = "qup-core", "qup-config"; 1460 status = "disabled"; 1461 }; 1462 }; 1463 1464 gpi_dma1: dma-controller@a00000 { 1465 #dma-cells = <3>; 1466 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1467 reg = <0 0x00a00000 0 0x60000>; 1468 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1480 dma-channels = <12>; 1481 dma-channel-mask = <0x1e>; 1482 iommus = <&apps_smmu 0x56 0x0>; 1483 status = "disabled"; 1484 }; 1485 1486 qupv3_id_1: geniqup@ac0000 { 1487 compatible = "qcom,geni-se-qup"; 1488 reg = <0 0x00ac0000 0 0x2000>; 1489 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1490 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1491 clock-names = "m-ahb", "s-ahb"; 1492 #address-cells = <2>; 1493 #size-cells = <2>; 1494 ranges; 1495 iommus = <&apps_smmu 0x43 0x0>; 1496 status = "disabled"; 1497 1498 i2c8: i2c@a80000 { 1499 compatible = "qcom,geni-i2c"; 1500 reg = <0 0x00a80000 0 0x4000>; 1501 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1502 clock-names = "se"; 1503 pinctrl-names = "default"; 1504 pinctrl-0 = <&qup_i2c8_data_clk>; 1505 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1506 #address-cells = <1>; 1507 #size-cells = <0>; 1508 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1509 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1510 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1511 interconnect-names = "qup-core", "qup-config", 1512 "qup-memory"; 1513 power-domains = <&rpmhpd SC7280_CX>; 1514 required-opps = <&rpmhpd_opp_low_svs>; 1515 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1516 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1517 dma-names = "tx", "rx"; 1518 status = "disabled"; 1519 }; 1520 1521 spi8: spi@a80000 { 1522 compatible = "qcom,geni-spi"; 1523 reg = <0 0x00a80000 0 0x4000>; 1524 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1525 clock-names = "se"; 1526 pinctrl-names = "default"; 1527 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1528 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1529 #address-cells = <1>; 1530 #size-cells = <0>; 1531 power-domains = <&rpmhpd SC7280_CX>; 1532 operating-points-v2 = <&qup_opp_table>; 1533 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1534 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1535 interconnect-names = "qup-core", "qup-config"; 1536 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1537 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1538 dma-names = "tx", "rx"; 1539 status = "disabled"; 1540 }; 1541 1542 uart8: serial@a80000 { 1543 compatible = "qcom,geni-uart"; 1544 reg = <0 0x00a80000 0 0x4000>; 1545 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1546 clock-names = "se"; 1547 pinctrl-names = "default"; 1548 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1549 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1550 power-domains = <&rpmhpd SC7280_CX>; 1551 operating-points-v2 = <&qup_opp_table>; 1552 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1553 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1554 interconnect-names = "qup-core", "qup-config"; 1555 status = "disabled"; 1556 }; 1557 1558 i2c9: i2c@a84000 { 1559 compatible = "qcom,geni-i2c"; 1560 reg = <0 0x00a84000 0 0x4000>; 1561 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1562 clock-names = "se"; 1563 pinctrl-names = "default"; 1564 pinctrl-0 = <&qup_i2c9_data_clk>; 1565 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1566 #address-cells = <1>; 1567 #size-cells = <0>; 1568 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1569 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1570 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1571 interconnect-names = "qup-core", "qup-config", 1572 "qup-memory"; 1573 power-domains = <&rpmhpd SC7280_CX>; 1574 required-opps = <&rpmhpd_opp_low_svs>; 1575 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1576 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1577 dma-names = "tx", "rx"; 1578 status = "disabled"; 1579 }; 1580 1581 spi9: spi@a84000 { 1582 compatible = "qcom,geni-spi"; 1583 reg = <0 0x00a84000 0 0x4000>; 1584 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1585 clock-names = "se"; 1586 pinctrl-names = "default"; 1587 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1588 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1589 #address-cells = <1>; 1590 #size-cells = <0>; 1591 power-domains = <&rpmhpd SC7280_CX>; 1592 operating-points-v2 = <&qup_opp_table>; 1593 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1594 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1595 interconnect-names = "qup-core", "qup-config"; 1596 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1597 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1598 dma-names = "tx", "rx"; 1599 status = "disabled"; 1600 }; 1601 1602 uart9: serial@a84000 { 1603 compatible = "qcom,geni-uart"; 1604 reg = <0 0x00a84000 0 0x4000>; 1605 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1606 clock-names = "se"; 1607 pinctrl-names = "default"; 1608 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1609 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1610 power-domains = <&rpmhpd SC7280_CX>; 1611 operating-points-v2 = <&qup_opp_table>; 1612 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1613 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1614 interconnect-names = "qup-core", "qup-config"; 1615 status = "disabled"; 1616 }; 1617 1618 i2c10: i2c@a88000 { 1619 compatible = "qcom,geni-i2c"; 1620 reg = <0 0x00a88000 0 0x4000>; 1621 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1622 clock-names = "se"; 1623 pinctrl-names = "default"; 1624 pinctrl-0 = <&qup_i2c10_data_clk>; 1625 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1626 #address-cells = <1>; 1627 #size-cells = <0>; 1628 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1629 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1630 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1631 interconnect-names = "qup-core", "qup-config", 1632 "qup-memory"; 1633 power-domains = <&rpmhpd SC7280_CX>; 1634 required-opps = <&rpmhpd_opp_low_svs>; 1635 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1636 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1637 dma-names = "tx", "rx"; 1638 status = "disabled"; 1639 }; 1640 1641 spi10: spi@a88000 { 1642 compatible = "qcom,geni-spi"; 1643 reg = <0 0x00a88000 0 0x4000>; 1644 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1645 clock-names = "se"; 1646 pinctrl-names = "default"; 1647 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1648 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1649 #address-cells = <1>; 1650 #size-cells = <0>; 1651 power-domains = <&rpmhpd SC7280_CX>; 1652 operating-points-v2 = <&qup_opp_table>; 1653 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1654 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1655 interconnect-names = "qup-core", "qup-config"; 1656 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1657 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1658 dma-names = "tx", "rx"; 1659 status = "disabled"; 1660 }; 1661 1662 uart10: serial@a88000 { 1663 compatible = "qcom,geni-uart"; 1664 reg = <0 0x00a88000 0 0x4000>; 1665 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1666 clock-names = "se"; 1667 pinctrl-names = "default"; 1668 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1669 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1670 power-domains = <&rpmhpd SC7280_CX>; 1671 operating-points-v2 = <&qup_opp_table>; 1672 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1673 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1674 interconnect-names = "qup-core", "qup-config"; 1675 status = "disabled"; 1676 }; 1677 1678 i2c11: i2c@a8c000 { 1679 compatible = "qcom,geni-i2c"; 1680 reg = <0 0x00a8c000 0 0x4000>; 1681 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1682 clock-names = "se"; 1683 pinctrl-names = "default"; 1684 pinctrl-0 = <&qup_i2c11_data_clk>; 1685 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1686 #address-cells = <1>; 1687 #size-cells = <0>; 1688 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1689 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1690 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1691 interconnect-names = "qup-core", "qup-config", 1692 "qup-memory"; 1693 power-domains = <&rpmhpd SC7280_CX>; 1694 required-opps = <&rpmhpd_opp_low_svs>; 1695 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1696 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1697 dma-names = "tx", "rx"; 1698 status = "disabled"; 1699 }; 1700 1701 spi11: spi@a8c000 { 1702 compatible = "qcom,geni-spi"; 1703 reg = <0 0x00a8c000 0 0x4000>; 1704 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1705 clock-names = "se"; 1706 pinctrl-names = "default"; 1707 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1708 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1709 #address-cells = <1>; 1710 #size-cells = <0>; 1711 power-domains = <&rpmhpd SC7280_CX>; 1712 operating-points-v2 = <&qup_opp_table>; 1713 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1714 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1715 interconnect-names = "qup-core", "qup-config"; 1716 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1717 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1718 dma-names = "tx", "rx"; 1719 status = "disabled"; 1720 }; 1721 1722 uart11: serial@a8c000 { 1723 compatible = "qcom,geni-uart"; 1724 reg = <0 0x00a8c000 0 0x4000>; 1725 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1726 clock-names = "se"; 1727 pinctrl-names = "default"; 1728 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1729 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1730 power-domains = <&rpmhpd SC7280_CX>; 1731 operating-points-v2 = <&qup_opp_table>; 1732 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1733 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1734 interconnect-names = "qup-core", "qup-config"; 1735 status = "disabled"; 1736 }; 1737 1738 i2c12: i2c@a90000 { 1739 compatible = "qcom,geni-i2c"; 1740 reg = <0 0x00a90000 0 0x4000>; 1741 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1742 clock-names = "se"; 1743 pinctrl-names = "default"; 1744 pinctrl-0 = <&qup_i2c12_data_clk>; 1745 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1746 #address-cells = <1>; 1747 #size-cells = <0>; 1748 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1749 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1750 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1751 interconnect-names = "qup-core", "qup-config", 1752 "qup-memory"; 1753 power-domains = <&rpmhpd SC7280_CX>; 1754 required-opps = <&rpmhpd_opp_low_svs>; 1755 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1756 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1757 dma-names = "tx", "rx"; 1758 status = "disabled"; 1759 }; 1760 1761 spi12: spi@a90000 { 1762 compatible = "qcom,geni-spi"; 1763 reg = <0 0x00a90000 0 0x4000>; 1764 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1765 clock-names = "se"; 1766 pinctrl-names = "default"; 1767 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1768 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1769 #address-cells = <1>; 1770 #size-cells = <0>; 1771 power-domains = <&rpmhpd SC7280_CX>; 1772 operating-points-v2 = <&qup_opp_table>; 1773 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1774 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1775 interconnect-names = "qup-core", "qup-config"; 1776 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1777 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1778 dma-names = "tx", "rx"; 1779 status = "disabled"; 1780 }; 1781 1782 uart12: serial@a90000 { 1783 compatible = "qcom,geni-uart"; 1784 reg = <0 0x00a90000 0 0x4000>; 1785 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1786 clock-names = "se"; 1787 pinctrl-names = "default"; 1788 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1789 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1790 power-domains = <&rpmhpd SC7280_CX>; 1791 operating-points-v2 = <&qup_opp_table>; 1792 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1793 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1794 interconnect-names = "qup-core", "qup-config"; 1795 status = "disabled"; 1796 }; 1797 1798 i2c13: i2c@a94000 { 1799 compatible = "qcom,geni-i2c"; 1800 reg = <0 0x00a94000 0 0x4000>; 1801 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1802 clock-names = "se"; 1803 pinctrl-names = "default"; 1804 pinctrl-0 = <&qup_i2c13_data_clk>; 1805 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1806 #address-cells = <1>; 1807 #size-cells = <0>; 1808 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1809 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1810 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1811 interconnect-names = "qup-core", "qup-config", 1812 "qup-memory"; 1813 power-domains = <&rpmhpd SC7280_CX>; 1814 required-opps = <&rpmhpd_opp_low_svs>; 1815 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1816 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1817 dma-names = "tx", "rx"; 1818 status = "disabled"; 1819 }; 1820 1821 spi13: spi@a94000 { 1822 compatible = "qcom,geni-spi"; 1823 reg = <0 0x00a94000 0 0x4000>; 1824 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1825 clock-names = "se"; 1826 pinctrl-names = "default"; 1827 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1828 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1829 #address-cells = <1>; 1830 #size-cells = <0>; 1831 power-domains = <&rpmhpd SC7280_CX>; 1832 operating-points-v2 = <&qup_opp_table>; 1833 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1834 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1835 interconnect-names = "qup-core", "qup-config"; 1836 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1837 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1838 dma-names = "tx", "rx"; 1839 status = "disabled"; 1840 }; 1841 1842 uart13: serial@a94000 { 1843 compatible = "qcom,geni-uart"; 1844 reg = <0 0x00a94000 0 0x4000>; 1845 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1846 clock-names = "se"; 1847 pinctrl-names = "default"; 1848 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1849 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1850 power-domains = <&rpmhpd SC7280_CX>; 1851 operating-points-v2 = <&qup_opp_table>; 1852 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1853 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1854 interconnect-names = "qup-core", "qup-config"; 1855 status = "disabled"; 1856 }; 1857 1858 i2c14: i2c@a98000 { 1859 compatible = "qcom,geni-i2c"; 1860 reg = <0 0x00a98000 0 0x4000>; 1861 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1862 clock-names = "se"; 1863 pinctrl-names = "default"; 1864 pinctrl-0 = <&qup_i2c14_data_clk>; 1865 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1866 #address-cells = <1>; 1867 #size-cells = <0>; 1868 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1869 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1870 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1871 interconnect-names = "qup-core", "qup-config", 1872 "qup-memory"; 1873 power-domains = <&rpmhpd SC7280_CX>; 1874 required-opps = <&rpmhpd_opp_low_svs>; 1875 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1876 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1877 dma-names = "tx", "rx"; 1878 status = "disabled"; 1879 }; 1880 1881 spi14: spi@a98000 { 1882 compatible = "qcom,geni-spi"; 1883 reg = <0 0x00a98000 0 0x4000>; 1884 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1885 clock-names = "se"; 1886 pinctrl-names = "default"; 1887 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1888 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1889 #address-cells = <1>; 1890 #size-cells = <0>; 1891 power-domains = <&rpmhpd SC7280_CX>; 1892 operating-points-v2 = <&qup_opp_table>; 1893 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1894 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1895 interconnect-names = "qup-core", "qup-config"; 1896 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1897 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1898 dma-names = "tx", "rx"; 1899 status = "disabled"; 1900 }; 1901 1902 uart14: serial@a98000 { 1903 compatible = "qcom,geni-uart"; 1904 reg = <0 0x00a98000 0 0x4000>; 1905 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1906 clock-names = "se"; 1907 pinctrl-names = "default"; 1908 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1909 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1910 power-domains = <&rpmhpd SC7280_CX>; 1911 operating-points-v2 = <&qup_opp_table>; 1912 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1913 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1914 interconnect-names = "qup-core", "qup-config"; 1915 status = "disabled"; 1916 }; 1917 1918 i2c15: i2c@a9c000 { 1919 compatible = "qcom,geni-i2c"; 1920 reg = <0 0x00a9c000 0 0x4000>; 1921 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1922 clock-names = "se"; 1923 pinctrl-names = "default"; 1924 pinctrl-0 = <&qup_i2c15_data_clk>; 1925 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1926 #address-cells = <1>; 1927 #size-cells = <0>; 1928 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1929 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1930 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1931 interconnect-names = "qup-core", "qup-config", 1932 "qup-memory"; 1933 power-domains = <&rpmhpd SC7280_CX>; 1934 required-opps = <&rpmhpd_opp_low_svs>; 1935 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1936 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1937 dma-names = "tx", "rx"; 1938 status = "disabled"; 1939 }; 1940 1941 spi15: spi@a9c000 { 1942 compatible = "qcom,geni-spi"; 1943 reg = <0 0x00a9c000 0 0x4000>; 1944 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1945 clock-names = "se"; 1946 pinctrl-names = "default"; 1947 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1948 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1949 #address-cells = <1>; 1950 #size-cells = <0>; 1951 power-domains = <&rpmhpd SC7280_CX>; 1952 operating-points-v2 = <&qup_opp_table>; 1953 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1954 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1955 interconnect-names = "qup-core", "qup-config"; 1956 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1957 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1958 dma-names = "tx", "rx"; 1959 status = "disabled"; 1960 }; 1961 1962 uart15: serial@a9c000 { 1963 compatible = "qcom,geni-uart"; 1964 reg = <0 0x00a9c000 0 0x4000>; 1965 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1966 clock-names = "se"; 1967 pinctrl-names = "default"; 1968 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1969 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1970 power-domains = <&rpmhpd SC7280_CX>; 1971 operating-points-v2 = <&qup_opp_table>; 1972 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1973 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1974 interconnect-names = "qup-core", "qup-config"; 1975 status = "disabled"; 1976 }; 1977 }; 1978 1979 cnoc2: interconnect@1500000 { 1980 reg = <0 0x01500000 0 0x1000>; 1981 compatible = "qcom,sc7280-cnoc2"; 1982 #interconnect-cells = <2>; 1983 qcom,bcm-voters = <&apps_bcm_voter>; 1984 }; 1985 1986 cnoc3: interconnect@1502000 { 1987 reg = <0 0x01502000 0 0x1000>; 1988 compatible = "qcom,sc7280-cnoc3"; 1989 #interconnect-cells = <2>; 1990 qcom,bcm-voters = <&apps_bcm_voter>; 1991 }; 1992 1993 mc_virt: interconnect@1580000 { 1994 reg = <0 0x01580000 0 0x4>; 1995 compatible = "qcom,sc7280-mc-virt"; 1996 #interconnect-cells = <2>; 1997 qcom,bcm-voters = <&apps_bcm_voter>; 1998 }; 1999 2000 system_noc: interconnect@1680000 { 2001 reg = <0 0x01680000 0 0x15480>; 2002 compatible = "qcom,sc7280-system-noc"; 2003 #interconnect-cells = <2>; 2004 qcom,bcm-voters = <&apps_bcm_voter>; 2005 }; 2006 2007 aggre1_noc: interconnect@16e0000 { 2008 compatible = "qcom,sc7280-aggre1-noc"; 2009 reg = <0 0x016e0000 0 0x1c080>; 2010 #interconnect-cells = <2>; 2011 qcom,bcm-voters = <&apps_bcm_voter>; 2012 }; 2013 2014 aggre2_noc: interconnect@1700000 { 2015 reg = <0 0x01700000 0 0x2b080>; 2016 compatible = "qcom,sc7280-aggre2-noc"; 2017 #interconnect-cells = <2>; 2018 qcom,bcm-voters = <&apps_bcm_voter>; 2019 }; 2020 2021 mmss_noc: interconnect@1740000 { 2022 reg = <0 0x01740000 0 0x1e080>; 2023 compatible = "qcom,sc7280-mmss-noc"; 2024 #interconnect-cells = <2>; 2025 qcom,bcm-voters = <&apps_bcm_voter>; 2026 }; 2027 2028 wifi: wifi@17a10040 { 2029 compatible = "qcom,wcn6750-wifi"; 2030 reg = <0 0x17a10040 0 0x0>; 2031 iommus = <&apps_smmu 0x1c00 0x1>; 2032 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2033 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2034 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2035 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2036 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2037 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2038 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2039 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2040 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2041 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2042 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2043 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2044 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2045 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2046 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2047 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2048 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2049 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2050 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2051 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2052 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2053 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2054 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2055 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2056 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2057 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2058 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2059 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2060 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2061 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2062 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2063 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2064 qcom,rproc = <&remoteproc_wpss>; 2065 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2066 status = "disabled"; 2067 qcom,smem-states = <&wlan_smp2p_out 0>; 2068 qcom,smem-state-names = "wlan-smp2p-out"; 2069 }; 2070 2071 pcie1: pci@1c08000 { 2072 compatible = "qcom,pcie-sc7280"; 2073 reg = <0 0x01c08000 0 0x3000>, 2074 <0 0x40000000 0 0xf1d>, 2075 <0 0x40000f20 0 0xa8>, 2076 <0 0x40001000 0 0x1000>, 2077 <0 0x40100000 0 0x100000>; 2078 2079 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2080 device_type = "pci"; 2081 linux,pci-domain = <1>; 2082 bus-range = <0x00 0xff>; 2083 num-lanes = <2>; 2084 2085 #address-cells = <3>; 2086 #size-cells = <2>; 2087 2088 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 2089 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2090 2091 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2092 interrupt-names = "msi"; 2093 #interrupt-cells = <1>; 2094 interrupt-map-mask = <0 0 0 0x7>; 2095 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2096 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2097 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2098 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2099 2100 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2101 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2102 <&pcie1_lane>, 2103 <&rpmhcc RPMH_CXO_CLK>, 2104 <&gcc GCC_PCIE_1_AUX_CLK>, 2105 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2106 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2107 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2108 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2109 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2110 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2111 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2112 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2113 2114 clock-names = "pipe", 2115 "pipe_mux", 2116 "phy_pipe", 2117 "ref", 2118 "aux", 2119 "cfg", 2120 "bus_master", 2121 "bus_slave", 2122 "slave_q2a", 2123 "tbu", 2124 "ddrss_sf_tbu", 2125 "aggre0", 2126 "aggre1"; 2127 2128 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2129 assigned-clock-rates = <19200000>; 2130 2131 resets = <&gcc GCC_PCIE_1_BCR>; 2132 reset-names = "pci"; 2133 2134 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2135 2136 phys = <&pcie1_lane>; 2137 phy-names = "pciephy"; 2138 2139 pinctrl-names = "default"; 2140 pinctrl-0 = <&pcie1_clkreq_n>; 2141 2142 iommus = <&apps_smmu 0x1c80 0x1>; 2143 2144 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2145 <0x100 &apps_smmu 0x1c81 0x1>; 2146 2147 status = "disabled"; 2148 }; 2149 2150 pcie1_phy: phy@1c0e000 { 2151 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2152 reg = <0 0x01c0e000 0 0x1c0>; 2153 #address-cells = <2>; 2154 #size-cells = <2>; 2155 ranges; 2156 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2157 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2158 <&gcc GCC_PCIE_CLKREF_EN>, 2159 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2160 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2161 2162 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2163 reset-names = "phy"; 2164 2165 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2166 assigned-clock-rates = <100000000>; 2167 2168 status = "disabled"; 2169 2170 pcie1_lane: phy@1c0e200 { 2171 reg = <0 0x01c0e200 0 0x170>, 2172 <0 0x01c0e400 0 0x200>, 2173 <0 0x01c0ea00 0 0x1f0>, 2174 <0 0x01c0e600 0 0x170>, 2175 <0 0x01c0e800 0 0x200>, 2176 <0 0x01c0ee00 0 0xf4>; 2177 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2178 clock-names = "pipe0"; 2179 2180 #phy-cells = <0>; 2181 #clock-cells = <0>; 2182 clock-output-names = "pcie_1_pipe_clk"; 2183 }; 2184 }; 2185 2186 ipa: ipa@1e40000 { 2187 compatible = "qcom,sc7280-ipa"; 2188 2189 iommus = <&apps_smmu 0x480 0x0>, 2190 <&apps_smmu 0x482 0x0>; 2191 reg = <0 0x01e40000 0 0x8000>, 2192 <0 0x01e50000 0 0x4ad0>, 2193 <0 0x01e04000 0 0x23000>; 2194 reg-names = "ipa-reg", 2195 "ipa-shared", 2196 "gsi"; 2197 2198 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2199 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2200 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2201 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2202 interrupt-names = "ipa", 2203 "gsi", 2204 "ipa-clock-query", 2205 "ipa-setup-ready"; 2206 2207 clocks = <&rpmhcc RPMH_IPA_CLK>; 2208 clock-names = "core"; 2209 2210 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2211 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2212 interconnect-names = "memory", 2213 "config"; 2214 2215 qcom,qmp = <&aoss_qmp>; 2216 2217 qcom,smem-states = <&ipa_smp2p_out 0>, 2218 <&ipa_smp2p_out 1>; 2219 qcom,smem-state-names = "ipa-clock-enabled-valid", 2220 "ipa-clock-enabled"; 2221 2222 status = "disabled"; 2223 }; 2224 2225 tcsr_mutex: hwlock@1f40000 { 2226 compatible = "qcom,tcsr-mutex"; 2227 reg = <0 0x01f40000 0 0x20000>; 2228 #hwlock-cells = <1>; 2229 }; 2230 2231 tcsr_1: syscon@1f60000 { 2232 compatible = "qcom,sc7280-tcsr", "syscon"; 2233 reg = <0 0x01f60000 0 0x20000>; 2234 }; 2235 2236 tcsr_2: syscon@1fc0000 { 2237 compatible = "qcom,sc7280-tcsr", "syscon"; 2238 reg = <0 0x01fc0000 0 0x30000>; 2239 }; 2240 2241 lpasscc: lpasscc@3000000 { 2242 compatible = "qcom,sc7280-lpasscc"; 2243 reg = <0 0x03000000 0 0x40>, 2244 <0 0x03c04000 0 0x4>; 2245 reg-names = "qdsp6ss", "top_cc"; 2246 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2247 clock-names = "iface"; 2248 #clock-cells = <1>; 2249 }; 2250 2251 lpass_rx_macro: codec@3200000 { 2252 compatible = "qcom,sc7280-lpass-rx-macro"; 2253 reg = <0 0x03200000 0 0x1000>; 2254 2255 pinctrl-names = "default"; 2256 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2257 2258 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2259 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2260 <&lpass_va_macro>; 2261 clock-names = "mclk", "npl", "fsgen"; 2262 2263 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2264 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2265 power-domain-names = "macro", "dcodec"; 2266 2267 #clock-cells = <0>; 2268 #sound-dai-cells = <1>; 2269 2270 status = "disabled"; 2271 }; 2272 2273 swr0: soundwire@3210000 { 2274 compatible = "qcom,soundwire-v1.6.0"; 2275 reg = <0 0x03210000 0 0x2000>; 2276 2277 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2278 clocks = <&lpass_rx_macro>; 2279 clock-names = "iface"; 2280 2281 qcom,din-ports = <0>; 2282 qcom,dout-ports = <5>; 2283 2284 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2285 reset-names = "swr_audio_cgcr"; 2286 2287 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2288 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2289 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2290 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2291 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2292 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2293 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2294 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2295 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2296 2297 #sound-dai-cells = <1>; 2298 #address-cells = <2>; 2299 #size-cells = <0>; 2300 2301 status = "disabled"; 2302 }; 2303 2304 lpass_tx_macro: codec@3220000 { 2305 compatible = "qcom,sc7280-lpass-tx-macro"; 2306 reg = <0 0x03220000 0 0x1000>; 2307 2308 pinctrl-names = "default"; 2309 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2310 2311 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2312 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2313 <&lpass_va_macro>; 2314 clock-names = "mclk", "npl", "fsgen"; 2315 2316 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2317 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2318 power-domain-names = "macro", "dcodec"; 2319 2320 #clock-cells = <0>; 2321 #sound-dai-cells = <1>; 2322 2323 status = "disabled"; 2324 }; 2325 2326 swr1: soundwire@3230000 { 2327 compatible = "qcom,soundwire-v1.6.0"; 2328 reg = <0 0x03230000 0 0x2000>; 2329 2330 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2331 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2332 clocks = <&lpass_tx_macro>; 2333 clock-names = "iface"; 2334 2335 qcom,din-ports = <3>; 2336 qcom,dout-ports = <0>; 2337 2338 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2339 reset-names = "swr_audio_cgcr"; 2340 2341 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2342 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2343 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2344 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2345 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2346 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2347 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2348 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2349 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2350 2351 #sound-dai-cells = <1>; 2352 #address-cells = <2>; 2353 #size-cells = <0>; 2354 2355 status = "disabled"; 2356 }; 2357 2358 lpass_audiocc: clock-controller@3300000 { 2359 compatible = "qcom,sc7280-lpassaudiocc"; 2360 reg = <0 0x03300000 0 0x30000>, 2361 <0 0x032a9000 0 0x1000>; 2362 clocks = <&rpmhcc RPMH_CXO_CLK>, 2363 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2364 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2365 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2366 #clock-cells = <1>; 2367 #power-domain-cells = <1>; 2368 #reset-cells = <1>; 2369 }; 2370 2371 lpass_va_macro: codec@3370000 { 2372 compatible = "qcom,sc7280-lpass-va-macro"; 2373 reg = <0 0x03370000 0 0x1000>; 2374 2375 pinctrl-names = "default"; 2376 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2377 2378 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2379 clock-names = "mclk"; 2380 2381 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2382 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2383 power-domain-names = "macro", "dcodec"; 2384 2385 #clock-cells = <0>; 2386 #sound-dai-cells = <1>; 2387 2388 status = "disabled"; 2389 }; 2390 2391 lpass_aon: clock-controller@3380000 { 2392 compatible = "qcom,sc7280-lpassaoncc"; 2393 reg = <0 0x03380000 0 0x30000>; 2394 clocks = <&rpmhcc RPMH_CXO_CLK>, 2395 <&rpmhcc RPMH_CXO_CLK_A>, 2396 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2397 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2398 #clock-cells = <1>; 2399 #power-domain-cells = <1>; 2400 }; 2401 2402 lpass_core: clock-controller@3900000 { 2403 compatible = "qcom,sc7280-lpasscorecc"; 2404 reg = <0 0x03900000 0 0x50000>; 2405 clocks = <&rpmhcc RPMH_CXO_CLK>; 2406 clock-names = "bi_tcxo"; 2407 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2408 #clock-cells = <1>; 2409 #power-domain-cells = <1>; 2410 }; 2411 2412 lpass_cpu: audio@3987000 { 2413 compatible = "qcom,sc7280-lpass-cpu"; 2414 2415 reg = <0 0x03987000 0 0x68000>, 2416 <0 0x03b00000 0 0x29000>, 2417 <0 0x03260000 0 0xc000>, 2418 <0 0x03280000 0 0x29000>, 2419 <0 0x03340000 0 0x29000>, 2420 <0 0x0336c000 0 0x3000>; 2421 reg-names = "lpass-hdmiif", 2422 "lpass-lpaif", 2423 "lpass-rxtx-cdc-dma-lpm", 2424 "lpass-rxtx-lpaif", 2425 "lpass-va-lpaif", 2426 "lpass-va-cdc-dma-lpm"; 2427 2428 iommus = <&apps_smmu 0x1820 0>, 2429 <&apps_smmu 0x1821 0>, 2430 <&apps_smmu 0x1832 0>; 2431 2432 power-domains = <&rpmhpd SC7280_LCX>; 2433 power-domain-names = "lcx"; 2434 required-opps = <&rpmhpd_opp_nom>; 2435 2436 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2437 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2438 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2439 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2440 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2441 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2442 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2443 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2444 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2445 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2446 clock-names = "aon_cc_audio_hm_h", 2447 "audio_cc_ext_mclk0", 2448 "core_cc_sysnoc_mport_core", 2449 "core_cc_ext_if0_ibit", 2450 "core_cc_ext_if1_ibit", 2451 "audio_cc_codec_mem", 2452 "audio_cc_codec_mem0", 2453 "audio_cc_codec_mem1", 2454 "audio_cc_codec_mem2", 2455 "aon_cc_va_mem0"; 2456 2457 #sound-dai-cells = <1>; 2458 #address-cells = <1>; 2459 #size-cells = <0>; 2460 2461 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2462 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2463 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2464 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2465 interrupt-names = "lpass-irq-lpaif", 2466 "lpass-irq-hdmi", 2467 "lpass-irq-vaif", 2468 "lpass-irq-rxtxif"; 2469 2470 status = "disabled"; 2471 }; 2472 2473 lpass_hm: clock-controller@3c00000 { 2474 compatible = "qcom,sc7280-lpasshm"; 2475 reg = <0 0x03c00000 0 0x28>; 2476 clocks = <&rpmhcc RPMH_CXO_CLK>; 2477 clock-names = "bi_tcxo"; 2478 #clock-cells = <1>; 2479 #power-domain-cells = <1>; 2480 }; 2481 2482 lpass_ag_noc: interconnect@3c40000 { 2483 reg = <0 0x03c40000 0 0xf080>; 2484 compatible = "qcom,sc7280-lpass-ag-noc"; 2485 #interconnect-cells = <2>; 2486 qcom,bcm-voters = <&apps_bcm_voter>; 2487 }; 2488 2489 lpass_tlmm: pinctrl@33c0000 { 2490 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2491 reg = <0 0x033c0000 0x0 0x20000>, 2492 <0 0x03550000 0x0 0x10000>; 2493 qcom,adsp-bypass-mode; 2494 gpio-controller; 2495 #gpio-cells = <2>; 2496 gpio-ranges = <&lpass_tlmm 0 0 15>; 2497 2498 lpass_dmic01_clk: dmic01-clk-state { 2499 pins = "gpio6"; 2500 function = "dmic1_clk"; 2501 }; 2502 2503 lpass_dmic01_data: dmic01-data-state { 2504 pins = "gpio7"; 2505 function = "dmic1_data"; 2506 }; 2507 2508 lpass_dmic23_clk: dmic23-clk-state { 2509 pins = "gpio8"; 2510 function = "dmic2_clk"; 2511 }; 2512 2513 lpass_dmic23_data: dmic23-data-state { 2514 pins = "gpio9"; 2515 function = "dmic2_data"; 2516 }; 2517 2518 lpass_rx_swr_clk: rx-swr-clk-state { 2519 pins = "gpio3"; 2520 function = "swr_rx_clk"; 2521 }; 2522 2523 lpass_rx_swr_data: rx-swr-data-state { 2524 pins = "gpio4", "gpio5"; 2525 function = "swr_rx_data"; 2526 }; 2527 2528 lpass_tx_swr_clk: tx-swr-clk-state { 2529 pins = "gpio0"; 2530 function = "swr_tx_clk"; 2531 }; 2532 2533 lpass_tx_swr_data: tx-swr-data-state { 2534 pins = "gpio1", "gpio2", "gpio14"; 2535 function = "swr_tx_data"; 2536 }; 2537 }; 2538 2539 gpu: gpu@3d00000 { 2540 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2541 reg = <0 0x03d00000 0 0x40000>, 2542 <0 0x03d9e000 0 0x1000>, 2543 <0 0x03d61000 0 0x800>; 2544 reg-names = "kgsl_3d0_reg_memory", 2545 "cx_mem", 2546 "cx_dbgc"; 2547 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2548 iommus = <&adreno_smmu 0 0x401>; 2549 operating-points-v2 = <&gpu_opp_table>; 2550 qcom,gmu = <&gmu>; 2551 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2552 interconnect-names = "gfx-mem"; 2553 #cooling-cells = <2>; 2554 2555 nvmem-cells = <&gpu_speed_bin>; 2556 nvmem-cell-names = "speed_bin"; 2557 2558 gpu_opp_table: opp-table { 2559 compatible = "operating-points-v2"; 2560 2561 opp-315000000 { 2562 opp-hz = /bits/ 64 <315000000>; 2563 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2564 opp-peak-kBps = <1804000>; 2565 opp-supported-hw = <0x03>; 2566 }; 2567 2568 opp-450000000 { 2569 opp-hz = /bits/ 64 <450000000>; 2570 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2571 opp-peak-kBps = <4068000>; 2572 opp-supported-hw = <0x03>; 2573 }; 2574 2575 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2576 opp-550000000-0 { 2577 opp-hz = /bits/ 64 <550000000>; 2578 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2579 opp-peak-kBps = <8368000>; 2580 opp-supported-hw = <0x01>; 2581 }; 2582 2583 opp-550000000-1 { 2584 opp-hz = /bits/ 64 <550000000>; 2585 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2586 opp-peak-kBps = <6832000>; 2587 opp-supported-hw = <0x02>; 2588 }; 2589 2590 opp-608000000 { 2591 opp-hz = /bits/ 64 <608000000>; 2592 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2593 opp-peak-kBps = <8368000>; 2594 opp-supported-hw = <0x02>; 2595 }; 2596 2597 opp-700000000 { 2598 opp-hz = /bits/ 64 <700000000>; 2599 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2600 opp-peak-kBps = <8532000>; 2601 opp-supported-hw = <0x02>; 2602 }; 2603 2604 opp-812000000 { 2605 opp-hz = /bits/ 64 <812000000>; 2606 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2607 opp-peak-kBps = <8532000>; 2608 opp-supported-hw = <0x02>; 2609 }; 2610 2611 opp-840000000 { 2612 opp-hz = /bits/ 64 <840000000>; 2613 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2614 opp-peak-kBps = <8532000>; 2615 opp-supported-hw = <0x02>; 2616 }; 2617 2618 opp-900000000 { 2619 opp-hz = /bits/ 64 <900000000>; 2620 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2621 opp-peak-kBps = <8532000>; 2622 opp-supported-hw = <0x02>; 2623 }; 2624 }; 2625 }; 2626 2627 gmu: gmu@3d6a000 { 2628 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2629 reg = <0 0x03d6a000 0 0x34000>, 2630 <0 0x3de0000 0 0x10000>, 2631 <0 0x0b290000 0 0x10000>; 2632 reg-names = "gmu", "rscc", "gmu_pdc"; 2633 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2634 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2635 interrupt-names = "hfi", "gmu"; 2636 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2637 <&gpucc GPU_CC_CXO_CLK>, 2638 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2639 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2640 <&gpucc GPU_CC_AHB_CLK>, 2641 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2642 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2643 clock-names = "gmu", 2644 "cxo", 2645 "axi", 2646 "memnoc", 2647 "ahb", 2648 "hub", 2649 "smmu_vote"; 2650 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2651 <&gpucc GPU_CC_GX_GDSC>; 2652 power-domain-names = "cx", 2653 "gx"; 2654 iommus = <&adreno_smmu 5 0x400>; 2655 operating-points-v2 = <&gmu_opp_table>; 2656 2657 gmu_opp_table: opp-table { 2658 compatible = "operating-points-v2"; 2659 2660 opp-200000000 { 2661 opp-hz = /bits/ 64 <200000000>; 2662 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2663 }; 2664 }; 2665 }; 2666 2667 gpucc: clock-controller@3d90000 { 2668 compatible = "qcom,sc7280-gpucc"; 2669 reg = <0 0x03d90000 0 0x9000>; 2670 clocks = <&rpmhcc RPMH_CXO_CLK>, 2671 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2672 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2673 clock-names = "bi_tcxo", 2674 "gcc_gpu_gpll0_clk_src", 2675 "gcc_gpu_gpll0_div_clk_src"; 2676 #clock-cells = <1>; 2677 #reset-cells = <1>; 2678 #power-domain-cells = <1>; 2679 }; 2680 2681 dma@117f000 { 2682 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 2683 reg = <0x0 0x0117f000 0x0 0x1000>, 2684 <0x0 0x01112000 0x0 0x6000>; 2685 }; 2686 2687 adreno_smmu: iommu@3da0000 { 2688 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", 2689 "qcom,smmu-500", "arm,mmu-500"; 2690 reg = <0 0x03da0000 0 0x20000>; 2691 #iommu-cells = <2>; 2692 #global-interrupts = <2>; 2693 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2694 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2695 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2696 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2697 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2698 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2699 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2700 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2701 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2702 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2703 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2704 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2705 2706 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2707 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2708 <&gpucc GPU_CC_AHB_CLK>, 2709 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2710 <&gpucc GPU_CC_CX_GMU_CLK>, 2711 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2712 <&gpucc GPU_CC_HUB_AON_CLK>; 2713 clock-names = "gcc_gpu_memnoc_gfx_clk", 2714 "gcc_gpu_snoc_dvm_gfx_clk", 2715 "gpu_cc_ahb_clk", 2716 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2717 "gpu_cc_cx_gmu_clk", 2718 "gpu_cc_hub_cx_int_clk", 2719 "gpu_cc_hub_aon_clk"; 2720 2721 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2722 }; 2723 2724 remoteproc_mpss: remoteproc@4080000 { 2725 compatible = "qcom,sc7280-mpss-pas"; 2726 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2727 reg-names = "qdsp6", "rmb"; 2728 2729 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2730 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2731 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2732 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2733 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2734 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2735 interrupt-names = "wdog", "fatal", "ready", "handover", 2736 "stop-ack", "shutdown-ack"; 2737 2738 clocks = <&rpmhcc RPMH_CXO_CLK>; 2739 clock-names = "xo"; 2740 2741 power-domains = <&rpmhpd SC7280_CX>, 2742 <&rpmhpd SC7280_MSS>; 2743 power-domain-names = "cx", "mss"; 2744 2745 memory-region = <&mpss_mem>; 2746 2747 qcom,qmp = <&aoss_qmp>; 2748 2749 qcom,smem-states = <&modem_smp2p_out 0>; 2750 qcom,smem-state-names = "stop"; 2751 2752 status = "disabled"; 2753 2754 glink-edge { 2755 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2756 IPCC_MPROC_SIGNAL_GLINK_QMP 2757 IRQ_TYPE_EDGE_RISING>; 2758 mboxes = <&ipcc IPCC_CLIENT_MPSS 2759 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2760 label = "modem"; 2761 qcom,remote-pid = <1>; 2762 }; 2763 }; 2764 2765 stm@6002000 { 2766 compatible = "arm,coresight-stm", "arm,primecell"; 2767 reg = <0 0x06002000 0 0x1000>, 2768 <0 0x16280000 0 0x180000>; 2769 reg-names = "stm-base", "stm-stimulus-base"; 2770 2771 clocks = <&aoss_qmp>; 2772 clock-names = "apb_pclk"; 2773 2774 out-ports { 2775 port { 2776 stm_out: endpoint { 2777 remote-endpoint = <&funnel0_in7>; 2778 }; 2779 }; 2780 }; 2781 }; 2782 2783 funnel@6041000 { 2784 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2785 reg = <0 0x06041000 0 0x1000>; 2786 2787 clocks = <&aoss_qmp>; 2788 clock-names = "apb_pclk"; 2789 2790 out-ports { 2791 port { 2792 funnel0_out: endpoint { 2793 remote-endpoint = <&merge_funnel_in0>; 2794 }; 2795 }; 2796 }; 2797 2798 in-ports { 2799 #address-cells = <1>; 2800 #size-cells = <0>; 2801 2802 port@7 { 2803 reg = <7>; 2804 funnel0_in7: endpoint { 2805 remote-endpoint = <&stm_out>; 2806 }; 2807 }; 2808 }; 2809 }; 2810 2811 funnel@6042000 { 2812 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2813 reg = <0 0x06042000 0 0x1000>; 2814 2815 clocks = <&aoss_qmp>; 2816 clock-names = "apb_pclk"; 2817 2818 out-ports { 2819 port { 2820 funnel1_out: endpoint { 2821 remote-endpoint = <&merge_funnel_in1>; 2822 }; 2823 }; 2824 }; 2825 2826 in-ports { 2827 #address-cells = <1>; 2828 #size-cells = <0>; 2829 2830 port@4 { 2831 reg = <4>; 2832 funnel1_in4: endpoint { 2833 remote-endpoint = <&apss_merge_funnel_out>; 2834 }; 2835 }; 2836 }; 2837 }; 2838 2839 funnel@6045000 { 2840 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2841 reg = <0 0x06045000 0 0x1000>; 2842 2843 clocks = <&aoss_qmp>; 2844 clock-names = "apb_pclk"; 2845 2846 out-ports { 2847 port { 2848 merge_funnel_out: endpoint { 2849 remote-endpoint = <&swao_funnel_in>; 2850 }; 2851 }; 2852 }; 2853 2854 in-ports { 2855 #address-cells = <1>; 2856 #size-cells = <0>; 2857 2858 port@0 { 2859 reg = <0>; 2860 merge_funnel_in0: endpoint { 2861 remote-endpoint = <&funnel0_out>; 2862 }; 2863 }; 2864 2865 port@1 { 2866 reg = <1>; 2867 merge_funnel_in1: endpoint { 2868 remote-endpoint = <&funnel1_out>; 2869 }; 2870 }; 2871 }; 2872 }; 2873 2874 replicator@6046000 { 2875 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2876 reg = <0 0x06046000 0 0x1000>; 2877 2878 clocks = <&aoss_qmp>; 2879 clock-names = "apb_pclk"; 2880 2881 out-ports { 2882 port { 2883 replicator_out: endpoint { 2884 remote-endpoint = <&etr_in>; 2885 }; 2886 }; 2887 }; 2888 2889 in-ports { 2890 port { 2891 replicator_in: endpoint { 2892 remote-endpoint = <&swao_replicator_out>; 2893 }; 2894 }; 2895 }; 2896 }; 2897 2898 etr@6048000 { 2899 compatible = "arm,coresight-tmc", "arm,primecell"; 2900 reg = <0 0x06048000 0 0x1000>; 2901 iommus = <&apps_smmu 0x04c0 0>; 2902 2903 clocks = <&aoss_qmp>; 2904 clock-names = "apb_pclk"; 2905 arm,scatter-gather; 2906 2907 in-ports { 2908 port { 2909 etr_in: endpoint { 2910 remote-endpoint = <&replicator_out>; 2911 }; 2912 }; 2913 }; 2914 }; 2915 2916 funnel@6b04000 { 2917 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2918 reg = <0 0x06b04000 0 0x1000>; 2919 2920 clocks = <&aoss_qmp>; 2921 clock-names = "apb_pclk"; 2922 2923 out-ports { 2924 port { 2925 swao_funnel_out: endpoint { 2926 remote-endpoint = <&etf_in>; 2927 }; 2928 }; 2929 }; 2930 2931 in-ports { 2932 #address-cells = <1>; 2933 #size-cells = <0>; 2934 2935 port@7 { 2936 reg = <7>; 2937 swao_funnel_in: endpoint { 2938 remote-endpoint = <&merge_funnel_out>; 2939 }; 2940 }; 2941 }; 2942 }; 2943 2944 etf@6b05000 { 2945 compatible = "arm,coresight-tmc", "arm,primecell"; 2946 reg = <0 0x06b05000 0 0x1000>; 2947 2948 clocks = <&aoss_qmp>; 2949 clock-names = "apb_pclk"; 2950 2951 out-ports { 2952 port { 2953 etf_out: endpoint { 2954 remote-endpoint = <&swao_replicator_in>; 2955 }; 2956 }; 2957 }; 2958 2959 in-ports { 2960 port { 2961 etf_in: endpoint { 2962 remote-endpoint = <&swao_funnel_out>; 2963 }; 2964 }; 2965 }; 2966 }; 2967 2968 replicator@6b06000 { 2969 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2970 reg = <0 0x06b06000 0 0x1000>; 2971 2972 clocks = <&aoss_qmp>; 2973 clock-names = "apb_pclk"; 2974 qcom,replicator-loses-context; 2975 2976 out-ports { 2977 port { 2978 swao_replicator_out: endpoint { 2979 remote-endpoint = <&replicator_in>; 2980 }; 2981 }; 2982 }; 2983 2984 in-ports { 2985 port { 2986 swao_replicator_in: endpoint { 2987 remote-endpoint = <&etf_out>; 2988 }; 2989 }; 2990 }; 2991 }; 2992 2993 etm@7040000 { 2994 compatible = "arm,coresight-etm4x", "arm,primecell"; 2995 reg = <0 0x07040000 0 0x1000>; 2996 2997 cpu = <&CPU0>; 2998 2999 clocks = <&aoss_qmp>; 3000 clock-names = "apb_pclk"; 3001 arm,coresight-loses-context-with-cpu; 3002 qcom,skip-power-up; 3003 3004 out-ports { 3005 port { 3006 etm0_out: endpoint { 3007 remote-endpoint = <&apss_funnel_in0>; 3008 }; 3009 }; 3010 }; 3011 }; 3012 3013 etm@7140000 { 3014 compatible = "arm,coresight-etm4x", "arm,primecell"; 3015 reg = <0 0x07140000 0 0x1000>; 3016 3017 cpu = <&CPU1>; 3018 3019 clocks = <&aoss_qmp>; 3020 clock-names = "apb_pclk"; 3021 arm,coresight-loses-context-with-cpu; 3022 qcom,skip-power-up; 3023 3024 out-ports { 3025 port { 3026 etm1_out: endpoint { 3027 remote-endpoint = <&apss_funnel_in1>; 3028 }; 3029 }; 3030 }; 3031 }; 3032 3033 etm@7240000 { 3034 compatible = "arm,coresight-etm4x", "arm,primecell"; 3035 reg = <0 0x07240000 0 0x1000>; 3036 3037 cpu = <&CPU2>; 3038 3039 clocks = <&aoss_qmp>; 3040 clock-names = "apb_pclk"; 3041 arm,coresight-loses-context-with-cpu; 3042 qcom,skip-power-up; 3043 3044 out-ports { 3045 port { 3046 etm2_out: endpoint { 3047 remote-endpoint = <&apss_funnel_in2>; 3048 }; 3049 }; 3050 }; 3051 }; 3052 3053 etm@7340000 { 3054 compatible = "arm,coresight-etm4x", "arm,primecell"; 3055 reg = <0 0x07340000 0 0x1000>; 3056 3057 cpu = <&CPU3>; 3058 3059 clocks = <&aoss_qmp>; 3060 clock-names = "apb_pclk"; 3061 arm,coresight-loses-context-with-cpu; 3062 qcom,skip-power-up; 3063 3064 out-ports { 3065 port { 3066 etm3_out: endpoint { 3067 remote-endpoint = <&apss_funnel_in3>; 3068 }; 3069 }; 3070 }; 3071 }; 3072 3073 etm@7440000 { 3074 compatible = "arm,coresight-etm4x", "arm,primecell"; 3075 reg = <0 0x07440000 0 0x1000>; 3076 3077 cpu = <&CPU4>; 3078 3079 clocks = <&aoss_qmp>; 3080 clock-names = "apb_pclk"; 3081 arm,coresight-loses-context-with-cpu; 3082 qcom,skip-power-up; 3083 3084 out-ports { 3085 port { 3086 etm4_out: endpoint { 3087 remote-endpoint = <&apss_funnel_in4>; 3088 }; 3089 }; 3090 }; 3091 }; 3092 3093 etm@7540000 { 3094 compatible = "arm,coresight-etm4x", "arm,primecell"; 3095 reg = <0 0x07540000 0 0x1000>; 3096 3097 cpu = <&CPU5>; 3098 3099 clocks = <&aoss_qmp>; 3100 clock-names = "apb_pclk"; 3101 arm,coresight-loses-context-with-cpu; 3102 qcom,skip-power-up; 3103 3104 out-ports { 3105 port { 3106 etm5_out: endpoint { 3107 remote-endpoint = <&apss_funnel_in5>; 3108 }; 3109 }; 3110 }; 3111 }; 3112 3113 etm@7640000 { 3114 compatible = "arm,coresight-etm4x", "arm,primecell"; 3115 reg = <0 0x07640000 0 0x1000>; 3116 3117 cpu = <&CPU6>; 3118 3119 clocks = <&aoss_qmp>; 3120 clock-names = "apb_pclk"; 3121 arm,coresight-loses-context-with-cpu; 3122 qcom,skip-power-up; 3123 3124 out-ports { 3125 port { 3126 etm6_out: endpoint { 3127 remote-endpoint = <&apss_funnel_in6>; 3128 }; 3129 }; 3130 }; 3131 }; 3132 3133 etm@7740000 { 3134 compatible = "arm,coresight-etm4x", "arm,primecell"; 3135 reg = <0 0x07740000 0 0x1000>; 3136 3137 cpu = <&CPU7>; 3138 3139 clocks = <&aoss_qmp>; 3140 clock-names = "apb_pclk"; 3141 arm,coresight-loses-context-with-cpu; 3142 qcom,skip-power-up; 3143 3144 out-ports { 3145 port { 3146 etm7_out: endpoint { 3147 remote-endpoint = <&apss_funnel_in7>; 3148 }; 3149 }; 3150 }; 3151 }; 3152 3153 funnel@7800000 { /* APSS Funnel */ 3154 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3155 reg = <0 0x07800000 0 0x1000>; 3156 3157 clocks = <&aoss_qmp>; 3158 clock-names = "apb_pclk"; 3159 3160 out-ports { 3161 port { 3162 apss_funnel_out: endpoint { 3163 remote-endpoint = <&apss_merge_funnel_in>; 3164 }; 3165 }; 3166 }; 3167 3168 in-ports { 3169 #address-cells = <1>; 3170 #size-cells = <0>; 3171 3172 port@0 { 3173 reg = <0>; 3174 apss_funnel_in0: endpoint { 3175 remote-endpoint = <&etm0_out>; 3176 }; 3177 }; 3178 3179 port@1 { 3180 reg = <1>; 3181 apss_funnel_in1: endpoint { 3182 remote-endpoint = <&etm1_out>; 3183 }; 3184 }; 3185 3186 port@2 { 3187 reg = <2>; 3188 apss_funnel_in2: endpoint { 3189 remote-endpoint = <&etm2_out>; 3190 }; 3191 }; 3192 3193 port@3 { 3194 reg = <3>; 3195 apss_funnel_in3: endpoint { 3196 remote-endpoint = <&etm3_out>; 3197 }; 3198 }; 3199 3200 port@4 { 3201 reg = <4>; 3202 apss_funnel_in4: endpoint { 3203 remote-endpoint = <&etm4_out>; 3204 }; 3205 }; 3206 3207 port@5 { 3208 reg = <5>; 3209 apss_funnel_in5: endpoint { 3210 remote-endpoint = <&etm5_out>; 3211 }; 3212 }; 3213 3214 port@6 { 3215 reg = <6>; 3216 apss_funnel_in6: endpoint { 3217 remote-endpoint = <&etm6_out>; 3218 }; 3219 }; 3220 3221 port@7 { 3222 reg = <7>; 3223 apss_funnel_in7: endpoint { 3224 remote-endpoint = <&etm7_out>; 3225 }; 3226 }; 3227 }; 3228 }; 3229 3230 funnel@7810000 { 3231 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3232 reg = <0 0x07810000 0 0x1000>; 3233 3234 clocks = <&aoss_qmp>; 3235 clock-names = "apb_pclk"; 3236 3237 out-ports { 3238 port { 3239 apss_merge_funnel_out: endpoint { 3240 remote-endpoint = <&funnel1_in4>; 3241 }; 3242 }; 3243 }; 3244 3245 in-ports { 3246 port { 3247 apss_merge_funnel_in: endpoint { 3248 remote-endpoint = <&apss_funnel_out>; 3249 }; 3250 }; 3251 }; 3252 }; 3253 3254 sdhc_2: mmc@8804000 { 3255 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3256 pinctrl-names = "default", "sleep"; 3257 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3258 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3259 status = "disabled"; 3260 3261 reg = <0 0x08804000 0 0x1000>; 3262 3263 iommus = <&apps_smmu 0x100 0x0>; 3264 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3265 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3266 interrupt-names = "hc_irq", "pwr_irq"; 3267 3268 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3269 <&gcc GCC_SDCC2_APPS_CLK>, 3270 <&rpmhcc RPMH_CXO_CLK>; 3271 clock-names = "iface", "core", "xo"; 3272 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3273 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3274 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3275 power-domains = <&rpmhpd SC7280_CX>; 3276 operating-points-v2 = <&sdhc2_opp_table>; 3277 3278 bus-width = <4>; 3279 3280 qcom,dll-config = <0x0007642c>; 3281 3282 resets = <&gcc GCC_SDCC2_BCR>; 3283 3284 sdhc2_opp_table: opp-table { 3285 compatible = "operating-points-v2"; 3286 3287 opp-100000000 { 3288 opp-hz = /bits/ 64 <100000000>; 3289 required-opps = <&rpmhpd_opp_low_svs>; 3290 opp-peak-kBps = <1800000 400000>; 3291 opp-avg-kBps = <100000 0>; 3292 }; 3293 3294 opp-202000000 { 3295 opp-hz = /bits/ 64 <202000000>; 3296 required-opps = <&rpmhpd_opp_nom>; 3297 opp-peak-kBps = <5400000 1600000>; 3298 opp-avg-kBps = <200000 0>; 3299 }; 3300 }; 3301 3302 }; 3303 3304 usb_1_hsphy: phy@88e3000 { 3305 compatible = "qcom,sc7280-usb-hs-phy", 3306 "qcom,usb-snps-hs-7nm-phy"; 3307 reg = <0 0x088e3000 0 0x400>; 3308 status = "disabled"; 3309 #phy-cells = <0>; 3310 3311 clocks = <&rpmhcc RPMH_CXO_CLK>; 3312 clock-names = "ref"; 3313 3314 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3315 }; 3316 3317 usb_2_hsphy: phy@88e4000 { 3318 compatible = "qcom,sc7280-usb-hs-phy", 3319 "qcom,usb-snps-hs-7nm-phy"; 3320 reg = <0 0x088e4000 0 0x400>; 3321 status = "disabled"; 3322 #phy-cells = <0>; 3323 3324 clocks = <&rpmhcc RPMH_CXO_CLK>; 3325 clock-names = "ref"; 3326 3327 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3328 }; 3329 3330 usb_1_qmpphy: phy-wrapper@88e9000 { 3331 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3332 "qcom,sm8250-qmp-usb3-dp-phy"; 3333 reg = <0 0x088e9000 0 0x200>, 3334 <0 0x088e8000 0 0x40>, 3335 <0 0x088ea000 0 0x200>; 3336 status = "disabled"; 3337 #address-cells = <2>; 3338 #size-cells = <2>; 3339 ranges; 3340 3341 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3342 <&rpmhcc RPMH_CXO_CLK>, 3343 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3344 clock-names = "aux", "ref_clk_src", "com_aux"; 3345 3346 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3347 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3348 reset-names = "phy", "common"; 3349 3350 usb_1_ssphy: usb3-phy@88e9200 { 3351 reg = <0 0x088e9200 0 0x200>, 3352 <0 0x088e9400 0 0x200>, 3353 <0 0x088e9c00 0 0x400>, 3354 <0 0x088e9600 0 0x200>, 3355 <0 0x088e9800 0 0x200>, 3356 <0 0x088e9a00 0 0x100>; 3357 #clock-cells = <0>; 3358 #phy-cells = <0>; 3359 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3360 clock-names = "pipe0"; 3361 clock-output-names = "usb3_phy_pipe_clk_src"; 3362 }; 3363 3364 dp_phy: dp-phy@88ea200 { 3365 reg = <0 0x088ea200 0 0x200>, 3366 <0 0x088ea400 0 0x200>, 3367 <0 0x088eaa00 0 0x200>, 3368 <0 0x088ea600 0 0x200>, 3369 <0 0x088ea800 0 0x200>; 3370 #phy-cells = <0>; 3371 #clock-cells = <1>; 3372 }; 3373 }; 3374 3375 usb_2: usb@8cf8800 { 3376 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3377 reg = <0 0x08cf8800 0 0x400>; 3378 status = "disabled"; 3379 #address-cells = <2>; 3380 #size-cells = <2>; 3381 ranges; 3382 dma-ranges; 3383 3384 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3385 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3386 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3387 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3388 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3389 clock-names = "cfg_noc", 3390 "core", 3391 "iface", 3392 "sleep", 3393 "mock_utmi"; 3394 3395 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3396 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3397 assigned-clock-rates = <19200000>, <200000000>; 3398 3399 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3400 <&pdc 12 IRQ_TYPE_EDGE_RISING>, 3401 <&pdc 13 IRQ_TYPE_EDGE_RISING>; 3402 interrupt-names = "hs_phy_irq", 3403 "dp_hs_phy_irq", 3404 "dm_hs_phy_irq"; 3405 3406 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3407 required-opps = <&rpmhpd_opp_nom>; 3408 3409 resets = <&gcc GCC_USB30_SEC_BCR>; 3410 3411 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3412 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3413 interconnect-names = "usb-ddr", "apps-usb"; 3414 3415 usb_2_dwc3: usb@8c00000 { 3416 compatible = "snps,dwc3"; 3417 reg = <0 0x08c00000 0 0xe000>; 3418 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3419 iommus = <&apps_smmu 0xa0 0x0>; 3420 snps,dis_u2_susphy_quirk; 3421 snps,dis_enblslpm_quirk; 3422 phys = <&usb_2_hsphy>; 3423 phy-names = "usb2-phy"; 3424 maximum-speed = "high-speed"; 3425 usb-role-switch; 3426 port { 3427 usb2_role_switch: endpoint { 3428 remote-endpoint = <&eud_ep>; 3429 }; 3430 }; 3431 }; 3432 }; 3433 3434 qspi: spi@88dc000 { 3435 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3436 reg = <0 0x088dc000 0 0x1000>; 3437 #address-cells = <1>; 3438 #size-cells = <0>; 3439 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3440 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3441 <&gcc GCC_QSPI_CORE_CLK>; 3442 clock-names = "iface", "core"; 3443 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3444 &cnoc2 SLAVE_QSPI_0 0>; 3445 interconnect-names = "qspi-config"; 3446 power-domains = <&rpmhpd SC7280_CX>; 3447 operating-points-v2 = <&qspi_opp_table>; 3448 status = "disabled"; 3449 }; 3450 3451 remoteproc_wpss: remoteproc@8a00000 { 3452 compatible = "qcom,sc7280-wpss-pil"; 3453 reg = <0 0x08a00000 0 0x10000>; 3454 3455 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3456 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3457 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3458 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3459 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3460 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3461 interrupt-names = "wdog", "fatal", "ready", "handover", 3462 "stop-ack", "shutdown-ack"; 3463 3464 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3465 <&gcc GCC_WPSS_AHB_CLK>, 3466 <&gcc GCC_WPSS_RSCP_CLK>, 3467 <&rpmhcc RPMH_CXO_CLK>; 3468 clock-names = "ahb_bdg", "ahb", 3469 "rscp", "xo"; 3470 3471 power-domains = <&rpmhpd SC7280_CX>, 3472 <&rpmhpd SC7280_MX>; 3473 power-domain-names = "cx", "mx"; 3474 3475 memory-region = <&wpss_mem>; 3476 3477 qcom,qmp = <&aoss_qmp>; 3478 3479 qcom,smem-states = <&wpss_smp2p_out 0>; 3480 qcom,smem-state-names = "stop"; 3481 3482 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3483 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3484 reset-names = "restart", "pdc_sync"; 3485 3486 qcom,halt-regs = <&tcsr_1 0x17000>; 3487 3488 status = "disabled"; 3489 3490 glink-edge { 3491 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3492 IPCC_MPROC_SIGNAL_GLINK_QMP 3493 IRQ_TYPE_EDGE_RISING>; 3494 mboxes = <&ipcc IPCC_CLIENT_WPSS 3495 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3496 3497 label = "wpss"; 3498 qcom,remote-pid = <13>; 3499 }; 3500 }; 3501 3502 pmu@9091000 { 3503 compatible = "qcom,sc7280-llcc-bwmon"; 3504 reg = <0 0x09091000 0 0x1000>; 3505 3506 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3507 3508 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3509 3510 operating-points-v2 = <&llcc_bwmon_opp_table>; 3511 3512 llcc_bwmon_opp_table: opp-table { 3513 compatible = "operating-points-v2"; 3514 3515 opp-0 { 3516 opp-peak-kBps = <800000>; 3517 }; 3518 opp-1 { 3519 opp-peak-kBps = <1804000>; 3520 }; 3521 opp-2 { 3522 opp-peak-kBps = <2188000>; 3523 }; 3524 opp-3 { 3525 opp-peak-kBps = <3072000>; 3526 }; 3527 opp-4 { 3528 opp-peak-kBps = <4068000>; 3529 }; 3530 opp-5 { 3531 opp-peak-kBps = <6220000>; 3532 }; 3533 opp-6 { 3534 opp-peak-kBps = <6832000>; 3535 }; 3536 opp-7 { 3537 opp-peak-kBps = <8532000>; 3538 }; 3539 }; 3540 }; 3541 3542 pmu@90b6400 { 3543 compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon"; 3544 reg = <0 0x090b6400 0 0x600>; 3545 3546 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3547 3548 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3549 operating-points-v2 = <&cpu_bwmon_opp_table>; 3550 3551 cpu_bwmon_opp_table: opp-table { 3552 compatible = "operating-points-v2"; 3553 3554 opp-0 { 3555 opp-peak-kBps = <2400000>; 3556 }; 3557 opp-1 { 3558 opp-peak-kBps = <4800000>; 3559 }; 3560 opp-2 { 3561 opp-peak-kBps = <7456000>; 3562 }; 3563 opp-3 { 3564 opp-peak-kBps = <9600000>; 3565 }; 3566 opp-4 { 3567 opp-peak-kBps = <12896000>; 3568 }; 3569 opp-5 { 3570 opp-peak-kBps = <14928000>; 3571 }; 3572 opp-6 { 3573 opp-peak-kBps = <17056000>; 3574 }; 3575 }; 3576 }; 3577 3578 dc_noc: interconnect@90e0000 { 3579 reg = <0 0x090e0000 0 0x5080>; 3580 compatible = "qcom,sc7280-dc-noc"; 3581 #interconnect-cells = <2>; 3582 qcom,bcm-voters = <&apps_bcm_voter>; 3583 }; 3584 3585 gem_noc: interconnect@9100000 { 3586 reg = <0 0x09100000 0 0xe2200>; 3587 compatible = "qcom,sc7280-gem-noc"; 3588 #interconnect-cells = <2>; 3589 qcom,bcm-voters = <&apps_bcm_voter>; 3590 }; 3591 3592 system-cache-controller@9200000 { 3593 compatible = "qcom,sc7280-llcc"; 3594 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3595 <0 0x09600000 0 0x58000>; 3596 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; 3597 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3598 }; 3599 3600 eud: eud@88e0000 { 3601 compatible = "qcom,sc7280-eud","qcom,eud"; 3602 reg = <0 0x088e0000 0 0x2000>, 3603 <0 0x088e2000 0 0x1000>; 3604 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3605 ports { 3606 port@0 { 3607 eud_ep: endpoint { 3608 remote-endpoint = <&usb2_role_switch>; 3609 }; 3610 }; 3611 port@1 { 3612 eud_con: endpoint { 3613 remote-endpoint = <&con_eud>; 3614 }; 3615 }; 3616 }; 3617 }; 3618 3619 eud_typec: connector { 3620 compatible = "usb-c-connector"; 3621 ports { 3622 port@0 { 3623 con_eud: endpoint { 3624 remote-endpoint = <&eud_con>; 3625 }; 3626 }; 3627 }; 3628 }; 3629 3630 nsp_noc: interconnect@a0c0000 { 3631 reg = <0 0x0a0c0000 0 0x10000>; 3632 compatible = "qcom,sc7280-nsp-noc"; 3633 #interconnect-cells = <2>; 3634 qcom,bcm-voters = <&apps_bcm_voter>; 3635 }; 3636 3637 usb_1: usb@a6f8800 { 3638 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3639 reg = <0 0x0a6f8800 0 0x400>; 3640 status = "disabled"; 3641 #address-cells = <2>; 3642 #size-cells = <2>; 3643 ranges; 3644 dma-ranges; 3645 3646 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3647 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3648 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3649 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3650 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3651 clock-names = "cfg_noc", 3652 "core", 3653 "iface", 3654 "sleep", 3655 "mock_utmi"; 3656 3657 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3658 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3659 assigned-clock-rates = <19200000>, <200000000>; 3660 3661 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3662 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3663 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3664 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3665 interrupt-names = "hs_phy_irq", 3666 "dp_hs_phy_irq", 3667 "dm_hs_phy_irq", 3668 "ss_phy_irq"; 3669 3670 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3671 required-opps = <&rpmhpd_opp_nom>; 3672 3673 resets = <&gcc GCC_USB30_PRIM_BCR>; 3674 3675 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3676 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3677 interconnect-names = "usb-ddr", "apps-usb"; 3678 3679 wakeup-source; 3680 3681 usb_1_dwc3: usb@a600000 { 3682 compatible = "snps,dwc3"; 3683 reg = <0 0x0a600000 0 0xe000>; 3684 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3685 iommus = <&apps_smmu 0xe0 0x0>; 3686 snps,dis_u2_susphy_quirk; 3687 snps,dis_enblslpm_quirk; 3688 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3689 phy-names = "usb2-phy", "usb3-phy"; 3690 maximum-speed = "super-speed"; 3691 }; 3692 }; 3693 3694 venus: video-codec@aa00000 { 3695 compatible = "qcom,sc7280-venus"; 3696 reg = <0 0x0aa00000 0 0xd0600>; 3697 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3698 3699 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3700 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3701 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3702 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3703 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3704 clock-names = "core", "bus", "iface", 3705 "vcodec_core", "vcodec_bus"; 3706 3707 power-domains = <&videocc MVSC_GDSC>, 3708 <&videocc MVS0_GDSC>, 3709 <&rpmhpd SC7280_CX>; 3710 power-domain-names = "venus", "vcodec0", "cx"; 3711 operating-points-v2 = <&venus_opp_table>; 3712 3713 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3714 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3715 interconnect-names = "cpu-cfg", "video-mem"; 3716 3717 iommus = <&apps_smmu 0x2180 0x20>, 3718 <&apps_smmu 0x2184 0x20>; 3719 memory-region = <&video_mem>; 3720 3721 video-decoder { 3722 compatible = "venus-decoder"; 3723 }; 3724 3725 video-encoder { 3726 compatible = "venus-encoder"; 3727 }; 3728 3729 video-firmware { 3730 iommus = <&apps_smmu 0x21a2 0x0>; 3731 }; 3732 3733 venus_opp_table: opp-table { 3734 compatible = "operating-points-v2"; 3735 3736 opp-133330000 { 3737 opp-hz = /bits/ 64 <133330000>; 3738 required-opps = <&rpmhpd_opp_low_svs>; 3739 }; 3740 3741 opp-240000000 { 3742 opp-hz = /bits/ 64 <240000000>; 3743 required-opps = <&rpmhpd_opp_svs>; 3744 }; 3745 3746 opp-335000000 { 3747 opp-hz = /bits/ 64 <335000000>; 3748 required-opps = <&rpmhpd_opp_svs_l1>; 3749 }; 3750 3751 opp-424000000 { 3752 opp-hz = /bits/ 64 <424000000>; 3753 required-opps = <&rpmhpd_opp_nom>; 3754 }; 3755 3756 opp-460000048 { 3757 opp-hz = /bits/ 64 <460000048>; 3758 required-opps = <&rpmhpd_opp_turbo>; 3759 }; 3760 }; 3761 3762 }; 3763 3764 videocc: clock-controller@aaf0000 { 3765 compatible = "qcom,sc7280-videocc"; 3766 reg = <0 0x0aaf0000 0 0x10000>; 3767 clocks = <&rpmhcc RPMH_CXO_CLK>, 3768 <&rpmhcc RPMH_CXO_CLK_A>; 3769 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3770 #clock-cells = <1>; 3771 #reset-cells = <1>; 3772 #power-domain-cells = <1>; 3773 }; 3774 3775 camcc: clock-controller@ad00000 { 3776 compatible = "qcom,sc7280-camcc"; 3777 reg = <0 0x0ad00000 0 0x10000>; 3778 clocks = <&rpmhcc RPMH_CXO_CLK>, 3779 <&rpmhcc RPMH_CXO_CLK_A>, 3780 <&sleep_clk>; 3781 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3782 #clock-cells = <1>; 3783 #reset-cells = <1>; 3784 #power-domain-cells = <1>; 3785 }; 3786 3787 dispcc: clock-controller@af00000 { 3788 compatible = "qcom,sc7280-dispcc"; 3789 reg = <0 0x0af00000 0 0x20000>; 3790 clocks = <&rpmhcc RPMH_CXO_CLK>, 3791 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3792 <&mdss_dsi_phy 0>, 3793 <&mdss_dsi_phy 1>, 3794 <&dp_phy 0>, 3795 <&dp_phy 1>, 3796 <&mdss_edp_phy 0>, 3797 <&mdss_edp_phy 1>; 3798 clock-names = "bi_tcxo", 3799 "gcc_disp_gpll0_clk", 3800 "dsi0_phy_pll_out_byteclk", 3801 "dsi0_phy_pll_out_dsiclk", 3802 "dp_phy_pll_link_clk", 3803 "dp_phy_pll_vco_div_clk", 3804 "edp_phy_pll_link_clk", 3805 "edp_phy_pll_vco_div_clk"; 3806 #clock-cells = <1>; 3807 #reset-cells = <1>; 3808 #power-domain-cells = <1>; 3809 }; 3810 3811 mdss: display-subsystem@ae00000 { 3812 compatible = "qcom,sc7280-mdss"; 3813 reg = <0 0x0ae00000 0 0x1000>; 3814 reg-names = "mdss"; 3815 3816 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3817 3818 clocks = <&gcc GCC_DISP_AHB_CLK>, 3819 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3820 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3821 clock-names = "iface", 3822 "ahb", 3823 "core"; 3824 3825 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3826 interrupt-controller; 3827 #interrupt-cells = <1>; 3828 3829 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3830 interconnect-names = "mdp0-mem"; 3831 3832 iommus = <&apps_smmu 0x900 0x402>; 3833 3834 #address-cells = <2>; 3835 #size-cells = <2>; 3836 ranges; 3837 3838 status = "disabled"; 3839 3840 mdss_mdp: display-controller@ae01000 { 3841 compatible = "qcom,sc7280-dpu"; 3842 reg = <0 0x0ae01000 0 0x8f030>, 3843 <0 0x0aeb0000 0 0x2008>; 3844 reg-names = "mdp", "vbif"; 3845 3846 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3847 <&gcc GCC_DISP_SF_AXI_CLK>, 3848 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3849 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3850 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3851 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3852 clock-names = "bus", 3853 "nrt_bus", 3854 "iface", 3855 "lut", 3856 "core", 3857 "vsync"; 3858 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3859 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3860 assigned-clock-rates = <19200000>, 3861 <19200000>; 3862 operating-points-v2 = <&mdp_opp_table>; 3863 power-domains = <&rpmhpd SC7280_CX>; 3864 3865 interrupt-parent = <&mdss>; 3866 interrupts = <0>; 3867 3868 status = "disabled"; 3869 3870 ports { 3871 #address-cells = <1>; 3872 #size-cells = <0>; 3873 3874 port@0 { 3875 reg = <0>; 3876 dpu_intf1_out: endpoint { 3877 remote-endpoint = <&dsi0_in>; 3878 }; 3879 }; 3880 3881 port@1 { 3882 reg = <1>; 3883 dpu_intf5_out: endpoint { 3884 remote-endpoint = <&edp_in>; 3885 }; 3886 }; 3887 3888 port@2 { 3889 reg = <2>; 3890 dpu_intf0_out: endpoint { 3891 remote-endpoint = <&dp_in>; 3892 }; 3893 }; 3894 }; 3895 3896 mdp_opp_table: opp-table { 3897 compatible = "operating-points-v2"; 3898 3899 opp-200000000 { 3900 opp-hz = /bits/ 64 <200000000>; 3901 required-opps = <&rpmhpd_opp_low_svs>; 3902 }; 3903 3904 opp-300000000 { 3905 opp-hz = /bits/ 64 <300000000>; 3906 required-opps = <&rpmhpd_opp_svs>; 3907 }; 3908 3909 opp-380000000 { 3910 opp-hz = /bits/ 64 <380000000>; 3911 required-opps = <&rpmhpd_opp_svs_l1>; 3912 }; 3913 3914 opp-506666667 { 3915 opp-hz = /bits/ 64 <506666667>; 3916 required-opps = <&rpmhpd_opp_nom>; 3917 }; 3918 }; 3919 }; 3920 3921 mdss_dsi: dsi@ae94000 { 3922 compatible = "qcom,sc7280-dsi-ctrl", 3923 "qcom,mdss-dsi-ctrl"; 3924 reg = <0 0x0ae94000 0 0x400>; 3925 reg-names = "dsi_ctrl"; 3926 3927 interrupt-parent = <&mdss>; 3928 interrupts = <4>; 3929 3930 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3931 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3932 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3933 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3934 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3935 <&gcc GCC_DISP_HF_AXI_CLK>; 3936 clock-names = "byte", 3937 "byte_intf", 3938 "pixel", 3939 "core", 3940 "iface", 3941 "bus"; 3942 3943 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3944 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; 3945 3946 operating-points-v2 = <&dsi_opp_table>; 3947 power-domains = <&rpmhpd SC7280_CX>; 3948 3949 phys = <&mdss_dsi_phy>; 3950 3951 #address-cells = <1>; 3952 #size-cells = <0>; 3953 3954 status = "disabled"; 3955 3956 ports { 3957 #address-cells = <1>; 3958 #size-cells = <0>; 3959 3960 port@0 { 3961 reg = <0>; 3962 dsi0_in: endpoint { 3963 remote-endpoint = <&dpu_intf1_out>; 3964 }; 3965 }; 3966 3967 port@1 { 3968 reg = <1>; 3969 dsi0_out: endpoint { 3970 }; 3971 }; 3972 }; 3973 3974 dsi_opp_table: opp-table { 3975 compatible = "operating-points-v2"; 3976 3977 opp-187500000 { 3978 opp-hz = /bits/ 64 <187500000>; 3979 required-opps = <&rpmhpd_opp_low_svs>; 3980 }; 3981 3982 opp-300000000 { 3983 opp-hz = /bits/ 64 <300000000>; 3984 required-opps = <&rpmhpd_opp_svs>; 3985 }; 3986 3987 opp-358000000 { 3988 opp-hz = /bits/ 64 <358000000>; 3989 required-opps = <&rpmhpd_opp_svs_l1>; 3990 }; 3991 }; 3992 }; 3993 3994 mdss_dsi_phy: phy@ae94400 { 3995 compatible = "qcom,sc7280-dsi-phy-7nm"; 3996 reg = <0 0x0ae94400 0 0x200>, 3997 <0 0x0ae94600 0 0x280>, 3998 <0 0x0ae94900 0 0x280>; 3999 reg-names = "dsi_phy", 4000 "dsi_phy_lane", 4001 "dsi_pll"; 4002 4003 #clock-cells = <1>; 4004 #phy-cells = <0>; 4005 4006 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4007 <&rpmhcc RPMH_CXO_CLK>; 4008 clock-names = "iface", "ref"; 4009 4010 status = "disabled"; 4011 }; 4012 4013 mdss_edp: edp@aea0000 { 4014 compatible = "qcom,sc7280-edp"; 4015 pinctrl-names = "default"; 4016 pinctrl-0 = <&edp_hot_plug_det>; 4017 4018 reg = <0 0x0aea0000 0 0x200>, 4019 <0 0x0aea0200 0 0x200>, 4020 <0 0x0aea0400 0 0xc00>, 4021 <0 0x0aea1000 0 0x400>; 4022 4023 interrupt-parent = <&mdss>; 4024 interrupts = <14>; 4025 4026 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4027 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4028 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4029 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4030 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4031 clock-names = "core_iface", 4032 "core_aux", 4033 "ctrl_link", 4034 "ctrl_link_iface", 4035 "stream_pixel"; 4036 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4037 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4038 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4039 4040 phys = <&mdss_edp_phy>; 4041 phy-names = "dp"; 4042 4043 operating-points-v2 = <&edp_opp_table>; 4044 power-domains = <&rpmhpd SC7280_CX>; 4045 4046 status = "disabled"; 4047 4048 ports { 4049 #address-cells = <1>; 4050 #size-cells = <0>; 4051 4052 port@0 { 4053 reg = <0>; 4054 edp_in: endpoint { 4055 remote-endpoint = <&dpu_intf5_out>; 4056 }; 4057 }; 4058 4059 port@1 { 4060 reg = <1>; 4061 mdss_edp_out: endpoint { }; 4062 }; 4063 }; 4064 4065 edp_opp_table: opp-table { 4066 compatible = "operating-points-v2"; 4067 4068 opp-160000000 { 4069 opp-hz = /bits/ 64 <160000000>; 4070 required-opps = <&rpmhpd_opp_low_svs>; 4071 }; 4072 4073 opp-270000000 { 4074 opp-hz = /bits/ 64 <270000000>; 4075 required-opps = <&rpmhpd_opp_svs>; 4076 }; 4077 4078 opp-540000000 { 4079 opp-hz = /bits/ 64 <540000000>; 4080 required-opps = <&rpmhpd_opp_nom>; 4081 }; 4082 4083 opp-810000000 { 4084 opp-hz = /bits/ 64 <810000000>; 4085 required-opps = <&rpmhpd_opp_nom>; 4086 }; 4087 }; 4088 }; 4089 4090 mdss_edp_phy: phy@aec2a00 { 4091 compatible = "qcom,sc7280-edp-phy"; 4092 4093 reg = <0 0x0aec2a00 0 0x19c>, 4094 <0 0x0aec2200 0 0xa0>, 4095 <0 0x0aec2600 0 0xa0>, 4096 <0 0x0aec2000 0 0x1c0>; 4097 4098 clocks = <&rpmhcc RPMH_CXO_CLK>, 4099 <&gcc GCC_EDP_CLKREF_EN>; 4100 clock-names = "aux", 4101 "cfg_ahb"; 4102 4103 #clock-cells = <1>; 4104 #phy-cells = <0>; 4105 4106 status = "disabled"; 4107 }; 4108 4109 mdss_dp: displayport-controller@ae90000 { 4110 compatible = "qcom,sc7280-dp"; 4111 4112 reg = <0 0x0ae90000 0 0x200>, 4113 <0 0x0ae90200 0 0x200>, 4114 <0 0x0ae90400 0 0xc00>, 4115 <0 0x0ae91000 0 0x400>, 4116 <0 0x0ae91400 0 0x400>; 4117 4118 interrupt-parent = <&mdss>; 4119 interrupts = <12>; 4120 4121 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4122 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4123 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4124 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4125 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4126 clock-names = "core_iface", 4127 "core_aux", 4128 "ctrl_link", 4129 "ctrl_link_iface", 4130 "stream_pixel"; 4131 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4132 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4133 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4134 phys = <&dp_phy>; 4135 phy-names = "dp"; 4136 4137 operating-points-v2 = <&dp_opp_table>; 4138 power-domains = <&rpmhpd SC7280_CX>; 4139 4140 #sound-dai-cells = <0>; 4141 4142 status = "disabled"; 4143 4144 ports { 4145 #address-cells = <1>; 4146 #size-cells = <0>; 4147 4148 port@0 { 4149 reg = <0>; 4150 dp_in: endpoint { 4151 remote-endpoint = <&dpu_intf0_out>; 4152 }; 4153 }; 4154 4155 port@1 { 4156 reg = <1>; 4157 mdss_dp_out: endpoint { }; 4158 }; 4159 }; 4160 4161 dp_opp_table: opp-table { 4162 compatible = "operating-points-v2"; 4163 4164 opp-160000000 { 4165 opp-hz = /bits/ 64 <160000000>; 4166 required-opps = <&rpmhpd_opp_low_svs>; 4167 }; 4168 4169 opp-270000000 { 4170 opp-hz = /bits/ 64 <270000000>; 4171 required-opps = <&rpmhpd_opp_svs>; 4172 }; 4173 4174 opp-540000000 { 4175 opp-hz = /bits/ 64 <540000000>; 4176 required-opps = <&rpmhpd_opp_svs_l1>; 4177 }; 4178 4179 opp-810000000 { 4180 opp-hz = /bits/ 64 <810000000>; 4181 required-opps = <&rpmhpd_opp_nom>; 4182 }; 4183 }; 4184 }; 4185 }; 4186 4187 pdc: interrupt-controller@b220000 { 4188 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4189 reg = <0 0x0b220000 0 0x30000>; 4190 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4191 <55 306 4>, <59 312 3>, <62 374 2>, 4192 <64 434 2>, <66 438 3>, <69 86 1>, 4193 <70 520 54>, <124 609 31>, <155 63 1>, 4194 <156 716 12>; 4195 #interrupt-cells = <2>; 4196 interrupt-parent = <&intc>; 4197 interrupt-controller; 4198 }; 4199 4200 pdc_reset: reset-controller@b5e0000 { 4201 compatible = "qcom,sc7280-pdc-global"; 4202 reg = <0 0x0b5e0000 0 0x20000>; 4203 #reset-cells = <1>; 4204 }; 4205 4206 tsens0: thermal-sensor@c263000 { 4207 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4208 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4209 <0 0x0c222000 0 0x1ff>; /* SROT */ 4210 #qcom,sensors = <15>; 4211 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4212 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4213 interrupt-names = "uplow","critical"; 4214 #thermal-sensor-cells = <1>; 4215 }; 4216 4217 tsens1: thermal-sensor@c265000 { 4218 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4219 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4220 <0 0x0c223000 0 0x1ff>; /* SROT */ 4221 #qcom,sensors = <12>; 4222 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4223 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4224 interrupt-names = "uplow","critical"; 4225 #thermal-sensor-cells = <1>; 4226 }; 4227 4228 aoss_reset: reset-controller@c2a0000 { 4229 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4230 reg = <0 0x0c2a0000 0 0x31000>; 4231 #reset-cells = <1>; 4232 }; 4233 4234 aoss_qmp: power-management@c300000 { 4235 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4236 reg = <0 0x0c300000 0 0x400>; 4237 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4238 IPCC_MPROC_SIGNAL_GLINK_QMP 4239 IRQ_TYPE_EDGE_RISING>; 4240 mboxes = <&ipcc IPCC_CLIENT_AOP 4241 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4242 4243 #clock-cells = <0>; 4244 }; 4245 4246 sram@c3f0000 { 4247 compatible = "qcom,rpmh-stats"; 4248 reg = <0 0x0c3f0000 0 0x400>; 4249 }; 4250 4251 spmi_bus: spmi@c440000 { 4252 compatible = "qcom,spmi-pmic-arb"; 4253 reg = <0 0x0c440000 0 0x1100>, 4254 <0 0x0c600000 0 0x2000000>, 4255 <0 0x0e600000 0 0x100000>, 4256 <0 0x0e700000 0 0xa0000>, 4257 <0 0x0c40a000 0 0x26000>; 4258 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4259 interrupt-names = "periph_irq"; 4260 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4261 qcom,ee = <0>; 4262 qcom,channel = <0>; 4263 #address-cells = <2>; 4264 #size-cells = <0>; 4265 interrupt-controller; 4266 #interrupt-cells = <4>; 4267 }; 4268 4269 tlmm: pinctrl@f100000 { 4270 compatible = "qcom,sc7280-pinctrl"; 4271 reg = <0 0x0f100000 0 0x300000>; 4272 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4273 gpio-controller; 4274 #gpio-cells = <2>; 4275 interrupt-controller; 4276 #interrupt-cells = <2>; 4277 gpio-ranges = <&tlmm 0 0 175>; 4278 wakeup-parent = <&pdc>; 4279 4280 dp_hot_plug_det: dp-hot-plug-det-state { 4281 pins = "gpio47"; 4282 function = "dp_hot"; 4283 }; 4284 4285 edp_hot_plug_det: edp-hot-plug-det-state { 4286 pins = "gpio60"; 4287 function = "edp_hot"; 4288 }; 4289 4290 mi2s0_data0: mi2s0-data0-state { 4291 pins = "gpio98"; 4292 function = "mi2s0_data0"; 4293 }; 4294 4295 mi2s0_data1: mi2s0-data1-state { 4296 pins = "gpio99"; 4297 function = "mi2s0_data1"; 4298 }; 4299 4300 mi2s0_mclk: mi2s0-mclk-state { 4301 pins = "gpio96"; 4302 function = "pri_mi2s"; 4303 }; 4304 4305 mi2s0_sclk: mi2s0-sclk-state { 4306 pins = "gpio97"; 4307 function = "mi2s0_sck"; 4308 }; 4309 4310 mi2s0_ws: mi2s0-ws-state { 4311 pins = "gpio100"; 4312 function = "mi2s0_ws"; 4313 }; 4314 4315 mi2s1_data0: mi2s1-data0-state { 4316 pins = "gpio107"; 4317 function = "mi2s1_data0"; 4318 }; 4319 4320 mi2s1_sclk: mi2s1-sclk-state { 4321 pins = "gpio106"; 4322 function = "mi2s1_sck"; 4323 }; 4324 4325 mi2s1_ws: mi2s1-ws-state { 4326 pins = "gpio108"; 4327 function = "mi2s1_ws"; 4328 }; 4329 4330 pcie1_clkreq_n: pcie1-clkreq-n-state { 4331 pins = "gpio79"; 4332 function = "pcie1_clkreqn"; 4333 }; 4334 4335 qspi_clk: qspi-clk-state { 4336 pins = "gpio14"; 4337 function = "qspi_clk"; 4338 }; 4339 4340 qspi_cs0: qspi-cs0-state { 4341 pins = "gpio15"; 4342 function = "qspi_cs"; 4343 }; 4344 4345 qspi_cs1: qspi-cs1-state { 4346 pins = "gpio19"; 4347 function = "qspi_cs"; 4348 }; 4349 4350 qspi_data01: qspi-data01-state { 4351 pins = "gpio12", "gpio13"; 4352 function = "qspi_data"; 4353 }; 4354 4355 qspi_data12: qspi-data12-state { 4356 pins = "gpio16", "gpio17"; 4357 function = "qspi_data"; 4358 }; 4359 4360 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4361 pins = "gpio0", "gpio1"; 4362 function = "qup00"; 4363 }; 4364 4365 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4366 pins = "gpio4", "gpio5"; 4367 function = "qup01"; 4368 }; 4369 4370 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4371 pins = "gpio8", "gpio9"; 4372 function = "qup02"; 4373 }; 4374 4375 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4376 pins = "gpio12", "gpio13"; 4377 function = "qup03"; 4378 }; 4379 4380 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4381 pins = "gpio16", "gpio17"; 4382 function = "qup04"; 4383 }; 4384 4385 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4386 pins = "gpio20", "gpio21"; 4387 function = "qup05"; 4388 }; 4389 4390 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4391 pins = "gpio24", "gpio25"; 4392 function = "qup06"; 4393 }; 4394 4395 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4396 pins = "gpio28", "gpio29"; 4397 function = "qup07"; 4398 }; 4399 4400 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4401 pins = "gpio32", "gpio33"; 4402 function = "qup10"; 4403 }; 4404 4405 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4406 pins = "gpio36", "gpio37"; 4407 function = "qup11"; 4408 }; 4409 4410 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4411 pins = "gpio40", "gpio41"; 4412 function = "qup12"; 4413 }; 4414 4415 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4416 pins = "gpio44", "gpio45"; 4417 function = "qup13"; 4418 }; 4419 4420 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4421 pins = "gpio48", "gpio49"; 4422 function = "qup14"; 4423 }; 4424 4425 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4426 pins = "gpio52", "gpio53"; 4427 function = "qup15"; 4428 }; 4429 4430 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4431 pins = "gpio56", "gpio57"; 4432 function = "qup16"; 4433 }; 4434 4435 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4436 pins = "gpio60", "gpio61"; 4437 function = "qup17"; 4438 }; 4439 4440 qup_spi0_data_clk: qup-spi0-data-clk-state { 4441 pins = "gpio0", "gpio1", "gpio2"; 4442 function = "qup00"; 4443 }; 4444 4445 qup_spi0_cs: qup-spi0-cs-state { 4446 pins = "gpio3"; 4447 function = "qup00"; 4448 }; 4449 4450 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4451 pins = "gpio3"; 4452 function = "gpio"; 4453 }; 4454 4455 qup_spi1_data_clk: qup-spi1-data-clk-state { 4456 pins = "gpio4", "gpio5", "gpio6"; 4457 function = "qup01"; 4458 }; 4459 4460 qup_spi1_cs: qup-spi1-cs-state { 4461 pins = "gpio7"; 4462 function = "qup01"; 4463 }; 4464 4465 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4466 pins = "gpio7"; 4467 function = "gpio"; 4468 }; 4469 4470 qup_spi2_data_clk: qup-spi2-data-clk-state { 4471 pins = "gpio8", "gpio9", "gpio10"; 4472 function = "qup02"; 4473 }; 4474 4475 qup_spi2_cs: qup-spi2-cs-state { 4476 pins = "gpio11"; 4477 function = "qup02"; 4478 }; 4479 4480 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4481 pins = "gpio11"; 4482 function = "gpio"; 4483 }; 4484 4485 qup_spi3_data_clk: qup-spi3-data-clk-state { 4486 pins = "gpio12", "gpio13", "gpio14"; 4487 function = "qup03"; 4488 }; 4489 4490 qup_spi3_cs: qup-spi3-cs-state { 4491 pins = "gpio15"; 4492 function = "qup03"; 4493 }; 4494 4495 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4496 pins = "gpio15"; 4497 function = "gpio"; 4498 }; 4499 4500 qup_spi4_data_clk: qup-spi4-data-clk-state { 4501 pins = "gpio16", "gpio17", "gpio18"; 4502 function = "qup04"; 4503 }; 4504 4505 qup_spi4_cs: qup-spi4-cs-state { 4506 pins = "gpio19"; 4507 function = "qup04"; 4508 }; 4509 4510 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4511 pins = "gpio19"; 4512 function = "gpio"; 4513 }; 4514 4515 qup_spi5_data_clk: qup-spi5-data-clk-state { 4516 pins = "gpio20", "gpio21", "gpio22"; 4517 function = "qup05"; 4518 }; 4519 4520 qup_spi5_cs: qup-spi5-cs-state { 4521 pins = "gpio23"; 4522 function = "qup05"; 4523 }; 4524 4525 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4526 pins = "gpio23"; 4527 function = "gpio"; 4528 }; 4529 4530 qup_spi6_data_clk: qup-spi6-data-clk-state { 4531 pins = "gpio24", "gpio25", "gpio26"; 4532 function = "qup06"; 4533 }; 4534 4535 qup_spi6_cs: qup-spi6-cs-state { 4536 pins = "gpio27"; 4537 function = "qup06"; 4538 }; 4539 4540 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4541 pins = "gpio27"; 4542 function = "gpio"; 4543 }; 4544 4545 qup_spi7_data_clk: qup-spi7-data-clk-state { 4546 pins = "gpio28", "gpio29", "gpio30"; 4547 function = "qup07"; 4548 }; 4549 4550 qup_spi7_cs: qup-spi7-cs-state { 4551 pins = "gpio31"; 4552 function = "qup07"; 4553 }; 4554 4555 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4556 pins = "gpio31"; 4557 function = "gpio"; 4558 }; 4559 4560 qup_spi8_data_clk: qup-spi8-data-clk-state { 4561 pins = "gpio32", "gpio33", "gpio34"; 4562 function = "qup10"; 4563 }; 4564 4565 qup_spi8_cs: qup-spi8-cs-state { 4566 pins = "gpio35"; 4567 function = "qup10"; 4568 }; 4569 4570 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4571 pins = "gpio35"; 4572 function = "gpio"; 4573 }; 4574 4575 qup_spi9_data_clk: qup-spi9-data-clk-state { 4576 pins = "gpio36", "gpio37", "gpio38"; 4577 function = "qup11"; 4578 }; 4579 4580 qup_spi9_cs: qup-spi9-cs-state { 4581 pins = "gpio39"; 4582 function = "qup11"; 4583 }; 4584 4585 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4586 pins = "gpio39"; 4587 function = "gpio"; 4588 }; 4589 4590 qup_spi10_data_clk: qup-spi10-data-clk-state { 4591 pins = "gpio40", "gpio41", "gpio42"; 4592 function = "qup12"; 4593 }; 4594 4595 qup_spi10_cs: qup-spi10-cs-state { 4596 pins = "gpio43"; 4597 function = "qup12"; 4598 }; 4599 4600 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4601 pins = "gpio43"; 4602 function = "gpio"; 4603 }; 4604 4605 qup_spi11_data_clk: qup-spi11-data-clk-state { 4606 pins = "gpio44", "gpio45", "gpio46"; 4607 function = "qup13"; 4608 }; 4609 4610 qup_spi11_cs: qup-spi11-cs-state { 4611 pins = "gpio47"; 4612 function = "qup13"; 4613 }; 4614 4615 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 4616 pins = "gpio47"; 4617 function = "gpio"; 4618 }; 4619 4620 qup_spi12_data_clk: qup-spi12-data-clk-state { 4621 pins = "gpio48", "gpio49", "gpio50"; 4622 function = "qup14"; 4623 }; 4624 4625 qup_spi12_cs: qup-spi12-cs-state { 4626 pins = "gpio51"; 4627 function = "qup14"; 4628 }; 4629 4630 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4631 pins = "gpio51"; 4632 function = "gpio"; 4633 }; 4634 4635 qup_spi13_data_clk: qup-spi13-data-clk-state { 4636 pins = "gpio52", "gpio53", "gpio54"; 4637 function = "qup15"; 4638 }; 4639 4640 qup_spi13_cs: qup-spi13-cs-state { 4641 pins = "gpio55"; 4642 function = "qup15"; 4643 }; 4644 4645 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 4646 pins = "gpio55"; 4647 function = "gpio"; 4648 }; 4649 4650 qup_spi14_data_clk: qup-spi14-data-clk-state { 4651 pins = "gpio56", "gpio57", "gpio58"; 4652 function = "qup16"; 4653 }; 4654 4655 qup_spi14_cs: qup-spi14-cs-state { 4656 pins = "gpio59"; 4657 function = "qup16"; 4658 }; 4659 4660 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 4661 pins = "gpio59"; 4662 function = "gpio"; 4663 }; 4664 4665 qup_spi15_data_clk: qup-spi15-data-clk-state { 4666 pins = "gpio60", "gpio61", "gpio62"; 4667 function = "qup17"; 4668 }; 4669 4670 qup_spi15_cs: qup-spi15-cs-state { 4671 pins = "gpio63"; 4672 function = "qup17"; 4673 }; 4674 4675 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 4676 pins = "gpio63"; 4677 function = "gpio"; 4678 }; 4679 4680 qup_uart0_cts: qup-uart0-cts-state { 4681 pins = "gpio0"; 4682 function = "qup00"; 4683 }; 4684 4685 qup_uart0_rts: qup-uart0-rts-state { 4686 pins = "gpio1"; 4687 function = "qup00"; 4688 }; 4689 4690 qup_uart0_tx: qup-uart0-tx-state { 4691 pins = "gpio2"; 4692 function = "qup00"; 4693 }; 4694 4695 qup_uart0_rx: qup-uart0-rx-state { 4696 pins = "gpio3"; 4697 function = "qup00"; 4698 }; 4699 4700 qup_uart1_cts: qup-uart1-cts-state { 4701 pins = "gpio4"; 4702 function = "qup01"; 4703 }; 4704 4705 qup_uart1_rts: qup-uart1-rts-state { 4706 pins = "gpio5"; 4707 function = "qup01"; 4708 }; 4709 4710 qup_uart1_tx: qup-uart1-tx-state { 4711 pins = "gpio6"; 4712 function = "qup01"; 4713 }; 4714 4715 qup_uart1_rx: qup-uart1-rx-state { 4716 pins = "gpio7"; 4717 function = "qup01"; 4718 }; 4719 4720 qup_uart2_cts: qup-uart2-cts-state { 4721 pins = "gpio8"; 4722 function = "qup02"; 4723 }; 4724 4725 qup_uart2_rts: qup-uart2-rts-state { 4726 pins = "gpio9"; 4727 function = "qup02"; 4728 }; 4729 4730 qup_uart2_tx: qup-uart2-tx-state { 4731 pins = "gpio10"; 4732 function = "qup02"; 4733 }; 4734 4735 qup_uart2_rx: qup-uart2-rx-state { 4736 pins = "gpio11"; 4737 function = "qup02"; 4738 }; 4739 4740 qup_uart3_cts: qup-uart3-cts-state { 4741 pins = "gpio12"; 4742 function = "qup03"; 4743 }; 4744 4745 qup_uart3_rts: qup-uart3-rts-state { 4746 pins = "gpio13"; 4747 function = "qup03"; 4748 }; 4749 4750 qup_uart3_tx: qup-uart3-tx-state { 4751 pins = "gpio14"; 4752 function = "qup03"; 4753 }; 4754 4755 qup_uart3_rx: qup-uart3-rx-state { 4756 pins = "gpio15"; 4757 function = "qup03"; 4758 }; 4759 4760 qup_uart4_cts: qup-uart4-cts-state { 4761 pins = "gpio16"; 4762 function = "qup04"; 4763 }; 4764 4765 qup_uart4_rts: qup-uart4-rts-state { 4766 pins = "gpio17"; 4767 function = "qup04"; 4768 }; 4769 4770 qup_uart4_tx: qup-uart4-tx-state { 4771 pins = "gpio18"; 4772 function = "qup04"; 4773 }; 4774 4775 qup_uart4_rx: qup-uart4-rx-state { 4776 pins = "gpio19"; 4777 function = "qup04"; 4778 }; 4779 4780 qup_uart5_cts: qup-uart5-cts-state { 4781 pins = "gpio20"; 4782 function = "qup05"; 4783 }; 4784 4785 qup_uart5_rts: qup-uart5-rts-state { 4786 pins = "gpio21"; 4787 function = "qup05"; 4788 }; 4789 4790 qup_uart5_tx: qup-uart5-tx-state { 4791 pins = "gpio22"; 4792 function = "qup05"; 4793 }; 4794 4795 qup_uart5_rx: qup-uart5-rx-state { 4796 pins = "gpio23"; 4797 function = "qup05"; 4798 }; 4799 4800 qup_uart6_cts: qup-uart6-cts-state { 4801 pins = "gpio24"; 4802 function = "qup06"; 4803 }; 4804 4805 qup_uart6_rts: qup-uart6-rts-state { 4806 pins = "gpio25"; 4807 function = "qup06"; 4808 }; 4809 4810 qup_uart6_tx: qup-uart6-tx-state { 4811 pins = "gpio26"; 4812 function = "qup06"; 4813 }; 4814 4815 qup_uart6_rx: qup-uart6-rx-state { 4816 pins = "gpio27"; 4817 function = "qup06"; 4818 }; 4819 4820 qup_uart7_cts: qup-uart7-cts-state { 4821 pins = "gpio28"; 4822 function = "qup07"; 4823 }; 4824 4825 qup_uart7_rts: qup-uart7-rts-state { 4826 pins = "gpio29"; 4827 function = "qup07"; 4828 }; 4829 4830 qup_uart7_tx: qup-uart7-tx-state { 4831 pins = "gpio30"; 4832 function = "qup07"; 4833 }; 4834 4835 qup_uart7_rx: qup-uart7-rx-state { 4836 pins = "gpio31"; 4837 function = "qup07"; 4838 }; 4839 4840 qup_uart8_cts: qup-uart8-cts-state { 4841 pins = "gpio32"; 4842 function = "qup10"; 4843 }; 4844 4845 qup_uart8_rts: qup-uart8-rts-state { 4846 pins = "gpio33"; 4847 function = "qup10"; 4848 }; 4849 4850 qup_uart8_tx: qup-uart8-tx-state { 4851 pins = "gpio34"; 4852 function = "qup10"; 4853 }; 4854 4855 qup_uart8_rx: qup-uart8-rx-state { 4856 pins = "gpio35"; 4857 function = "qup10"; 4858 }; 4859 4860 qup_uart9_cts: qup-uart9-cts-state { 4861 pins = "gpio36"; 4862 function = "qup11"; 4863 }; 4864 4865 qup_uart9_rts: qup-uart9-rts-state { 4866 pins = "gpio37"; 4867 function = "qup11"; 4868 }; 4869 4870 qup_uart9_tx: qup-uart9-tx-state { 4871 pins = "gpio38"; 4872 function = "qup11"; 4873 }; 4874 4875 qup_uart9_rx: qup-uart9-rx-state { 4876 pins = "gpio39"; 4877 function = "qup11"; 4878 }; 4879 4880 qup_uart10_cts: qup-uart10-cts-state { 4881 pins = "gpio40"; 4882 function = "qup12"; 4883 }; 4884 4885 qup_uart10_rts: qup-uart10-rts-state { 4886 pins = "gpio41"; 4887 function = "qup12"; 4888 }; 4889 4890 qup_uart10_tx: qup-uart10-tx-state { 4891 pins = "gpio42"; 4892 function = "qup12"; 4893 }; 4894 4895 qup_uart10_rx: qup-uart10-rx-state { 4896 pins = "gpio43"; 4897 function = "qup12"; 4898 }; 4899 4900 qup_uart11_cts: qup-uart11-cts-state { 4901 pins = "gpio44"; 4902 function = "qup13"; 4903 }; 4904 4905 qup_uart11_rts: qup-uart11-rts-state { 4906 pins = "gpio45"; 4907 function = "qup13"; 4908 }; 4909 4910 qup_uart11_tx: qup-uart11-tx-state { 4911 pins = "gpio46"; 4912 function = "qup13"; 4913 }; 4914 4915 qup_uart11_rx: qup-uart11-rx-state { 4916 pins = "gpio47"; 4917 function = "qup13"; 4918 }; 4919 4920 qup_uart12_cts: qup-uart12-cts-state { 4921 pins = "gpio48"; 4922 function = "qup14"; 4923 }; 4924 4925 qup_uart12_rts: qup-uart12-rts-state { 4926 pins = "gpio49"; 4927 function = "qup14"; 4928 }; 4929 4930 qup_uart12_tx: qup-uart12-tx-state { 4931 pins = "gpio50"; 4932 function = "qup14"; 4933 }; 4934 4935 qup_uart12_rx: qup-uart12-rx-state { 4936 pins = "gpio51"; 4937 function = "qup14"; 4938 }; 4939 4940 qup_uart13_cts: qup-uart13-cts-state { 4941 pins = "gpio52"; 4942 function = "qup15"; 4943 }; 4944 4945 qup_uart13_rts: qup-uart13-rts-state { 4946 pins = "gpio53"; 4947 function = "qup15"; 4948 }; 4949 4950 qup_uart13_tx: qup-uart13-tx-state { 4951 pins = "gpio54"; 4952 function = "qup15"; 4953 }; 4954 4955 qup_uart13_rx: qup-uart13-rx-state { 4956 pins = "gpio55"; 4957 function = "qup15"; 4958 }; 4959 4960 qup_uart14_cts: qup-uart14-cts-state { 4961 pins = "gpio56"; 4962 function = "qup16"; 4963 }; 4964 4965 qup_uart14_rts: qup-uart14-rts-state { 4966 pins = "gpio57"; 4967 function = "qup16"; 4968 }; 4969 4970 qup_uart14_tx: qup-uart14-tx-state { 4971 pins = "gpio58"; 4972 function = "qup16"; 4973 }; 4974 4975 qup_uart14_rx: qup-uart14-rx-state { 4976 pins = "gpio59"; 4977 function = "qup16"; 4978 }; 4979 4980 qup_uart15_cts: qup-uart15-cts-state { 4981 pins = "gpio60"; 4982 function = "qup17"; 4983 }; 4984 4985 qup_uart15_rts: qup-uart15-rts-state { 4986 pins = "gpio61"; 4987 function = "qup17"; 4988 }; 4989 4990 qup_uart15_tx: qup-uart15-tx-state { 4991 pins = "gpio62"; 4992 function = "qup17"; 4993 }; 4994 4995 qup_uart15_rx: qup-uart15-rx-state { 4996 pins = "gpio63"; 4997 function = "qup17"; 4998 }; 4999 5000 sdc1_clk: sdc1-clk-state { 5001 pins = "sdc1_clk"; 5002 }; 5003 5004 sdc1_cmd: sdc1-cmd-state { 5005 pins = "sdc1_cmd"; 5006 }; 5007 5008 sdc1_data: sdc1-data-state { 5009 pins = "sdc1_data"; 5010 }; 5011 5012 sdc1_rclk: sdc1-rclk-state { 5013 pins = "sdc1_rclk"; 5014 }; 5015 5016 sdc1_clk_sleep: sdc1-clk-sleep-state { 5017 pins = "sdc1_clk"; 5018 drive-strength = <2>; 5019 bias-bus-hold; 5020 }; 5021 5022 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5023 pins = "sdc1_cmd"; 5024 drive-strength = <2>; 5025 bias-bus-hold; 5026 }; 5027 5028 sdc1_data_sleep: sdc1-data-sleep-state { 5029 pins = "sdc1_data"; 5030 drive-strength = <2>; 5031 bias-bus-hold; 5032 }; 5033 5034 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5035 pins = "sdc1_rclk"; 5036 drive-strength = <2>; 5037 bias-bus-hold; 5038 }; 5039 5040 sdc2_clk: sdc2-clk-state { 5041 pins = "sdc2_clk"; 5042 }; 5043 5044 sdc2_cmd: sdc2-cmd-state { 5045 pins = "sdc2_cmd"; 5046 }; 5047 5048 sdc2_data: sdc2-data-state { 5049 pins = "sdc2_data"; 5050 }; 5051 5052 sdc2_clk_sleep: sdc2-clk-sleep-state { 5053 pins = "sdc2_clk"; 5054 drive-strength = <2>; 5055 bias-bus-hold; 5056 }; 5057 5058 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 5059 pins = "sdc2_cmd"; 5060 drive-strength = <2>; 5061 bias-bus-hold; 5062 }; 5063 5064 sdc2_data_sleep: sdc2-data-sleep-state { 5065 pins = "sdc2_data"; 5066 drive-strength = <2>; 5067 bias-bus-hold; 5068 }; 5069 }; 5070 5071 sram@146a5000 { 5072 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5073 reg = <0 0x146a5000 0 0x6000>; 5074 5075 #address-cells = <1>; 5076 #size-cells = <1>; 5077 5078 ranges = <0 0 0x146a5000 0x6000>; 5079 5080 pil-reloc@594c { 5081 compatible = "qcom,pil-reloc-info"; 5082 reg = <0x594c 0xc8>; 5083 }; 5084 }; 5085 5086 apps_smmu: iommu@15000000 { 5087 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5088 reg = <0 0x15000000 0 0x100000>; 5089 #iommu-cells = <2>; 5090 #global-interrupts = <1>; 5091 dma-coherent; 5092 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5093 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5094 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5095 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5096 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5097 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5098 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5099 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5100 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5101 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5102 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5103 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5104 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5169 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5170 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5171 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5172 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5173 }; 5174 5175 intc: interrupt-controller@17a00000 { 5176 compatible = "arm,gic-v3"; 5177 #address-cells = <2>; 5178 #size-cells = <2>; 5179 ranges; 5180 #interrupt-cells = <3>; 5181 interrupt-controller; 5182 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5183 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5184 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5185 5186 gic-its@17a40000 { 5187 compatible = "arm,gic-v3-its"; 5188 msi-controller; 5189 #msi-cells = <1>; 5190 reg = <0 0x17a40000 0 0x20000>; 5191 status = "disabled"; 5192 }; 5193 }; 5194 5195 watchdog@17c10000 { 5196 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5197 reg = <0 0x17c10000 0 0x1000>; 5198 clocks = <&sleep_clk>; 5199 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5200 }; 5201 5202 timer@17c20000 { 5203 #address-cells = <1>; 5204 #size-cells = <1>; 5205 ranges = <0 0 0 0x20000000>; 5206 compatible = "arm,armv7-timer-mem"; 5207 reg = <0 0x17c20000 0 0x1000>; 5208 5209 frame@17c21000 { 5210 frame-number = <0>; 5211 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5212 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5213 reg = <0x17c21000 0x1000>, 5214 <0x17c22000 0x1000>; 5215 }; 5216 5217 frame@17c23000 { 5218 frame-number = <1>; 5219 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5220 reg = <0x17c23000 0x1000>; 5221 status = "disabled"; 5222 }; 5223 5224 frame@17c25000 { 5225 frame-number = <2>; 5226 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5227 reg = <0x17c25000 0x1000>; 5228 status = "disabled"; 5229 }; 5230 5231 frame@17c27000 { 5232 frame-number = <3>; 5233 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5234 reg = <0x17c27000 0x1000>; 5235 status = "disabled"; 5236 }; 5237 5238 frame@17c29000 { 5239 frame-number = <4>; 5240 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5241 reg = <0x17c29000 0x1000>; 5242 status = "disabled"; 5243 }; 5244 5245 frame@17c2b000 { 5246 frame-number = <5>; 5247 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5248 reg = <0x17c2b000 0x1000>; 5249 status = "disabled"; 5250 }; 5251 5252 frame@17c2d000 { 5253 frame-number = <6>; 5254 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5255 reg = <0x17c2d000 0x1000>; 5256 status = "disabled"; 5257 }; 5258 }; 5259 5260 apps_rsc: rsc@18200000 { 5261 compatible = "qcom,rpmh-rsc"; 5262 reg = <0 0x18200000 0 0x10000>, 5263 <0 0x18210000 0 0x10000>, 5264 <0 0x18220000 0 0x10000>; 5265 reg-names = "drv-0", "drv-1", "drv-2"; 5266 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5267 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5268 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5269 qcom,tcs-offset = <0xd00>; 5270 qcom,drv-id = <2>; 5271 qcom,tcs-config = <ACTIVE_TCS 2>, 5272 <SLEEP_TCS 3>, 5273 <WAKE_TCS 3>, 5274 <CONTROL_TCS 1>; 5275 5276 apps_bcm_voter: bcm-voter { 5277 compatible = "qcom,bcm-voter"; 5278 }; 5279 5280 rpmhpd: power-controller { 5281 compatible = "qcom,sc7280-rpmhpd"; 5282 #power-domain-cells = <1>; 5283 operating-points-v2 = <&rpmhpd_opp_table>; 5284 5285 rpmhpd_opp_table: opp-table { 5286 compatible = "operating-points-v2"; 5287 5288 rpmhpd_opp_ret: opp1 { 5289 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5290 }; 5291 5292 rpmhpd_opp_low_svs: opp2 { 5293 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5294 }; 5295 5296 rpmhpd_opp_svs: opp3 { 5297 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5298 }; 5299 5300 rpmhpd_opp_svs_l1: opp4 { 5301 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5302 }; 5303 5304 rpmhpd_opp_svs_l2: opp5 { 5305 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5306 }; 5307 5308 rpmhpd_opp_nom: opp6 { 5309 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5310 }; 5311 5312 rpmhpd_opp_nom_l1: opp7 { 5313 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5314 }; 5315 5316 rpmhpd_opp_turbo: opp8 { 5317 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5318 }; 5319 5320 rpmhpd_opp_turbo_l1: opp9 { 5321 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5322 }; 5323 }; 5324 }; 5325 5326 rpmhcc: clock-controller { 5327 compatible = "qcom,sc7280-rpmh-clk"; 5328 clocks = <&xo_board>; 5329 clock-names = "xo"; 5330 #clock-cells = <1>; 5331 }; 5332 }; 5333 5334 epss_l3: interconnect@18590000 { 5335 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 5336 reg = <0 0x18590000 0 0x1000>; 5337 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5338 clock-names = "xo", "alternate"; 5339 #interconnect-cells = <1>; 5340 }; 5341 5342 cpufreq_hw: cpufreq@18591000 { 5343 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 5344 reg = <0 0x18591000 0 0x1000>, 5345 <0 0x18592000 0 0x1000>, 5346 <0 0x18593000 0 0x1000>; 5347 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5348 clock-names = "xo", "alternate"; 5349 #freq-domain-cells = <1>; 5350 #clock-cells = <1>; 5351 }; 5352 }; 5353 5354 thermal_zones: thermal-zones { 5355 cpu0-thermal { 5356 polling-delay-passive = <250>; 5357 polling-delay = <0>; 5358 5359 thermal-sensors = <&tsens0 1>; 5360 5361 trips { 5362 cpu0_alert0: trip-point0 { 5363 temperature = <90000>; 5364 hysteresis = <2000>; 5365 type = "passive"; 5366 }; 5367 5368 cpu0_alert1: trip-point1 { 5369 temperature = <95000>; 5370 hysteresis = <2000>; 5371 type = "passive"; 5372 }; 5373 5374 cpu0_crit: cpu-crit { 5375 temperature = <110000>; 5376 hysteresis = <0>; 5377 type = "critical"; 5378 }; 5379 }; 5380 5381 cooling-maps { 5382 map0 { 5383 trip = <&cpu0_alert0>; 5384 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5385 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5386 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5387 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5388 }; 5389 map1 { 5390 trip = <&cpu0_alert1>; 5391 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5392 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5393 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5394 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5395 }; 5396 }; 5397 }; 5398 5399 cpu1-thermal { 5400 polling-delay-passive = <250>; 5401 polling-delay = <0>; 5402 5403 thermal-sensors = <&tsens0 2>; 5404 5405 trips { 5406 cpu1_alert0: trip-point0 { 5407 temperature = <90000>; 5408 hysteresis = <2000>; 5409 type = "passive"; 5410 }; 5411 5412 cpu1_alert1: trip-point1 { 5413 temperature = <95000>; 5414 hysteresis = <2000>; 5415 type = "passive"; 5416 }; 5417 5418 cpu1_crit: cpu-crit { 5419 temperature = <110000>; 5420 hysteresis = <0>; 5421 type = "critical"; 5422 }; 5423 }; 5424 5425 cooling-maps { 5426 map0 { 5427 trip = <&cpu1_alert0>; 5428 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5429 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5430 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5431 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5432 }; 5433 map1 { 5434 trip = <&cpu1_alert1>; 5435 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5436 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5437 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5438 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5439 }; 5440 }; 5441 }; 5442 5443 cpu2-thermal { 5444 polling-delay-passive = <250>; 5445 polling-delay = <0>; 5446 5447 thermal-sensors = <&tsens0 3>; 5448 5449 trips { 5450 cpu2_alert0: trip-point0 { 5451 temperature = <90000>; 5452 hysteresis = <2000>; 5453 type = "passive"; 5454 }; 5455 5456 cpu2_alert1: trip-point1 { 5457 temperature = <95000>; 5458 hysteresis = <2000>; 5459 type = "passive"; 5460 }; 5461 5462 cpu2_crit: cpu-crit { 5463 temperature = <110000>; 5464 hysteresis = <0>; 5465 type = "critical"; 5466 }; 5467 }; 5468 5469 cooling-maps { 5470 map0 { 5471 trip = <&cpu2_alert0>; 5472 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5473 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5474 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5475 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5476 }; 5477 map1 { 5478 trip = <&cpu2_alert1>; 5479 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5480 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5481 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5482 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5483 }; 5484 }; 5485 }; 5486 5487 cpu3-thermal { 5488 polling-delay-passive = <250>; 5489 polling-delay = <0>; 5490 5491 thermal-sensors = <&tsens0 4>; 5492 5493 trips { 5494 cpu3_alert0: trip-point0 { 5495 temperature = <90000>; 5496 hysteresis = <2000>; 5497 type = "passive"; 5498 }; 5499 5500 cpu3_alert1: trip-point1 { 5501 temperature = <95000>; 5502 hysteresis = <2000>; 5503 type = "passive"; 5504 }; 5505 5506 cpu3_crit: cpu-crit { 5507 temperature = <110000>; 5508 hysteresis = <0>; 5509 type = "critical"; 5510 }; 5511 }; 5512 5513 cooling-maps { 5514 map0 { 5515 trip = <&cpu3_alert0>; 5516 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5517 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5518 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5519 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5520 }; 5521 map1 { 5522 trip = <&cpu3_alert1>; 5523 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5524 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5525 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5526 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5527 }; 5528 }; 5529 }; 5530 5531 cpu4-thermal { 5532 polling-delay-passive = <250>; 5533 polling-delay = <0>; 5534 5535 thermal-sensors = <&tsens0 7>; 5536 5537 trips { 5538 cpu4_alert0: trip-point0 { 5539 temperature = <90000>; 5540 hysteresis = <2000>; 5541 type = "passive"; 5542 }; 5543 5544 cpu4_alert1: trip-point1 { 5545 temperature = <95000>; 5546 hysteresis = <2000>; 5547 type = "passive"; 5548 }; 5549 5550 cpu4_crit: cpu-crit { 5551 temperature = <110000>; 5552 hysteresis = <0>; 5553 type = "critical"; 5554 }; 5555 }; 5556 5557 cooling-maps { 5558 map0 { 5559 trip = <&cpu4_alert0>; 5560 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5561 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5562 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5563 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5564 }; 5565 map1 { 5566 trip = <&cpu4_alert1>; 5567 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5568 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5569 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5570 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5571 }; 5572 }; 5573 }; 5574 5575 cpu5-thermal { 5576 polling-delay-passive = <250>; 5577 polling-delay = <0>; 5578 5579 thermal-sensors = <&tsens0 8>; 5580 5581 trips { 5582 cpu5_alert0: trip-point0 { 5583 temperature = <90000>; 5584 hysteresis = <2000>; 5585 type = "passive"; 5586 }; 5587 5588 cpu5_alert1: trip-point1 { 5589 temperature = <95000>; 5590 hysteresis = <2000>; 5591 type = "passive"; 5592 }; 5593 5594 cpu5_crit: cpu-crit { 5595 temperature = <110000>; 5596 hysteresis = <0>; 5597 type = "critical"; 5598 }; 5599 }; 5600 5601 cooling-maps { 5602 map0 { 5603 trip = <&cpu5_alert0>; 5604 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5605 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5606 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5607 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5608 }; 5609 map1 { 5610 trip = <&cpu5_alert1>; 5611 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5612 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5613 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5614 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5615 }; 5616 }; 5617 }; 5618 5619 cpu6-thermal { 5620 polling-delay-passive = <250>; 5621 polling-delay = <0>; 5622 5623 thermal-sensors = <&tsens0 9>; 5624 5625 trips { 5626 cpu6_alert0: trip-point0 { 5627 temperature = <90000>; 5628 hysteresis = <2000>; 5629 type = "passive"; 5630 }; 5631 5632 cpu6_alert1: trip-point1 { 5633 temperature = <95000>; 5634 hysteresis = <2000>; 5635 type = "passive"; 5636 }; 5637 5638 cpu6_crit: cpu-crit { 5639 temperature = <110000>; 5640 hysteresis = <0>; 5641 type = "critical"; 5642 }; 5643 }; 5644 5645 cooling-maps { 5646 map0 { 5647 trip = <&cpu6_alert0>; 5648 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5649 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5650 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5651 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5652 }; 5653 map1 { 5654 trip = <&cpu6_alert1>; 5655 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5656 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5657 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5658 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5659 }; 5660 }; 5661 }; 5662 5663 cpu7-thermal { 5664 polling-delay-passive = <250>; 5665 polling-delay = <0>; 5666 5667 thermal-sensors = <&tsens0 10>; 5668 5669 trips { 5670 cpu7_alert0: trip-point0 { 5671 temperature = <90000>; 5672 hysteresis = <2000>; 5673 type = "passive"; 5674 }; 5675 5676 cpu7_alert1: trip-point1 { 5677 temperature = <95000>; 5678 hysteresis = <2000>; 5679 type = "passive"; 5680 }; 5681 5682 cpu7_crit: cpu-crit { 5683 temperature = <110000>; 5684 hysteresis = <0>; 5685 type = "critical"; 5686 }; 5687 }; 5688 5689 cooling-maps { 5690 map0 { 5691 trip = <&cpu7_alert0>; 5692 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5693 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5694 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5695 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5696 }; 5697 map1 { 5698 trip = <&cpu7_alert1>; 5699 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5700 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5701 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5702 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5703 }; 5704 }; 5705 }; 5706 5707 cpu8-thermal { 5708 polling-delay-passive = <250>; 5709 polling-delay = <0>; 5710 5711 thermal-sensors = <&tsens0 11>; 5712 5713 trips { 5714 cpu8_alert0: trip-point0 { 5715 temperature = <90000>; 5716 hysteresis = <2000>; 5717 type = "passive"; 5718 }; 5719 5720 cpu8_alert1: trip-point1 { 5721 temperature = <95000>; 5722 hysteresis = <2000>; 5723 type = "passive"; 5724 }; 5725 5726 cpu8_crit: cpu-crit { 5727 temperature = <110000>; 5728 hysteresis = <0>; 5729 type = "critical"; 5730 }; 5731 }; 5732 5733 cooling-maps { 5734 map0 { 5735 trip = <&cpu8_alert0>; 5736 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5737 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5738 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5739 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5740 }; 5741 map1 { 5742 trip = <&cpu8_alert1>; 5743 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5744 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5745 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5746 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5747 }; 5748 }; 5749 }; 5750 5751 cpu9-thermal { 5752 polling-delay-passive = <250>; 5753 polling-delay = <0>; 5754 5755 thermal-sensors = <&tsens0 12>; 5756 5757 trips { 5758 cpu9_alert0: trip-point0 { 5759 temperature = <90000>; 5760 hysteresis = <2000>; 5761 type = "passive"; 5762 }; 5763 5764 cpu9_alert1: trip-point1 { 5765 temperature = <95000>; 5766 hysteresis = <2000>; 5767 type = "passive"; 5768 }; 5769 5770 cpu9_crit: cpu-crit { 5771 temperature = <110000>; 5772 hysteresis = <0>; 5773 type = "critical"; 5774 }; 5775 }; 5776 5777 cooling-maps { 5778 map0 { 5779 trip = <&cpu9_alert0>; 5780 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5781 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5782 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5783 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5784 }; 5785 map1 { 5786 trip = <&cpu9_alert1>; 5787 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5788 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5789 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5790 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5791 }; 5792 }; 5793 }; 5794 5795 cpu10-thermal { 5796 polling-delay-passive = <250>; 5797 polling-delay = <0>; 5798 5799 thermal-sensors = <&tsens0 13>; 5800 5801 trips { 5802 cpu10_alert0: trip-point0 { 5803 temperature = <90000>; 5804 hysteresis = <2000>; 5805 type = "passive"; 5806 }; 5807 5808 cpu10_alert1: trip-point1 { 5809 temperature = <95000>; 5810 hysteresis = <2000>; 5811 type = "passive"; 5812 }; 5813 5814 cpu10_crit: cpu-crit { 5815 temperature = <110000>; 5816 hysteresis = <0>; 5817 type = "critical"; 5818 }; 5819 }; 5820 5821 cooling-maps { 5822 map0 { 5823 trip = <&cpu10_alert0>; 5824 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5825 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5826 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5827 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5828 }; 5829 map1 { 5830 trip = <&cpu10_alert1>; 5831 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5832 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5833 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5834 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5835 }; 5836 }; 5837 }; 5838 5839 cpu11-thermal { 5840 polling-delay-passive = <250>; 5841 polling-delay = <0>; 5842 5843 thermal-sensors = <&tsens0 14>; 5844 5845 trips { 5846 cpu11_alert0: trip-point0 { 5847 temperature = <90000>; 5848 hysteresis = <2000>; 5849 type = "passive"; 5850 }; 5851 5852 cpu11_alert1: trip-point1 { 5853 temperature = <95000>; 5854 hysteresis = <2000>; 5855 type = "passive"; 5856 }; 5857 5858 cpu11_crit: cpu-crit { 5859 temperature = <110000>; 5860 hysteresis = <0>; 5861 type = "critical"; 5862 }; 5863 }; 5864 5865 cooling-maps { 5866 map0 { 5867 trip = <&cpu11_alert0>; 5868 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5869 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5870 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5871 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5872 }; 5873 map1 { 5874 trip = <&cpu11_alert1>; 5875 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5876 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5877 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5878 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5879 }; 5880 }; 5881 }; 5882 5883 aoss0-thermal { 5884 polling-delay-passive = <0>; 5885 polling-delay = <0>; 5886 5887 thermal-sensors = <&tsens0 0>; 5888 5889 trips { 5890 aoss0_alert0: trip-point0 { 5891 temperature = <90000>; 5892 hysteresis = <2000>; 5893 type = "hot"; 5894 }; 5895 5896 aoss0_crit: aoss0-crit { 5897 temperature = <110000>; 5898 hysteresis = <0>; 5899 type = "critical"; 5900 }; 5901 }; 5902 }; 5903 5904 aoss1-thermal { 5905 polling-delay-passive = <0>; 5906 polling-delay = <0>; 5907 5908 thermal-sensors = <&tsens1 0>; 5909 5910 trips { 5911 aoss1_alert0: trip-point0 { 5912 temperature = <90000>; 5913 hysteresis = <2000>; 5914 type = "hot"; 5915 }; 5916 5917 aoss1_crit: aoss1-crit { 5918 temperature = <110000>; 5919 hysteresis = <0>; 5920 type = "critical"; 5921 }; 5922 }; 5923 }; 5924 5925 cpuss0-thermal { 5926 polling-delay-passive = <0>; 5927 polling-delay = <0>; 5928 5929 thermal-sensors = <&tsens0 5>; 5930 5931 trips { 5932 cpuss0_alert0: trip-point0 { 5933 temperature = <90000>; 5934 hysteresis = <2000>; 5935 type = "hot"; 5936 }; 5937 cpuss0_crit: cluster0-crit { 5938 temperature = <110000>; 5939 hysteresis = <0>; 5940 type = "critical"; 5941 }; 5942 }; 5943 }; 5944 5945 cpuss1-thermal { 5946 polling-delay-passive = <0>; 5947 polling-delay = <0>; 5948 5949 thermal-sensors = <&tsens0 6>; 5950 5951 trips { 5952 cpuss1_alert0: trip-point0 { 5953 temperature = <90000>; 5954 hysteresis = <2000>; 5955 type = "hot"; 5956 }; 5957 cpuss1_crit: cluster0-crit { 5958 temperature = <110000>; 5959 hysteresis = <0>; 5960 type = "critical"; 5961 }; 5962 }; 5963 }; 5964 5965 gpuss0-thermal { 5966 polling-delay-passive = <100>; 5967 polling-delay = <0>; 5968 5969 thermal-sensors = <&tsens1 1>; 5970 5971 trips { 5972 gpuss0_alert0: trip-point0 { 5973 temperature = <95000>; 5974 hysteresis = <2000>; 5975 type = "passive"; 5976 }; 5977 5978 gpuss0_crit: gpuss0-crit { 5979 temperature = <110000>; 5980 hysteresis = <0>; 5981 type = "critical"; 5982 }; 5983 }; 5984 5985 cooling-maps { 5986 map0 { 5987 trip = <&gpuss0_alert0>; 5988 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5989 }; 5990 }; 5991 }; 5992 5993 gpuss1-thermal { 5994 polling-delay-passive = <100>; 5995 polling-delay = <0>; 5996 5997 thermal-sensors = <&tsens1 2>; 5998 5999 trips { 6000 gpuss1_alert0: trip-point0 { 6001 temperature = <95000>; 6002 hysteresis = <2000>; 6003 type = "passive"; 6004 }; 6005 6006 gpuss1_crit: gpuss1-crit { 6007 temperature = <110000>; 6008 hysteresis = <0>; 6009 type = "critical"; 6010 }; 6011 }; 6012 6013 cooling-maps { 6014 map0 { 6015 trip = <&gpuss1_alert0>; 6016 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6017 }; 6018 }; 6019 }; 6020 6021 nspss0-thermal { 6022 polling-delay-passive = <0>; 6023 polling-delay = <0>; 6024 6025 thermal-sensors = <&tsens1 3>; 6026 6027 trips { 6028 nspss0_alert0: trip-point0 { 6029 temperature = <90000>; 6030 hysteresis = <2000>; 6031 type = "hot"; 6032 }; 6033 6034 nspss0_crit: nspss0-crit { 6035 temperature = <110000>; 6036 hysteresis = <0>; 6037 type = "critical"; 6038 }; 6039 }; 6040 }; 6041 6042 nspss1-thermal { 6043 polling-delay-passive = <0>; 6044 polling-delay = <0>; 6045 6046 thermal-sensors = <&tsens1 4>; 6047 6048 trips { 6049 nspss1_alert0: trip-point0 { 6050 temperature = <90000>; 6051 hysteresis = <2000>; 6052 type = "hot"; 6053 }; 6054 6055 nspss1_crit: nspss1-crit { 6056 temperature = <110000>; 6057 hysteresis = <0>; 6058 type = "critical"; 6059 }; 6060 }; 6061 }; 6062 6063 video-thermal { 6064 polling-delay-passive = <0>; 6065 polling-delay = <0>; 6066 6067 thermal-sensors = <&tsens1 5>; 6068 6069 trips { 6070 video_alert0: trip-point0 { 6071 temperature = <90000>; 6072 hysteresis = <2000>; 6073 type = "hot"; 6074 }; 6075 6076 video_crit: video-crit { 6077 temperature = <110000>; 6078 hysteresis = <0>; 6079 type = "critical"; 6080 }; 6081 }; 6082 }; 6083 6084 ddr-thermal { 6085 polling-delay-passive = <0>; 6086 polling-delay = <0>; 6087 6088 thermal-sensors = <&tsens1 6>; 6089 6090 trips { 6091 ddr_alert0: trip-point0 { 6092 temperature = <90000>; 6093 hysteresis = <2000>; 6094 type = "hot"; 6095 }; 6096 6097 ddr_crit: ddr-crit { 6098 temperature = <110000>; 6099 hysteresis = <0>; 6100 type = "critical"; 6101 }; 6102 }; 6103 }; 6104 6105 mdmss0-thermal { 6106 polling-delay-passive = <0>; 6107 polling-delay = <0>; 6108 6109 thermal-sensors = <&tsens1 7>; 6110 6111 trips { 6112 mdmss0_alert0: trip-point0 { 6113 temperature = <90000>; 6114 hysteresis = <2000>; 6115 type = "hot"; 6116 }; 6117 6118 mdmss0_crit: mdmss0-crit { 6119 temperature = <110000>; 6120 hysteresis = <0>; 6121 type = "critical"; 6122 }; 6123 }; 6124 }; 6125 6126 mdmss1-thermal { 6127 polling-delay-passive = <0>; 6128 polling-delay = <0>; 6129 6130 thermal-sensors = <&tsens1 8>; 6131 6132 trips { 6133 mdmss1_alert0: trip-point0 { 6134 temperature = <90000>; 6135 hysteresis = <2000>; 6136 type = "hot"; 6137 }; 6138 6139 mdmss1_crit: mdmss1-crit { 6140 temperature = <110000>; 6141 hysteresis = <0>; 6142 type = "critical"; 6143 }; 6144 }; 6145 }; 6146 6147 mdmss2-thermal { 6148 polling-delay-passive = <0>; 6149 polling-delay = <0>; 6150 6151 thermal-sensors = <&tsens1 9>; 6152 6153 trips { 6154 mdmss2_alert0: trip-point0 { 6155 temperature = <90000>; 6156 hysteresis = <2000>; 6157 type = "hot"; 6158 }; 6159 6160 mdmss2_crit: mdmss2-crit { 6161 temperature = <110000>; 6162 hysteresis = <0>; 6163 type = "critical"; 6164 }; 6165 }; 6166 }; 6167 6168 mdmss3-thermal { 6169 polling-delay-passive = <0>; 6170 polling-delay = <0>; 6171 6172 thermal-sensors = <&tsens1 10>; 6173 6174 trips { 6175 mdmss3_alert0: trip-point0 { 6176 temperature = <90000>; 6177 hysteresis = <2000>; 6178 type = "hot"; 6179 }; 6180 6181 mdmss3_crit: mdmss3-crit { 6182 temperature = <110000>; 6183 hysteresis = <0>; 6184 type = "critical"; 6185 }; 6186 }; 6187 }; 6188 6189 camera0-thermal { 6190 polling-delay-passive = <0>; 6191 polling-delay = <0>; 6192 6193 thermal-sensors = <&tsens1 11>; 6194 6195 trips { 6196 camera0_alert0: trip-point0 { 6197 temperature = <90000>; 6198 hysteresis = <2000>; 6199 type = "hot"; 6200 }; 6201 6202 camera0_crit: camera0-crit { 6203 temperature = <110000>; 6204 hysteresis = <0>; 6205 type = "critical"; 6206 }; 6207 }; 6208 }; 6209 }; 6210 6211 timer { 6212 compatible = "arm,armv8-timer"; 6213 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6214 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6215 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6216 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6217 }; 6218}; 6219