1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7280.h> 13#include <dt-bindings/interconnect/qcom,sc7280.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-aoss-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/reset/qcom,sdm845-aoss.h> 19#include <dt-bindings/reset/qcom,sdm845-pdc.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 chosen { }; 30 31 aliases { 32 i2c0 = &i2c0; 33 i2c1 = &i2c1; 34 i2c2 = &i2c2; 35 i2c3 = &i2c3; 36 i2c4 = &i2c4; 37 i2c5 = &i2c5; 38 i2c6 = &i2c6; 39 i2c7 = &i2c7; 40 i2c8 = &i2c8; 41 i2c9 = &i2c9; 42 i2c10 = &i2c10; 43 i2c11 = &i2c11; 44 i2c12 = &i2c12; 45 i2c13 = &i2c13; 46 i2c14 = &i2c14; 47 i2c15 = &i2c15; 48 mmc1 = &sdhc_1; 49 mmc2 = &sdhc_2; 50 spi0 = &spi0; 51 spi1 = &spi1; 52 spi2 = &spi2; 53 spi3 = &spi3; 54 spi4 = &spi4; 55 spi5 = &spi5; 56 spi6 = &spi6; 57 spi7 = &spi7; 58 spi8 = &spi8; 59 spi9 = &spi9; 60 spi10 = &spi10; 61 spi11 = &spi11; 62 spi12 = &spi12; 63 spi13 = &spi13; 64 spi14 = &spi14; 65 spi15 = &spi15; 66 }; 67 68 clocks { 69 xo_board: xo-board { 70 compatible = "fixed-clock"; 71 clock-frequency = <76800000>; 72 #clock-cells = <0>; 73 }; 74 75 sleep_clk: sleep-clk { 76 compatible = "fixed-clock"; 77 clock-frequency = <32000>; 78 #clock-cells = <0>; 79 }; 80 }; 81 82 reserved-memory { 83 #address-cells = <2>; 84 #size-cells = <2>; 85 ranges; 86 87 aop_mem: memory@80800000 { 88 reg = <0x0 0x80800000 0x0 0x60000>; 89 no-map; 90 }; 91 92 aop_cmd_db_mem: memory@80860000 { 93 reg = <0x0 0x80860000 0x0 0x20000>; 94 compatible = "qcom,cmd-db"; 95 no-map; 96 }; 97 98 smem_mem: memory@80900000 { 99 reg = <0x0 0x80900000 0x0 0x200000>; 100 no-map; 101 }; 102 103 cpucp_mem: memory@80b00000 { 104 no-map; 105 reg = <0x0 0x80b00000 0x0 0x100000>; 106 }; 107 108 ipa_fw_mem: memory@8b700000 { 109 reg = <0 0x8b700000 0 0x10000>; 110 no-map; 111 }; 112 }; 113 114 cpus { 115 #address-cells = <2>; 116 #size-cells = <0>; 117 118 CPU0: cpu@0 { 119 device_type = "cpu"; 120 compatible = "arm,kryo"; 121 reg = <0x0 0x0>; 122 enable-method = "psci"; 123 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 124 &LITTLE_CPU_SLEEP_1 125 &CLUSTER_SLEEP_0>; 126 next-level-cache = <&L2_0>; 127 qcom,freq-domain = <&cpufreq_hw 0>; 128 #cooling-cells = <2>; 129 L2_0: l2-cache { 130 compatible = "cache"; 131 next-level-cache = <&L3_0>; 132 L3_0: l3-cache { 133 compatible = "cache"; 134 }; 135 }; 136 }; 137 138 CPU1: cpu@100 { 139 device_type = "cpu"; 140 compatible = "arm,kryo"; 141 reg = <0x0 0x100>; 142 enable-method = "psci"; 143 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 144 &LITTLE_CPU_SLEEP_1 145 &CLUSTER_SLEEP_0>; 146 next-level-cache = <&L2_100>; 147 qcom,freq-domain = <&cpufreq_hw 0>; 148 #cooling-cells = <2>; 149 L2_100: l2-cache { 150 compatible = "cache"; 151 next-level-cache = <&L3_0>; 152 }; 153 }; 154 155 CPU2: cpu@200 { 156 device_type = "cpu"; 157 compatible = "arm,kryo"; 158 reg = <0x0 0x200>; 159 enable-method = "psci"; 160 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 161 &LITTLE_CPU_SLEEP_1 162 &CLUSTER_SLEEP_0>; 163 next-level-cache = <&L2_200>; 164 qcom,freq-domain = <&cpufreq_hw 0>; 165 #cooling-cells = <2>; 166 L2_200: l2-cache { 167 compatible = "cache"; 168 next-level-cache = <&L3_0>; 169 }; 170 }; 171 172 CPU3: cpu@300 { 173 device_type = "cpu"; 174 compatible = "arm,kryo"; 175 reg = <0x0 0x300>; 176 enable-method = "psci"; 177 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 178 &LITTLE_CPU_SLEEP_1 179 &CLUSTER_SLEEP_0>; 180 next-level-cache = <&L2_300>; 181 qcom,freq-domain = <&cpufreq_hw 0>; 182 #cooling-cells = <2>; 183 L2_300: l2-cache { 184 compatible = "cache"; 185 next-level-cache = <&L3_0>; 186 }; 187 }; 188 189 CPU4: cpu@400 { 190 device_type = "cpu"; 191 compatible = "arm,kryo"; 192 reg = <0x0 0x400>; 193 enable-method = "psci"; 194 cpu-idle-states = <&BIG_CPU_SLEEP_0 195 &BIG_CPU_SLEEP_1 196 &CLUSTER_SLEEP_0>; 197 next-level-cache = <&L2_400>; 198 qcom,freq-domain = <&cpufreq_hw 1>; 199 #cooling-cells = <2>; 200 L2_400: l2-cache { 201 compatible = "cache"; 202 next-level-cache = <&L3_0>; 203 }; 204 }; 205 206 CPU5: cpu@500 { 207 device_type = "cpu"; 208 compatible = "arm,kryo"; 209 reg = <0x0 0x500>; 210 enable-method = "psci"; 211 cpu-idle-states = <&BIG_CPU_SLEEP_0 212 &BIG_CPU_SLEEP_1 213 &CLUSTER_SLEEP_0>; 214 next-level-cache = <&L2_500>; 215 qcom,freq-domain = <&cpufreq_hw 1>; 216 #cooling-cells = <2>; 217 L2_500: l2-cache { 218 compatible = "cache"; 219 next-level-cache = <&L3_0>; 220 }; 221 }; 222 223 CPU6: cpu@600 { 224 device_type = "cpu"; 225 compatible = "arm,kryo"; 226 reg = <0x0 0x600>; 227 enable-method = "psci"; 228 cpu-idle-states = <&BIG_CPU_SLEEP_0 229 &BIG_CPU_SLEEP_1 230 &CLUSTER_SLEEP_0>; 231 next-level-cache = <&L2_600>; 232 qcom,freq-domain = <&cpufreq_hw 1>; 233 #cooling-cells = <2>; 234 L2_600: l2-cache { 235 compatible = "cache"; 236 next-level-cache = <&L3_0>; 237 }; 238 }; 239 240 CPU7: cpu@700 { 241 device_type = "cpu"; 242 compatible = "arm,kryo"; 243 reg = <0x0 0x700>; 244 enable-method = "psci"; 245 cpu-idle-states = <&BIG_CPU_SLEEP_0 246 &BIG_CPU_SLEEP_1 247 &CLUSTER_SLEEP_0>; 248 next-level-cache = <&L2_700>; 249 qcom,freq-domain = <&cpufreq_hw 2>; 250 #cooling-cells = <2>; 251 L2_700: l2-cache { 252 compatible = "cache"; 253 next-level-cache = <&L3_0>; 254 }; 255 }; 256 257 cpu-map { 258 cluster0 { 259 core0 { 260 cpu = <&CPU0>; 261 }; 262 263 core1 { 264 cpu = <&CPU1>; 265 }; 266 267 core2 { 268 cpu = <&CPU2>; 269 }; 270 271 core3 { 272 cpu = <&CPU3>; 273 }; 274 275 core4 { 276 cpu = <&CPU4>; 277 }; 278 279 core5 { 280 cpu = <&CPU5>; 281 }; 282 283 core6 { 284 cpu = <&CPU6>; 285 }; 286 287 core7 { 288 cpu = <&CPU7>; 289 }; 290 }; 291 }; 292 293 idle-states { 294 entry-method = "psci"; 295 296 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 297 compatible = "arm,idle-state"; 298 idle-state-name = "little-power-down"; 299 arm,psci-suspend-param = <0x40000003>; 300 entry-latency-us = <549>; 301 exit-latency-us = <901>; 302 min-residency-us = <1774>; 303 local-timer-stop; 304 }; 305 306 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 307 compatible = "arm,idle-state"; 308 idle-state-name = "little-rail-power-down"; 309 arm,psci-suspend-param = <0x40000004>; 310 entry-latency-us = <702>; 311 exit-latency-us = <915>; 312 min-residency-us = <4001>; 313 local-timer-stop; 314 }; 315 316 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 317 compatible = "arm,idle-state"; 318 idle-state-name = "big-power-down"; 319 arm,psci-suspend-param = <0x40000003>; 320 entry-latency-us = <523>; 321 exit-latency-us = <1244>; 322 min-residency-us = <2207>; 323 local-timer-stop; 324 }; 325 326 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 327 compatible = "arm,idle-state"; 328 idle-state-name = "big-rail-power-down"; 329 arm,psci-suspend-param = <0x40000004>; 330 entry-latency-us = <526>; 331 exit-latency-us = <1854>; 332 min-residency-us = <5555>; 333 local-timer-stop; 334 }; 335 336 CLUSTER_SLEEP_0: cluster-sleep-0 { 337 compatible = "arm,idle-state"; 338 idle-state-name = "cluster-power-down"; 339 arm,psci-suspend-param = <0x40003444>; 340 entry-latency-us = <3263>; 341 exit-latency-us = <6562>; 342 min-residency-us = <9926>; 343 local-timer-stop; 344 }; 345 }; 346 }; 347 348 memory@80000000 { 349 device_type = "memory"; 350 /* We expect the bootloader to fill in the size */ 351 reg = <0 0x80000000 0 0>; 352 }; 353 354 firmware { 355 scm { 356 compatible = "qcom,scm-sc7280", "qcom,scm"; 357 }; 358 }; 359 360 clk_virt: interconnect { 361 compatible = "qcom,sc7280-clk-virt"; 362 #interconnect-cells = <2>; 363 qcom,bcm-voters = <&apps_bcm_voter>; 364 }; 365 366 smem { 367 compatible = "qcom,smem"; 368 memory-region = <&smem_mem>; 369 hwlocks = <&tcsr_mutex 3>; 370 }; 371 372 smp2p-adsp { 373 compatible = "qcom,smp2p"; 374 qcom,smem = <443>, <429>; 375 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 376 IPCC_MPROC_SIGNAL_SMP2P 377 IRQ_TYPE_EDGE_RISING>; 378 mboxes = <&ipcc IPCC_CLIENT_LPASS 379 IPCC_MPROC_SIGNAL_SMP2P>; 380 381 qcom,local-pid = <0>; 382 qcom,remote-pid = <2>; 383 384 adsp_smp2p_out: master-kernel { 385 qcom,entry-name = "master-kernel"; 386 #qcom,smem-state-cells = <1>; 387 }; 388 389 adsp_smp2p_in: slave-kernel { 390 qcom,entry-name = "slave-kernel"; 391 interrupt-controller; 392 #interrupt-cells = <2>; 393 }; 394 }; 395 396 smp2p-cdsp { 397 compatible = "qcom,smp2p"; 398 qcom,smem = <94>, <432>; 399 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 400 IPCC_MPROC_SIGNAL_SMP2P 401 IRQ_TYPE_EDGE_RISING>; 402 mboxes = <&ipcc IPCC_CLIENT_CDSP 403 IPCC_MPROC_SIGNAL_SMP2P>; 404 405 qcom,local-pid = <0>; 406 qcom,remote-pid = <5>; 407 408 cdsp_smp2p_out: master-kernel { 409 qcom,entry-name = "master-kernel"; 410 #qcom,smem-state-cells = <1>; 411 }; 412 413 cdsp_smp2p_in: slave-kernel { 414 qcom,entry-name = "slave-kernel"; 415 interrupt-controller; 416 #interrupt-cells = <2>; 417 }; 418 }; 419 420 smp2p-mpss { 421 compatible = "qcom,smp2p"; 422 qcom,smem = <435>, <428>; 423 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 424 IPCC_MPROC_SIGNAL_SMP2P 425 IRQ_TYPE_EDGE_RISING>; 426 mboxes = <&ipcc IPCC_CLIENT_MPSS 427 IPCC_MPROC_SIGNAL_SMP2P>; 428 429 qcom,local-pid = <0>; 430 qcom,remote-pid = <1>; 431 432 modem_smp2p_out: master-kernel { 433 qcom,entry-name = "master-kernel"; 434 #qcom,smem-state-cells = <1>; 435 }; 436 437 modem_smp2p_in: slave-kernel { 438 qcom,entry-name = "slave-kernel"; 439 interrupt-controller; 440 #interrupt-cells = <2>; 441 }; 442 443 ipa_smp2p_out: ipa-ap-to-modem { 444 qcom,entry-name = "ipa"; 445 #qcom,smem-state-cells = <1>; 446 }; 447 448 ipa_smp2p_in: ipa-modem-to-ap { 449 qcom,entry-name = "ipa"; 450 interrupt-controller; 451 #interrupt-cells = <2>; 452 }; 453 }; 454 455 smp2p-wpss { 456 compatible = "qcom,smp2p"; 457 qcom,smem = <617>, <616>; 458 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 459 IPCC_MPROC_SIGNAL_SMP2P 460 IRQ_TYPE_EDGE_RISING>; 461 mboxes = <&ipcc IPCC_CLIENT_WPSS 462 IPCC_MPROC_SIGNAL_SMP2P>; 463 464 qcom,local-pid = <0>; 465 qcom,remote-pid = <13>; 466 467 wpss_smp2p_out: master-kernel { 468 qcom,entry-name = "master-kernel"; 469 #qcom,smem-state-cells = <1>; 470 }; 471 472 wpss_smp2p_in: slave-kernel { 473 qcom,entry-name = "slave-kernel"; 474 interrupt-controller; 475 #interrupt-cells = <2>; 476 }; 477 }; 478 479 pmu { 480 compatible = "arm,armv8-pmuv3"; 481 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 482 }; 483 484 psci { 485 compatible = "arm,psci-1.0"; 486 method = "smc"; 487 }; 488 489 qspi_opp_table: qspi-opp-table { 490 compatible = "operating-points-v2"; 491 492 opp-75000000 { 493 opp-hz = /bits/ 64 <75000000>; 494 required-opps = <&rpmhpd_opp_low_svs>; 495 }; 496 497 opp-150000000 { 498 opp-hz = /bits/ 64 <150000000>; 499 required-opps = <&rpmhpd_opp_svs>; 500 }; 501 502 opp-300000000 { 503 opp-hz = /bits/ 64 <300000000>; 504 required-opps = <&rpmhpd_opp_nom>; 505 }; 506 }; 507 508 qup_opp_table: qup-opp-table { 509 compatible = "operating-points-v2"; 510 511 opp-75000000 { 512 opp-hz = /bits/ 64 <75000000>; 513 required-opps = <&rpmhpd_opp_low_svs>; 514 }; 515 516 opp-100000000 { 517 opp-hz = /bits/ 64 <100000000>; 518 required-opps = <&rpmhpd_opp_svs>; 519 }; 520 521 opp-128000000 { 522 opp-hz = /bits/ 64 <128000000>; 523 required-opps = <&rpmhpd_opp_nom>; 524 }; 525 }; 526 527 soc: soc@0 { 528 #address-cells = <2>; 529 #size-cells = <2>; 530 ranges = <0 0 0 0 0x10 0>; 531 dma-ranges = <0 0 0 0 0x10 0>; 532 compatible = "simple-bus"; 533 534 gcc: clock-controller@100000 { 535 compatible = "qcom,gcc-sc7280"; 536 reg = <0 0x00100000 0 0x1f0000>; 537 clocks = <&rpmhcc RPMH_CXO_CLK>, 538 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 539 <0>, <0>, <0>, <0>, <0>, <0>; 540 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 541 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 542 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 543 "ufs_phy_tx_symbol_0_clk", 544 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 545 #clock-cells = <1>; 546 #reset-cells = <1>; 547 #power-domain-cells = <1>; 548 }; 549 550 ipcc: mailbox@408000 { 551 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 552 reg = <0 0x00408000 0 0x1000>; 553 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 554 interrupt-controller; 555 #interrupt-cells = <3>; 556 #mbox-cells = <2>; 557 }; 558 559 qfprom: efuse@784000 { 560 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 561 reg = <0 0x00784000 0 0xa20>, 562 <0 0x00780000 0 0xa20>, 563 <0 0x00782000 0 0x120>, 564 <0 0x00786000 0 0x1fff>; 565 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 566 clock-names = "core"; 567 power-domains = <&rpmhpd SC7280_MX>; 568 #address-cells = <1>; 569 #size-cells = <1>; 570 }; 571 572 sdhc_1: sdhci@7c4000 { 573 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 574 status = "disabled"; 575 576 reg = <0 0x007c4000 0 0x1000>, 577 <0 0x007c5000 0 0x1000>; 578 reg-names = "hc", "cqhci"; 579 580 iommus = <&apps_smmu 0xc0 0x0>; 581 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 583 interrupt-names = "hc_irq", "pwr_irq"; 584 585 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 586 <&gcc GCC_SDCC1_AHB_CLK>, 587 <&rpmhcc RPMH_CXO_CLK>; 588 clock-names = "core", "iface", "xo"; 589 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 590 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 591 interconnect-names = "sdhc-ddr","cpu-sdhc"; 592 power-domains = <&rpmhpd SC7280_CX>; 593 operating-points-v2 = <&sdhc1_opp_table>; 594 595 bus-width = <8>; 596 supports-cqe; 597 598 qcom,dll-config = <0x0007642c>; 599 qcom,ddr-config = <0x80040868>; 600 601 mmc-ddr-1_8v; 602 mmc-hs200-1_8v; 603 mmc-hs400-1_8v; 604 mmc-hs400-enhanced-strobe; 605 606 sdhc1_opp_table: opp-table { 607 compatible = "operating-points-v2"; 608 609 opp-100000000 { 610 opp-hz = /bits/ 64 <100000000>; 611 required-opps = <&rpmhpd_opp_low_svs>; 612 opp-peak-kBps = <1800000 400000>; 613 opp-avg-kBps = <100000 0>; 614 }; 615 616 opp-384000000 { 617 opp-hz = /bits/ 64 <384000000>; 618 required-opps = <&rpmhpd_opp_nom>; 619 opp-peak-kBps = <5400000 1600000>; 620 opp-avg-kBps = <390000 0>; 621 }; 622 }; 623 624 }; 625 626 qupv3_id_0: geniqup@9c0000 { 627 compatible = "qcom,geni-se-qup"; 628 reg = <0 0x009c0000 0 0x2000>; 629 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 630 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 631 clock-names = "m-ahb", "s-ahb"; 632 #address-cells = <2>; 633 #size-cells = <2>; 634 ranges; 635 iommus = <&apps_smmu 0x123 0x0>; 636 status = "disabled"; 637 638 i2c0: i2c@980000 { 639 compatible = "qcom,geni-i2c"; 640 reg = <0 0x00980000 0 0x4000>; 641 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 642 clock-names = "se"; 643 pinctrl-names = "default"; 644 pinctrl-0 = <&qup_i2c0_data_clk>; 645 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 649 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 650 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 651 interconnect-names = "qup-core", "qup-config", 652 "qup-memory"; 653 status = "disabled"; 654 }; 655 656 spi0: spi@980000 { 657 compatible = "qcom,geni-spi"; 658 reg = <0 0x00980000 0 0x4000>; 659 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 660 clock-names = "se"; 661 pinctrl-names = "default"; 662 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 663 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 664 #address-cells = <1>; 665 #size-cells = <0>; 666 power-domains = <&rpmhpd SC7280_CX>; 667 operating-points-v2 = <&qup_opp_table>; 668 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 669 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 670 interconnect-names = "qup-core", "qup-config"; 671 status = "disabled"; 672 }; 673 674 uart0: serial@980000 { 675 compatible = "qcom,geni-uart"; 676 reg = <0 0x00980000 0 0x4000>; 677 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 678 clock-names = "se"; 679 pinctrl-names = "default"; 680 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 681 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 682 power-domains = <&rpmhpd SC7280_CX>; 683 operating-points-v2 = <&qup_opp_table>; 684 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 685 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 686 interconnect-names = "qup-core", "qup-config"; 687 status = "disabled"; 688 }; 689 690 i2c1: i2c@984000 { 691 compatible = "qcom,geni-i2c"; 692 reg = <0 0x00984000 0 0x4000>; 693 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 694 clock-names = "se"; 695 pinctrl-names = "default"; 696 pinctrl-0 = <&qup_i2c1_data_clk>; 697 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 701 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 702 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 703 interconnect-names = "qup-core", "qup-config", 704 "qup-memory"; 705 status = "disabled"; 706 }; 707 708 spi1: spi@984000 { 709 compatible = "qcom,geni-spi"; 710 reg = <0 0x00984000 0 0x4000>; 711 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 712 clock-names = "se"; 713 pinctrl-names = "default"; 714 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 715 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 716 #address-cells = <1>; 717 #size-cells = <0>; 718 power-domains = <&rpmhpd SC7280_CX>; 719 operating-points-v2 = <&qup_opp_table>; 720 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 721 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 722 interconnect-names = "qup-core", "qup-config"; 723 status = "disabled"; 724 }; 725 726 uart1: serial@984000 { 727 compatible = "qcom,geni-uart"; 728 reg = <0 0x00984000 0 0x4000>; 729 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 730 clock-names = "se"; 731 pinctrl-names = "default"; 732 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 733 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 734 power-domains = <&rpmhpd SC7280_CX>; 735 operating-points-v2 = <&qup_opp_table>; 736 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 737 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 738 interconnect-names = "qup-core", "qup-config"; 739 status = "disabled"; 740 }; 741 742 i2c2: i2c@988000 { 743 compatible = "qcom,geni-i2c"; 744 reg = <0 0x00988000 0 0x4000>; 745 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 746 clock-names = "se"; 747 pinctrl-names = "default"; 748 pinctrl-0 = <&qup_i2c2_data_clk>; 749 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 750 #address-cells = <1>; 751 #size-cells = <0>; 752 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 753 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 754 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 755 interconnect-names = "qup-core", "qup-config", 756 "qup-memory"; 757 status = "disabled"; 758 }; 759 760 spi2: spi@988000 { 761 compatible = "qcom,geni-spi"; 762 reg = <0 0x00988000 0 0x4000>; 763 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 764 clock-names = "se"; 765 pinctrl-names = "default"; 766 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 767 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 768 #address-cells = <1>; 769 #size-cells = <0>; 770 power-domains = <&rpmhpd SC7280_CX>; 771 operating-points-v2 = <&qup_opp_table>; 772 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 773 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 774 interconnect-names = "qup-core", "qup-config"; 775 status = "disabled"; 776 }; 777 778 uart2: serial@988000 { 779 compatible = "qcom,geni-uart"; 780 reg = <0 0x00988000 0 0x4000>; 781 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 782 clock-names = "se"; 783 pinctrl-names = "default"; 784 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 785 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 786 power-domains = <&rpmhpd SC7280_CX>; 787 operating-points-v2 = <&qup_opp_table>; 788 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 789 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 790 interconnect-names = "qup-core", "qup-config"; 791 status = "disabled"; 792 }; 793 794 i2c3: i2c@98c000 { 795 compatible = "qcom,geni-i2c"; 796 reg = <0 0x0098c000 0 0x4000>; 797 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 798 clock-names = "se"; 799 pinctrl-names = "default"; 800 pinctrl-0 = <&qup_i2c3_data_clk>; 801 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 805 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 806 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 807 interconnect-names = "qup-core", "qup-config", 808 "qup-memory"; 809 status = "disabled"; 810 }; 811 812 spi3: spi@98c000 { 813 compatible = "qcom,geni-spi"; 814 reg = <0 0x0098c000 0 0x4000>; 815 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 816 clock-names = "se"; 817 pinctrl-names = "default"; 818 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 819 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 820 #address-cells = <1>; 821 #size-cells = <0>; 822 power-domains = <&rpmhpd SC7280_CX>; 823 operating-points-v2 = <&qup_opp_table>; 824 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 825 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 826 interconnect-names = "qup-core", "qup-config"; 827 status = "disabled"; 828 }; 829 830 uart3: serial@98c000 { 831 compatible = "qcom,geni-uart"; 832 reg = <0 0x0098c000 0 0x4000>; 833 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 834 clock-names = "se"; 835 pinctrl-names = "default"; 836 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 837 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 838 power-domains = <&rpmhpd SC7280_CX>; 839 operating-points-v2 = <&qup_opp_table>; 840 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 841 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 842 interconnect-names = "qup-core", "qup-config"; 843 status = "disabled"; 844 }; 845 846 i2c4: i2c@990000 { 847 compatible = "qcom,geni-i2c"; 848 reg = <0 0x00990000 0 0x4000>; 849 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 850 clock-names = "se"; 851 pinctrl-names = "default"; 852 pinctrl-0 = <&qup_i2c4_data_clk>; 853 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 854 #address-cells = <1>; 855 #size-cells = <0>; 856 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 857 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 858 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 859 interconnect-names = "qup-core", "qup-config", 860 "qup-memory"; 861 status = "disabled"; 862 }; 863 864 spi4: spi@990000 { 865 compatible = "qcom,geni-spi"; 866 reg = <0 0x00990000 0 0x4000>; 867 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 868 clock-names = "se"; 869 pinctrl-names = "default"; 870 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 871 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 872 #address-cells = <1>; 873 #size-cells = <0>; 874 power-domains = <&rpmhpd SC7280_CX>; 875 operating-points-v2 = <&qup_opp_table>; 876 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 877 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 878 interconnect-names = "qup-core", "qup-config"; 879 status = "disabled"; 880 }; 881 882 uart4: serial@990000 { 883 compatible = "qcom,geni-uart"; 884 reg = <0 0x00990000 0 0x4000>; 885 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 886 clock-names = "se"; 887 pinctrl-names = "default"; 888 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 889 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 890 power-domains = <&rpmhpd SC7280_CX>; 891 operating-points-v2 = <&qup_opp_table>; 892 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 893 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 894 interconnect-names = "qup-core", "qup-config"; 895 status = "disabled"; 896 }; 897 898 i2c5: i2c@994000 { 899 compatible = "qcom,geni-i2c"; 900 reg = <0 0x00994000 0 0x4000>; 901 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 902 clock-names = "se"; 903 pinctrl-names = "default"; 904 pinctrl-0 = <&qup_i2c5_data_clk>; 905 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 906 #address-cells = <1>; 907 #size-cells = <0>; 908 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 909 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 910 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 911 interconnect-names = "qup-core", "qup-config", 912 "qup-memory"; 913 status = "disabled"; 914 }; 915 916 spi5: spi@994000 { 917 compatible = "qcom,geni-spi"; 918 reg = <0 0x00994000 0 0x4000>; 919 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 920 clock-names = "se"; 921 pinctrl-names = "default"; 922 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 923 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 924 #address-cells = <1>; 925 #size-cells = <0>; 926 power-domains = <&rpmhpd SC7280_CX>; 927 operating-points-v2 = <&qup_opp_table>; 928 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 929 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 930 interconnect-names = "qup-core", "qup-config"; 931 status = "disabled"; 932 }; 933 934 uart5: serial@994000 { 935 compatible = "qcom,geni-uart"; 936 reg = <0 0x00994000 0 0x4000>; 937 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 938 clock-names = "se"; 939 pinctrl-names = "default"; 940 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 941 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 942 power-domains = <&rpmhpd SC7280_CX>; 943 operating-points-v2 = <&qup_opp_table>; 944 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 945 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 946 interconnect-names = "qup-core", "qup-config"; 947 status = "disabled"; 948 }; 949 950 i2c6: i2c@998000 { 951 compatible = "qcom,geni-i2c"; 952 reg = <0 0x00998000 0 0x4000>; 953 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 954 clock-names = "se"; 955 pinctrl-names = "default"; 956 pinctrl-0 = <&qup_i2c6_data_clk>; 957 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 958 #address-cells = <1>; 959 #size-cells = <0>; 960 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 961 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 962 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 963 interconnect-names = "qup-core", "qup-config", 964 "qup-memory"; 965 status = "disabled"; 966 }; 967 968 spi6: spi@998000 { 969 compatible = "qcom,geni-spi"; 970 reg = <0 0x00998000 0 0x4000>; 971 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 972 clock-names = "se"; 973 pinctrl-names = "default"; 974 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 975 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 976 #address-cells = <1>; 977 #size-cells = <0>; 978 power-domains = <&rpmhpd SC7280_CX>; 979 operating-points-v2 = <&qup_opp_table>; 980 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 981 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 982 interconnect-names = "qup-core", "qup-config"; 983 status = "disabled"; 984 }; 985 986 uart6: serial@998000 { 987 compatible = "qcom,geni-uart"; 988 reg = <0 0x00998000 0 0x4000>; 989 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 990 clock-names = "se"; 991 pinctrl-names = "default"; 992 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 993 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 994 power-domains = <&rpmhpd SC7280_CX>; 995 operating-points-v2 = <&qup_opp_table>; 996 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 997 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 998 interconnect-names = "qup-core", "qup-config"; 999 status = "disabled"; 1000 }; 1001 1002 i2c7: i2c@99c000 { 1003 compatible = "qcom,geni-i2c"; 1004 reg = <0 0x0099c000 0 0x4000>; 1005 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1006 clock-names = "se"; 1007 pinctrl-names = "default"; 1008 pinctrl-0 = <&qup_i2c7_data_clk>; 1009 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1013 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1014 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1015 interconnect-names = "qup-core", "qup-config", 1016 "qup-memory"; 1017 status = "disabled"; 1018 }; 1019 1020 spi7: spi@99c000 { 1021 compatible = "qcom,geni-spi"; 1022 reg = <0 0x0099c000 0 0x4000>; 1023 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1024 clock-names = "se"; 1025 pinctrl-names = "default"; 1026 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1027 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 power-domains = <&rpmhpd SC7280_CX>; 1031 operating-points-v2 = <&qup_opp_table>; 1032 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1033 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1034 interconnect-names = "qup-core", "qup-config"; 1035 status = "disabled"; 1036 }; 1037 1038 uart7: serial@99c000 { 1039 compatible = "qcom,geni-uart"; 1040 reg = <0 0x0099c000 0 0x4000>; 1041 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1042 clock-names = "se"; 1043 pinctrl-names = "default"; 1044 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1045 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1046 power-domains = <&rpmhpd SC7280_CX>; 1047 operating-points-v2 = <&qup_opp_table>; 1048 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1049 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1050 interconnect-names = "qup-core", "qup-config"; 1051 status = "disabled"; 1052 }; 1053 }; 1054 1055 qupv3_id_1: geniqup@ac0000 { 1056 compatible = "qcom,geni-se-qup"; 1057 reg = <0 0x00ac0000 0 0x2000>; 1058 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1059 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1060 clock-names = "m-ahb", "s-ahb"; 1061 #address-cells = <2>; 1062 #size-cells = <2>; 1063 ranges; 1064 iommus = <&apps_smmu 0x43 0x0>; 1065 status = "disabled"; 1066 1067 i2c8: i2c@a80000 { 1068 compatible = "qcom,geni-i2c"; 1069 reg = <0 0x00a80000 0 0x4000>; 1070 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1071 clock-names = "se"; 1072 pinctrl-names = "default"; 1073 pinctrl-0 = <&qup_i2c8_data_clk>; 1074 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1075 #address-cells = <1>; 1076 #size-cells = <0>; 1077 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1078 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1079 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1080 interconnect-names = "qup-core", "qup-config", 1081 "qup-memory"; 1082 status = "disabled"; 1083 }; 1084 1085 spi8: spi@a80000 { 1086 compatible = "qcom,geni-spi"; 1087 reg = <0 0x00a80000 0 0x4000>; 1088 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1089 clock-names = "se"; 1090 pinctrl-names = "default"; 1091 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1092 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 power-domains = <&rpmhpd SC7280_CX>; 1096 operating-points-v2 = <&qup_opp_table>; 1097 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1098 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1099 interconnect-names = "qup-core", "qup-config"; 1100 status = "disabled"; 1101 }; 1102 1103 uart8: serial@a80000 { 1104 compatible = "qcom,geni-uart"; 1105 reg = <0 0x00a80000 0 0x4000>; 1106 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1107 clock-names = "se"; 1108 pinctrl-names = "default"; 1109 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1110 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1111 power-domains = <&rpmhpd SC7280_CX>; 1112 operating-points-v2 = <&qup_opp_table>; 1113 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1114 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1115 interconnect-names = "qup-core", "qup-config"; 1116 status = "disabled"; 1117 }; 1118 1119 i2c9: i2c@a84000 { 1120 compatible = "qcom,geni-i2c"; 1121 reg = <0 0x00a84000 0 0x4000>; 1122 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1123 clock-names = "se"; 1124 pinctrl-names = "default"; 1125 pinctrl-0 = <&qup_i2c9_data_clk>; 1126 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1130 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1131 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1132 interconnect-names = "qup-core", "qup-config", 1133 "qup-memory"; 1134 status = "disabled"; 1135 }; 1136 1137 spi9: spi@a84000 { 1138 compatible = "qcom,geni-spi"; 1139 reg = <0 0x00a84000 0 0x4000>; 1140 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1141 clock-names = "se"; 1142 pinctrl-names = "default"; 1143 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1144 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 power-domains = <&rpmhpd SC7280_CX>; 1148 operating-points-v2 = <&qup_opp_table>; 1149 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1150 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1151 interconnect-names = "qup-core", "qup-config"; 1152 status = "disabled"; 1153 }; 1154 1155 uart9: serial@a84000 { 1156 compatible = "qcom,geni-uart"; 1157 reg = <0 0x00a84000 0 0x4000>; 1158 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1159 clock-names = "se"; 1160 pinctrl-names = "default"; 1161 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1162 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1163 power-domains = <&rpmhpd SC7280_CX>; 1164 operating-points-v2 = <&qup_opp_table>; 1165 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1166 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1167 interconnect-names = "qup-core", "qup-config"; 1168 status = "disabled"; 1169 }; 1170 1171 i2c10: i2c@a88000 { 1172 compatible = "qcom,geni-i2c"; 1173 reg = <0 0x00a88000 0 0x4000>; 1174 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1175 clock-names = "se"; 1176 pinctrl-names = "default"; 1177 pinctrl-0 = <&qup_i2c10_data_clk>; 1178 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1179 #address-cells = <1>; 1180 #size-cells = <0>; 1181 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1182 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1183 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1184 interconnect-names = "qup-core", "qup-config", 1185 "qup-memory"; 1186 status = "disabled"; 1187 }; 1188 1189 spi10: spi@a88000 { 1190 compatible = "qcom,geni-spi"; 1191 reg = <0 0x00a88000 0 0x4000>; 1192 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1193 clock-names = "se"; 1194 pinctrl-names = "default"; 1195 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1196 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 power-domains = <&rpmhpd SC7280_CX>; 1200 operating-points-v2 = <&qup_opp_table>; 1201 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1202 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1203 interconnect-names = "qup-core", "qup-config"; 1204 status = "disabled"; 1205 }; 1206 1207 uart10: serial@a88000 { 1208 compatible = "qcom,geni-uart"; 1209 reg = <0 0x00a88000 0 0x4000>; 1210 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1211 clock-names = "se"; 1212 pinctrl-names = "default"; 1213 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1214 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1215 power-domains = <&rpmhpd SC7280_CX>; 1216 operating-points-v2 = <&qup_opp_table>; 1217 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1218 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1219 interconnect-names = "qup-core", "qup-config"; 1220 status = "disabled"; 1221 }; 1222 1223 i2c11: i2c@a8c000 { 1224 compatible = "qcom,geni-i2c"; 1225 reg = <0 0x00a8c000 0 0x4000>; 1226 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1227 clock-names = "se"; 1228 pinctrl-names = "default"; 1229 pinctrl-0 = <&qup_i2c11_data_clk>; 1230 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1234 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1235 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1236 interconnect-names = "qup-core", "qup-config", 1237 "qup-memory"; 1238 status = "disabled"; 1239 }; 1240 1241 spi11: spi@a8c000 { 1242 compatible = "qcom,geni-spi"; 1243 reg = <0 0x00a8c000 0 0x4000>; 1244 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1245 clock-names = "se"; 1246 pinctrl-names = "default"; 1247 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1248 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 power-domains = <&rpmhpd SC7280_CX>; 1252 operating-points-v2 = <&qup_opp_table>; 1253 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1254 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1255 interconnect-names = "qup-core", "qup-config"; 1256 status = "disabled"; 1257 }; 1258 1259 uart11: serial@a8c000 { 1260 compatible = "qcom,geni-uart"; 1261 reg = <0 0x00a8c000 0 0x4000>; 1262 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1263 clock-names = "se"; 1264 pinctrl-names = "default"; 1265 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1266 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1267 power-domains = <&rpmhpd SC7280_CX>; 1268 operating-points-v2 = <&qup_opp_table>; 1269 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1270 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1271 interconnect-names = "qup-core", "qup-config"; 1272 status = "disabled"; 1273 }; 1274 1275 i2c12: i2c@a90000 { 1276 compatible = "qcom,geni-i2c"; 1277 reg = <0 0x00a90000 0 0x4000>; 1278 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1279 clock-names = "se"; 1280 pinctrl-names = "default"; 1281 pinctrl-0 = <&qup_i2c12_data_clk>; 1282 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1283 #address-cells = <1>; 1284 #size-cells = <0>; 1285 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1286 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1287 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1288 interconnect-names = "qup-core", "qup-config", 1289 "qup-memory"; 1290 status = "disabled"; 1291 }; 1292 1293 spi12: spi@a90000 { 1294 compatible = "qcom,geni-spi"; 1295 reg = <0 0x00a90000 0 0x4000>; 1296 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1297 clock-names = "se"; 1298 pinctrl-names = "default"; 1299 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1300 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 power-domains = <&rpmhpd SC7280_CX>; 1304 operating-points-v2 = <&qup_opp_table>; 1305 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1306 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1307 interconnect-names = "qup-core", "qup-config"; 1308 status = "disabled"; 1309 }; 1310 1311 uart12: serial@a90000 { 1312 compatible = "qcom,geni-uart"; 1313 reg = <0 0x00a90000 0 0x4000>; 1314 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1315 clock-names = "se"; 1316 pinctrl-names = "default"; 1317 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1318 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1319 power-domains = <&rpmhpd SC7280_CX>; 1320 operating-points-v2 = <&qup_opp_table>; 1321 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1322 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1323 interconnect-names = "qup-core", "qup-config"; 1324 status = "disabled"; 1325 }; 1326 1327 i2c13: i2c@a94000 { 1328 compatible = "qcom,geni-i2c"; 1329 reg = <0 0x00a94000 0 0x4000>; 1330 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1331 clock-names = "se"; 1332 pinctrl-names = "default"; 1333 pinctrl-0 = <&qup_i2c13_data_clk>; 1334 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1335 #address-cells = <1>; 1336 #size-cells = <0>; 1337 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1338 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1339 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1340 interconnect-names = "qup-core", "qup-config", 1341 "qup-memory"; 1342 status = "disabled"; 1343 }; 1344 1345 spi13: spi@a94000 { 1346 compatible = "qcom,geni-spi"; 1347 reg = <0 0x00a94000 0 0x4000>; 1348 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1349 clock-names = "se"; 1350 pinctrl-names = "default"; 1351 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1352 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1353 #address-cells = <1>; 1354 #size-cells = <0>; 1355 power-domains = <&rpmhpd SC7280_CX>; 1356 operating-points-v2 = <&qup_opp_table>; 1357 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1358 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1359 interconnect-names = "qup-core", "qup-config"; 1360 status = "disabled"; 1361 }; 1362 1363 uart13: serial@a94000 { 1364 compatible = "qcom,geni-uart"; 1365 reg = <0 0x00a94000 0 0x4000>; 1366 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1367 clock-names = "se"; 1368 pinctrl-names = "default"; 1369 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1370 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1371 power-domains = <&rpmhpd SC7280_CX>; 1372 operating-points-v2 = <&qup_opp_table>; 1373 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1374 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1375 interconnect-names = "qup-core", "qup-config"; 1376 status = "disabled"; 1377 }; 1378 1379 i2c14: i2c@a98000 { 1380 compatible = "qcom,geni-i2c"; 1381 reg = <0 0x00a98000 0 0x4000>; 1382 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1383 clock-names = "se"; 1384 pinctrl-names = "default"; 1385 pinctrl-0 = <&qup_i2c14_data_clk>; 1386 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1387 #address-cells = <1>; 1388 #size-cells = <0>; 1389 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1390 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1391 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1392 interconnect-names = "qup-core", "qup-config", 1393 "qup-memory"; 1394 status = "disabled"; 1395 }; 1396 1397 spi14: spi@a98000 { 1398 compatible = "qcom,geni-spi"; 1399 reg = <0 0x00a98000 0 0x4000>; 1400 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1401 clock-names = "se"; 1402 pinctrl-names = "default"; 1403 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1404 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1405 #address-cells = <1>; 1406 #size-cells = <0>; 1407 power-domains = <&rpmhpd SC7280_CX>; 1408 operating-points-v2 = <&qup_opp_table>; 1409 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1410 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1411 interconnect-names = "qup-core", "qup-config"; 1412 status = "disabled"; 1413 }; 1414 1415 uart14: serial@a98000 { 1416 compatible = "qcom,geni-uart"; 1417 reg = <0 0x00a98000 0 0x4000>; 1418 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1419 clock-names = "se"; 1420 pinctrl-names = "default"; 1421 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1422 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1423 power-domains = <&rpmhpd SC7280_CX>; 1424 operating-points-v2 = <&qup_opp_table>; 1425 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1426 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1427 interconnect-names = "qup-core", "qup-config"; 1428 status = "disabled"; 1429 }; 1430 1431 i2c15: i2c@a9c000 { 1432 compatible = "qcom,geni-i2c"; 1433 reg = <0 0x00a9c000 0 0x4000>; 1434 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1435 clock-names = "se"; 1436 pinctrl-names = "default"; 1437 pinctrl-0 = <&qup_i2c15_data_clk>; 1438 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1439 #address-cells = <1>; 1440 #size-cells = <0>; 1441 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1442 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1443 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1444 interconnect-names = "qup-core", "qup-config", 1445 "qup-memory"; 1446 status = "disabled"; 1447 }; 1448 1449 spi15: spi@a9c000 { 1450 compatible = "qcom,geni-spi"; 1451 reg = <0 0x00a9c000 0 0x4000>; 1452 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1453 clock-names = "se"; 1454 pinctrl-names = "default"; 1455 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1456 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1457 #address-cells = <1>; 1458 #size-cells = <0>; 1459 power-domains = <&rpmhpd SC7280_CX>; 1460 operating-points-v2 = <&qup_opp_table>; 1461 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1462 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1463 interconnect-names = "qup-core", "qup-config"; 1464 status = "disabled"; 1465 }; 1466 1467 uart15: serial@a9c000 { 1468 compatible = "qcom,geni-uart"; 1469 reg = <0 0x00a9c000 0 0x4000>; 1470 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1471 clock-names = "se"; 1472 pinctrl-names = "default"; 1473 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1474 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1475 power-domains = <&rpmhpd SC7280_CX>; 1476 operating-points-v2 = <&qup_opp_table>; 1477 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1478 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1479 interconnect-names = "qup-core", "qup-config"; 1480 status = "disabled"; 1481 }; 1482 }; 1483 1484 cnoc2: interconnect@1500000 { 1485 reg = <0 0x01500000 0 0x1000>; 1486 compatible = "qcom,sc7280-cnoc2"; 1487 #interconnect-cells = <2>; 1488 qcom,bcm-voters = <&apps_bcm_voter>; 1489 }; 1490 1491 cnoc3: interconnect@1502000 { 1492 reg = <0 0x01502000 0 0x1000>; 1493 compatible = "qcom,sc7280-cnoc3"; 1494 #interconnect-cells = <2>; 1495 qcom,bcm-voters = <&apps_bcm_voter>; 1496 }; 1497 1498 mc_virt: interconnect@1580000 { 1499 reg = <0 0x01580000 0 0x4>; 1500 compatible = "qcom,sc7280-mc-virt"; 1501 #interconnect-cells = <2>; 1502 qcom,bcm-voters = <&apps_bcm_voter>; 1503 }; 1504 1505 system_noc: interconnect@1680000 { 1506 reg = <0 0x01680000 0 0x15480>; 1507 compatible = "qcom,sc7280-system-noc"; 1508 #interconnect-cells = <2>; 1509 qcom,bcm-voters = <&apps_bcm_voter>; 1510 }; 1511 1512 aggre1_noc: interconnect@16e0000 { 1513 compatible = "qcom,sc7280-aggre1-noc"; 1514 reg = <0 0x016e0000 0 0x1c080>; 1515 #interconnect-cells = <2>; 1516 qcom,bcm-voters = <&apps_bcm_voter>; 1517 }; 1518 1519 aggre2_noc: interconnect@1700000 { 1520 reg = <0 0x01700000 0 0x2b080>; 1521 compatible = "qcom,sc7280-aggre2-noc"; 1522 #interconnect-cells = <2>; 1523 qcom,bcm-voters = <&apps_bcm_voter>; 1524 }; 1525 1526 mmss_noc: interconnect@1740000 { 1527 reg = <0 0x01740000 0 0x1e080>; 1528 compatible = "qcom,sc7280-mmss-noc"; 1529 #interconnect-cells = <2>; 1530 qcom,bcm-voters = <&apps_bcm_voter>; 1531 }; 1532 1533 ipa: ipa@1e40000 { 1534 compatible = "qcom,sc7280-ipa"; 1535 1536 iommus = <&apps_smmu 0x480 0x0>, 1537 <&apps_smmu 0x482 0x0>; 1538 reg = <0 0x1e40000 0 0x8000>, 1539 <0 0x1e50000 0 0x4ad0>, 1540 <0 0x1e04000 0 0x23000>; 1541 reg-names = "ipa-reg", 1542 "ipa-shared", 1543 "gsi"; 1544 1545 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 1546 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1547 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1548 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1549 interrupt-names = "ipa", 1550 "gsi", 1551 "ipa-clock-query", 1552 "ipa-setup-ready"; 1553 1554 clocks = <&rpmhcc RPMH_IPA_CLK>; 1555 clock-names = "core"; 1556 1557 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1558 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 1559 interconnect-names = "memory", 1560 "config"; 1561 1562 qcom,smem-states = <&ipa_smp2p_out 0>, 1563 <&ipa_smp2p_out 1>; 1564 qcom,smem-state-names = "ipa-clock-enabled-valid", 1565 "ipa-clock-enabled"; 1566 1567 status = "disabled"; 1568 }; 1569 1570 tcsr_mutex: hwlock@1f40000 { 1571 compatible = "qcom,tcsr-mutex", "syscon"; 1572 reg = <0 0x01f40000 0 0x40000>; 1573 #hwlock-cells = <1>; 1574 }; 1575 1576 lpasscc: lpasscc@3000000 { 1577 compatible = "qcom,sc7280-lpasscc"; 1578 reg = <0 0x03000000 0 0x40>, 1579 <0 0x03c04000 0 0x4>, 1580 <0 0x03389000 0 0x24>; 1581 reg-names = "qdsp6ss", "top_cc", "cc"; 1582 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 1583 clock-names = "iface"; 1584 #clock-cells = <1>; 1585 }; 1586 1587 lpass_ag_noc: interconnect@3c40000 { 1588 reg = <0 0x03c40000 0 0xf080>; 1589 compatible = "qcom,sc7280-lpass-ag-noc"; 1590 #interconnect-cells = <2>; 1591 qcom,bcm-voters = <&apps_bcm_voter>; 1592 }; 1593 1594 gpu: gpu@3d00000 { 1595 compatible = "qcom,adreno-635.0", "qcom,adreno"; 1596 #stream-id-cells = <16>; 1597 reg = <0 0x03d00000 0 0x40000>, 1598 <0 0x03d9e000 0 0x1000>, 1599 <0 0x03d61000 0 0x800>; 1600 reg-names = "kgsl_3d0_reg_memory", 1601 "cx_mem", 1602 "cx_dbgc"; 1603 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1604 iommus = <&adreno_smmu 0 0x401>; 1605 operating-points-v2 = <&gpu_opp_table>; 1606 qcom,gmu = <&gmu>; 1607 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 1608 interconnect-names = "gfx-mem"; 1609 #cooling-cells = <2>; 1610 1611 gpu_opp_table: opp-table { 1612 compatible = "operating-points-v2"; 1613 1614 opp-315000000 { 1615 opp-hz = /bits/ 64 <315000000>; 1616 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1617 opp-peak-kBps = <1804000>; 1618 }; 1619 1620 opp-450000000 { 1621 opp-hz = /bits/ 64 <450000000>; 1622 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1623 opp-peak-kBps = <4068000>; 1624 }; 1625 1626 opp-550000000 { 1627 opp-hz = /bits/ 64 <550000000>; 1628 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1629 opp-peak-kBps = <6832000>; 1630 }; 1631 }; 1632 }; 1633 1634 gmu: gmu@3d69000 { 1635 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 1636 reg = <0 0x03d6a000 0 0x34000>, 1637 <0 0x3de0000 0 0x10000>, 1638 <0 0x0b290000 0 0x10000>; 1639 reg-names = "gmu", "rscc", "gmu_pdc"; 1640 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1642 interrupt-names = "hfi", "gmu"; 1643 clocks = <&gpucc 5>, 1644 <&gpucc 8>, 1645 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1646 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1647 <&gpucc 2>, 1648 <&gpucc 15>, 1649 <&gpucc 11>; 1650 clock-names = "gmu", 1651 "cxo", 1652 "axi", 1653 "memnoc", 1654 "ahb", 1655 "hub", 1656 "smmu_vote"; 1657 power-domains = <&gpucc 0>, 1658 <&gpucc 1>; 1659 power-domain-names = "cx", 1660 "gx"; 1661 iommus = <&adreno_smmu 5 0x400>; 1662 operating-points-v2 = <&gmu_opp_table>; 1663 1664 gmu_opp_table: opp-table { 1665 compatible = "operating-points-v2"; 1666 1667 opp-200000000 { 1668 opp-hz = /bits/ 64 <200000000>; 1669 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1670 }; 1671 }; 1672 }; 1673 1674 gpucc: clock-controller@3d90000 { 1675 compatible = "qcom,sc7280-gpucc"; 1676 reg = <0 0x03d90000 0 0x9000>; 1677 clocks = <&rpmhcc RPMH_CXO_CLK>, 1678 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1679 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1680 clock-names = "bi_tcxo", 1681 "gcc_gpu_gpll0_clk_src", 1682 "gcc_gpu_gpll0_div_clk_src"; 1683 #clock-cells = <1>; 1684 #reset-cells = <1>; 1685 #power-domain-cells = <1>; 1686 }; 1687 1688 adreno_smmu: iommu@3da0000 { 1689 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 1690 reg = <0 0x03da0000 0 0x20000>; 1691 #iommu-cells = <2>; 1692 #global-interrupts = <2>; 1693 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1694 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 1695 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1696 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1697 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1698 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1699 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1700 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1701 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1702 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1703 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1704 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1705 1706 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1707 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1708 <&gpucc 2>, 1709 <&gpucc 11>, 1710 <&gpucc 5>, 1711 <&gpucc 15>, 1712 <&gpucc 13>; 1713 clock-names = "gcc_gpu_memnoc_gfx_clk", 1714 "gcc_gpu_snoc_dvm_gfx_clk", 1715 "gpu_cc_ahb_clk", 1716 "gpu_cc_hlos1_vote_gpu_smmu_clk", 1717 "gpu_cc_cx_gmu_clk", 1718 "gpu_cc_hub_cx_int_clk", 1719 "gpu_cc_hub_aon_clk"; 1720 1721 power-domains = <&gpucc 0>; 1722 }; 1723 1724 stm@6002000 { 1725 compatible = "arm,coresight-stm", "arm,primecell"; 1726 reg = <0 0x06002000 0 0x1000>, 1727 <0 0x16280000 0 0x180000>; 1728 reg-names = "stm-base", "stm-stimulus-base"; 1729 1730 clocks = <&aoss_qmp>; 1731 clock-names = "apb_pclk"; 1732 1733 out-ports { 1734 port { 1735 stm_out: endpoint { 1736 remote-endpoint = <&funnel0_in7>; 1737 }; 1738 }; 1739 }; 1740 }; 1741 1742 funnel@6041000 { 1743 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1744 reg = <0 0x06041000 0 0x1000>; 1745 1746 clocks = <&aoss_qmp>; 1747 clock-names = "apb_pclk"; 1748 1749 out-ports { 1750 port { 1751 funnel0_out: endpoint { 1752 remote-endpoint = <&merge_funnel_in0>; 1753 }; 1754 }; 1755 }; 1756 1757 in-ports { 1758 #address-cells = <1>; 1759 #size-cells = <0>; 1760 1761 port@7 { 1762 reg = <7>; 1763 funnel0_in7: endpoint { 1764 remote-endpoint = <&stm_out>; 1765 }; 1766 }; 1767 }; 1768 }; 1769 1770 funnel@6042000 { 1771 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1772 reg = <0 0x06042000 0 0x1000>; 1773 1774 clocks = <&aoss_qmp>; 1775 clock-names = "apb_pclk"; 1776 1777 out-ports { 1778 port { 1779 funnel1_out: endpoint { 1780 remote-endpoint = <&merge_funnel_in1>; 1781 }; 1782 }; 1783 }; 1784 1785 in-ports { 1786 #address-cells = <1>; 1787 #size-cells = <0>; 1788 1789 port@4 { 1790 reg = <4>; 1791 funnel1_in4: endpoint { 1792 remote-endpoint = <&apss_merge_funnel_out>; 1793 }; 1794 }; 1795 }; 1796 }; 1797 1798 funnel@6045000 { 1799 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1800 reg = <0 0x06045000 0 0x1000>; 1801 1802 clocks = <&aoss_qmp>; 1803 clock-names = "apb_pclk"; 1804 1805 out-ports { 1806 port { 1807 merge_funnel_out: endpoint { 1808 remote-endpoint = <&swao_funnel_in>; 1809 }; 1810 }; 1811 }; 1812 1813 in-ports { 1814 #address-cells = <1>; 1815 #size-cells = <0>; 1816 1817 port@0 { 1818 reg = <0>; 1819 merge_funnel_in0: endpoint { 1820 remote-endpoint = <&funnel0_out>; 1821 }; 1822 }; 1823 1824 port@1 { 1825 reg = <1>; 1826 merge_funnel_in1: endpoint { 1827 remote-endpoint = <&funnel1_out>; 1828 }; 1829 }; 1830 }; 1831 }; 1832 1833 replicator@6046000 { 1834 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1835 reg = <0 0x06046000 0 0x1000>; 1836 1837 clocks = <&aoss_qmp>; 1838 clock-names = "apb_pclk"; 1839 1840 out-ports { 1841 port { 1842 replicator_out: endpoint { 1843 remote-endpoint = <&etr_in>; 1844 }; 1845 }; 1846 }; 1847 1848 in-ports { 1849 port { 1850 replicator_in: endpoint { 1851 remote-endpoint = <&swao_replicator_out>; 1852 }; 1853 }; 1854 }; 1855 }; 1856 1857 etr@6048000 { 1858 compatible = "arm,coresight-tmc", "arm,primecell"; 1859 reg = <0 0x06048000 0 0x1000>; 1860 iommus = <&apps_smmu 0x04c0 0>; 1861 1862 clocks = <&aoss_qmp>; 1863 clock-names = "apb_pclk"; 1864 arm,scatter-gather; 1865 1866 in-ports { 1867 port { 1868 etr_in: endpoint { 1869 remote-endpoint = <&replicator_out>; 1870 }; 1871 }; 1872 }; 1873 }; 1874 1875 funnel@6b04000 { 1876 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1877 reg = <0 0x06b04000 0 0x1000>; 1878 1879 clocks = <&aoss_qmp>; 1880 clock-names = "apb_pclk"; 1881 1882 out-ports { 1883 port { 1884 swao_funnel_out: endpoint { 1885 remote-endpoint = <&etf_in>; 1886 }; 1887 }; 1888 }; 1889 1890 in-ports { 1891 #address-cells = <1>; 1892 #size-cells = <0>; 1893 1894 port@7 { 1895 reg = <7>; 1896 swao_funnel_in: endpoint { 1897 remote-endpoint = <&merge_funnel_out>; 1898 }; 1899 }; 1900 }; 1901 }; 1902 1903 etf@6b05000 { 1904 compatible = "arm,coresight-tmc", "arm,primecell"; 1905 reg = <0 0x06b05000 0 0x1000>; 1906 1907 clocks = <&aoss_qmp>; 1908 clock-names = "apb_pclk"; 1909 1910 out-ports { 1911 port { 1912 etf_out: endpoint { 1913 remote-endpoint = <&swao_replicator_in>; 1914 }; 1915 }; 1916 }; 1917 1918 in-ports { 1919 port { 1920 etf_in: endpoint { 1921 remote-endpoint = <&swao_funnel_out>; 1922 }; 1923 }; 1924 }; 1925 }; 1926 1927 replicator@6b06000 { 1928 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1929 reg = <0 0x06b06000 0 0x1000>; 1930 1931 clocks = <&aoss_qmp>; 1932 clock-names = "apb_pclk"; 1933 qcom,replicator-loses-context; 1934 1935 out-ports { 1936 port { 1937 swao_replicator_out: endpoint { 1938 remote-endpoint = <&replicator_in>; 1939 }; 1940 }; 1941 }; 1942 1943 in-ports { 1944 port { 1945 swao_replicator_in: endpoint { 1946 remote-endpoint = <&etf_out>; 1947 }; 1948 }; 1949 }; 1950 }; 1951 1952 etm@7040000 { 1953 compatible = "arm,coresight-etm4x", "arm,primecell"; 1954 reg = <0 0x07040000 0 0x1000>; 1955 1956 cpu = <&CPU0>; 1957 1958 clocks = <&aoss_qmp>; 1959 clock-names = "apb_pclk"; 1960 arm,coresight-loses-context-with-cpu; 1961 qcom,skip-power-up; 1962 1963 out-ports { 1964 port { 1965 etm0_out: endpoint { 1966 remote-endpoint = <&apss_funnel_in0>; 1967 }; 1968 }; 1969 }; 1970 }; 1971 1972 etm@7140000 { 1973 compatible = "arm,coresight-etm4x", "arm,primecell"; 1974 reg = <0 0x07140000 0 0x1000>; 1975 1976 cpu = <&CPU1>; 1977 1978 clocks = <&aoss_qmp>; 1979 clock-names = "apb_pclk"; 1980 arm,coresight-loses-context-with-cpu; 1981 qcom,skip-power-up; 1982 1983 out-ports { 1984 port { 1985 etm1_out: endpoint { 1986 remote-endpoint = <&apss_funnel_in1>; 1987 }; 1988 }; 1989 }; 1990 }; 1991 1992 etm@7240000 { 1993 compatible = "arm,coresight-etm4x", "arm,primecell"; 1994 reg = <0 0x07240000 0 0x1000>; 1995 1996 cpu = <&CPU2>; 1997 1998 clocks = <&aoss_qmp>; 1999 clock-names = "apb_pclk"; 2000 arm,coresight-loses-context-with-cpu; 2001 qcom,skip-power-up; 2002 2003 out-ports { 2004 port { 2005 etm2_out: endpoint { 2006 remote-endpoint = <&apss_funnel_in2>; 2007 }; 2008 }; 2009 }; 2010 }; 2011 2012 etm@7340000 { 2013 compatible = "arm,coresight-etm4x", "arm,primecell"; 2014 reg = <0 0x07340000 0 0x1000>; 2015 2016 cpu = <&CPU3>; 2017 2018 clocks = <&aoss_qmp>; 2019 clock-names = "apb_pclk"; 2020 arm,coresight-loses-context-with-cpu; 2021 qcom,skip-power-up; 2022 2023 out-ports { 2024 port { 2025 etm3_out: endpoint { 2026 remote-endpoint = <&apss_funnel_in3>; 2027 }; 2028 }; 2029 }; 2030 }; 2031 2032 etm@7440000 { 2033 compatible = "arm,coresight-etm4x", "arm,primecell"; 2034 reg = <0 0x07440000 0 0x1000>; 2035 2036 cpu = <&CPU4>; 2037 2038 clocks = <&aoss_qmp>; 2039 clock-names = "apb_pclk"; 2040 arm,coresight-loses-context-with-cpu; 2041 qcom,skip-power-up; 2042 2043 out-ports { 2044 port { 2045 etm4_out: endpoint { 2046 remote-endpoint = <&apss_funnel_in4>; 2047 }; 2048 }; 2049 }; 2050 }; 2051 2052 etm@7540000 { 2053 compatible = "arm,coresight-etm4x", "arm,primecell"; 2054 reg = <0 0x07540000 0 0x1000>; 2055 2056 cpu = <&CPU5>; 2057 2058 clocks = <&aoss_qmp>; 2059 clock-names = "apb_pclk"; 2060 arm,coresight-loses-context-with-cpu; 2061 qcom,skip-power-up; 2062 2063 out-ports { 2064 port { 2065 etm5_out: endpoint { 2066 remote-endpoint = <&apss_funnel_in5>; 2067 }; 2068 }; 2069 }; 2070 }; 2071 2072 etm@7640000 { 2073 compatible = "arm,coresight-etm4x", "arm,primecell"; 2074 reg = <0 0x07640000 0 0x1000>; 2075 2076 cpu = <&CPU6>; 2077 2078 clocks = <&aoss_qmp>; 2079 clock-names = "apb_pclk"; 2080 arm,coresight-loses-context-with-cpu; 2081 qcom,skip-power-up; 2082 2083 out-ports { 2084 port { 2085 etm6_out: endpoint { 2086 remote-endpoint = <&apss_funnel_in6>; 2087 }; 2088 }; 2089 }; 2090 }; 2091 2092 etm@7740000 { 2093 compatible = "arm,coresight-etm4x", "arm,primecell"; 2094 reg = <0 0x07740000 0 0x1000>; 2095 2096 cpu = <&CPU7>; 2097 2098 clocks = <&aoss_qmp>; 2099 clock-names = "apb_pclk"; 2100 arm,coresight-loses-context-with-cpu; 2101 qcom,skip-power-up; 2102 2103 out-ports { 2104 port { 2105 etm7_out: endpoint { 2106 remote-endpoint = <&apss_funnel_in7>; 2107 }; 2108 }; 2109 }; 2110 }; 2111 2112 funnel@7800000 { /* APSS Funnel */ 2113 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2114 reg = <0 0x07800000 0 0x1000>; 2115 2116 clocks = <&aoss_qmp>; 2117 clock-names = "apb_pclk"; 2118 2119 out-ports { 2120 port { 2121 apss_funnel_out: endpoint { 2122 remote-endpoint = <&apss_merge_funnel_in>; 2123 }; 2124 }; 2125 }; 2126 2127 in-ports { 2128 #address-cells = <1>; 2129 #size-cells = <0>; 2130 2131 port@0 { 2132 reg = <0>; 2133 apss_funnel_in0: endpoint { 2134 remote-endpoint = <&etm0_out>; 2135 }; 2136 }; 2137 2138 port@1 { 2139 reg = <1>; 2140 apss_funnel_in1: endpoint { 2141 remote-endpoint = <&etm1_out>; 2142 }; 2143 }; 2144 2145 port@2 { 2146 reg = <2>; 2147 apss_funnel_in2: endpoint { 2148 remote-endpoint = <&etm2_out>; 2149 }; 2150 }; 2151 2152 port@3 { 2153 reg = <3>; 2154 apss_funnel_in3: endpoint { 2155 remote-endpoint = <&etm3_out>; 2156 }; 2157 }; 2158 2159 port@4 { 2160 reg = <4>; 2161 apss_funnel_in4: endpoint { 2162 remote-endpoint = <&etm4_out>; 2163 }; 2164 }; 2165 2166 port@5 { 2167 reg = <5>; 2168 apss_funnel_in5: endpoint { 2169 remote-endpoint = <&etm5_out>; 2170 }; 2171 }; 2172 2173 port@6 { 2174 reg = <6>; 2175 apss_funnel_in6: endpoint { 2176 remote-endpoint = <&etm6_out>; 2177 }; 2178 }; 2179 2180 port@7 { 2181 reg = <7>; 2182 apss_funnel_in7: endpoint { 2183 remote-endpoint = <&etm7_out>; 2184 }; 2185 }; 2186 }; 2187 }; 2188 2189 funnel@7810000 { 2190 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2191 reg = <0 0x07810000 0 0x1000>; 2192 2193 clocks = <&aoss_qmp>; 2194 clock-names = "apb_pclk"; 2195 2196 out-ports { 2197 port { 2198 apss_merge_funnel_out: endpoint { 2199 remote-endpoint = <&funnel1_in4>; 2200 }; 2201 }; 2202 }; 2203 2204 in-ports { 2205 port { 2206 apss_merge_funnel_in: endpoint { 2207 remote-endpoint = <&apss_funnel_out>; 2208 }; 2209 }; 2210 }; 2211 }; 2212 2213 sdhc_2: sdhci@8804000 { 2214 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 2215 status = "disabled"; 2216 2217 reg = <0 0x08804000 0 0x1000>; 2218 2219 iommus = <&apps_smmu 0x100 0x0>; 2220 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2221 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2222 interrupt-names = "hc_irq", "pwr_irq"; 2223 2224 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2225 <&gcc GCC_SDCC2_AHB_CLK>, 2226 <&rpmhcc RPMH_CXO_CLK>; 2227 clock-names = "core", "iface", "xo"; 2228 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2229 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 2230 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2231 power-domains = <&rpmhpd SC7280_CX>; 2232 operating-points-v2 = <&sdhc2_opp_table>; 2233 2234 bus-width = <4>; 2235 2236 qcom,dll-config = <0x0007642c>; 2237 2238 sdhc2_opp_table: opp-table { 2239 compatible = "operating-points-v2"; 2240 2241 opp-100000000 { 2242 opp-hz = /bits/ 64 <100000000>; 2243 required-opps = <&rpmhpd_opp_low_svs>; 2244 opp-peak-kBps = <1800000 400000>; 2245 opp-avg-kBps = <100000 0>; 2246 }; 2247 2248 opp-202000000 { 2249 opp-hz = /bits/ 64 <202000000>; 2250 required-opps = <&rpmhpd_opp_nom>; 2251 opp-peak-kBps = <5400000 1600000>; 2252 opp-avg-kBps = <200000 0>; 2253 }; 2254 }; 2255 2256 }; 2257 2258 usb_1_hsphy: phy@88e3000 { 2259 compatible = "qcom,sc7280-usb-hs-phy", 2260 "qcom,usb-snps-hs-7nm-phy"; 2261 reg = <0 0x088e3000 0 0x400>; 2262 status = "disabled"; 2263 #phy-cells = <0>; 2264 2265 clocks = <&rpmhcc RPMH_CXO_CLK>; 2266 clock-names = "ref"; 2267 2268 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2269 }; 2270 2271 usb_2_hsphy: phy@88e4000 { 2272 compatible = "qcom,sc7280-usb-hs-phy", 2273 "qcom,usb-snps-hs-7nm-phy"; 2274 reg = <0 0x088e4000 0 0x400>; 2275 status = "disabled"; 2276 #phy-cells = <0>; 2277 2278 clocks = <&rpmhcc RPMH_CXO_CLK>; 2279 clock-names = "ref"; 2280 2281 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2282 }; 2283 2284 usb_1_qmpphy: phy-wrapper@88e9000 { 2285 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 2286 "qcom,sm8250-qmp-usb3-dp-phy"; 2287 reg = <0 0x088e9000 0 0x200>, 2288 <0 0x088e8000 0 0x40>, 2289 <0 0x088ea000 0 0x200>; 2290 status = "disabled"; 2291 #address-cells = <2>; 2292 #size-cells = <2>; 2293 ranges; 2294 2295 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2296 <&rpmhcc RPMH_CXO_CLK>, 2297 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2298 clock-names = "aux", "ref_clk_src", "com_aux"; 2299 2300 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2301 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2302 reset-names = "phy", "common"; 2303 2304 usb_1_ssphy: usb3-phy@88e9200 { 2305 reg = <0 0x088e9200 0 0x200>, 2306 <0 0x088e9400 0 0x200>, 2307 <0 0x088e9c00 0 0x400>, 2308 <0 0x088e9600 0 0x200>, 2309 <0 0x088e9800 0 0x200>, 2310 <0 0x088e9a00 0 0x100>; 2311 #clock-cells = <0>; 2312 #phy-cells = <0>; 2313 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2314 clock-names = "pipe0"; 2315 clock-output-names = "usb3_phy_pipe_clk_src"; 2316 }; 2317 2318 dp_phy: dp-phy@88ea200 { 2319 reg = <0 0x088ea200 0 0x200>, 2320 <0 0x088ea400 0 0x200>, 2321 <0 0x088eaa00 0 0x200>, 2322 <0 0x088ea600 0 0x200>, 2323 <0 0x088ea800 0 0x200>; 2324 #phy-cells = <0>; 2325 #clock-cells = <1>; 2326 }; 2327 }; 2328 2329 usb_2: usb@8cf8800 { 2330 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2331 reg = <0 0x08cf8800 0 0x400>; 2332 status = "disabled"; 2333 #address-cells = <2>; 2334 #size-cells = <2>; 2335 ranges; 2336 dma-ranges; 2337 2338 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2339 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2340 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2341 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2342 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 2343 clock-names = "cfg_noc", "core", "iface","mock_utmi", 2344 "sleep"; 2345 2346 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2347 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2348 assigned-clock-rates = <19200000>, <200000000>; 2349 2350 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2351 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 2352 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 2353 interrupt-names = "hs_phy_irq", 2354 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2355 2356 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 2357 2358 resets = <&gcc GCC_USB30_SEC_BCR>; 2359 2360 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 2361 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 2362 interconnect-names = "usb-ddr", "apps-usb"; 2363 2364 usb_2_dwc3: usb@8c00000 { 2365 compatible = "snps,dwc3"; 2366 reg = <0 0x08c00000 0 0xe000>; 2367 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2368 iommus = <&apps_smmu 0xa0 0x0>; 2369 snps,dis_u2_susphy_quirk; 2370 snps,dis_enblslpm_quirk; 2371 phys = <&usb_2_hsphy>; 2372 phy-names = "usb2-phy"; 2373 maximum-speed = "high-speed"; 2374 }; 2375 }; 2376 2377 qspi: spi@88dc000 { 2378 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 2379 reg = <0 0x088dc000 0 0x1000>; 2380 #address-cells = <1>; 2381 #size-cells = <0>; 2382 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2383 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2384 <&gcc GCC_QSPI_CORE_CLK>; 2385 clock-names = "iface", "core"; 2386 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2387 &cnoc2 SLAVE_QSPI_0 0>; 2388 interconnect-names = "qspi-config"; 2389 power-domains = <&rpmhpd SC7280_CX>; 2390 operating-points-v2 = <&qspi_opp_table>; 2391 status = "disabled"; 2392 }; 2393 2394 dc_noc: interconnect@90e0000 { 2395 reg = <0 0x090e0000 0 0x5080>; 2396 compatible = "qcom,sc7280-dc-noc"; 2397 #interconnect-cells = <2>; 2398 qcom,bcm-voters = <&apps_bcm_voter>; 2399 }; 2400 2401 gem_noc: interconnect@9100000 { 2402 reg = <0 0x9100000 0 0xe2200>; 2403 compatible = "qcom,sc7280-gem-noc"; 2404 #interconnect-cells = <2>; 2405 qcom,bcm-voters = <&apps_bcm_voter>; 2406 }; 2407 2408 system-cache-controller@9200000 { 2409 compatible = "qcom,sc7280-llcc"; 2410 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 2411 reg-names = "llcc_base", "llcc_broadcast_base"; 2412 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2413 }; 2414 2415 nsp_noc: interconnect@a0c0000 { 2416 reg = <0 0x0a0c0000 0 0x10000>; 2417 compatible = "qcom,sc7280-nsp-noc"; 2418 #interconnect-cells = <2>; 2419 qcom,bcm-voters = <&apps_bcm_voter>; 2420 }; 2421 2422 usb_1: usb@a6f8800 { 2423 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2424 reg = <0 0x0a6f8800 0 0x400>; 2425 status = "disabled"; 2426 #address-cells = <2>; 2427 #size-cells = <2>; 2428 ranges; 2429 dma-ranges; 2430 2431 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2432 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2433 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2434 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2435 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2436 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2437 "sleep"; 2438 2439 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2440 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2441 assigned-clock-rates = <19200000>, <200000000>; 2442 2443 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2444 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2445 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2446 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2447 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2448 "dm_hs_phy_irq", "ss_phy_irq"; 2449 2450 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 2451 2452 resets = <&gcc GCC_USB30_PRIM_BCR>; 2453 2454 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2455 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 2456 interconnect-names = "usb-ddr", "apps-usb"; 2457 2458 usb_1_dwc3: usb@a600000 { 2459 compatible = "snps,dwc3"; 2460 reg = <0 0x0a600000 0 0xe000>; 2461 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2462 iommus = <&apps_smmu 0xe0 0x0>; 2463 snps,dis_u2_susphy_quirk; 2464 snps,dis_enblslpm_quirk; 2465 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2466 phy-names = "usb2-phy", "usb3-phy"; 2467 maximum-speed = "super-speed"; 2468 }; 2469 }; 2470 2471 videocc: clock-controller@aaf0000 { 2472 compatible = "qcom,sc7280-videocc"; 2473 reg = <0 0xaaf0000 0 0x10000>; 2474 clocks = <&rpmhcc RPMH_CXO_CLK>, 2475 <&rpmhcc RPMH_CXO_CLK_A>; 2476 clock-names = "bi_tcxo", "bi_tcxo_ao"; 2477 #clock-cells = <1>; 2478 #reset-cells = <1>; 2479 #power-domain-cells = <1>; 2480 }; 2481 2482 dispcc: clock-controller@af00000 { 2483 compatible = "qcom,sc7280-dispcc"; 2484 reg = <0 0xaf00000 0 0x20000>; 2485 clocks = <&rpmhcc RPMH_CXO_CLK>, 2486 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2487 <0>, <0>, <0>, <0>, <0>, <0>; 2488 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 2489 "dsi0_phy_pll_out_byteclk", 2490 "dsi0_phy_pll_out_dsiclk", 2491 "dp_phy_pll_link_clk", 2492 "dp_phy_pll_vco_div_clk", 2493 "edp_phy_pll_link_clk", 2494 "edp_phy_pll_vco_div_clk"; 2495 #clock-cells = <1>; 2496 #reset-cells = <1>; 2497 #power-domain-cells = <1>; 2498 }; 2499 2500 pdc: interrupt-controller@b220000 { 2501 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 2502 reg = <0 0x0b220000 0 0x30000>; 2503 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 2504 <55 306 4>, <59 312 3>, <62 374 2>, 2505 <64 434 2>, <66 438 3>, <69 86 1>, 2506 <70 520 54>, <124 609 31>, <155 63 1>, 2507 <156 716 12>; 2508 #interrupt-cells = <2>; 2509 interrupt-parent = <&intc>; 2510 interrupt-controller; 2511 }; 2512 2513 pdc_reset: reset-controller@b5e0000 { 2514 compatible = "qcom,sc7280-pdc-global"; 2515 reg = <0 0x0b5e0000 0 0x20000>; 2516 #reset-cells = <1>; 2517 }; 2518 2519 tsens0: thermal-sensor@c263000 { 2520 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 2521 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2522 <0 0x0c222000 0 0x1ff>; /* SROT */ 2523 #qcom,sensors = <15>; 2524 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2525 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2526 interrupt-names = "uplow","critical"; 2527 #thermal-sensor-cells = <1>; 2528 }; 2529 2530 tsens1: thermal-sensor@c265000 { 2531 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 2532 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2533 <0 0x0c223000 0 0x1ff>; /* SROT */ 2534 #qcom,sensors = <12>; 2535 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2536 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2537 interrupt-names = "uplow","critical"; 2538 #thermal-sensor-cells = <1>; 2539 }; 2540 2541 aoss_reset: reset-controller@c2a0000 { 2542 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 2543 reg = <0 0x0c2a0000 0 0x31000>; 2544 #reset-cells = <1>; 2545 }; 2546 2547 aoss_qmp: power-controller@c300000 { 2548 compatible = "qcom,sc7280-aoss-qmp"; 2549 reg = <0 0x0c300000 0 0x100000>; 2550 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 2551 IPCC_MPROC_SIGNAL_GLINK_QMP 2552 IRQ_TYPE_EDGE_RISING>; 2553 mboxes = <&ipcc IPCC_CLIENT_AOP 2554 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2555 2556 #clock-cells = <0>; 2557 #power-domain-cells = <1>; 2558 }; 2559 2560 spmi_bus: spmi@c440000 { 2561 compatible = "qcom,spmi-pmic-arb"; 2562 reg = <0 0x0c440000 0 0x1100>, 2563 <0 0x0c600000 0 0x2000000>, 2564 <0 0x0e600000 0 0x100000>, 2565 <0 0x0e700000 0 0xa0000>, 2566 <0 0x0c40a000 0 0x26000>; 2567 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2568 interrupt-names = "periph_irq"; 2569 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2570 qcom,ee = <0>; 2571 qcom,channel = <0>; 2572 #address-cells = <1>; 2573 #size-cells = <1>; 2574 interrupt-controller; 2575 #interrupt-cells = <4>; 2576 }; 2577 2578 tlmm: pinctrl@f100000 { 2579 compatible = "qcom,sc7280-pinctrl"; 2580 reg = <0 0x0f100000 0 0x300000>; 2581 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2582 gpio-controller; 2583 #gpio-cells = <2>; 2584 interrupt-controller; 2585 #interrupt-cells = <2>; 2586 gpio-ranges = <&tlmm 0 0 175>; 2587 wakeup-parent = <&pdc>; 2588 2589 qspi_clk: qspi-clk { 2590 pins = "gpio14"; 2591 function = "qspi_clk"; 2592 }; 2593 2594 qspi_cs0: qspi-cs0 { 2595 pins = "gpio15"; 2596 function = "qspi_cs"; 2597 }; 2598 2599 qspi_cs1: qspi-cs1 { 2600 pins = "gpio19"; 2601 function = "qspi_cs"; 2602 }; 2603 2604 qspi_data01: qspi-data01 { 2605 pins = "gpio12", "gpio13"; 2606 function = "qspi_data"; 2607 }; 2608 2609 qspi_data12: qspi-data12 { 2610 pins = "gpio16", "gpio17"; 2611 function = "qspi_data"; 2612 }; 2613 2614 qup_i2c0_data_clk: qup-i2c0-data-clk { 2615 pins = "gpio0", "gpio1"; 2616 function = "qup00"; 2617 }; 2618 2619 qup_i2c1_data_clk: qup-i2c1-data-clk { 2620 pins = "gpio4", "gpio5"; 2621 function = "qup01"; 2622 }; 2623 2624 qup_i2c2_data_clk: qup-i2c2-data-clk { 2625 pins = "gpio8", "gpio9"; 2626 function = "qup02"; 2627 }; 2628 2629 qup_i2c3_data_clk: qup-i2c3-data-clk { 2630 pins = "gpio12", "gpio13"; 2631 function = "qup03"; 2632 }; 2633 2634 qup_i2c4_data_clk: qup-i2c4-data-clk { 2635 pins = "gpio16", "gpio17"; 2636 function = "qup04"; 2637 }; 2638 2639 qup_i2c5_data_clk: qup-i2c5-data-clk { 2640 pins = "gpio20", "gpio21"; 2641 function = "qup05"; 2642 }; 2643 2644 qup_i2c6_data_clk: qup-i2c6-data-clk { 2645 pins = "gpio24", "gpio25"; 2646 function = "qup06"; 2647 }; 2648 2649 qup_i2c7_data_clk: qup-i2c7-data-clk { 2650 pins = "gpio28", "gpio29"; 2651 function = "qup07"; 2652 }; 2653 2654 qup_i2c8_data_clk: qup-i2c8-data-clk { 2655 pins = "gpio32", "gpio33"; 2656 function = "qup10"; 2657 }; 2658 2659 qup_i2c9_data_clk: qup-i2c9-data-clk { 2660 pins = "gpio36", "gpio37"; 2661 function = "qup11"; 2662 }; 2663 2664 qup_i2c10_data_clk: qup-i2c10-data-clk { 2665 pins = "gpio40", "gpio41"; 2666 function = "qup12"; 2667 }; 2668 2669 qup_i2c11_data_clk: qup-i2c11-data-clk { 2670 pins = "gpio44", "gpio45"; 2671 function = "qup13"; 2672 }; 2673 2674 qup_i2c12_data_clk: qup-i2c12-data-clk { 2675 pins = "gpio48", "gpio49"; 2676 function = "qup14"; 2677 }; 2678 2679 qup_i2c13_data_clk: qup-i2c13-data-clk { 2680 pins = "gpio52", "gpio53"; 2681 function = "qup15"; 2682 }; 2683 2684 qup_i2c14_data_clk: qup-i2c14-data-clk { 2685 pins = "gpio56", "gpio57"; 2686 function = "qup16"; 2687 }; 2688 2689 qup_i2c15_data_clk: qup-i2c15-data-clk { 2690 pins = "gpio60", "gpio61"; 2691 function = "qup17"; 2692 }; 2693 2694 qup_spi0_data_clk: qup-spi0-data-clk { 2695 pins = "gpio0", "gpio1", "gpio2"; 2696 function = "qup00"; 2697 }; 2698 2699 qup_spi0_cs: qup-spi0-cs { 2700 pins = "gpio3"; 2701 function = "qup00"; 2702 }; 2703 2704 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 2705 pins = "gpio3"; 2706 function = "gpio"; 2707 }; 2708 2709 qup_spi1_data_clk: qup-spi1-data-clk { 2710 pins = "gpio4", "gpio5", "gpio6"; 2711 function = "qup01"; 2712 }; 2713 2714 qup_spi1_cs: qup-spi1-cs { 2715 pins = "gpio7"; 2716 function = "qup01"; 2717 }; 2718 2719 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 2720 pins = "gpio7"; 2721 function = "gpio"; 2722 }; 2723 2724 qup_spi2_data_clk: qup-spi2-data-clk { 2725 pins = "gpio8", "gpio9", "gpio10"; 2726 function = "qup02"; 2727 }; 2728 2729 qup_spi2_cs: qup-spi2-cs { 2730 pins = "gpio11"; 2731 function = "qup02"; 2732 }; 2733 2734 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 2735 pins = "gpio11"; 2736 function = "gpio"; 2737 }; 2738 2739 qup_spi3_data_clk: qup-spi3-data-clk { 2740 pins = "gpio12", "gpio13", "gpio14"; 2741 function = "qup03"; 2742 }; 2743 2744 qup_spi3_cs: qup-spi3-cs { 2745 pins = "gpio15"; 2746 function = "qup03"; 2747 }; 2748 2749 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 2750 pins = "gpio15"; 2751 function = "gpio"; 2752 }; 2753 2754 qup_spi4_data_clk: qup-spi4-data-clk { 2755 pins = "gpio16", "gpio17", "gpio18"; 2756 function = "qup04"; 2757 }; 2758 2759 qup_spi4_cs: qup-spi4-cs { 2760 pins = "gpio19"; 2761 function = "qup04"; 2762 }; 2763 2764 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 2765 pins = "gpio19"; 2766 function = "gpio"; 2767 }; 2768 2769 qup_spi5_data_clk: qup-spi5-data-clk { 2770 pins = "gpio20", "gpio21", "gpio22"; 2771 function = "qup05"; 2772 }; 2773 2774 qup_spi5_cs: qup-spi5-cs { 2775 pins = "gpio23"; 2776 function = "qup05"; 2777 }; 2778 2779 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 2780 pins = "gpio23"; 2781 function = "gpio"; 2782 }; 2783 2784 qup_spi6_data_clk: qup-spi6-data-clk { 2785 pins = "gpio24", "gpio25", "gpio26"; 2786 function = "qup06"; 2787 }; 2788 2789 qup_spi6_cs: qup-spi6-cs { 2790 pins = "gpio27"; 2791 function = "qup06"; 2792 }; 2793 2794 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 2795 pins = "gpio27"; 2796 function = "gpio"; 2797 }; 2798 2799 qup_spi7_data_clk: qup-spi7-data-clk { 2800 pins = "gpio28", "gpio29", "gpio30"; 2801 function = "qup07"; 2802 }; 2803 2804 qup_spi7_cs: qup-spi7-cs { 2805 pins = "gpio31"; 2806 function = "qup07"; 2807 }; 2808 2809 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 2810 pins = "gpio31"; 2811 function = "gpio"; 2812 }; 2813 2814 qup_spi8_data_clk: qup-spi8-data-clk { 2815 pins = "gpio32", "gpio33", "gpio34"; 2816 function = "qup10"; 2817 }; 2818 2819 qup_spi8_cs: qup-spi8-cs { 2820 pins = "gpio35"; 2821 function = "qup10"; 2822 }; 2823 2824 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 2825 pins = "gpio35"; 2826 function = "gpio"; 2827 }; 2828 2829 qup_spi9_data_clk: qup-spi9-data-clk { 2830 pins = "gpio36", "gpio37", "gpio38"; 2831 function = "qup11"; 2832 }; 2833 2834 qup_spi9_cs: qup-spi9-cs { 2835 pins = "gpio39"; 2836 function = "qup11"; 2837 }; 2838 2839 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 2840 pins = "gpio39"; 2841 function = "gpio"; 2842 }; 2843 2844 qup_spi10_data_clk: qup-spi10-data-clk { 2845 pins = "gpio40", "gpio41", "gpio42"; 2846 function = "qup12"; 2847 }; 2848 2849 qup_spi10_cs: qup-spi10-cs { 2850 pins = "gpio43"; 2851 function = "qup12"; 2852 }; 2853 2854 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 2855 pins = "gpio43"; 2856 function = "gpio"; 2857 }; 2858 2859 qup_spi11_data_clk: qup-spi11-data-clk { 2860 pins = "gpio44", "gpio45", "gpio46"; 2861 function = "qup13"; 2862 }; 2863 2864 qup_spi11_cs: qup-spi11-cs { 2865 pins = "gpio47"; 2866 function = "qup13"; 2867 }; 2868 2869 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 2870 pins = "gpio47"; 2871 function = "gpio"; 2872 }; 2873 2874 qup_spi12_data_clk: qup-spi12-data-clk { 2875 pins = "gpio48", "gpio49", "gpio50"; 2876 function = "qup14"; 2877 }; 2878 2879 qup_spi12_cs: qup-spi12-cs { 2880 pins = "gpio51"; 2881 function = "qup14"; 2882 }; 2883 2884 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 2885 pins = "gpio51"; 2886 function = "gpio"; 2887 }; 2888 2889 qup_spi13_data_clk: qup-spi13-data-clk { 2890 pins = "gpio52", "gpio53", "gpio54"; 2891 function = "qup15"; 2892 }; 2893 2894 qup_spi13_cs: qup-spi13-cs { 2895 pins = "gpio55"; 2896 function = "qup15"; 2897 }; 2898 2899 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 2900 pins = "gpio55"; 2901 function = "gpio"; 2902 }; 2903 2904 qup_spi14_data_clk: qup-spi14-data-clk { 2905 pins = "gpio56", "gpio57", "gpio58"; 2906 function = "qup16"; 2907 }; 2908 2909 qup_spi14_cs: qup-spi14-cs { 2910 pins = "gpio59"; 2911 function = "qup16"; 2912 }; 2913 2914 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 2915 pins = "gpio59"; 2916 function = "gpio"; 2917 }; 2918 2919 qup_spi15_data_clk: qup-spi15-data-clk { 2920 pins = "gpio60", "gpio61", "gpio62"; 2921 function = "qup17"; 2922 }; 2923 2924 qup_spi15_cs: qup-spi15-cs { 2925 pins = "gpio63"; 2926 function = "qup17"; 2927 }; 2928 2929 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 2930 pins = "gpio63"; 2931 function = "gpio"; 2932 }; 2933 2934 qup_uart0_cts: qup-uart0-cts { 2935 pins = "gpio0"; 2936 function = "qup00"; 2937 }; 2938 2939 qup_uart0_rts: qup-uart0-rts { 2940 pins = "gpio1"; 2941 function = "qup00"; 2942 }; 2943 2944 qup_uart0_tx: qup-uart0-tx { 2945 pins = "gpio2"; 2946 function = "qup00"; 2947 }; 2948 2949 qup_uart0_rx: qup-uart0-rx { 2950 pins = "gpio3"; 2951 function = "qup00"; 2952 }; 2953 2954 qup_uart1_cts: qup-uart1-cts { 2955 pins = "gpio4"; 2956 function = "qup01"; 2957 }; 2958 2959 qup_uart1_rts: qup-uart1-rts { 2960 pins = "gpio5"; 2961 function = "qup01"; 2962 }; 2963 2964 qup_uart1_tx: qup-uart1-tx { 2965 pins = "gpio6"; 2966 function = "qup01"; 2967 }; 2968 2969 qup_uart1_rx: qup-uart1-rx { 2970 pins = "gpio7"; 2971 function = "qup01"; 2972 }; 2973 2974 qup_uart2_cts: qup-uart2-cts { 2975 pins = "gpio8"; 2976 function = "qup02"; 2977 }; 2978 2979 qup_uart2_rts: qup-uart2-rts { 2980 pins = "gpio9"; 2981 function = "qup02"; 2982 }; 2983 2984 qup_uart2_tx: qup-uart2-tx { 2985 pins = "gpio10"; 2986 function = "qup02"; 2987 }; 2988 2989 qup_uart2_rx: qup-uart2-rx { 2990 pins = "gpio11"; 2991 function = "qup02"; 2992 }; 2993 2994 qup_uart3_cts: qup-uart3-cts { 2995 pins = "gpio12"; 2996 function = "qup03"; 2997 }; 2998 2999 qup_uart3_rts: qup-uart3-rts { 3000 pins = "gpio13"; 3001 function = "qup03"; 3002 }; 3003 3004 qup_uart3_tx: qup-uart3-tx { 3005 pins = "gpio14"; 3006 function = "qup03"; 3007 }; 3008 3009 qup_uart3_rx: qup-uart3-rx { 3010 pins = "gpio15"; 3011 function = "qup03"; 3012 }; 3013 3014 qup_uart4_cts: qup-uart4-cts { 3015 pins = "gpio16"; 3016 function = "qup04"; 3017 }; 3018 3019 qup_uart4_rts: qup-uart4-rts { 3020 pins = "gpio17"; 3021 function = "qup04"; 3022 }; 3023 3024 qup_uart4_tx: qup-uart4-tx { 3025 pins = "gpio18"; 3026 function = "qup04"; 3027 }; 3028 3029 qup_uart4_rx: qup-uart4-rx { 3030 pins = "gpio19"; 3031 function = "qup04"; 3032 }; 3033 3034 qup_uart5_cts: qup-uart5-cts { 3035 pins = "gpio20"; 3036 function = "qup05"; 3037 }; 3038 3039 qup_uart5_rts: qup-uart5-rts { 3040 pins = "gpio21"; 3041 function = "qup05"; 3042 }; 3043 3044 qup_uart5_tx: qup-uart5-tx { 3045 pins = "gpio22"; 3046 function = "qup05"; 3047 }; 3048 3049 qup_uart5_rx: qup-uart5-rx { 3050 pins = "gpio23"; 3051 function = "qup05"; 3052 }; 3053 3054 qup_uart6_cts: qup-uart6-cts { 3055 pins = "gpio24"; 3056 function = "qup06"; 3057 }; 3058 3059 qup_uart6_rts: qup-uart6-rts { 3060 pins = "gpio25"; 3061 function = "qup06"; 3062 }; 3063 3064 qup_uart6_tx: qup-uart6-tx { 3065 pins = "gpio26"; 3066 function = "qup06"; 3067 }; 3068 3069 qup_uart6_rx: qup-uart6-rx { 3070 pins = "gpio27"; 3071 function = "qup06"; 3072 }; 3073 3074 qup_uart7_cts: qup-uart7-cts { 3075 pins = "gpio28"; 3076 function = "qup07"; 3077 }; 3078 3079 qup_uart7_rts: qup-uart7-rts { 3080 pins = "gpio29"; 3081 function = "qup07"; 3082 }; 3083 3084 qup_uart7_tx: qup-uart7-tx { 3085 pins = "gpio30"; 3086 function = "qup07"; 3087 }; 3088 3089 qup_uart7_rx: qup-uart7-rx { 3090 pins = "gpio31"; 3091 function = "qup07"; 3092 }; 3093 3094 sdc1_on: sdc1-on { 3095 clk { 3096 pins = "sdc1_clk"; 3097 }; 3098 3099 cmd { 3100 pins = "sdc1_cmd"; 3101 }; 3102 3103 data { 3104 pins = "sdc1_data"; 3105 }; 3106 3107 rclk { 3108 pins = "sdc1_rclk"; 3109 }; 3110 }; 3111 3112 sdc1_off: sdc1-off { 3113 clk { 3114 pins = "sdc1_clk"; 3115 drive-strength = <2>; 3116 bias-bus-hold; 3117 }; 3118 3119 cmd { 3120 pins = "sdc1_cmd"; 3121 drive-strength = <2>; 3122 bias-bus-hold; 3123 }; 3124 3125 data { 3126 pins = "sdc1_data"; 3127 drive-strength = <2>; 3128 bias-bus-hold; 3129 }; 3130 3131 rclk { 3132 pins = "sdc1_rclk"; 3133 bias-bus-hold; 3134 }; 3135 }; 3136 3137 sdc2_on: sdc2-on { 3138 clk { 3139 pins = "sdc2_clk"; 3140 }; 3141 3142 cmd { 3143 pins = "sdc2_cmd"; 3144 }; 3145 3146 data { 3147 pins = "sdc2_data"; 3148 }; 3149 }; 3150 3151 sdc2_off: sdc2-off { 3152 clk { 3153 pins = "sdc2_clk"; 3154 drive-strength = <2>; 3155 bias-bus-hold; 3156 }; 3157 3158 cmd { 3159 pins ="sdc2_cmd"; 3160 drive-strength = <2>; 3161 bias-bus-hold; 3162 }; 3163 3164 data { 3165 pins ="sdc2_data"; 3166 drive-strength = <2>; 3167 bias-bus-hold; 3168 }; 3169 }; 3170 3171 qup_uart8_cts: qup-uart8-cts { 3172 pins = "gpio32"; 3173 function = "qup10"; 3174 }; 3175 3176 qup_uart8_rts: qup-uart8-rts { 3177 pins = "gpio33"; 3178 function = "qup10"; 3179 }; 3180 3181 qup_uart8_tx: qup-uart8-tx { 3182 pins = "gpio34"; 3183 function = "qup10"; 3184 }; 3185 3186 qup_uart8_rx: qup-uart8-rx { 3187 pins = "gpio35"; 3188 function = "qup10"; 3189 }; 3190 3191 qup_uart9_cts: qup-uart9-cts { 3192 pins = "gpio36"; 3193 function = "qup11"; 3194 }; 3195 3196 qup_uart9_rts: qup-uart9-rts { 3197 pins = "gpio37"; 3198 function = "qup11"; 3199 }; 3200 3201 qup_uart9_tx: qup-uart9-tx { 3202 pins = "gpio38"; 3203 function = "qup11"; 3204 }; 3205 3206 qup_uart9_rx: qup-uart9-rx { 3207 pins = "gpio39"; 3208 function = "qup11"; 3209 }; 3210 3211 qup_uart10_cts: qup-uart10-cts { 3212 pins = "gpio40"; 3213 function = "qup12"; 3214 }; 3215 3216 qup_uart10_rts: qup-uart10-rts { 3217 pins = "gpio41"; 3218 function = "qup12"; 3219 }; 3220 3221 qup_uart10_tx: qup-uart10-tx { 3222 pins = "gpio42"; 3223 function = "qup12"; 3224 }; 3225 3226 qup_uart10_rx: qup-uart10-rx { 3227 pins = "gpio43"; 3228 function = "qup12"; 3229 }; 3230 3231 qup_uart11_cts: qup-uart11-cts { 3232 pins = "gpio44"; 3233 function = "qup13"; 3234 }; 3235 3236 qup_uart11_rts: qup-uart11-rts { 3237 pins = "gpio45"; 3238 function = "qup13"; 3239 }; 3240 3241 qup_uart11_tx: qup-uart11-tx { 3242 pins = "gpio46"; 3243 function = "qup13"; 3244 }; 3245 3246 qup_uart11_rx: qup-uart11-rx { 3247 pins = "gpio47"; 3248 function = "qup13"; 3249 }; 3250 3251 qup_uart12_cts: qup-uart12-cts { 3252 pins = "gpio48"; 3253 function = "qup14"; 3254 }; 3255 3256 qup_uart12_rts: qup-uart12-rts { 3257 pins = "gpio49"; 3258 function = "qup14"; 3259 }; 3260 3261 qup_uart12_tx: qup-uart12-tx { 3262 pins = "gpio50"; 3263 function = "qup14"; 3264 }; 3265 3266 qup_uart12_rx: qup-uart12-rx { 3267 pins = "gpio51"; 3268 function = "qup14"; 3269 }; 3270 3271 qup_uart13_cts: qup-uart13-cts { 3272 pins = "gpio52"; 3273 function = "qup15"; 3274 }; 3275 3276 qup_uart13_rts: qup-uart13-rts { 3277 pins = "gpio53"; 3278 function = "qup15"; 3279 }; 3280 3281 qup_uart13_tx: qup-uart13-tx { 3282 pins = "gpio54"; 3283 function = "qup15"; 3284 }; 3285 3286 qup_uart13_rx: qup-uart13-rx { 3287 pins = "gpio55"; 3288 function = "qup15"; 3289 }; 3290 3291 qup_uart14_cts: qup-uart14-cts { 3292 pins = "gpio56"; 3293 function = "qup16"; 3294 }; 3295 3296 qup_uart14_rts: qup-uart14-rts { 3297 pins = "gpio57"; 3298 function = "qup16"; 3299 }; 3300 3301 qup_uart14_tx: qup-uart14-tx { 3302 pins = "gpio58"; 3303 function = "qup16"; 3304 }; 3305 3306 qup_uart14_rx: qup-uart14-rx { 3307 pins = "gpio59"; 3308 function = "qup16"; 3309 }; 3310 3311 qup_uart15_cts: qup-uart15-cts { 3312 pins = "gpio60"; 3313 function = "qup17"; 3314 }; 3315 3316 qup_uart15_rts: qup-uart15-rts { 3317 pins = "gpio61"; 3318 function = "qup17"; 3319 }; 3320 3321 qup_uart15_tx: qup-uart15-tx { 3322 pins = "gpio62"; 3323 function = "qup17"; 3324 }; 3325 3326 qup_uart15_rx: qup-uart15-rx { 3327 pins = "gpio63"; 3328 function = "qup17"; 3329 }; 3330 }; 3331 3332 apps_smmu: iommu@15000000 { 3333 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 3334 reg = <0 0x15000000 0 0x100000>; 3335 #iommu-cells = <2>; 3336 #global-interrupts = <1>; 3337 dma-coherent; 3338 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3339 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3340 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3341 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3342 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3343 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3344 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3345 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3346 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3347 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3348 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3349 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3350 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3351 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3352 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3353 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3354 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3355 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3356 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3357 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3358 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3359 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3360 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3361 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3362 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3363 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3364 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3365 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3366 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3367 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3368 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3369 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3370 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3371 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3372 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3373 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3374 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3375 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3377 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3378 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3379 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3380 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3381 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3382 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3383 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3384 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3385 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3386 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3387 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3388 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3389 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3390 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3391 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3392 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3393 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3394 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3395 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3396 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3397 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3398 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3399 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3400 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3401 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3402 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3403 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3404 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3405 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3406 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3407 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3408 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3409 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3410 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3411 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3412 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3413 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3414 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3415 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3416 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3417 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3418 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 3419 }; 3420 3421 intc: interrupt-controller@17a00000 { 3422 compatible = "arm,gic-v3"; 3423 #address-cells = <2>; 3424 #size-cells = <2>; 3425 ranges; 3426 #interrupt-cells = <3>; 3427 interrupt-controller; 3428 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3429 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3430 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 3431 3432 gic-its@17a40000 { 3433 compatible = "arm,gic-v3-its"; 3434 msi-controller; 3435 #msi-cells = <1>; 3436 reg = <0 0x17a40000 0 0x20000>; 3437 status = "disabled"; 3438 }; 3439 }; 3440 3441 watchdog@17c10000 { 3442 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 3443 reg = <0 0x17c10000 0 0x1000>; 3444 clocks = <&sleep_clk>; 3445 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3446 }; 3447 3448 timer@17c20000 { 3449 #address-cells = <2>; 3450 #size-cells = <2>; 3451 ranges; 3452 compatible = "arm,armv7-timer-mem"; 3453 reg = <0 0x17c20000 0 0x1000>; 3454 3455 frame@17c21000 { 3456 frame-number = <0>; 3457 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3458 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3459 reg = <0 0x17c21000 0 0x1000>, 3460 <0 0x17c22000 0 0x1000>; 3461 }; 3462 3463 frame@17c23000 { 3464 frame-number = <1>; 3465 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3466 reg = <0 0x17c23000 0 0x1000>; 3467 status = "disabled"; 3468 }; 3469 3470 frame@17c25000 { 3471 frame-number = <2>; 3472 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3473 reg = <0 0x17c25000 0 0x1000>; 3474 status = "disabled"; 3475 }; 3476 3477 frame@17c27000 { 3478 frame-number = <3>; 3479 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3480 reg = <0 0x17c27000 0 0x1000>; 3481 status = "disabled"; 3482 }; 3483 3484 frame@17c29000 { 3485 frame-number = <4>; 3486 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3487 reg = <0 0x17c29000 0 0x1000>; 3488 status = "disabled"; 3489 }; 3490 3491 frame@17c2b000 { 3492 frame-number = <5>; 3493 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3494 reg = <0 0x17c2b000 0 0x1000>; 3495 status = "disabled"; 3496 }; 3497 3498 frame@17c2d000 { 3499 frame-number = <6>; 3500 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3501 reg = <0 0x17c2d000 0 0x1000>; 3502 status = "disabled"; 3503 }; 3504 }; 3505 3506 apps_rsc: rsc@18200000 { 3507 compatible = "qcom,rpmh-rsc"; 3508 reg = <0 0x18200000 0 0x10000>, 3509 <0 0x18210000 0 0x10000>, 3510 <0 0x18220000 0 0x10000>; 3511 reg-names = "drv-0", "drv-1", "drv-2"; 3512 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3513 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3514 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3515 qcom,tcs-offset = <0xd00>; 3516 qcom,drv-id = <2>; 3517 qcom,tcs-config = <ACTIVE_TCS 2>, 3518 <SLEEP_TCS 3>, 3519 <WAKE_TCS 3>, 3520 <CONTROL_TCS 1>; 3521 3522 apps_bcm_voter: bcm-voter { 3523 compatible = "qcom,bcm-voter"; 3524 }; 3525 3526 rpmhpd: power-controller { 3527 compatible = "qcom,sc7280-rpmhpd"; 3528 #power-domain-cells = <1>; 3529 operating-points-v2 = <&rpmhpd_opp_table>; 3530 3531 rpmhpd_opp_table: opp-table { 3532 compatible = "operating-points-v2"; 3533 3534 rpmhpd_opp_ret: opp1 { 3535 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3536 }; 3537 3538 rpmhpd_opp_low_svs: opp2 { 3539 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3540 }; 3541 3542 rpmhpd_opp_svs: opp3 { 3543 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3544 }; 3545 3546 rpmhpd_opp_svs_l1: opp4 { 3547 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3548 }; 3549 3550 rpmhpd_opp_svs_l2: opp5 { 3551 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3552 }; 3553 3554 rpmhpd_opp_nom: opp6 { 3555 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3556 }; 3557 3558 rpmhpd_opp_nom_l1: opp7 { 3559 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3560 }; 3561 3562 rpmhpd_opp_turbo: opp8 { 3563 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3564 }; 3565 3566 rpmhpd_opp_turbo_l1: opp9 { 3567 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3568 }; 3569 }; 3570 }; 3571 3572 rpmhcc: clock-controller { 3573 compatible = "qcom,sc7280-rpmh-clk"; 3574 clocks = <&xo_board>; 3575 clock-names = "xo"; 3576 #clock-cells = <1>; 3577 }; 3578 }; 3579 3580 cpufreq_hw: cpufreq@18591000 { 3581 compatible = "qcom,cpufreq-epss"; 3582 reg = <0 0x18591100 0 0x900>, 3583 <0 0x18592100 0 0x900>, 3584 <0 0x18593100 0 0x900>; 3585 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3586 clock-names = "xo", "alternate"; 3587 #freq-domain-cells = <1>; 3588 }; 3589 }; 3590 3591 thermal_zones: thermal-zones { 3592 cpu0-thermal { 3593 polling-delay-passive = <250>; 3594 polling-delay = <0>; 3595 3596 thermal-sensors = <&tsens0 1>; 3597 3598 trips { 3599 cpu0_alert0: trip-point0 { 3600 temperature = <90000>; 3601 hysteresis = <2000>; 3602 type = "passive"; 3603 }; 3604 3605 cpu0_alert1: trip-point1 { 3606 temperature = <95000>; 3607 hysteresis = <2000>; 3608 type = "passive"; 3609 }; 3610 3611 cpu0_crit: cpu-crit { 3612 temperature = <110000>; 3613 hysteresis = <0>; 3614 type = "critical"; 3615 }; 3616 }; 3617 3618 cooling-maps { 3619 map0 { 3620 trip = <&cpu0_alert0>; 3621 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3622 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3623 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3624 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3625 }; 3626 map1 { 3627 trip = <&cpu0_alert1>; 3628 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3629 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3630 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3631 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3632 }; 3633 }; 3634 }; 3635 3636 cpu1-thermal { 3637 polling-delay-passive = <250>; 3638 polling-delay = <0>; 3639 3640 thermal-sensors = <&tsens0 2>; 3641 3642 trips { 3643 cpu1_alert0: trip-point0 { 3644 temperature = <90000>; 3645 hysteresis = <2000>; 3646 type = "passive"; 3647 }; 3648 3649 cpu1_alert1: trip-point1 { 3650 temperature = <95000>; 3651 hysteresis = <2000>; 3652 type = "passive"; 3653 }; 3654 3655 cpu1_crit: cpu-crit { 3656 temperature = <110000>; 3657 hysteresis = <0>; 3658 type = "critical"; 3659 }; 3660 }; 3661 3662 cooling-maps { 3663 map0 { 3664 trip = <&cpu1_alert0>; 3665 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3666 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3667 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3668 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3669 }; 3670 map1 { 3671 trip = <&cpu1_alert1>; 3672 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3673 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3674 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3675 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3676 }; 3677 }; 3678 }; 3679 3680 cpu2-thermal { 3681 polling-delay-passive = <250>; 3682 polling-delay = <0>; 3683 3684 thermal-sensors = <&tsens0 3>; 3685 3686 trips { 3687 cpu2_alert0: trip-point0 { 3688 temperature = <90000>; 3689 hysteresis = <2000>; 3690 type = "passive"; 3691 }; 3692 3693 cpu2_alert1: trip-point1 { 3694 temperature = <95000>; 3695 hysteresis = <2000>; 3696 type = "passive"; 3697 }; 3698 3699 cpu2_crit: cpu-crit { 3700 temperature = <110000>; 3701 hysteresis = <0>; 3702 type = "critical"; 3703 }; 3704 }; 3705 3706 cooling-maps { 3707 map0 { 3708 trip = <&cpu2_alert0>; 3709 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3710 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3711 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3712 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3713 }; 3714 map1 { 3715 trip = <&cpu2_alert1>; 3716 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3717 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3718 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3719 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3720 }; 3721 }; 3722 }; 3723 3724 cpu3-thermal { 3725 polling-delay-passive = <250>; 3726 polling-delay = <0>; 3727 3728 thermal-sensors = <&tsens0 4>; 3729 3730 trips { 3731 cpu3_alert0: trip-point0 { 3732 temperature = <90000>; 3733 hysteresis = <2000>; 3734 type = "passive"; 3735 }; 3736 3737 cpu3_alert1: trip-point1 { 3738 temperature = <95000>; 3739 hysteresis = <2000>; 3740 type = "passive"; 3741 }; 3742 3743 cpu3_crit: cpu-crit { 3744 temperature = <110000>; 3745 hysteresis = <0>; 3746 type = "critical"; 3747 }; 3748 }; 3749 3750 cooling-maps { 3751 map0 { 3752 trip = <&cpu3_alert0>; 3753 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3754 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3755 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3756 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3757 }; 3758 map1 { 3759 trip = <&cpu3_alert1>; 3760 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3761 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3762 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3763 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3764 }; 3765 }; 3766 }; 3767 3768 cpu4-thermal { 3769 polling-delay-passive = <250>; 3770 polling-delay = <0>; 3771 3772 thermal-sensors = <&tsens0 7>; 3773 3774 trips { 3775 cpu4_alert0: trip-point0 { 3776 temperature = <90000>; 3777 hysteresis = <2000>; 3778 type = "passive"; 3779 }; 3780 3781 cpu4_alert1: trip-point1 { 3782 temperature = <95000>; 3783 hysteresis = <2000>; 3784 type = "passive"; 3785 }; 3786 3787 cpu4_crit: cpu-crit { 3788 temperature = <110000>; 3789 hysteresis = <0>; 3790 type = "critical"; 3791 }; 3792 }; 3793 3794 cooling-maps { 3795 map0 { 3796 trip = <&cpu4_alert0>; 3797 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3798 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3799 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3800 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3801 }; 3802 map1 { 3803 trip = <&cpu4_alert1>; 3804 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3805 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3806 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3807 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3808 }; 3809 }; 3810 }; 3811 3812 cpu5-thermal { 3813 polling-delay-passive = <250>; 3814 polling-delay = <0>; 3815 3816 thermal-sensors = <&tsens0 8>; 3817 3818 trips { 3819 cpu5_alert0: trip-point0 { 3820 temperature = <90000>; 3821 hysteresis = <2000>; 3822 type = "passive"; 3823 }; 3824 3825 cpu5_alert1: trip-point1 { 3826 temperature = <95000>; 3827 hysteresis = <2000>; 3828 type = "passive"; 3829 }; 3830 3831 cpu5_crit: cpu-crit { 3832 temperature = <110000>; 3833 hysteresis = <0>; 3834 type = "critical"; 3835 }; 3836 }; 3837 3838 cooling-maps { 3839 map0 { 3840 trip = <&cpu5_alert0>; 3841 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3842 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3843 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3844 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3845 }; 3846 map1 { 3847 trip = <&cpu5_alert1>; 3848 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3849 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3850 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3851 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3852 }; 3853 }; 3854 }; 3855 3856 cpu6-thermal { 3857 polling-delay-passive = <250>; 3858 polling-delay = <0>; 3859 3860 thermal-sensors = <&tsens0 9>; 3861 3862 trips { 3863 cpu6_alert0: trip-point0 { 3864 temperature = <90000>; 3865 hysteresis = <2000>; 3866 type = "passive"; 3867 }; 3868 3869 cpu6_alert1: trip-point1 { 3870 temperature = <95000>; 3871 hysteresis = <2000>; 3872 type = "passive"; 3873 }; 3874 3875 cpu6_crit: cpu-crit { 3876 temperature = <110000>; 3877 hysteresis = <0>; 3878 type = "critical"; 3879 }; 3880 }; 3881 3882 cooling-maps { 3883 map0 { 3884 trip = <&cpu6_alert0>; 3885 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3886 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3887 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3888 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3889 }; 3890 map1 { 3891 trip = <&cpu6_alert1>; 3892 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3893 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3894 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3895 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3896 }; 3897 }; 3898 }; 3899 3900 cpu7-thermal { 3901 polling-delay-passive = <250>; 3902 polling-delay = <0>; 3903 3904 thermal-sensors = <&tsens0 10>; 3905 3906 trips { 3907 cpu7_alert0: trip-point0 { 3908 temperature = <90000>; 3909 hysteresis = <2000>; 3910 type = "passive"; 3911 }; 3912 3913 cpu7_alert1: trip-point1 { 3914 temperature = <95000>; 3915 hysteresis = <2000>; 3916 type = "passive"; 3917 }; 3918 3919 cpu7_crit: cpu-crit { 3920 temperature = <110000>; 3921 hysteresis = <0>; 3922 type = "critical"; 3923 }; 3924 }; 3925 3926 cooling-maps { 3927 map0 { 3928 trip = <&cpu7_alert0>; 3929 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3930 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3931 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3932 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3933 }; 3934 map1 { 3935 trip = <&cpu7_alert1>; 3936 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3937 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3938 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3939 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3940 }; 3941 }; 3942 }; 3943 3944 cpu8-thermal { 3945 polling-delay-passive = <250>; 3946 polling-delay = <0>; 3947 3948 thermal-sensors = <&tsens0 11>; 3949 3950 trips { 3951 cpu8_alert0: trip-point0 { 3952 temperature = <90000>; 3953 hysteresis = <2000>; 3954 type = "passive"; 3955 }; 3956 3957 cpu8_alert1: trip-point1 { 3958 temperature = <95000>; 3959 hysteresis = <2000>; 3960 type = "passive"; 3961 }; 3962 3963 cpu8_crit: cpu-crit { 3964 temperature = <110000>; 3965 hysteresis = <0>; 3966 type = "critical"; 3967 }; 3968 }; 3969 3970 cooling-maps { 3971 map0 { 3972 trip = <&cpu8_alert0>; 3973 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3974 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3975 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3976 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3977 }; 3978 map1 { 3979 trip = <&cpu8_alert1>; 3980 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3981 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3982 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3983 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3984 }; 3985 }; 3986 }; 3987 3988 cpu9-thermal { 3989 polling-delay-passive = <250>; 3990 polling-delay = <0>; 3991 3992 thermal-sensors = <&tsens0 12>; 3993 3994 trips { 3995 cpu9_alert0: trip-point0 { 3996 temperature = <90000>; 3997 hysteresis = <2000>; 3998 type = "passive"; 3999 }; 4000 4001 cpu9_alert1: trip-point1 { 4002 temperature = <95000>; 4003 hysteresis = <2000>; 4004 type = "passive"; 4005 }; 4006 4007 cpu9_crit: cpu-crit { 4008 temperature = <110000>; 4009 hysteresis = <0>; 4010 type = "critical"; 4011 }; 4012 }; 4013 4014 cooling-maps { 4015 map0 { 4016 trip = <&cpu9_alert0>; 4017 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4018 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4019 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4020 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4021 }; 4022 map1 { 4023 trip = <&cpu9_alert1>; 4024 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4025 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4026 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4027 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4028 }; 4029 }; 4030 }; 4031 4032 cpu10-thermal { 4033 polling-delay-passive = <250>; 4034 polling-delay = <0>; 4035 4036 thermal-sensors = <&tsens0 13>; 4037 4038 trips { 4039 cpu10_alert0: trip-point0 { 4040 temperature = <90000>; 4041 hysteresis = <2000>; 4042 type = "passive"; 4043 }; 4044 4045 cpu10_alert1: trip-point1 { 4046 temperature = <95000>; 4047 hysteresis = <2000>; 4048 type = "passive"; 4049 }; 4050 4051 cpu10_crit: cpu-crit { 4052 temperature = <110000>; 4053 hysteresis = <0>; 4054 type = "critical"; 4055 }; 4056 }; 4057 4058 cooling-maps { 4059 map0 { 4060 trip = <&cpu10_alert0>; 4061 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4062 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4063 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4064 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4065 }; 4066 map1 { 4067 trip = <&cpu10_alert1>; 4068 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4069 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4070 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4071 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4072 }; 4073 }; 4074 }; 4075 4076 cpu11-thermal { 4077 polling-delay-passive = <250>; 4078 polling-delay = <0>; 4079 4080 thermal-sensors = <&tsens0 14>; 4081 4082 trips { 4083 cpu11_alert0: trip-point0 { 4084 temperature = <90000>; 4085 hysteresis = <2000>; 4086 type = "passive"; 4087 }; 4088 4089 cpu11_alert1: trip-point1 { 4090 temperature = <95000>; 4091 hysteresis = <2000>; 4092 type = "passive"; 4093 }; 4094 4095 cpu11_crit: cpu-crit { 4096 temperature = <110000>; 4097 hysteresis = <0>; 4098 type = "critical"; 4099 }; 4100 }; 4101 4102 cooling-maps { 4103 map0 { 4104 trip = <&cpu11_alert0>; 4105 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4106 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4107 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4108 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4109 }; 4110 map1 { 4111 trip = <&cpu11_alert1>; 4112 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4113 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4114 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4115 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4116 }; 4117 }; 4118 }; 4119 4120 aoss0-thermal { 4121 polling-delay-passive = <0>; 4122 polling-delay = <0>; 4123 4124 thermal-sensors = <&tsens0 0>; 4125 4126 trips { 4127 aoss0_alert0: trip-point0 { 4128 temperature = <90000>; 4129 hysteresis = <2000>; 4130 type = "hot"; 4131 }; 4132 4133 aoss0_crit: aoss0-crit { 4134 temperature = <110000>; 4135 hysteresis = <0>; 4136 type = "critical"; 4137 }; 4138 }; 4139 }; 4140 4141 aoss1-thermal { 4142 polling-delay-passive = <0>; 4143 polling-delay = <0>; 4144 4145 thermal-sensors = <&tsens1 0>; 4146 4147 trips { 4148 aoss1_alert0: trip-point0 { 4149 temperature = <90000>; 4150 hysteresis = <2000>; 4151 type = "hot"; 4152 }; 4153 4154 aoss1_crit: aoss1-crit { 4155 temperature = <110000>; 4156 hysteresis = <0>; 4157 type = "critical"; 4158 }; 4159 }; 4160 }; 4161 4162 cpuss0-thermal { 4163 polling-delay-passive = <0>; 4164 polling-delay = <0>; 4165 4166 thermal-sensors = <&tsens0 5>; 4167 4168 trips { 4169 cpuss0_alert0: trip-point0 { 4170 temperature = <90000>; 4171 hysteresis = <2000>; 4172 type = "hot"; 4173 }; 4174 cpuss0_crit: cluster0-crit { 4175 temperature = <110000>; 4176 hysteresis = <0>; 4177 type = "critical"; 4178 }; 4179 }; 4180 }; 4181 4182 cpuss1-thermal { 4183 polling-delay-passive = <0>; 4184 polling-delay = <0>; 4185 4186 thermal-sensors = <&tsens0 6>; 4187 4188 trips { 4189 cpuss1_alert0: trip-point0 { 4190 temperature = <90000>; 4191 hysteresis = <2000>; 4192 type = "hot"; 4193 }; 4194 cpuss1_crit: cluster0-crit { 4195 temperature = <110000>; 4196 hysteresis = <0>; 4197 type = "critical"; 4198 }; 4199 }; 4200 }; 4201 4202 gpuss0-thermal { 4203 polling-delay-passive = <100>; 4204 polling-delay = <0>; 4205 4206 thermal-sensors = <&tsens1 1>; 4207 4208 trips { 4209 gpuss0_alert0: trip-point0 { 4210 temperature = <95000>; 4211 hysteresis = <2000>; 4212 type = "passive"; 4213 }; 4214 4215 gpuss0_crit: gpuss0-crit { 4216 temperature = <110000>; 4217 hysteresis = <0>; 4218 type = "critical"; 4219 }; 4220 }; 4221 4222 cooling-maps { 4223 map0 { 4224 trip = <&gpuss0_alert0>; 4225 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4226 }; 4227 }; 4228 }; 4229 4230 gpuss1-thermal { 4231 polling-delay-passive = <100>; 4232 polling-delay = <0>; 4233 4234 thermal-sensors = <&tsens1 2>; 4235 4236 trips { 4237 gpuss1_alert0: trip-point0 { 4238 temperature = <95000>; 4239 hysteresis = <2000>; 4240 type = "passive"; 4241 }; 4242 4243 gpuss1_crit: gpuss1-crit { 4244 temperature = <110000>; 4245 hysteresis = <0>; 4246 type = "critical"; 4247 }; 4248 }; 4249 4250 cooling-maps { 4251 map0 { 4252 trip = <&gpuss1_alert0>; 4253 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4254 }; 4255 }; 4256 }; 4257 4258 nspss0-thermal { 4259 polling-delay-passive = <0>; 4260 polling-delay = <0>; 4261 4262 thermal-sensors = <&tsens1 3>; 4263 4264 trips { 4265 nspss0_alert0: trip-point0 { 4266 temperature = <90000>; 4267 hysteresis = <2000>; 4268 type = "hot"; 4269 }; 4270 4271 nspss0_crit: nspss0-crit { 4272 temperature = <110000>; 4273 hysteresis = <0>; 4274 type = "critical"; 4275 }; 4276 }; 4277 }; 4278 4279 nspss1-thermal { 4280 polling-delay-passive = <0>; 4281 polling-delay = <0>; 4282 4283 thermal-sensors = <&tsens1 4>; 4284 4285 trips { 4286 nspss1_alert0: trip-point0 { 4287 temperature = <90000>; 4288 hysteresis = <2000>; 4289 type = "hot"; 4290 }; 4291 4292 nspss1_crit: nspss1-crit { 4293 temperature = <110000>; 4294 hysteresis = <0>; 4295 type = "critical"; 4296 }; 4297 }; 4298 }; 4299 4300 video-thermal { 4301 polling-delay-passive = <0>; 4302 polling-delay = <0>; 4303 4304 thermal-sensors = <&tsens1 5>; 4305 4306 trips { 4307 video_alert0: trip-point0 { 4308 temperature = <90000>; 4309 hysteresis = <2000>; 4310 type = "hot"; 4311 }; 4312 4313 video_crit: video-crit { 4314 temperature = <110000>; 4315 hysteresis = <0>; 4316 type = "critical"; 4317 }; 4318 }; 4319 }; 4320 4321 ddr-thermal { 4322 polling-delay-passive = <0>; 4323 polling-delay = <0>; 4324 4325 thermal-sensors = <&tsens1 6>; 4326 4327 trips { 4328 ddr_alert0: trip-point0 { 4329 temperature = <90000>; 4330 hysteresis = <2000>; 4331 type = "hot"; 4332 }; 4333 4334 ddr_crit: ddr-crit { 4335 temperature = <110000>; 4336 hysteresis = <0>; 4337 type = "critical"; 4338 }; 4339 }; 4340 }; 4341 4342 mdmss0-thermal { 4343 polling-delay-passive = <0>; 4344 polling-delay = <0>; 4345 4346 thermal-sensors = <&tsens1 7>; 4347 4348 trips { 4349 mdmss0_alert0: trip-point0 { 4350 temperature = <90000>; 4351 hysteresis = <2000>; 4352 type = "hot"; 4353 }; 4354 4355 mdmss0_crit: mdmss0-crit { 4356 temperature = <110000>; 4357 hysteresis = <0>; 4358 type = "critical"; 4359 }; 4360 }; 4361 }; 4362 4363 mdmss1-thermal { 4364 polling-delay-passive = <0>; 4365 polling-delay = <0>; 4366 4367 thermal-sensors = <&tsens1 8>; 4368 4369 trips { 4370 mdmss1_alert0: trip-point0 { 4371 temperature = <90000>; 4372 hysteresis = <2000>; 4373 type = "hot"; 4374 }; 4375 4376 mdmss1_crit: mdmss1-crit { 4377 temperature = <110000>; 4378 hysteresis = <0>; 4379 type = "critical"; 4380 }; 4381 }; 4382 }; 4383 4384 mdmss2-thermal { 4385 polling-delay-passive = <0>; 4386 polling-delay = <0>; 4387 4388 thermal-sensors = <&tsens1 9>; 4389 4390 trips { 4391 mdmss2_alert0: trip-point0 { 4392 temperature = <90000>; 4393 hysteresis = <2000>; 4394 type = "hot"; 4395 }; 4396 4397 mdmss2_crit: mdmss2-crit { 4398 temperature = <110000>; 4399 hysteresis = <0>; 4400 type = "critical"; 4401 }; 4402 }; 4403 }; 4404 4405 mdmss3-thermal { 4406 polling-delay-passive = <0>; 4407 polling-delay = <0>; 4408 4409 thermal-sensors = <&tsens1 10>; 4410 4411 trips { 4412 mdmss3_alert0: trip-point0 { 4413 temperature = <90000>; 4414 hysteresis = <2000>; 4415 type = "hot"; 4416 }; 4417 4418 mdmss3_crit: mdmss3-crit { 4419 temperature = <110000>; 4420 hysteresis = <0>; 4421 type = "critical"; 4422 }; 4423 }; 4424 }; 4425 4426 camera0-thermal { 4427 polling-delay-passive = <0>; 4428 polling-delay = <0>; 4429 4430 thermal-sensors = <&tsens1 11>; 4431 4432 trips { 4433 camera0_alert0: trip-point0 { 4434 temperature = <90000>; 4435 hysteresis = <2000>; 4436 type = "hot"; 4437 }; 4438 4439 camera0_crit: camera0-crit { 4440 temperature = <110000>; 4441 hysteresis = <0>; 4442 type = "critical"; 4443 }; 4444 }; 4445 }; 4446 }; 4447 4448 timer { 4449 compatible = "arm,armv8-timer"; 4450 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 4451 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 4452 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 4453 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 4454 }; 4455}; 4456