1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7280.h> 13#include <dt-bindings/interconnect/qcom,sc7280.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-aoss-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/reset/qcom,sdm845-aoss.h> 19#include <dt-bindings/reset/qcom,sdm845-pdc.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 chosen { }; 30 31 aliases { 32 mmc1 = &sdhc_1; 33 mmc2 = &sdhc_2; 34 }; 35 36 clocks { 37 xo_board: xo-board { 38 compatible = "fixed-clock"; 39 clock-frequency = <76800000>; 40 #clock-cells = <0>; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 clock-frequency = <32000>; 46 #clock-cells = <0>; 47 }; 48 }; 49 50 reserved-memory { 51 #address-cells = <2>; 52 #size-cells = <2>; 53 ranges; 54 55 aop_mem: memory@80800000 { 56 reg = <0x0 0x80800000 0x0 0x60000>; 57 no-map; 58 }; 59 60 aop_cmd_db_mem: memory@80860000 { 61 reg = <0x0 0x80860000 0x0 0x20000>; 62 compatible = "qcom,cmd-db"; 63 no-map; 64 }; 65 66 smem_mem: memory@80900000 { 67 reg = <0x0 0x80900000 0x0 0x200000>; 68 no-map; 69 }; 70 71 cpucp_mem: memory@80b00000 { 72 no-map; 73 reg = <0x0 0x80b00000 0x0 0x100000>; 74 }; 75 76 ipa_fw_mem: memory@8b700000 { 77 reg = <0 0x8b700000 0 0x10000>; 78 no-map; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <2>; 84 #size-cells = <0>; 85 86 CPU0: cpu@0 { 87 device_type = "cpu"; 88 compatible = "arm,kryo"; 89 reg = <0x0 0x0>; 90 enable-method = "psci"; 91 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 92 &LITTLE_CPU_SLEEP_1 93 &CLUSTER_SLEEP_0>; 94 next-level-cache = <&L2_0>; 95 qcom,freq-domain = <&cpufreq_hw 0>; 96 #cooling-cells = <2>; 97 L2_0: l2-cache { 98 compatible = "cache"; 99 next-level-cache = <&L3_0>; 100 L3_0: l3-cache { 101 compatible = "cache"; 102 }; 103 }; 104 }; 105 106 CPU1: cpu@100 { 107 device_type = "cpu"; 108 compatible = "arm,kryo"; 109 reg = <0x0 0x100>; 110 enable-method = "psci"; 111 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 112 &LITTLE_CPU_SLEEP_1 113 &CLUSTER_SLEEP_0>; 114 next-level-cache = <&L2_100>; 115 qcom,freq-domain = <&cpufreq_hw 0>; 116 #cooling-cells = <2>; 117 L2_100: l2-cache { 118 compatible = "cache"; 119 next-level-cache = <&L3_0>; 120 }; 121 }; 122 123 CPU2: cpu@200 { 124 device_type = "cpu"; 125 compatible = "arm,kryo"; 126 reg = <0x0 0x200>; 127 enable-method = "psci"; 128 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 129 &LITTLE_CPU_SLEEP_1 130 &CLUSTER_SLEEP_0>; 131 next-level-cache = <&L2_200>; 132 qcom,freq-domain = <&cpufreq_hw 0>; 133 #cooling-cells = <2>; 134 L2_200: l2-cache { 135 compatible = "cache"; 136 next-level-cache = <&L3_0>; 137 }; 138 }; 139 140 CPU3: cpu@300 { 141 device_type = "cpu"; 142 compatible = "arm,kryo"; 143 reg = <0x0 0x300>; 144 enable-method = "psci"; 145 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 146 &LITTLE_CPU_SLEEP_1 147 &CLUSTER_SLEEP_0>; 148 next-level-cache = <&L2_300>; 149 qcom,freq-domain = <&cpufreq_hw 0>; 150 #cooling-cells = <2>; 151 L2_300: l2-cache { 152 compatible = "cache"; 153 next-level-cache = <&L3_0>; 154 }; 155 }; 156 157 CPU4: cpu@400 { 158 device_type = "cpu"; 159 compatible = "arm,kryo"; 160 reg = <0x0 0x400>; 161 enable-method = "psci"; 162 cpu-idle-states = <&BIG_CPU_SLEEP_0 163 &BIG_CPU_SLEEP_1 164 &CLUSTER_SLEEP_0>; 165 next-level-cache = <&L2_400>; 166 qcom,freq-domain = <&cpufreq_hw 1>; 167 #cooling-cells = <2>; 168 L2_400: l2-cache { 169 compatible = "cache"; 170 next-level-cache = <&L3_0>; 171 }; 172 }; 173 174 CPU5: cpu@500 { 175 device_type = "cpu"; 176 compatible = "arm,kryo"; 177 reg = <0x0 0x500>; 178 enable-method = "psci"; 179 cpu-idle-states = <&BIG_CPU_SLEEP_0 180 &BIG_CPU_SLEEP_1 181 &CLUSTER_SLEEP_0>; 182 next-level-cache = <&L2_500>; 183 qcom,freq-domain = <&cpufreq_hw 1>; 184 #cooling-cells = <2>; 185 L2_500: l2-cache { 186 compatible = "cache"; 187 next-level-cache = <&L3_0>; 188 }; 189 }; 190 191 CPU6: cpu@600 { 192 device_type = "cpu"; 193 compatible = "arm,kryo"; 194 reg = <0x0 0x600>; 195 enable-method = "psci"; 196 cpu-idle-states = <&BIG_CPU_SLEEP_0 197 &BIG_CPU_SLEEP_1 198 &CLUSTER_SLEEP_0>; 199 next-level-cache = <&L2_600>; 200 qcom,freq-domain = <&cpufreq_hw 1>; 201 #cooling-cells = <2>; 202 L2_600: l2-cache { 203 compatible = "cache"; 204 next-level-cache = <&L3_0>; 205 }; 206 }; 207 208 CPU7: cpu@700 { 209 device_type = "cpu"; 210 compatible = "arm,kryo"; 211 reg = <0x0 0x700>; 212 enable-method = "psci"; 213 cpu-idle-states = <&BIG_CPU_SLEEP_0 214 &BIG_CPU_SLEEP_1 215 &CLUSTER_SLEEP_0>; 216 next-level-cache = <&L2_700>; 217 qcom,freq-domain = <&cpufreq_hw 2>; 218 #cooling-cells = <2>; 219 L2_700: l2-cache { 220 compatible = "cache"; 221 next-level-cache = <&L3_0>; 222 }; 223 }; 224 225 cpu-map { 226 cluster0 { 227 core0 { 228 cpu = <&CPU0>; 229 }; 230 231 core1 { 232 cpu = <&CPU1>; 233 }; 234 235 core2 { 236 cpu = <&CPU2>; 237 }; 238 239 core3 { 240 cpu = <&CPU3>; 241 }; 242 243 core4 { 244 cpu = <&CPU4>; 245 }; 246 247 core5 { 248 cpu = <&CPU5>; 249 }; 250 251 core6 { 252 cpu = <&CPU6>; 253 }; 254 255 core7 { 256 cpu = <&CPU7>; 257 }; 258 }; 259 }; 260 261 idle-states { 262 entry-method = "psci"; 263 264 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 265 compatible = "arm,idle-state"; 266 idle-state-name = "little-power-down"; 267 arm,psci-suspend-param = <0x40000003>; 268 entry-latency-us = <549>; 269 exit-latency-us = <901>; 270 min-residency-us = <1774>; 271 local-timer-stop; 272 }; 273 274 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 275 compatible = "arm,idle-state"; 276 idle-state-name = "little-rail-power-down"; 277 arm,psci-suspend-param = <0x40000004>; 278 entry-latency-us = <702>; 279 exit-latency-us = <915>; 280 min-residency-us = <4001>; 281 local-timer-stop; 282 }; 283 284 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 285 compatible = "arm,idle-state"; 286 idle-state-name = "big-power-down"; 287 arm,psci-suspend-param = <0x40000003>; 288 entry-latency-us = <523>; 289 exit-latency-us = <1244>; 290 min-residency-us = <2207>; 291 local-timer-stop; 292 }; 293 294 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 295 compatible = "arm,idle-state"; 296 idle-state-name = "big-rail-power-down"; 297 arm,psci-suspend-param = <0x40000004>; 298 entry-latency-us = <526>; 299 exit-latency-us = <1854>; 300 min-residency-us = <5555>; 301 local-timer-stop; 302 }; 303 304 CLUSTER_SLEEP_0: cluster-sleep-0 { 305 compatible = "arm,idle-state"; 306 idle-state-name = "cluster-power-down"; 307 arm,psci-suspend-param = <0x40003444>; 308 entry-latency-us = <3263>; 309 exit-latency-us = <6562>; 310 min-residency-us = <9926>; 311 local-timer-stop; 312 }; 313 }; 314 }; 315 316 memory@80000000 { 317 device_type = "memory"; 318 /* We expect the bootloader to fill in the size */ 319 reg = <0 0x80000000 0 0>; 320 }; 321 322 firmware { 323 scm { 324 compatible = "qcom,scm-sc7280", "qcom,scm"; 325 }; 326 }; 327 328 clk_virt: interconnect { 329 compatible = "qcom,sc7280-clk-virt"; 330 #interconnect-cells = <2>; 331 qcom,bcm-voters = <&apps_bcm_voter>; 332 }; 333 334 smem { 335 compatible = "qcom,smem"; 336 memory-region = <&smem_mem>; 337 hwlocks = <&tcsr_mutex 3>; 338 }; 339 340 smp2p-adsp { 341 compatible = "qcom,smp2p"; 342 qcom,smem = <443>, <429>; 343 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 344 IPCC_MPROC_SIGNAL_SMP2P 345 IRQ_TYPE_EDGE_RISING>; 346 mboxes = <&ipcc IPCC_CLIENT_LPASS 347 IPCC_MPROC_SIGNAL_SMP2P>; 348 349 qcom,local-pid = <0>; 350 qcom,remote-pid = <2>; 351 352 adsp_smp2p_out: master-kernel { 353 qcom,entry-name = "master-kernel"; 354 #qcom,smem-state-cells = <1>; 355 }; 356 357 adsp_smp2p_in: slave-kernel { 358 qcom,entry-name = "slave-kernel"; 359 interrupt-controller; 360 #interrupt-cells = <2>; 361 }; 362 }; 363 364 smp2p-cdsp { 365 compatible = "qcom,smp2p"; 366 qcom,smem = <94>, <432>; 367 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 368 IPCC_MPROC_SIGNAL_SMP2P 369 IRQ_TYPE_EDGE_RISING>; 370 mboxes = <&ipcc IPCC_CLIENT_CDSP 371 IPCC_MPROC_SIGNAL_SMP2P>; 372 373 qcom,local-pid = <0>; 374 qcom,remote-pid = <5>; 375 376 cdsp_smp2p_out: master-kernel { 377 qcom,entry-name = "master-kernel"; 378 #qcom,smem-state-cells = <1>; 379 }; 380 381 cdsp_smp2p_in: slave-kernel { 382 qcom,entry-name = "slave-kernel"; 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 }; 386 }; 387 388 smp2p-mpss { 389 compatible = "qcom,smp2p"; 390 qcom,smem = <435>, <428>; 391 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 392 IPCC_MPROC_SIGNAL_SMP2P 393 IRQ_TYPE_EDGE_RISING>; 394 mboxes = <&ipcc IPCC_CLIENT_MPSS 395 IPCC_MPROC_SIGNAL_SMP2P>; 396 397 qcom,local-pid = <0>; 398 qcom,remote-pid = <1>; 399 400 modem_smp2p_out: master-kernel { 401 qcom,entry-name = "master-kernel"; 402 #qcom,smem-state-cells = <1>; 403 }; 404 405 modem_smp2p_in: slave-kernel { 406 qcom,entry-name = "slave-kernel"; 407 interrupt-controller; 408 #interrupt-cells = <2>; 409 }; 410 411 ipa_smp2p_out: ipa-ap-to-modem { 412 qcom,entry-name = "ipa"; 413 #qcom,smem-state-cells = <1>; 414 }; 415 416 ipa_smp2p_in: ipa-modem-to-ap { 417 qcom,entry-name = "ipa"; 418 interrupt-controller; 419 #interrupt-cells = <2>; 420 }; 421 }; 422 423 smp2p-wpss { 424 compatible = "qcom,smp2p"; 425 qcom,smem = <617>, <616>; 426 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 427 IPCC_MPROC_SIGNAL_SMP2P 428 IRQ_TYPE_EDGE_RISING>; 429 mboxes = <&ipcc IPCC_CLIENT_WPSS 430 IPCC_MPROC_SIGNAL_SMP2P>; 431 432 qcom,local-pid = <0>; 433 qcom,remote-pid = <13>; 434 435 wpss_smp2p_out: master-kernel { 436 qcom,entry-name = "master-kernel"; 437 #qcom,smem-state-cells = <1>; 438 }; 439 440 wpss_smp2p_in: slave-kernel { 441 qcom,entry-name = "slave-kernel"; 442 interrupt-controller; 443 #interrupt-cells = <2>; 444 }; 445 }; 446 447 pmu { 448 compatible = "arm,armv8-pmuv3"; 449 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 450 }; 451 452 psci { 453 compatible = "arm,psci-1.0"; 454 method = "smc"; 455 }; 456 457 qspi_opp_table: qspi-opp-table { 458 compatible = "operating-points-v2"; 459 460 opp-75000000 { 461 opp-hz = /bits/ 64 <75000000>; 462 required-opps = <&rpmhpd_opp_low_svs>; 463 }; 464 465 opp-150000000 { 466 opp-hz = /bits/ 64 <150000000>; 467 required-opps = <&rpmhpd_opp_svs>; 468 }; 469 470 opp-300000000 { 471 opp-hz = /bits/ 64 <300000000>; 472 required-opps = <&rpmhpd_opp_nom>; 473 }; 474 }; 475 476 qup_opp_table: qup-opp-table { 477 compatible = "operating-points-v2"; 478 479 opp-75000000 { 480 opp-hz = /bits/ 64 <75000000>; 481 required-opps = <&rpmhpd_opp_low_svs>; 482 }; 483 484 opp-100000000 { 485 opp-hz = /bits/ 64 <100000000>; 486 required-opps = <&rpmhpd_opp_svs>; 487 }; 488 489 opp-128000000 { 490 opp-hz = /bits/ 64 <128000000>; 491 required-opps = <&rpmhpd_opp_nom>; 492 }; 493 }; 494 495 soc: soc@0 { 496 #address-cells = <2>; 497 #size-cells = <2>; 498 ranges = <0 0 0 0 0x10 0>; 499 dma-ranges = <0 0 0 0 0x10 0>; 500 compatible = "simple-bus"; 501 502 gcc: clock-controller@100000 { 503 compatible = "qcom,gcc-sc7280"; 504 reg = <0 0x00100000 0 0x1f0000>; 505 clocks = <&rpmhcc RPMH_CXO_CLK>, 506 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 507 <0>, <0>, <0>, <0>, <0>, <0>; 508 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 509 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 510 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 511 "ufs_phy_tx_symbol_0_clk", 512 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 513 #clock-cells = <1>; 514 #reset-cells = <1>; 515 #power-domain-cells = <1>; 516 }; 517 518 ipcc: mailbox@408000 { 519 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 520 reg = <0 0x00408000 0 0x1000>; 521 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 522 interrupt-controller; 523 #interrupt-cells = <3>; 524 #mbox-cells = <2>; 525 }; 526 527 qfprom: efuse@784000 { 528 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 529 reg = <0 0x00784000 0 0xa20>, 530 <0 0x00780000 0 0xa20>, 531 <0 0x00782000 0 0x120>, 532 <0 0x00786000 0 0x1fff>; 533 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 534 clock-names = "core"; 535 power-domains = <&rpmhpd SC7280_MX>; 536 #address-cells = <1>; 537 #size-cells = <1>; 538 }; 539 540 sdhc_1: sdhci@7c4000 { 541 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 542 status = "disabled"; 543 544 reg = <0 0x007c4000 0 0x1000>, 545 <0 0x007c5000 0 0x1000>; 546 reg-names = "hc", "cqhci"; 547 548 iommus = <&apps_smmu 0xc0 0x0>; 549 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 551 interrupt-names = "hc_irq", "pwr_irq"; 552 553 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 554 <&gcc GCC_SDCC1_AHB_CLK>, 555 <&rpmhcc RPMH_CXO_CLK>; 556 clock-names = "core", "iface", "xo"; 557 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 558 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 559 interconnect-names = "sdhc-ddr","cpu-sdhc"; 560 power-domains = <&rpmhpd SC7280_CX>; 561 operating-points-v2 = <&sdhc1_opp_table>; 562 563 bus-width = <8>; 564 supports-cqe; 565 566 qcom,dll-config = <0x0007642c>; 567 qcom,ddr-config = <0x80040868>; 568 569 mmc-ddr-1_8v; 570 mmc-hs200-1_8v; 571 mmc-hs400-1_8v; 572 mmc-hs400-enhanced-strobe; 573 574 sdhc1_opp_table: opp-table { 575 compatible = "operating-points-v2"; 576 577 opp-100000000 { 578 opp-hz = /bits/ 64 <100000000>; 579 required-opps = <&rpmhpd_opp_low_svs>; 580 opp-peak-kBps = <1800000 400000>; 581 opp-avg-kBps = <100000 0>; 582 }; 583 584 opp-384000000 { 585 opp-hz = /bits/ 64 <384000000>; 586 required-opps = <&rpmhpd_opp_nom>; 587 opp-peak-kBps = <5400000 1600000>; 588 opp-avg-kBps = <390000 0>; 589 }; 590 }; 591 592 }; 593 594 qupv3_id_0: geniqup@9c0000 { 595 compatible = "qcom,geni-se-qup"; 596 reg = <0 0x009c0000 0 0x2000>; 597 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 598 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 599 clock-names = "m-ahb", "s-ahb"; 600 #address-cells = <2>; 601 #size-cells = <2>; 602 ranges; 603 iommus = <&apps_smmu 0x123 0x0>; 604 status = "disabled"; 605 606 i2c0: i2c@980000 { 607 compatible = "qcom,geni-i2c"; 608 reg = <0 0x00980000 0 0x4000>; 609 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 610 clock-names = "se"; 611 pinctrl-names = "default"; 612 pinctrl-0 = <&qup_i2c0_data_clk>; 613 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 614 #address-cells = <1>; 615 #size-cells = <0>; 616 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 617 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 618 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 619 interconnect-names = "qup-core", "qup-config", 620 "qup-memory"; 621 status = "disabled"; 622 }; 623 624 spi0: spi@980000 { 625 compatible = "qcom,geni-spi"; 626 reg = <0 0x00980000 0 0x4000>; 627 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 628 clock-names = "se"; 629 pinctrl-names = "default"; 630 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 631 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 power-domains = <&rpmhpd SC7280_CX>; 635 operating-points-v2 = <&qup_opp_table>; 636 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 637 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 638 interconnect-names = "qup-core", "qup-config"; 639 status = "disabled"; 640 }; 641 642 uart0: serial@980000 { 643 compatible = "qcom,geni-uart"; 644 reg = <0 0x00980000 0 0x4000>; 645 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 646 clock-names = "se"; 647 pinctrl-names = "default"; 648 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 649 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 650 power-domains = <&rpmhpd SC7280_CX>; 651 operating-points-v2 = <&qup_opp_table>; 652 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 653 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 654 interconnect-names = "qup-core", "qup-config"; 655 status = "disabled"; 656 }; 657 658 i2c1: i2c@984000 { 659 compatible = "qcom,geni-i2c"; 660 reg = <0 0x00984000 0 0x4000>; 661 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 662 clock-names = "se"; 663 pinctrl-names = "default"; 664 pinctrl-0 = <&qup_i2c1_data_clk>; 665 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 666 #address-cells = <1>; 667 #size-cells = <0>; 668 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 669 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 670 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 671 interconnect-names = "qup-core", "qup-config", 672 "qup-memory"; 673 status = "disabled"; 674 }; 675 676 spi1: spi@984000 { 677 compatible = "qcom,geni-spi"; 678 reg = <0 0x00984000 0 0x4000>; 679 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 680 clock-names = "se"; 681 pinctrl-names = "default"; 682 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 683 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 power-domains = <&rpmhpd SC7280_CX>; 687 operating-points-v2 = <&qup_opp_table>; 688 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 689 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 690 interconnect-names = "qup-core", "qup-config"; 691 status = "disabled"; 692 }; 693 694 uart1: serial@984000 { 695 compatible = "qcom,geni-uart"; 696 reg = <0 0x00984000 0 0x4000>; 697 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 698 clock-names = "se"; 699 pinctrl-names = "default"; 700 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 701 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 702 power-domains = <&rpmhpd SC7280_CX>; 703 operating-points-v2 = <&qup_opp_table>; 704 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 705 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 706 interconnect-names = "qup-core", "qup-config"; 707 status = "disabled"; 708 }; 709 710 i2c2: i2c@988000 { 711 compatible = "qcom,geni-i2c"; 712 reg = <0 0x00988000 0 0x4000>; 713 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 714 clock-names = "se"; 715 pinctrl-names = "default"; 716 pinctrl-0 = <&qup_i2c2_data_clk>; 717 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 721 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 722 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 723 interconnect-names = "qup-core", "qup-config", 724 "qup-memory"; 725 status = "disabled"; 726 }; 727 728 spi2: spi@988000 { 729 compatible = "qcom,geni-spi"; 730 reg = <0 0x00988000 0 0x4000>; 731 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 732 clock-names = "se"; 733 pinctrl-names = "default"; 734 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 735 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 736 #address-cells = <1>; 737 #size-cells = <0>; 738 power-domains = <&rpmhpd SC7280_CX>; 739 operating-points-v2 = <&qup_opp_table>; 740 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 741 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 742 interconnect-names = "qup-core", "qup-config"; 743 status = "disabled"; 744 }; 745 746 uart2: serial@988000 { 747 compatible = "qcom,geni-uart"; 748 reg = <0 0x00988000 0 0x4000>; 749 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 750 clock-names = "se"; 751 pinctrl-names = "default"; 752 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 753 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 754 power-domains = <&rpmhpd SC7280_CX>; 755 operating-points-v2 = <&qup_opp_table>; 756 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 757 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 758 interconnect-names = "qup-core", "qup-config"; 759 status = "disabled"; 760 }; 761 762 i2c3: i2c@98c000 { 763 compatible = "qcom,geni-i2c"; 764 reg = <0 0x0098c000 0 0x4000>; 765 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 766 clock-names = "se"; 767 pinctrl-names = "default"; 768 pinctrl-0 = <&qup_i2c3_data_clk>; 769 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 770 #address-cells = <1>; 771 #size-cells = <0>; 772 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 773 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 774 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 775 interconnect-names = "qup-core", "qup-config", 776 "qup-memory"; 777 status = "disabled"; 778 }; 779 780 spi3: spi@98c000 { 781 compatible = "qcom,geni-spi"; 782 reg = <0 0x0098c000 0 0x4000>; 783 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 784 clock-names = "se"; 785 pinctrl-names = "default"; 786 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 787 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 power-domains = <&rpmhpd SC7280_CX>; 791 operating-points-v2 = <&qup_opp_table>; 792 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 793 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 794 interconnect-names = "qup-core", "qup-config"; 795 status = "disabled"; 796 }; 797 798 uart3: serial@98c000 { 799 compatible = "qcom,geni-uart"; 800 reg = <0 0x0098c000 0 0x4000>; 801 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 802 clock-names = "se"; 803 pinctrl-names = "default"; 804 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 805 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 806 power-domains = <&rpmhpd SC7280_CX>; 807 operating-points-v2 = <&qup_opp_table>; 808 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 809 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 810 interconnect-names = "qup-core", "qup-config"; 811 status = "disabled"; 812 }; 813 814 i2c4: i2c@990000 { 815 compatible = "qcom,geni-i2c"; 816 reg = <0 0x00990000 0 0x4000>; 817 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 818 clock-names = "se"; 819 pinctrl-names = "default"; 820 pinctrl-0 = <&qup_i2c4_data_clk>; 821 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 825 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 826 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 827 interconnect-names = "qup-core", "qup-config", 828 "qup-memory"; 829 status = "disabled"; 830 }; 831 832 spi4: spi@990000 { 833 compatible = "qcom,geni-spi"; 834 reg = <0 0x00990000 0 0x4000>; 835 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 836 clock-names = "se"; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 839 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 power-domains = <&rpmhpd SC7280_CX>; 843 operating-points-v2 = <&qup_opp_table>; 844 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 845 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 846 interconnect-names = "qup-core", "qup-config"; 847 status = "disabled"; 848 }; 849 850 uart4: serial@990000 { 851 compatible = "qcom,geni-uart"; 852 reg = <0 0x00990000 0 0x4000>; 853 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 854 clock-names = "se"; 855 pinctrl-names = "default"; 856 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 857 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 858 power-domains = <&rpmhpd SC7280_CX>; 859 operating-points-v2 = <&qup_opp_table>; 860 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 861 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 862 interconnect-names = "qup-core", "qup-config"; 863 status = "disabled"; 864 }; 865 866 i2c5: i2c@994000 { 867 compatible = "qcom,geni-i2c"; 868 reg = <0 0x00994000 0 0x4000>; 869 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 870 clock-names = "se"; 871 pinctrl-names = "default"; 872 pinctrl-0 = <&qup_i2c5_data_clk>; 873 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 874 #address-cells = <1>; 875 #size-cells = <0>; 876 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 877 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 878 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 879 interconnect-names = "qup-core", "qup-config", 880 "qup-memory"; 881 status = "disabled"; 882 }; 883 884 spi5: spi@994000 { 885 compatible = "qcom,geni-spi"; 886 reg = <0 0x00994000 0 0x4000>; 887 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 888 clock-names = "se"; 889 pinctrl-names = "default"; 890 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 891 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 892 #address-cells = <1>; 893 #size-cells = <0>; 894 power-domains = <&rpmhpd SC7280_CX>; 895 operating-points-v2 = <&qup_opp_table>; 896 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 897 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 898 interconnect-names = "qup-core", "qup-config"; 899 status = "disabled"; 900 }; 901 902 uart5: serial@994000 { 903 compatible = "qcom,geni-uart"; 904 reg = <0 0x00994000 0 0x4000>; 905 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 906 clock-names = "se"; 907 pinctrl-names = "default"; 908 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 909 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 910 power-domains = <&rpmhpd SC7280_CX>; 911 operating-points-v2 = <&qup_opp_table>; 912 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 913 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 914 interconnect-names = "qup-core", "qup-config"; 915 status = "disabled"; 916 }; 917 918 i2c6: i2c@998000 { 919 compatible = "qcom,geni-i2c"; 920 reg = <0 0x00998000 0 0x4000>; 921 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 922 clock-names = "se"; 923 pinctrl-names = "default"; 924 pinctrl-0 = <&qup_i2c6_data_clk>; 925 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 926 #address-cells = <1>; 927 #size-cells = <0>; 928 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 929 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 930 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 931 interconnect-names = "qup-core", "qup-config", 932 "qup-memory"; 933 status = "disabled"; 934 }; 935 936 spi6: spi@998000 { 937 compatible = "qcom,geni-spi"; 938 reg = <0 0x00998000 0 0x4000>; 939 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 940 clock-names = "se"; 941 pinctrl-names = "default"; 942 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 943 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 944 #address-cells = <1>; 945 #size-cells = <0>; 946 power-domains = <&rpmhpd SC7280_CX>; 947 operating-points-v2 = <&qup_opp_table>; 948 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 949 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 950 interconnect-names = "qup-core", "qup-config"; 951 status = "disabled"; 952 }; 953 954 uart6: serial@998000 { 955 compatible = "qcom,geni-uart"; 956 reg = <0 0x00998000 0 0x4000>; 957 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 958 clock-names = "se"; 959 pinctrl-names = "default"; 960 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 961 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 962 power-domains = <&rpmhpd SC7280_CX>; 963 operating-points-v2 = <&qup_opp_table>; 964 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 965 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 966 interconnect-names = "qup-core", "qup-config"; 967 status = "disabled"; 968 }; 969 970 i2c7: i2c@99c000 { 971 compatible = "qcom,geni-i2c"; 972 reg = <0 0x0099c000 0 0x4000>; 973 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 974 clock-names = "se"; 975 pinctrl-names = "default"; 976 pinctrl-0 = <&qup_i2c7_data_clk>; 977 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 978 #address-cells = <1>; 979 #size-cells = <0>; 980 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 981 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 982 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 983 interconnect-names = "qup-core", "qup-config", 984 "qup-memory"; 985 status = "disabled"; 986 }; 987 988 spi7: spi@99c000 { 989 compatible = "qcom,geni-spi"; 990 reg = <0 0x0099c000 0 0x4000>; 991 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 992 clock-names = "se"; 993 pinctrl-names = "default"; 994 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 995 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 996 #address-cells = <1>; 997 #size-cells = <0>; 998 power-domains = <&rpmhpd SC7280_CX>; 999 operating-points-v2 = <&qup_opp_table>; 1000 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1001 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1002 interconnect-names = "qup-core", "qup-config"; 1003 status = "disabled"; 1004 }; 1005 1006 uart7: serial@99c000 { 1007 compatible = "qcom,geni-uart"; 1008 reg = <0 0x0099c000 0 0x4000>; 1009 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1010 clock-names = "se"; 1011 pinctrl-names = "default"; 1012 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1013 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1014 power-domains = <&rpmhpd SC7280_CX>; 1015 operating-points-v2 = <&qup_opp_table>; 1016 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1017 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1018 interconnect-names = "qup-core", "qup-config"; 1019 status = "disabled"; 1020 }; 1021 }; 1022 1023 qupv3_id_1: geniqup@ac0000 { 1024 compatible = "qcom,geni-se-qup"; 1025 reg = <0 0x00ac0000 0 0x2000>; 1026 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1027 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1028 clock-names = "m-ahb", "s-ahb"; 1029 #address-cells = <2>; 1030 #size-cells = <2>; 1031 ranges; 1032 iommus = <&apps_smmu 0x43 0x0>; 1033 status = "disabled"; 1034 1035 i2c8: i2c@a80000 { 1036 compatible = "qcom,geni-i2c"; 1037 reg = <0 0x00a80000 0 0x4000>; 1038 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1039 clock-names = "se"; 1040 pinctrl-names = "default"; 1041 pinctrl-0 = <&qup_i2c8_data_clk>; 1042 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1043 #address-cells = <1>; 1044 #size-cells = <0>; 1045 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1046 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1047 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1048 interconnect-names = "qup-core", "qup-config", 1049 "qup-memory"; 1050 status = "disabled"; 1051 }; 1052 1053 spi8: spi@a80000 { 1054 compatible = "qcom,geni-spi"; 1055 reg = <0 0x00a80000 0 0x4000>; 1056 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1057 clock-names = "se"; 1058 pinctrl-names = "default"; 1059 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1060 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 power-domains = <&rpmhpd SC7280_CX>; 1064 operating-points-v2 = <&qup_opp_table>; 1065 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1066 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1067 interconnect-names = "qup-core", "qup-config"; 1068 status = "disabled"; 1069 }; 1070 1071 uart8: serial@a80000 { 1072 compatible = "qcom,geni-uart"; 1073 reg = <0 0x00a80000 0 0x4000>; 1074 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1075 clock-names = "se"; 1076 pinctrl-names = "default"; 1077 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1078 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1079 power-domains = <&rpmhpd SC7280_CX>; 1080 operating-points-v2 = <&qup_opp_table>; 1081 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1082 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1083 interconnect-names = "qup-core", "qup-config"; 1084 status = "disabled"; 1085 }; 1086 1087 i2c9: i2c@a84000 { 1088 compatible = "qcom,geni-i2c"; 1089 reg = <0 0x00a84000 0 0x4000>; 1090 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1091 clock-names = "se"; 1092 pinctrl-names = "default"; 1093 pinctrl-0 = <&qup_i2c9_data_clk>; 1094 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1098 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1099 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1100 interconnect-names = "qup-core", "qup-config", 1101 "qup-memory"; 1102 status = "disabled"; 1103 }; 1104 1105 spi9: spi@a84000 { 1106 compatible = "qcom,geni-spi"; 1107 reg = <0 0x00a84000 0 0x4000>; 1108 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1109 clock-names = "se"; 1110 pinctrl-names = "default"; 1111 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1112 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 power-domains = <&rpmhpd SC7280_CX>; 1116 operating-points-v2 = <&qup_opp_table>; 1117 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1118 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1119 interconnect-names = "qup-core", "qup-config"; 1120 status = "disabled"; 1121 }; 1122 1123 uart9: serial@a84000 { 1124 compatible = "qcom,geni-uart"; 1125 reg = <0 0x00a84000 0 0x4000>; 1126 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1127 clock-names = "se"; 1128 pinctrl-names = "default"; 1129 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1130 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1131 power-domains = <&rpmhpd SC7280_CX>; 1132 operating-points-v2 = <&qup_opp_table>; 1133 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1134 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1135 interconnect-names = "qup-core", "qup-config"; 1136 status = "disabled"; 1137 }; 1138 1139 i2c10: i2c@a88000 { 1140 compatible = "qcom,geni-i2c"; 1141 reg = <0 0x00a88000 0 0x4000>; 1142 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1143 clock-names = "se"; 1144 pinctrl-names = "default"; 1145 pinctrl-0 = <&qup_i2c10_data_clk>; 1146 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1147 #address-cells = <1>; 1148 #size-cells = <0>; 1149 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1150 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1151 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1152 interconnect-names = "qup-core", "qup-config", 1153 "qup-memory"; 1154 status = "disabled"; 1155 }; 1156 1157 spi10: spi@a88000 { 1158 compatible = "qcom,geni-spi"; 1159 reg = <0 0x00a88000 0 0x4000>; 1160 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1161 clock-names = "se"; 1162 pinctrl-names = "default"; 1163 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1164 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 power-domains = <&rpmhpd SC7280_CX>; 1168 operating-points-v2 = <&qup_opp_table>; 1169 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1170 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1171 interconnect-names = "qup-core", "qup-config"; 1172 status = "disabled"; 1173 }; 1174 1175 uart10: serial@a88000 { 1176 compatible = "qcom,geni-uart"; 1177 reg = <0 0x00a88000 0 0x4000>; 1178 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1179 clock-names = "se"; 1180 pinctrl-names = "default"; 1181 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1182 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1183 power-domains = <&rpmhpd SC7280_CX>; 1184 operating-points-v2 = <&qup_opp_table>; 1185 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1186 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1187 interconnect-names = "qup-core", "qup-config"; 1188 status = "disabled"; 1189 }; 1190 1191 i2c11: i2c@a8c000 { 1192 compatible = "qcom,geni-i2c"; 1193 reg = <0 0x00a8c000 0 0x4000>; 1194 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1195 clock-names = "se"; 1196 pinctrl-names = "default"; 1197 pinctrl-0 = <&qup_i2c11_data_clk>; 1198 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1202 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1203 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1204 interconnect-names = "qup-core", "qup-config", 1205 "qup-memory"; 1206 status = "disabled"; 1207 }; 1208 1209 spi11: spi@a8c000 { 1210 compatible = "qcom,geni-spi"; 1211 reg = <0 0x00a8c000 0 0x4000>; 1212 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1213 clock-names = "se"; 1214 pinctrl-names = "default"; 1215 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1216 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 power-domains = <&rpmhpd SC7280_CX>; 1220 operating-points-v2 = <&qup_opp_table>; 1221 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1222 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1223 interconnect-names = "qup-core", "qup-config"; 1224 status = "disabled"; 1225 }; 1226 1227 uart11: serial@a8c000 { 1228 compatible = "qcom,geni-uart"; 1229 reg = <0 0x00a8c000 0 0x4000>; 1230 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1231 clock-names = "se"; 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1234 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1235 power-domains = <&rpmhpd SC7280_CX>; 1236 operating-points-v2 = <&qup_opp_table>; 1237 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1238 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1239 interconnect-names = "qup-core", "qup-config"; 1240 status = "disabled"; 1241 }; 1242 1243 i2c12: i2c@a90000 { 1244 compatible = "qcom,geni-i2c"; 1245 reg = <0 0x00a90000 0 0x4000>; 1246 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1247 clock-names = "se"; 1248 pinctrl-names = "default"; 1249 pinctrl-0 = <&qup_i2c12_data_clk>; 1250 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1254 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1255 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1256 interconnect-names = "qup-core", "qup-config", 1257 "qup-memory"; 1258 status = "disabled"; 1259 }; 1260 1261 spi12: spi@a90000 { 1262 compatible = "qcom,geni-spi"; 1263 reg = <0 0x00a90000 0 0x4000>; 1264 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1265 clock-names = "se"; 1266 pinctrl-names = "default"; 1267 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1268 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 power-domains = <&rpmhpd SC7280_CX>; 1272 operating-points-v2 = <&qup_opp_table>; 1273 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1274 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1275 interconnect-names = "qup-core", "qup-config"; 1276 status = "disabled"; 1277 }; 1278 1279 uart12: serial@a90000 { 1280 compatible = "qcom,geni-uart"; 1281 reg = <0 0x00a90000 0 0x4000>; 1282 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1283 clock-names = "se"; 1284 pinctrl-names = "default"; 1285 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1286 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1287 power-domains = <&rpmhpd SC7280_CX>; 1288 operating-points-v2 = <&qup_opp_table>; 1289 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1290 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1291 interconnect-names = "qup-core", "qup-config"; 1292 status = "disabled"; 1293 }; 1294 1295 i2c13: i2c@a94000 { 1296 compatible = "qcom,geni-i2c"; 1297 reg = <0 0x00a94000 0 0x4000>; 1298 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1299 clock-names = "se"; 1300 pinctrl-names = "default"; 1301 pinctrl-0 = <&qup_i2c13_data_clk>; 1302 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1303 #address-cells = <1>; 1304 #size-cells = <0>; 1305 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1306 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1307 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1308 interconnect-names = "qup-core", "qup-config", 1309 "qup-memory"; 1310 status = "disabled"; 1311 }; 1312 1313 spi13: spi@a94000 { 1314 compatible = "qcom,geni-spi"; 1315 reg = <0 0x00a94000 0 0x4000>; 1316 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1317 clock-names = "se"; 1318 pinctrl-names = "default"; 1319 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1320 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1321 #address-cells = <1>; 1322 #size-cells = <0>; 1323 power-domains = <&rpmhpd SC7280_CX>; 1324 operating-points-v2 = <&qup_opp_table>; 1325 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1326 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1327 interconnect-names = "qup-core", "qup-config"; 1328 status = "disabled"; 1329 }; 1330 1331 uart13: serial@a94000 { 1332 compatible = "qcom,geni-uart"; 1333 reg = <0 0x00a94000 0 0x4000>; 1334 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1335 clock-names = "se"; 1336 pinctrl-names = "default"; 1337 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1338 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1339 power-domains = <&rpmhpd SC7280_CX>; 1340 operating-points-v2 = <&qup_opp_table>; 1341 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1342 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1343 interconnect-names = "qup-core", "qup-config"; 1344 status = "disabled"; 1345 }; 1346 1347 i2c14: i2c@a98000 { 1348 compatible = "qcom,geni-i2c"; 1349 reg = <0 0x00a98000 0 0x4000>; 1350 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1351 clock-names = "se"; 1352 pinctrl-names = "default"; 1353 pinctrl-0 = <&qup_i2c14_data_clk>; 1354 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1355 #address-cells = <1>; 1356 #size-cells = <0>; 1357 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1358 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1359 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1360 interconnect-names = "qup-core", "qup-config", 1361 "qup-memory"; 1362 status = "disabled"; 1363 }; 1364 1365 spi14: spi@a98000 { 1366 compatible = "qcom,geni-spi"; 1367 reg = <0 0x00a98000 0 0x4000>; 1368 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1369 clock-names = "se"; 1370 pinctrl-names = "default"; 1371 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1372 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1373 #address-cells = <1>; 1374 #size-cells = <0>; 1375 power-domains = <&rpmhpd SC7280_CX>; 1376 operating-points-v2 = <&qup_opp_table>; 1377 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1378 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1379 interconnect-names = "qup-core", "qup-config"; 1380 status = "disabled"; 1381 }; 1382 1383 uart14: serial@a98000 { 1384 compatible = "qcom,geni-uart"; 1385 reg = <0 0x00a98000 0 0x4000>; 1386 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1387 clock-names = "se"; 1388 pinctrl-names = "default"; 1389 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1390 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1391 power-domains = <&rpmhpd SC7280_CX>; 1392 operating-points-v2 = <&qup_opp_table>; 1393 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1394 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1395 interconnect-names = "qup-core", "qup-config"; 1396 status = "disabled"; 1397 }; 1398 1399 i2c15: i2c@a9c000 { 1400 compatible = "qcom,geni-i2c"; 1401 reg = <0 0x00a9c000 0 0x4000>; 1402 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1403 clock-names = "se"; 1404 pinctrl-names = "default"; 1405 pinctrl-0 = <&qup_i2c15_data_clk>; 1406 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1407 #address-cells = <1>; 1408 #size-cells = <0>; 1409 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1410 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1411 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1412 interconnect-names = "qup-core", "qup-config", 1413 "qup-memory"; 1414 status = "disabled"; 1415 }; 1416 1417 spi15: spi@a9c000 { 1418 compatible = "qcom,geni-spi"; 1419 reg = <0 0x00a9c000 0 0x4000>; 1420 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1421 clock-names = "se"; 1422 pinctrl-names = "default"; 1423 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1424 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1425 #address-cells = <1>; 1426 #size-cells = <0>; 1427 power-domains = <&rpmhpd SC7280_CX>; 1428 operating-points-v2 = <&qup_opp_table>; 1429 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1430 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1431 interconnect-names = "qup-core", "qup-config"; 1432 status = "disabled"; 1433 }; 1434 1435 uart15: serial@a9c000 { 1436 compatible = "qcom,geni-uart"; 1437 reg = <0 0x00a9c000 0 0x4000>; 1438 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1439 clock-names = "se"; 1440 pinctrl-names = "default"; 1441 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1442 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1443 power-domains = <&rpmhpd SC7280_CX>; 1444 operating-points-v2 = <&qup_opp_table>; 1445 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1446 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1447 interconnect-names = "qup-core", "qup-config"; 1448 status = "disabled"; 1449 }; 1450 }; 1451 1452 cnoc2: interconnect@1500000 { 1453 reg = <0 0x01500000 0 0x1000>; 1454 compatible = "qcom,sc7280-cnoc2"; 1455 #interconnect-cells = <2>; 1456 qcom,bcm-voters = <&apps_bcm_voter>; 1457 }; 1458 1459 cnoc3: interconnect@1502000 { 1460 reg = <0 0x01502000 0 0x1000>; 1461 compatible = "qcom,sc7280-cnoc3"; 1462 #interconnect-cells = <2>; 1463 qcom,bcm-voters = <&apps_bcm_voter>; 1464 }; 1465 1466 mc_virt: interconnect@1580000 { 1467 reg = <0 0x01580000 0 0x4>; 1468 compatible = "qcom,sc7280-mc-virt"; 1469 #interconnect-cells = <2>; 1470 qcom,bcm-voters = <&apps_bcm_voter>; 1471 }; 1472 1473 system_noc: interconnect@1680000 { 1474 reg = <0 0x01680000 0 0x15480>; 1475 compatible = "qcom,sc7280-system-noc"; 1476 #interconnect-cells = <2>; 1477 qcom,bcm-voters = <&apps_bcm_voter>; 1478 }; 1479 1480 aggre1_noc: interconnect@16e0000 { 1481 compatible = "qcom,sc7280-aggre1-noc"; 1482 reg = <0 0x016e0000 0 0x1c080>; 1483 #interconnect-cells = <2>; 1484 qcom,bcm-voters = <&apps_bcm_voter>; 1485 }; 1486 1487 aggre2_noc: interconnect@1700000 { 1488 reg = <0 0x01700000 0 0x2b080>; 1489 compatible = "qcom,sc7280-aggre2-noc"; 1490 #interconnect-cells = <2>; 1491 qcom,bcm-voters = <&apps_bcm_voter>; 1492 }; 1493 1494 mmss_noc: interconnect@1740000 { 1495 reg = <0 0x01740000 0 0x1e080>; 1496 compatible = "qcom,sc7280-mmss-noc"; 1497 #interconnect-cells = <2>; 1498 qcom,bcm-voters = <&apps_bcm_voter>; 1499 }; 1500 1501 ipa: ipa@1e40000 { 1502 compatible = "qcom,sc7280-ipa"; 1503 1504 iommus = <&apps_smmu 0x480 0x0>, 1505 <&apps_smmu 0x482 0x0>; 1506 reg = <0 0x1e40000 0 0x8000>, 1507 <0 0x1e50000 0 0x4ad0>, 1508 <0 0x1e04000 0 0x23000>; 1509 reg-names = "ipa-reg", 1510 "ipa-shared", 1511 "gsi"; 1512 1513 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 1514 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1515 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1516 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1517 interrupt-names = "ipa", 1518 "gsi", 1519 "ipa-clock-query", 1520 "ipa-setup-ready"; 1521 1522 clocks = <&rpmhcc RPMH_IPA_CLK>; 1523 clock-names = "core"; 1524 1525 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1526 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 1527 interconnect-names = "memory", 1528 "config"; 1529 1530 qcom,smem-states = <&ipa_smp2p_out 0>, 1531 <&ipa_smp2p_out 1>; 1532 qcom,smem-state-names = "ipa-clock-enabled-valid", 1533 "ipa-clock-enabled"; 1534 1535 status = "disabled"; 1536 }; 1537 1538 tcsr_mutex: hwlock@1f40000 { 1539 compatible = "qcom,tcsr-mutex", "syscon"; 1540 reg = <0 0x01f40000 0 0x40000>; 1541 #hwlock-cells = <1>; 1542 }; 1543 1544 lpasscc: lpasscc@3000000 { 1545 compatible = "qcom,sc7280-lpasscc"; 1546 reg = <0 0x03000000 0 0x40>, 1547 <0 0x03c04000 0 0x4>, 1548 <0 0x03389000 0 0x24>; 1549 reg-names = "qdsp6ss", "top_cc", "cc"; 1550 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 1551 clock-names = "iface"; 1552 #clock-cells = <1>; 1553 }; 1554 1555 lpass_ag_noc: interconnect@3c40000 { 1556 reg = <0 0x03c40000 0 0xf080>; 1557 compatible = "qcom,sc7280-lpass-ag-noc"; 1558 #interconnect-cells = <2>; 1559 qcom,bcm-voters = <&apps_bcm_voter>; 1560 }; 1561 1562 gpu: gpu@3d00000 { 1563 compatible = "qcom,adreno-635.0", "qcom,adreno"; 1564 #stream-id-cells = <16>; 1565 reg = <0 0x03d00000 0 0x40000>, 1566 <0 0x03d9e000 0 0x1000>, 1567 <0 0x03d61000 0 0x800>; 1568 reg-names = "kgsl_3d0_reg_memory", 1569 "cx_mem", 1570 "cx_dbgc"; 1571 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1572 iommus = <&adreno_smmu 0 0x401>; 1573 operating-points-v2 = <&gpu_opp_table>; 1574 qcom,gmu = <&gmu>; 1575 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 1576 interconnect-names = "gfx-mem"; 1577 #cooling-cells = <2>; 1578 1579 gpu_opp_table: opp-table { 1580 compatible = "operating-points-v2"; 1581 1582 opp-315000000 { 1583 opp-hz = /bits/ 64 <315000000>; 1584 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1585 opp-peak-kBps = <1804000>; 1586 }; 1587 1588 opp-450000000 { 1589 opp-hz = /bits/ 64 <450000000>; 1590 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1591 opp-peak-kBps = <4068000>; 1592 }; 1593 1594 opp-550000000 { 1595 opp-hz = /bits/ 64 <550000000>; 1596 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1597 opp-peak-kBps = <6832000>; 1598 }; 1599 }; 1600 }; 1601 1602 gmu: gmu@3d69000 { 1603 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 1604 reg = <0 0x03d6a000 0 0x34000>, 1605 <0 0x3de0000 0 0x10000>, 1606 <0 0x0b290000 0 0x10000>; 1607 reg-names = "gmu", "rscc", "gmu_pdc"; 1608 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1610 interrupt-names = "hfi", "gmu"; 1611 clocks = <&gpucc 5>, 1612 <&gpucc 8>, 1613 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1614 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1615 <&gpucc 2>, 1616 <&gpucc 15>, 1617 <&gpucc 11>; 1618 clock-names = "gmu", 1619 "cxo", 1620 "axi", 1621 "memnoc", 1622 "ahb", 1623 "hub", 1624 "smmu_vote"; 1625 power-domains = <&gpucc 0>, 1626 <&gpucc 1>; 1627 power-domain-names = "cx", 1628 "gx"; 1629 iommus = <&adreno_smmu 5 0x400>; 1630 operating-points-v2 = <&gmu_opp_table>; 1631 1632 gmu_opp_table: opp-table { 1633 compatible = "operating-points-v2"; 1634 1635 opp-200000000 { 1636 opp-hz = /bits/ 64 <200000000>; 1637 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1638 }; 1639 }; 1640 }; 1641 1642 gpucc: clock-controller@3d90000 { 1643 compatible = "qcom,sc7280-gpucc"; 1644 reg = <0 0x03d90000 0 0x9000>; 1645 clocks = <&rpmhcc RPMH_CXO_CLK>, 1646 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1647 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1648 clock-names = "bi_tcxo", 1649 "gcc_gpu_gpll0_clk_src", 1650 "gcc_gpu_gpll0_div_clk_src"; 1651 #clock-cells = <1>; 1652 #reset-cells = <1>; 1653 #power-domain-cells = <1>; 1654 }; 1655 1656 adreno_smmu: iommu@3da0000 { 1657 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 1658 reg = <0 0x03da0000 0 0x20000>; 1659 #iommu-cells = <2>; 1660 #global-interrupts = <2>; 1661 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1662 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 1663 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1665 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1666 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1667 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1668 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1669 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1670 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1672 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1673 1674 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1675 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1676 <&gpucc 2>, 1677 <&gpucc 11>, 1678 <&gpucc 5>, 1679 <&gpucc 15>, 1680 <&gpucc 13>; 1681 clock-names = "gcc_gpu_memnoc_gfx_clk", 1682 "gcc_gpu_snoc_dvm_gfx_clk", 1683 "gpu_cc_ahb_clk", 1684 "gpu_cc_hlos1_vote_gpu_smmu_clk", 1685 "gpu_cc_cx_gmu_clk", 1686 "gpu_cc_hub_cx_int_clk", 1687 "gpu_cc_hub_aon_clk"; 1688 1689 power-domains = <&gpucc 0>; 1690 }; 1691 1692 stm@6002000 { 1693 compatible = "arm,coresight-stm", "arm,primecell"; 1694 reg = <0 0x06002000 0 0x1000>, 1695 <0 0x16280000 0 0x180000>; 1696 reg-names = "stm-base", "stm-stimulus-base"; 1697 1698 clocks = <&aoss_qmp>; 1699 clock-names = "apb_pclk"; 1700 1701 out-ports { 1702 port { 1703 stm_out: endpoint { 1704 remote-endpoint = <&funnel0_in7>; 1705 }; 1706 }; 1707 }; 1708 }; 1709 1710 funnel@6041000 { 1711 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1712 reg = <0 0x06041000 0 0x1000>; 1713 1714 clocks = <&aoss_qmp>; 1715 clock-names = "apb_pclk"; 1716 1717 out-ports { 1718 port { 1719 funnel0_out: endpoint { 1720 remote-endpoint = <&merge_funnel_in0>; 1721 }; 1722 }; 1723 }; 1724 1725 in-ports { 1726 #address-cells = <1>; 1727 #size-cells = <0>; 1728 1729 port@7 { 1730 reg = <7>; 1731 funnel0_in7: endpoint { 1732 remote-endpoint = <&stm_out>; 1733 }; 1734 }; 1735 }; 1736 }; 1737 1738 funnel@6042000 { 1739 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1740 reg = <0 0x06042000 0 0x1000>; 1741 1742 clocks = <&aoss_qmp>; 1743 clock-names = "apb_pclk"; 1744 1745 out-ports { 1746 port { 1747 funnel1_out: endpoint { 1748 remote-endpoint = <&merge_funnel_in1>; 1749 }; 1750 }; 1751 }; 1752 1753 in-ports { 1754 #address-cells = <1>; 1755 #size-cells = <0>; 1756 1757 port@4 { 1758 reg = <4>; 1759 funnel1_in4: endpoint { 1760 remote-endpoint = <&apss_merge_funnel_out>; 1761 }; 1762 }; 1763 }; 1764 }; 1765 1766 funnel@6045000 { 1767 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1768 reg = <0 0x06045000 0 0x1000>; 1769 1770 clocks = <&aoss_qmp>; 1771 clock-names = "apb_pclk"; 1772 1773 out-ports { 1774 port { 1775 merge_funnel_out: endpoint { 1776 remote-endpoint = <&swao_funnel_in>; 1777 }; 1778 }; 1779 }; 1780 1781 in-ports { 1782 #address-cells = <1>; 1783 #size-cells = <0>; 1784 1785 port@0 { 1786 reg = <0>; 1787 merge_funnel_in0: endpoint { 1788 remote-endpoint = <&funnel0_out>; 1789 }; 1790 }; 1791 1792 port@1 { 1793 reg = <1>; 1794 merge_funnel_in1: endpoint { 1795 remote-endpoint = <&funnel1_out>; 1796 }; 1797 }; 1798 }; 1799 }; 1800 1801 replicator@6046000 { 1802 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1803 reg = <0 0x06046000 0 0x1000>; 1804 1805 clocks = <&aoss_qmp>; 1806 clock-names = "apb_pclk"; 1807 1808 out-ports { 1809 port { 1810 replicator_out: endpoint { 1811 remote-endpoint = <&etr_in>; 1812 }; 1813 }; 1814 }; 1815 1816 in-ports { 1817 port { 1818 replicator_in: endpoint { 1819 remote-endpoint = <&swao_replicator_out>; 1820 }; 1821 }; 1822 }; 1823 }; 1824 1825 etr@6048000 { 1826 compatible = "arm,coresight-tmc", "arm,primecell"; 1827 reg = <0 0x06048000 0 0x1000>; 1828 iommus = <&apps_smmu 0x04c0 0>; 1829 1830 clocks = <&aoss_qmp>; 1831 clock-names = "apb_pclk"; 1832 arm,scatter-gather; 1833 1834 in-ports { 1835 port { 1836 etr_in: endpoint { 1837 remote-endpoint = <&replicator_out>; 1838 }; 1839 }; 1840 }; 1841 }; 1842 1843 funnel@6b04000 { 1844 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1845 reg = <0 0x06b04000 0 0x1000>; 1846 1847 clocks = <&aoss_qmp>; 1848 clock-names = "apb_pclk"; 1849 1850 out-ports { 1851 port { 1852 swao_funnel_out: endpoint { 1853 remote-endpoint = <&etf_in>; 1854 }; 1855 }; 1856 }; 1857 1858 in-ports { 1859 #address-cells = <1>; 1860 #size-cells = <0>; 1861 1862 port@7 { 1863 reg = <7>; 1864 swao_funnel_in: endpoint { 1865 remote-endpoint = <&merge_funnel_out>; 1866 }; 1867 }; 1868 }; 1869 }; 1870 1871 etf@6b05000 { 1872 compatible = "arm,coresight-tmc", "arm,primecell"; 1873 reg = <0 0x06b05000 0 0x1000>; 1874 1875 clocks = <&aoss_qmp>; 1876 clock-names = "apb_pclk"; 1877 1878 out-ports { 1879 port { 1880 etf_out: endpoint { 1881 remote-endpoint = <&swao_replicator_in>; 1882 }; 1883 }; 1884 }; 1885 1886 in-ports { 1887 port { 1888 etf_in: endpoint { 1889 remote-endpoint = <&swao_funnel_out>; 1890 }; 1891 }; 1892 }; 1893 }; 1894 1895 replicator@6b06000 { 1896 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1897 reg = <0 0x06b06000 0 0x1000>; 1898 1899 clocks = <&aoss_qmp>; 1900 clock-names = "apb_pclk"; 1901 qcom,replicator-loses-context; 1902 1903 out-ports { 1904 port { 1905 swao_replicator_out: endpoint { 1906 remote-endpoint = <&replicator_in>; 1907 }; 1908 }; 1909 }; 1910 1911 in-ports { 1912 port { 1913 swao_replicator_in: endpoint { 1914 remote-endpoint = <&etf_out>; 1915 }; 1916 }; 1917 }; 1918 }; 1919 1920 etm@7040000 { 1921 compatible = "arm,coresight-etm4x", "arm,primecell"; 1922 reg = <0 0x07040000 0 0x1000>; 1923 1924 cpu = <&CPU0>; 1925 1926 clocks = <&aoss_qmp>; 1927 clock-names = "apb_pclk"; 1928 arm,coresight-loses-context-with-cpu; 1929 qcom,skip-power-up; 1930 1931 out-ports { 1932 port { 1933 etm0_out: endpoint { 1934 remote-endpoint = <&apss_funnel_in0>; 1935 }; 1936 }; 1937 }; 1938 }; 1939 1940 etm@7140000 { 1941 compatible = "arm,coresight-etm4x", "arm,primecell"; 1942 reg = <0 0x07140000 0 0x1000>; 1943 1944 cpu = <&CPU1>; 1945 1946 clocks = <&aoss_qmp>; 1947 clock-names = "apb_pclk"; 1948 arm,coresight-loses-context-with-cpu; 1949 qcom,skip-power-up; 1950 1951 out-ports { 1952 port { 1953 etm1_out: endpoint { 1954 remote-endpoint = <&apss_funnel_in1>; 1955 }; 1956 }; 1957 }; 1958 }; 1959 1960 etm@7240000 { 1961 compatible = "arm,coresight-etm4x", "arm,primecell"; 1962 reg = <0 0x07240000 0 0x1000>; 1963 1964 cpu = <&CPU2>; 1965 1966 clocks = <&aoss_qmp>; 1967 clock-names = "apb_pclk"; 1968 arm,coresight-loses-context-with-cpu; 1969 qcom,skip-power-up; 1970 1971 out-ports { 1972 port { 1973 etm2_out: endpoint { 1974 remote-endpoint = <&apss_funnel_in2>; 1975 }; 1976 }; 1977 }; 1978 }; 1979 1980 etm@7340000 { 1981 compatible = "arm,coresight-etm4x", "arm,primecell"; 1982 reg = <0 0x07340000 0 0x1000>; 1983 1984 cpu = <&CPU3>; 1985 1986 clocks = <&aoss_qmp>; 1987 clock-names = "apb_pclk"; 1988 arm,coresight-loses-context-with-cpu; 1989 qcom,skip-power-up; 1990 1991 out-ports { 1992 port { 1993 etm3_out: endpoint { 1994 remote-endpoint = <&apss_funnel_in3>; 1995 }; 1996 }; 1997 }; 1998 }; 1999 2000 etm@7440000 { 2001 compatible = "arm,coresight-etm4x", "arm,primecell"; 2002 reg = <0 0x07440000 0 0x1000>; 2003 2004 cpu = <&CPU4>; 2005 2006 clocks = <&aoss_qmp>; 2007 clock-names = "apb_pclk"; 2008 arm,coresight-loses-context-with-cpu; 2009 qcom,skip-power-up; 2010 2011 out-ports { 2012 port { 2013 etm4_out: endpoint { 2014 remote-endpoint = <&apss_funnel_in4>; 2015 }; 2016 }; 2017 }; 2018 }; 2019 2020 etm@7540000 { 2021 compatible = "arm,coresight-etm4x", "arm,primecell"; 2022 reg = <0 0x07540000 0 0x1000>; 2023 2024 cpu = <&CPU5>; 2025 2026 clocks = <&aoss_qmp>; 2027 clock-names = "apb_pclk"; 2028 arm,coresight-loses-context-with-cpu; 2029 qcom,skip-power-up; 2030 2031 out-ports { 2032 port { 2033 etm5_out: endpoint { 2034 remote-endpoint = <&apss_funnel_in5>; 2035 }; 2036 }; 2037 }; 2038 }; 2039 2040 etm@7640000 { 2041 compatible = "arm,coresight-etm4x", "arm,primecell"; 2042 reg = <0 0x07640000 0 0x1000>; 2043 2044 cpu = <&CPU6>; 2045 2046 clocks = <&aoss_qmp>; 2047 clock-names = "apb_pclk"; 2048 arm,coresight-loses-context-with-cpu; 2049 qcom,skip-power-up; 2050 2051 out-ports { 2052 port { 2053 etm6_out: endpoint { 2054 remote-endpoint = <&apss_funnel_in6>; 2055 }; 2056 }; 2057 }; 2058 }; 2059 2060 etm@7740000 { 2061 compatible = "arm,coresight-etm4x", "arm,primecell"; 2062 reg = <0 0x07740000 0 0x1000>; 2063 2064 cpu = <&CPU7>; 2065 2066 clocks = <&aoss_qmp>; 2067 clock-names = "apb_pclk"; 2068 arm,coresight-loses-context-with-cpu; 2069 qcom,skip-power-up; 2070 2071 out-ports { 2072 port { 2073 etm7_out: endpoint { 2074 remote-endpoint = <&apss_funnel_in7>; 2075 }; 2076 }; 2077 }; 2078 }; 2079 2080 funnel@7800000 { /* APSS Funnel */ 2081 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2082 reg = <0 0x07800000 0 0x1000>; 2083 2084 clocks = <&aoss_qmp>; 2085 clock-names = "apb_pclk"; 2086 2087 out-ports { 2088 port { 2089 apss_funnel_out: endpoint { 2090 remote-endpoint = <&apss_merge_funnel_in>; 2091 }; 2092 }; 2093 }; 2094 2095 in-ports { 2096 #address-cells = <1>; 2097 #size-cells = <0>; 2098 2099 port@0 { 2100 reg = <0>; 2101 apss_funnel_in0: endpoint { 2102 remote-endpoint = <&etm0_out>; 2103 }; 2104 }; 2105 2106 port@1 { 2107 reg = <1>; 2108 apss_funnel_in1: endpoint { 2109 remote-endpoint = <&etm1_out>; 2110 }; 2111 }; 2112 2113 port@2 { 2114 reg = <2>; 2115 apss_funnel_in2: endpoint { 2116 remote-endpoint = <&etm2_out>; 2117 }; 2118 }; 2119 2120 port@3 { 2121 reg = <3>; 2122 apss_funnel_in3: endpoint { 2123 remote-endpoint = <&etm3_out>; 2124 }; 2125 }; 2126 2127 port@4 { 2128 reg = <4>; 2129 apss_funnel_in4: endpoint { 2130 remote-endpoint = <&etm4_out>; 2131 }; 2132 }; 2133 2134 port@5 { 2135 reg = <5>; 2136 apss_funnel_in5: endpoint { 2137 remote-endpoint = <&etm5_out>; 2138 }; 2139 }; 2140 2141 port@6 { 2142 reg = <6>; 2143 apss_funnel_in6: endpoint { 2144 remote-endpoint = <&etm6_out>; 2145 }; 2146 }; 2147 2148 port@7 { 2149 reg = <7>; 2150 apss_funnel_in7: endpoint { 2151 remote-endpoint = <&etm7_out>; 2152 }; 2153 }; 2154 }; 2155 }; 2156 2157 funnel@7810000 { 2158 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2159 reg = <0 0x07810000 0 0x1000>; 2160 2161 clocks = <&aoss_qmp>; 2162 clock-names = "apb_pclk"; 2163 2164 out-ports { 2165 port { 2166 apss_merge_funnel_out: endpoint { 2167 remote-endpoint = <&funnel1_in4>; 2168 }; 2169 }; 2170 }; 2171 2172 in-ports { 2173 port { 2174 apss_merge_funnel_in: endpoint { 2175 remote-endpoint = <&apss_funnel_out>; 2176 }; 2177 }; 2178 }; 2179 }; 2180 2181 sdhc_2: sdhci@8804000 { 2182 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 2183 status = "disabled"; 2184 2185 reg = <0 0x08804000 0 0x1000>; 2186 2187 iommus = <&apps_smmu 0x100 0x0>; 2188 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2189 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2190 interrupt-names = "hc_irq", "pwr_irq"; 2191 2192 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2193 <&gcc GCC_SDCC2_AHB_CLK>, 2194 <&rpmhcc RPMH_CXO_CLK>; 2195 clock-names = "core", "iface", "xo"; 2196 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2197 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 2198 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2199 power-domains = <&rpmhpd SC7280_CX>; 2200 operating-points-v2 = <&sdhc2_opp_table>; 2201 2202 bus-width = <4>; 2203 2204 qcom,dll-config = <0x0007642c>; 2205 2206 sdhc2_opp_table: opp-table { 2207 compatible = "operating-points-v2"; 2208 2209 opp-100000000 { 2210 opp-hz = /bits/ 64 <100000000>; 2211 required-opps = <&rpmhpd_opp_low_svs>; 2212 opp-peak-kBps = <1800000 400000>; 2213 opp-avg-kBps = <100000 0>; 2214 }; 2215 2216 opp-202000000 { 2217 opp-hz = /bits/ 64 <202000000>; 2218 required-opps = <&rpmhpd_opp_nom>; 2219 opp-peak-kBps = <5400000 1600000>; 2220 opp-avg-kBps = <200000 0>; 2221 }; 2222 }; 2223 2224 }; 2225 2226 usb_1_hsphy: phy@88e3000 { 2227 compatible = "qcom,sc7280-usb-hs-phy", 2228 "qcom,usb-snps-hs-7nm-phy"; 2229 reg = <0 0x088e3000 0 0x400>; 2230 status = "disabled"; 2231 #phy-cells = <0>; 2232 2233 clocks = <&rpmhcc RPMH_CXO_CLK>; 2234 clock-names = "ref"; 2235 2236 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2237 }; 2238 2239 usb_2_hsphy: phy@88e4000 { 2240 compatible = "qcom,sc7280-usb-hs-phy", 2241 "qcom,usb-snps-hs-7nm-phy"; 2242 reg = <0 0x088e4000 0 0x400>; 2243 status = "disabled"; 2244 #phy-cells = <0>; 2245 2246 clocks = <&rpmhcc RPMH_CXO_CLK>; 2247 clock-names = "ref"; 2248 2249 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2250 }; 2251 2252 usb_1_qmpphy: phy-wrapper@88e9000 { 2253 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 2254 "qcom,sm8250-qmp-usb3-dp-phy"; 2255 reg = <0 0x088e9000 0 0x200>, 2256 <0 0x088e8000 0 0x40>, 2257 <0 0x088ea000 0 0x200>; 2258 status = "disabled"; 2259 #address-cells = <2>; 2260 #size-cells = <2>; 2261 ranges; 2262 2263 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2264 <&rpmhcc RPMH_CXO_CLK>, 2265 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2266 clock-names = "aux", "ref_clk_src", "com_aux"; 2267 2268 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2269 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2270 reset-names = "phy", "common"; 2271 2272 usb_1_ssphy: usb3-phy@88e9200 { 2273 reg = <0 0x088e9200 0 0x200>, 2274 <0 0x088e9400 0 0x200>, 2275 <0 0x088e9c00 0 0x400>, 2276 <0 0x088e9600 0 0x200>, 2277 <0 0x088e9800 0 0x200>, 2278 <0 0x088e9a00 0 0x100>; 2279 #clock-cells = <0>; 2280 #phy-cells = <0>; 2281 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2282 clock-names = "pipe0"; 2283 clock-output-names = "usb3_phy_pipe_clk_src"; 2284 }; 2285 2286 dp_phy: dp-phy@88ea200 { 2287 reg = <0 0x088ea200 0 0x200>, 2288 <0 0x088ea400 0 0x200>, 2289 <0 0x088eaa00 0 0x200>, 2290 <0 0x088ea600 0 0x200>, 2291 <0 0x088ea800 0 0x200>; 2292 #phy-cells = <0>; 2293 #clock-cells = <1>; 2294 }; 2295 }; 2296 2297 usb_2: usb@8cf8800 { 2298 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2299 reg = <0 0x08cf8800 0 0x400>; 2300 status = "disabled"; 2301 #address-cells = <2>; 2302 #size-cells = <2>; 2303 ranges; 2304 dma-ranges; 2305 2306 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2307 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2308 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2309 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2310 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 2311 clock-names = "cfg_noc", "core", "iface","mock_utmi", 2312 "sleep"; 2313 2314 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2315 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2316 assigned-clock-rates = <19200000>, <200000000>; 2317 2318 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2319 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 2320 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 2321 interrupt-names = "hs_phy_irq", 2322 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2323 2324 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 2325 2326 resets = <&gcc GCC_USB30_SEC_BCR>; 2327 2328 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 2329 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 2330 interconnect-names = "usb-ddr", "apps-usb"; 2331 2332 usb_2_dwc3: usb@8c00000 { 2333 compatible = "snps,dwc3"; 2334 reg = <0 0x08c00000 0 0xe000>; 2335 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2336 iommus = <&apps_smmu 0xa0 0x0>; 2337 snps,dis_u2_susphy_quirk; 2338 snps,dis_enblslpm_quirk; 2339 phys = <&usb_2_hsphy>; 2340 phy-names = "usb2-phy"; 2341 maximum-speed = "high-speed"; 2342 }; 2343 }; 2344 2345 qspi: spi@88dc000 { 2346 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 2347 reg = <0 0x088dc000 0 0x1000>; 2348 #address-cells = <1>; 2349 #size-cells = <0>; 2350 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2351 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2352 <&gcc GCC_QSPI_CORE_CLK>; 2353 clock-names = "iface", "core"; 2354 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2355 &cnoc2 SLAVE_QSPI_0 0>; 2356 interconnect-names = "qspi-config"; 2357 power-domains = <&rpmhpd SC7280_CX>; 2358 operating-points-v2 = <&qspi_opp_table>; 2359 status = "disabled"; 2360 }; 2361 2362 dc_noc: interconnect@90e0000 { 2363 reg = <0 0x090e0000 0 0x5080>; 2364 compatible = "qcom,sc7280-dc-noc"; 2365 #interconnect-cells = <2>; 2366 qcom,bcm-voters = <&apps_bcm_voter>; 2367 }; 2368 2369 gem_noc: interconnect@9100000 { 2370 reg = <0 0x9100000 0 0xe2200>; 2371 compatible = "qcom,sc7280-gem-noc"; 2372 #interconnect-cells = <2>; 2373 qcom,bcm-voters = <&apps_bcm_voter>; 2374 }; 2375 2376 system-cache-controller@9200000 { 2377 compatible = "qcom,sc7280-llcc"; 2378 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 2379 reg-names = "llcc_base", "llcc_broadcast_base"; 2380 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2381 }; 2382 2383 nsp_noc: interconnect@a0c0000 { 2384 reg = <0 0x0a0c0000 0 0x10000>; 2385 compatible = "qcom,sc7280-nsp-noc"; 2386 #interconnect-cells = <2>; 2387 qcom,bcm-voters = <&apps_bcm_voter>; 2388 }; 2389 2390 usb_1: usb@a6f8800 { 2391 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2392 reg = <0 0x0a6f8800 0 0x400>; 2393 status = "disabled"; 2394 #address-cells = <2>; 2395 #size-cells = <2>; 2396 ranges; 2397 dma-ranges; 2398 2399 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2400 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2401 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2402 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2403 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2404 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2405 "sleep"; 2406 2407 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2408 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2409 assigned-clock-rates = <19200000>, <200000000>; 2410 2411 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2412 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2413 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2414 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2415 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2416 "dm_hs_phy_irq", "ss_phy_irq"; 2417 2418 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 2419 2420 resets = <&gcc GCC_USB30_PRIM_BCR>; 2421 2422 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2423 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 2424 interconnect-names = "usb-ddr", "apps-usb"; 2425 2426 usb_1_dwc3: usb@a600000 { 2427 compatible = "snps,dwc3"; 2428 reg = <0 0x0a600000 0 0xe000>; 2429 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2430 iommus = <&apps_smmu 0xe0 0x0>; 2431 snps,dis_u2_susphy_quirk; 2432 snps,dis_enblslpm_quirk; 2433 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2434 phy-names = "usb2-phy", "usb3-phy"; 2435 maximum-speed = "super-speed"; 2436 }; 2437 }; 2438 2439 videocc: clock-controller@aaf0000 { 2440 compatible = "qcom,sc7280-videocc"; 2441 reg = <0 0xaaf0000 0 0x10000>; 2442 clocks = <&rpmhcc RPMH_CXO_CLK>, 2443 <&rpmhcc RPMH_CXO_CLK_A>; 2444 clock-names = "bi_tcxo", "bi_tcxo_ao"; 2445 #clock-cells = <1>; 2446 #reset-cells = <1>; 2447 #power-domain-cells = <1>; 2448 }; 2449 2450 dispcc: clock-controller@af00000 { 2451 compatible = "qcom,sc7280-dispcc"; 2452 reg = <0 0xaf00000 0 0x20000>; 2453 clocks = <&rpmhcc RPMH_CXO_CLK>, 2454 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2455 <0>, <0>, <0>, <0>, <0>, <0>; 2456 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 2457 "dsi0_phy_pll_out_byteclk", 2458 "dsi0_phy_pll_out_dsiclk", 2459 "dp_phy_pll_link_clk", 2460 "dp_phy_pll_vco_div_clk", 2461 "edp_phy_pll_link_clk", 2462 "edp_phy_pll_vco_div_clk"; 2463 #clock-cells = <1>; 2464 #reset-cells = <1>; 2465 #power-domain-cells = <1>; 2466 }; 2467 2468 pdc: interrupt-controller@b220000 { 2469 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 2470 reg = <0 0x0b220000 0 0x30000>; 2471 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 2472 <55 306 4>, <59 312 3>, <62 374 2>, 2473 <64 434 2>, <66 438 3>, <69 86 1>, 2474 <70 520 54>, <124 609 31>, <155 63 1>, 2475 <156 716 12>; 2476 #interrupt-cells = <2>; 2477 interrupt-parent = <&intc>; 2478 interrupt-controller; 2479 }; 2480 2481 pdc_reset: reset-controller@b5e0000 { 2482 compatible = "qcom,sc7280-pdc-global"; 2483 reg = <0 0x0b5e0000 0 0x20000>; 2484 #reset-cells = <1>; 2485 }; 2486 2487 tsens0: thermal-sensor@c263000 { 2488 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 2489 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2490 <0 0x0c222000 0 0x1ff>; /* SROT */ 2491 #qcom,sensors = <15>; 2492 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2493 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2494 interrupt-names = "uplow","critical"; 2495 #thermal-sensor-cells = <1>; 2496 }; 2497 2498 tsens1: thermal-sensor@c265000 { 2499 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 2500 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2501 <0 0x0c223000 0 0x1ff>; /* SROT */ 2502 #qcom,sensors = <12>; 2503 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2504 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2505 interrupt-names = "uplow","critical"; 2506 #thermal-sensor-cells = <1>; 2507 }; 2508 2509 aoss_reset: reset-controller@c2a0000 { 2510 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 2511 reg = <0 0x0c2a0000 0 0x31000>; 2512 #reset-cells = <1>; 2513 }; 2514 2515 aoss_qmp: power-controller@c300000 { 2516 compatible = "qcom,sc7280-aoss-qmp"; 2517 reg = <0 0x0c300000 0 0x100000>; 2518 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 2519 IPCC_MPROC_SIGNAL_GLINK_QMP 2520 IRQ_TYPE_EDGE_RISING>; 2521 mboxes = <&ipcc IPCC_CLIENT_AOP 2522 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2523 2524 #clock-cells = <0>; 2525 #power-domain-cells = <1>; 2526 }; 2527 2528 spmi_bus: spmi@c440000 { 2529 compatible = "qcom,spmi-pmic-arb"; 2530 reg = <0 0x0c440000 0 0x1100>, 2531 <0 0x0c600000 0 0x2000000>, 2532 <0 0x0e600000 0 0x100000>, 2533 <0 0x0e700000 0 0xa0000>, 2534 <0 0x0c40a000 0 0x26000>; 2535 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2536 interrupt-names = "periph_irq"; 2537 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2538 qcom,ee = <0>; 2539 qcom,channel = <0>; 2540 #address-cells = <1>; 2541 #size-cells = <1>; 2542 interrupt-controller; 2543 #interrupt-cells = <4>; 2544 }; 2545 2546 tlmm: pinctrl@f100000 { 2547 compatible = "qcom,sc7280-pinctrl"; 2548 reg = <0 0x0f100000 0 0x300000>; 2549 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2550 gpio-controller; 2551 #gpio-cells = <2>; 2552 interrupt-controller; 2553 #interrupt-cells = <2>; 2554 gpio-ranges = <&tlmm 0 0 175>; 2555 wakeup-parent = <&pdc>; 2556 2557 qspi_clk: qspi-clk { 2558 pins = "gpio14"; 2559 function = "qspi_clk"; 2560 }; 2561 2562 qspi_cs0: qspi-cs0 { 2563 pins = "gpio15"; 2564 function = "qspi_cs"; 2565 }; 2566 2567 qspi_cs1: qspi-cs1 { 2568 pins = "gpio19"; 2569 function = "qspi_cs"; 2570 }; 2571 2572 qspi_data01: qspi-data01 { 2573 pins = "gpio12", "gpio13"; 2574 function = "qspi_data"; 2575 }; 2576 2577 qspi_data12: qspi-data12 { 2578 pins = "gpio16", "gpio17"; 2579 function = "qspi_data"; 2580 }; 2581 2582 qup_i2c0_data_clk: qup-i2c0-data-clk { 2583 pins = "gpio0", "gpio1"; 2584 function = "qup00"; 2585 }; 2586 2587 qup_i2c1_data_clk: qup-i2c1-data-clk { 2588 pins = "gpio4", "gpio5"; 2589 function = "qup01"; 2590 }; 2591 2592 qup_i2c2_data_clk: qup-i2c2-data-clk { 2593 pins = "gpio8", "gpio9"; 2594 function = "qup02"; 2595 }; 2596 2597 qup_i2c3_data_clk: qup-i2c3-data-clk { 2598 pins = "gpio12", "gpio13"; 2599 function = "qup03"; 2600 }; 2601 2602 qup_i2c4_data_clk: qup-i2c4-data-clk { 2603 pins = "gpio16", "gpio17"; 2604 function = "qup04"; 2605 }; 2606 2607 qup_i2c5_data_clk: qup-i2c5-data-clk { 2608 pins = "gpio20", "gpio21"; 2609 function = "qup05"; 2610 }; 2611 2612 qup_i2c6_data_clk: qup-i2c6-data-clk { 2613 pins = "gpio24", "gpio25"; 2614 function = "qup06"; 2615 }; 2616 2617 qup_i2c7_data_clk: qup-i2c7-data-clk { 2618 pins = "gpio28", "gpio29"; 2619 function = "qup07"; 2620 }; 2621 2622 qup_i2c8_data_clk: qup-i2c8-data-clk { 2623 pins = "gpio32", "gpio33"; 2624 function = "qup10"; 2625 }; 2626 2627 qup_i2c9_data_clk: qup-i2c9-data-clk { 2628 pins = "gpio36", "gpio37"; 2629 function = "qup11"; 2630 }; 2631 2632 qup_i2c10_data_clk: qup-i2c10-data-clk { 2633 pins = "gpio40", "gpio41"; 2634 function = "qup12"; 2635 }; 2636 2637 qup_i2c11_data_clk: qup-i2c11-data-clk { 2638 pins = "gpio44", "gpio45"; 2639 function = "qup13"; 2640 }; 2641 2642 qup_i2c12_data_clk: qup-i2c12-data-clk { 2643 pins = "gpio48", "gpio49"; 2644 function = "qup14"; 2645 }; 2646 2647 qup_i2c13_data_clk: qup-i2c13-data-clk { 2648 pins = "gpio52", "gpio53"; 2649 function = "qup15"; 2650 }; 2651 2652 qup_i2c14_data_clk: qup-i2c14-data-clk { 2653 pins = "gpio56", "gpio57"; 2654 function = "qup16"; 2655 }; 2656 2657 qup_i2c15_data_clk: qup-i2c15-data-clk { 2658 pins = "gpio60", "gpio61"; 2659 function = "qup17"; 2660 }; 2661 2662 qup_spi0_data_clk: qup-spi0-data-clk { 2663 pins = "gpio0", "gpio1", "gpio2"; 2664 function = "qup00"; 2665 }; 2666 2667 qup_spi0_cs: qup-spi0-cs { 2668 pins = "gpio3"; 2669 function = "qup00"; 2670 }; 2671 2672 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 2673 pins = "gpio3"; 2674 function = "gpio"; 2675 }; 2676 2677 qup_spi1_data_clk: qup-spi1-data-clk { 2678 pins = "gpio4", "gpio5", "gpio6"; 2679 function = "qup01"; 2680 }; 2681 2682 qup_spi1_cs: qup-spi1-cs { 2683 pins = "gpio7"; 2684 function = "qup01"; 2685 }; 2686 2687 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 2688 pins = "gpio7"; 2689 function = "gpio"; 2690 }; 2691 2692 qup_spi2_data_clk: qup-spi2-data-clk { 2693 pins = "gpio8", "gpio9", "gpio10"; 2694 function = "qup02"; 2695 }; 2696 2697 qup_spi2_cs: qup-spi2-cs { 2698 pins = "gpio11"; 2699 function = "qup02"; 2700 }; 2701 2702 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 2703 pins = "gpio11"; 2704 function = "gpio"; 2705 }; 2706 2707 qup_spi3_data_clk: qup-spi3-data-clk { 2708 pins = "gpio12", "gpio13", "gpio14"; 2709 function = "qup03"; 2710 }; 2711 2712 qup_spi3_cs: qup-spi3-cs { 2713 pins = "gpio15"; 2714 function = "qup03"; 2715 }; 2716 2717 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 2718 pins = "gpio15"; 2719 function = "gpio"; 2720 }; 2721 2722 qup_spi4_data_clk: qup-spi4-data-clk { 2723 pins = "gpio16", "gpio17", "gpio18"; 2724 function = "qup04"; 2725 }; 2726 2727 qup_spi4_cs: qup-spi4-cs { 2728 pins = "gpio19"; 2729 function = "qup04"; 2730 }; 2731 2732 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 2733 pins = "gpio19"; 2734 function = "gpio"; 2735 }; 2736 2737 qup_spi5_data_clk: qup-spi5-data-clk { 2738 pins = "gpio20", "gpio21", "gpio22"; 2739 function = "qup05"; 2740 }; 2741 2742 qup_spi5_cs: qup-spi5-cs { 2743 pins = "gpio23"; 2744 function = "qup05"; 2745 }; 2746 2747 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 2748 pins = "gpio23"; 2749 function = "gpio"; 2750 }; 2751 2752 qup_spi6_data_clk: qup-spi6-data-clk { 2753 pins = "gpio24", "gpio25", "gpio26"; 2754 function = "qup06"; 2755 }; 2756 2757 qup_spi6_cs: qup-spi6-cs { 2758 pins = "gpio27"; 2759 function = "qup06"; 2760 }; 2761 2762 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 2763 pins = "gpio27"; 2764 function = "gpio"; 2765 }; 2766 2767 qup_spi7_data_clk: qup-spi7-data-clk { 2768 pins = "gpio28", "gpio29", "gpio30"; 2769 function = "qup07"; 2770 }; 2771 2772 qup_spi7_cs: qup-spi7-cs { 2773 pins = "gpio31"; 2774 function = "qup07"; 2775 }; 2776 2777 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 2778 pins = "gpio31"; 2779 function = "gpio"; 2780 }; 2781 2782 qup_spi8_data_clk: qup-spi8-data-clk { 2783 pins = "gpio32", "gpio33", "gpio34"; 2784 function = "qup10"; 2785 }; 2786 2787 qup_spi8_cs: qup-spi8-cs { 2788 pins = "gpio35"; 2789 function = "qup10"; 2790 }; 2791 2792 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 2793 pins = "gpio35"; 2794 function = "gpio"; 2795 }; 2796 2797 qup_spi9_data_clk: qup-spi9-data-clk { 2798 pins = "gpio36", "gpio37", "gpio38"; 2799 function = "qup11"; 2800 }; 2801 2802 qup_spi9_cs: qup-spi9-cs { 2803 pins = "gpio39"; 2804 function = "qup11"; 2805 }; 2806 2807 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 2808 pins = "gpio39"; 2809 function = "gpio"; 2810 }; 2811 2812 qup_spi10_data_clk: qup-spi10-data-clk { 2813 pins = "gpio40", "gpio41", "gpio42"; 2814 function = "qup12"; 2815 }; 2816 2817 qup_spi10_cs: qup-spi10-cs { 2818 pins = "gpio43"; 2819 function = "qup12"; 2820 }; 2821 2822 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 2823 pins = "gpio43"; 2824 function = "gpio"; 2825 }; 2826 2827 qup_spi11_data_clk: qup-spi11-data-clk { 2828 pins = "gpio44", "gpio45", "gpio46"; 2829 function = "qup13"; 2830 }; 2831 2832 qup_spi11_cs: qup-spi11-cs { 2833 pins = "gpio47"; 2834 function = "qup13"; 2835 }; 2836 2837 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 2838 pins = "gpio47"; 2839 function = "gpio"; 2840 }; 2841 2842 qup_spi12_data_clk: qup-spi12-data-clk { 2843 pins = "gpio48", "gpio49", "gpio50"; 2844 function = "qup14"; 2845 }; 2846 2847 qup_spi12_cs: qup-spi12-cs { 2848 pins = "gpio51"; 2849 function = "qup14"; 2850 }; 2851 2852 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 2853 pins = "gpio51"; 2854 function = "gpio"; 2855 }; 2856 2857 qup_spi13_data_clk: qup-spi13-data-clk { 2858 pins = "gpio52", "gpio53", "gpio54"; 2859 function = "qup15"; 2860 }; 2861 2862 qup_spi13_cs: qup-spi13-cs { 2863 pins = "gpio55"; 2864 function = "qup15"; 2865 }; 2866 2867 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 2868 pins = "gpio55"; 2869 function = "gpio"; 2870 }; 2871 2872 qup_spi14_data_clk: qup-spi14-data-clk { 2873 pins = "gpio56", "gpio57", "gpio58"; 2874 function = "qup16"; 2875 }; 2876 2877 qup_spi14_cs: qup-spi14-cs { 2878 pins = "gpio59"; 2879 function = "qup16"; 2880 }; 2881 2882 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 2883 pins = "gpio59"; 2884 function = "gpio"; 2885 }; 2886 2887 qup_spi15_data_clk: qup-spi15-data-clk { 2888 pins = "gpio60", "gpio61", "gpio62"; 2889 function = "qup17"; 2890 }; 2891 2892 qup_spi15_cs: qup-spi15-cs { 2893 pins = "gpio63"; 2894 function = "qup17"; 2895 }; 2896 2897 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 2898 pins = "gpio63"; 2899 function = "gpio"; 2900 }; 2901 2902 qup_uart0_cts: qup-uart0-cts { 2903 pins = "gpio0"; 2904 function = "qup00"; 2905 }; 2906 2907 qup_uart0_rts: qup-uart0-rts { 2908 pins = "gpio1"; 2909 function = "qup00"; 2910 }; 2911 2912 qup_uart0_tx: qup-uart0-tx { 2913 pins = "gpio2"; 2914 function = "qup00"; 2915 }; 2916 2917 qup_uart0_rx: qup-uart0-rx { 2918 pins = "gpio3"; 2919 function = "qup00"; 2920 }; 2921 2922 qup_uart1_cts: qup-uart1-cts { 2923 pins = "gpio4"; 2924 function = "qup01"; 2925 }; 2926 2927 qup_uart1_rts: qup-uart1-rts { 2928 pins = "gpio5"; 2929 function = "qup01"; 2930 }; 2931 2932 qup_uart1_tx: qup-uart1-tx { 2933 pins = "gpio6"; 2934 function = "qup01"; 2935 }; 2936 2937 qup_uart1_rx: qup-uart1-rx { 2938 pins = "gpio7"; 2939 function = "qup01"; 2940 }; 2941 2942 qup_uart2_cts: qup-uart2-cts { 2943 pins = "gpio8"; 2944 function = "qup02"; 2945 }; 2946 2947 qup_uart2_rts: qup-uart2-rts { 2948 pins = "gpio9"; 2949 function = "qup02"; 2950 }; 2951 2952 qup_uart2_tx: qup-uart2-tx { 2953 pins = "gpio10"; 2954 function = "qup02"; 2955 }; 2956 2957 qup_uart2_rx: qup-uart2-rx { 2958 pins = "gpio11"; 2959 function = "qup02"; 2960 }; 2961 2962 qup_uart3_cts: qup-uart3-cts { 2963 pins = "gpio12"; 2964 function = "qup03"; 2965 }; 2966 2967 qup_uart3_rts: qup-uart3-rts { 2968 pins = "gpio13"; 2969 function = "qup03"; 2970 }; 2971 2972 qup_uart3_tx: qup-uart3-tx { 2973 pins = "gpio14"; 2974 function = "qup03"; 2975 }; 2976 2977 qup_uart3_rx: qup-uart3-rx { 2978 pins = "gpio15"; 2979 function = "qup03"; 2980 }; 2981 2982 qup_uart4_cts: qup-uart4-cts { 2983 pins = "gpio16"; 2984 function = "qup04"; 2985 }; 2986 2987 qup_uart4_rts: qup-uart4-rts { 2988 pins = "gpio17"; 2989 function = "qup04"; 2990 }; 2991 2992 qup_uart4_tx: qup-uart4-tx { 2993 pins = "gpio18"; 2994 function = "qup04"; 2995 }; 2996 2997 qup_uart4_rx: qup-uart4-rx { 2998 pins = "gpio19"; 2999 function = "qup04"; 3000 }; 3001 3002 qup_uart5_cts: qup-uart5-cts { 3003 pins = "gpio20"; 3004 function = "qup05"; 3005 }; 3006 3007 qup_uart5_rts: qup-uart5-rts { 3008 pins = "gpio21"; 3009 function = "qup05"; 3010 }; 3011 3012 qup_uart5_tx: qup-uart5-tx { 3013 pins = "gpio22"; 3014 function = "qup05"; 3015 }; 3016 3017 qup_uart5_rx: qup-uart5-rx { 3018 pins = "gpio23"; 3019 function = "qup05"; 3020 }; 3021 3022 qup_uart6_cts: qup-uart6-cts { 3023 pins = "gpio24"; 3024 function = "qup06"; 3025 }; 3026 3027 qup_uart6_rts: qup-uart6-rts { 3028 pins = "gpio25"; 3029 function = "qup06"; 3030 }; 3031 3032 qup_uart6_tx: qup-uart6-tx { 3033 pins = "gpio26"; 3034 function = "qup06"; 3035 }; 3036 3037 qup_uart6_rx: qup-uart6-rx { 3038 pins = "gpio27"; 3039 function = "qup06"; 3040 }; 3041 3042 qup_uart7_cts: qup-uart7-cts { 3043 pins = "gpio28"; 3044 function = "qup07"; 3045 }; 3046 3047 qup_uart7_rts: qup-uart7-rts { 3048 pins = "gpio29"; 3049 function = "qup07"; 3050 }; 3051 3052 qup_uart7_tx: qup-uart7-tx { 3053 pins = "gpio30"; 3054 function = "qup07"; 3055 }; 3056 3057 qup_uart7_rx: qup-uart7-rx { 3058 pins = "gpio31"; 3059 function = "qup07"; 3060 }; 3061 3062 sdc1_on: sdc1-on { 3063 clk { 3064 pins = "sdc1_clk"; 3065 }; 3066 3067 cmd { 3068 pins = "sdc1_cmd"; 3069 }; 3070 3071 data { 3072 pins = "sdc1_data"; 3073 }; 3074 3075 rclk { 3076 pins = "sdc1_rclk"; 3077 }; 3078 }; 3079 3080 sdc1_off: sdc1-off { 3081 clk { 3082 pins = "sdc1_clk"; 3083 drive-strength = <2>; 3084 bias-bus-hold; 3085 }; 3086 3087 cmd { 3088 pins = "sdc1_cmd"; 3089 drive-strength = <2>; 3090 bias-bus-hold; 3091 }; 3092 3093 data { 3094 pins = "sdc1_data"; 3095 drive-strength = <2>; 3096 bias-bus-hold; 3097 }; 3098 3099 rclk { 3100 pins = "sdc1_rclk"; 3101 bias-bus-hold; 3102 }; 3103 }; 3104 3105 sdc2_on: sdc2-on { 3106 clk { 3107 pins = "sdc2_clk"; 3108 }; 3109 3110 cmd { 3111 pins = "sdc2_cmd"; 3112 }; 3113 3114 data { 3115 pins = "sdc2_data"; 3116 }; 3117 }; 3118 3119 sdc2_off: sdc2-off { 3120 clk { 3121 pins = "sdc2_clk"; 3122 drive-strength = <2>; 3123 bias-bus-hold; 3124 }; 3125 3126 cmd { 3127 pins ="sdc2_cmd"; 3128 drive-strength = <2>; 3129 bias-bus-hold; 3130 }; 3131 3132 data { 3133 pins ="sdc2_data"; 3134 drive-strength = <2>; 3135 bias-bus-hold; 3136 }; 3137 }; 3138 3139 qup_uart8_cts: qup-uart8-cts { 3140 pins = "gpio32"; 3141 function = "qup10"; 3142 }; 3143 3144 qup_uart8_rts: qup-uart8-rts { 3145 pins = "gpio33"; 3146 function = "qup10"; 3147 }; 3148 3149 qup_uart8_tx: qup-uart8-tx { 3150 pins = "gpio34"; 3151 function = "qup10"; 3152 }; 3153 3154 qup_uart8_rx: qup-uart8-rx { 3155 pins = "gpio35"; 3156 function = "qup10"; 3157 }; 3158 3159 qup_uart9_cts: qup-uart9-cts { 3160 pins = "gpio36"; 3161 function = "qup11"; 3162 }; 3163 3164 qup_uart9_rts: qup-uart9-rts { 3165 pins = "gpio37"; 3166 function = "qup11"; 3167 }; 3168 3169 qup_uart9_tx: qup-uart9-tx { 3170 pins = "gpio38"; 3171 function = "qup11"; 3172 }; 3173 3174 qup_uart9_rx: qup-uart9-rx { 3175 pins = "gpio39"; 3176 function = "qup11"; 3177 }; 3178 3179 qup_uart10_cts: qup-uart10-cts { 3180 pins = "gpio40"; 3181 function = "qup12"; 3182 }; 3183 3184 qup_uart10_rts: qup-uart10-rts { 3185 pins = "gpio41"; 3186 function = "qup12"; 3187 }; 3188 3189 qup_uart10_tx: qup-uart10-tx { 3190 pins = "gpio42"; 3191 function = "qup12"; 3192 }; 3193 3194 qup_uart10_rx: qup-uart10-rx { 3195 pins = "gpio43"; 3196 function = "qup12"; 3197 }; 3198 3199 qup_uart11_cts: qup-uart11-cts { 3200 pins = "gpio44"; 3201 function = "qup13"; 3202 }; 3203 3204 qup_uart11_rts: qup-uart11-rts { 3205 pins = "gpio45"; 3206 function = "qup13"; 3207 }; 3208 3209 qup_uart11_tx: qup-uart11-tx { 3210 pins = "gpio46"; 3211 function = "qup13"; 3212 }; 3213 3214 qup_uart11_rx: qup-uart11-rx { 3215 pins = "gpio47"; 3216 function = "qup13"; 3217 }; 3218 3219 qup_uart12_cts: qup-uart12-cts { 3220 pins = "gpio48"; 3221 function = "qup14"; 3222 }; 3223 3224 qup_uart12_rts: qup-uart12-rts { 3225 pins = "gpio49"; 3226 function = "qup14"; 3227 }; 3228 3229 qup_uart12_tx: qup-uart12-tx { 3230 pins = "gpio50"; 3231 function = "qup14"; 3232 }; 3233 3234 qup_uart12_rx: qup-uart12-rx { 3235 pins = "gpio51"; 3236 function = "qup14"; 3237 }; 3238 3239 qup_uart13_cts: qup-uart13-cts { 3240 pins = "gpio52"; 3241 function = "qup15"; 3242 }; 3243 3244 qup_uart13_rts: qup-uart13-rts { 3245 pins = "gpio53"; 3246 function = "qup15"; 3247 }; 3248 3249 qup_uart13_tx: qup-uart13-tx { 3250 pins = "gpio54"; 3251 function = "qup15"; 3252 }; 3253 3254 qup_uart13_rx: qup-uart13-rx { 3255 pins = "gpio55"; 3256 function = "qup15"; 3257 }; 3258 3259 qup_uart14_cts: qup-uart14-cts { 3260 pins = "gpio56"; 3261 function = "qup16"; 3262 }; 3263 3264 qup_uart14_rts: qup-uart14-rts { 3265 pins = "gpio57"; 3266 function = "qup16"; 3267 }; 3268 3269 qup_uart14_tx: qup-uart14-tx { 3270 pins = "gpio58"; 3271 function = "qup16"; 3272 }; 3273 3274 qup_uart14_rx: qup-uart14-rx { 3275 pins = "gpio59"; 3276 function = "qup16"; 3277 }; 3278 3279 qup_uart15_cts: qup-uart15-cts { 3280 pins = "gpio60"; 3281 function = "qup17"; 3282 }; 3283 3284 qup_uart15_rts: qup-uart15-rts { 3285 pins = "gpio61"; 3286 function = "qup17"; 3287 }; 3288 3289 qup_uart15_tx: qup-uart15-tx { 3290 pins = "gpio62"; 3291 function = "qup17"; 3292 }; 3293 3294 qup_uart15_rx: qup-uart15-rx { 3295 pins = "gpio63"; 3296 function = "qup17"; 3297 }; 3298 }; 3299 3300 apps_smmu: iommu@15000000 { 3301 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 3302 reg = <0 0x15000000 0 0x100000>; 3303 #iommu-cells = <2>; 3304 #global-interrupts = <1>; 3305 dma-coherent; 3306 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3307 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3308 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3309 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3310 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3311 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3312 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3313 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3314 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3315 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3316 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3317 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3318 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3319 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3320 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3321 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3322 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3323 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3324 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3325 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3326 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3327 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3328 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3329 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3330 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3331 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3332 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3333 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3334 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3335 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3336 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3337 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3338 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3339 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3340 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3341 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3342 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3343 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3344 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3345 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3346 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3347 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3348 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3349 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3350 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3351 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3352 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3353 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3354 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3355 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3356 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3357 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3358 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3359 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3360 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3361 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3362 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3363 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3364 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3365 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3366 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3367 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3368 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3369 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3370 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3371 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3372 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3373 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3374 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3375 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3377 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3378 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3379 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3380 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3381 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3382 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3383 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3384 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3385 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3386 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 3387 }; 3388 3389 intc: interrupt-controller@17a00000 { 3390 compatible = "arm,gic-v3"; 3391 #address-cells = <2>; 3392 #size-cells = <2>; 3393 ranges; 3394 #interrupt-cells = <3>; 3395 interrupt-controller; 3396 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3397 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3398 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 3399 3400 gic-its@17a40000 { 3401 compatible = "arm,gic-v3-its"; 3402 msi-controller; 3403 #msi-cells = <1>; 3404 reg = <0 0x17a40000 0 0x20000>; 3405 status = "disabled"; 3406 }; 3407 }; 3408 3409 watchdog@17c10000 { 3410 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 3411 reg = <0 0x17c10000 0 0x1000>; 3412 clocks = <&sleep_clk>; 3413 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3414 }; 3415 3416 timer@17c20000 { 3417 #address-cells = <2>; 3418 #size-cells = <2>; 3419 ranges; 3420 compatible = "arm,armv7-timer-mem"; 3421 reg = <0 0x17c20000 0 0x1000>; 3422 3423 frame@17c21000 { 3424 frame-number = <0>; 3425 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3426 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3427 reg = <0 0x17c21000 0 0x1000>, 3428 <0 0x17c22000 0 0x1000>; 3429 }; 3430 3431 frame@17c23000 { 3432 frame-number = <1>; 3433 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3434 reg = <0 0x17c23000 0 0x1000>; 3435 status = "disabled"; 3436 }; 3437 3438 frame@17c25000 { 3439 frame-number = <2>; 3440 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3441 reg = <0 0x17c25000 0 0x1000>; 3442 status = "disabled"; 3443 }; 3444 3445 frame@17c27000 { 3446 frame-number = <3>; 3447 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3448 reg = <0 0x17c27000 0 0x1000>; 3449 status = "disabled"; 3450 }; 3451 3452 frame@17c29000 { 3453 frame-number = <4>; 3454 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3455 reg = <0 0x17c29000 0 0x1000>; 3456 status = "disabled"; 3457 }; 3458 3459 frame@17c2b000 { 3460 frame-number = <5>; 3461 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3462 reg = <0 0x17c2b000 0 0x1000>; 3463 status = "disabled"; 3464 }; 3465 3466 frame@17c2d000 { 3467 frame-number = <6>; 3468 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3469 reg = <0 0x17c2d000 0 0x1000>; 3470 status = "disabled"; 3471 }; 3472 }; 3473 3474 apps_rsc: rsc@18200000 { 3475 compatible = "qcom,rpmh-rsc"; 3476 reg = <0 0x18200000 0 0x10000>, 3477 <0 0x18210000 0 0x10000>, 3478 <0 0x18220000 0 0x10000>; 3479 reg-names = "drv-0", "drv-1", "drv-2"; 3480 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3481 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3482 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3483 qcom,tcs-offset = <0xd00>; 3484 qcom,drv-id = <2>; 3485 qcom,tcs-config = <ACTIVE_TCS 2>, 3486 <SLEEP_TCS 3>, 3487 <WAKE_TCS 3>, 3488 <CONTROL_TCS 1>; 3489 3490 apps_bcm_voter: bcm-voter { 3491 compatible = "qcom,bcm-voter"; 3492 }; 3493 3494 rpmhpd: power-controller { 3495 compatible = "qcom,sc7280-rpmhpd"; 3496 #power-domain-cells = <1>; 3497 operating-points-v2 = <&rpmhpd_opp_table>; 3498 3499 rpmhpd_opp_table: opp-table { 3500 compatible = "operating-points-v2"; 3501 3502 rpmhpd_opp_ret: opp1 { 3503 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3504 }; 3505 3506 rpmhpd_opp_low_svs: opp2 { 3507 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3508 }; 3509 3510 rpmhpd_opp_svs: opp3 { 3511 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3512 }; 3513 3514 rpmhpd_opp_svs_l1: opp4 { 3515 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3516 }; 3517 3518 rpmhpd_opp_svs_l2: opp5 { 3519 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3520 }; 3521 3522 rpmhpd_opp_nom: opp6 { 3523 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3524 }; 3525 3526 rpmhpd_opp_nom_l1: opp7 { 3527 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3528 }; 3529 3530 rpmhpd_opp_turbo: opp8 { 3531 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3532 }; 3533 3534 rpmhpd_opp_turbo_l1: opp9 { 3535 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3536 }; 3537 }; 3538 }; 3539 3540 rpmhcc: clock-controller { 3541 compatible = "qcom,sc7280-rpmh-clk"; 3542 clocks = <&xo_board>; 3543 clock-names = "xo"; 3544 #clock-cells = <1>; 3545 }; 3546 }; 3547 3548 cpufreq_hw: cpufreq@18591000 { 3549 compatible = "qcom,cpufreq-epss"; 3550 reg = <0 0x18591100 0 0x900>, 3551 <0 0x18592100 0 0x900>, 3552 <0 0x18593100 0 0x900>; 3553 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3554 clock-names = "xo", "alternate"; 3555 #freq-domain-cells = <1>; 3556 }; 3557 }; 3558 3559 thermal_zones: thermal-zones { 3560 cpu0-thermal { 3561 polling-delay-passive = <250>; 3562 polling-delay = <0>; 3563 3564 thermal-sensors = <&tsens0 1>; 3565 3566 trips { 3567 cpu0_alert0: trip-point0 { 3568 temperature = <90000>; 3569 hysteresis = <2000>; 3570 type = "passive"; 3571 }; 3572 3573 cpu0_alert1: trip-point1 { 3574 temperature = <95000>; 3575 hysteresis = <2000>; 3576 type = "passive"; 3577 }; 3578 3579 cpu0_crit: cpu-crit { 3580 temperature = <110000>; 3581 hysteresis = <0>; 3582 type = "critical"; 3583 }; 3584 }; 3585 3586 cooling-maps { 3587 map0 { 3588 trip = <&cpu0_alert0>; 3589 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3590 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3591 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3592 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3593 }; 3594 map1 { 3595 trip = <&cpu0_alert1>; 3596 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3597 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3598 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3599 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3600 }; 3601 }; 3602 }; 3603 3604 cpu1-thermal { 3605 polling-delay-passive = <250>; 3606 polling-delay = <0>; 3607 3608 thermal-sensors = <&tsens0 2>; 3609 3610 trips { 3611 cpu1_alert0: trip-point0 { 3612 temperature = <90000>; 3613 hysteresis = <2000>; 3614 type = "passive"; 3615 }; 3616 3617 cpu1_alert1: trip-point1 { 3618 temperature = <95000>; 3619 hysteresis = <2000>; 3620 type = "passive"; 3621 }; 3622 3623 cpu1_crit: cpu-crit { 3624 temperature = <110000>; 3625 hysteresis = <0>; 3626 type = "critical"; 3627 }; 3628 }; 3629 3630 cooling-maps { 3631 map0 { 3632 trip = <&cpu1_alert0>; 3633 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3634 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3635 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3636 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3637 }; 3638 map1 { 3639 trip = <&cpu1_alert1>; 3640 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3641 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3642 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3643 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3644 }; 3645 }; 3646 }; 3647 3648 cpu2-thermal { 3649 polling-delay-passive = <250>; 3650 polling-delay = <0>; 3651 3652 thermal-sensors = <&tsens0 3>; 3653 3654 trips { 3655 cpu2_alert0: trip-point0 { 3656 temperature = <90000>; 3657 hysteresis = <2000>; 3658 type = "passive"; 3659 }; 3660 3661 cpu2_alert1: trip-point1 { 3662 temperature = <95000>; 3663 hysteresis = <2000>; 3664 type = "passive"; 3665 }; 3666 3667 cpu2_crit: cpu-crit { 3668 temperature = <110000>; 3669 hysteresis = <0>; 3670 type = "critical"; 3671 }; 3672 }; 3673 3674 cooling-maps { 3675 map0 { 3676 trip = <&cpu2_alert0>; 3677 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3678 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3679 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3680 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3681 }; 3682 map1 { 3683 trip = <&cpu2_alert1>; 3684 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3685 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3686 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3687 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3688 }; 3689 }; 3690 }; 3691 3692 cpu3-thermal { 3693 polling-delay-passive = <250>; 3694 polling-delay = <0>; 3695 3696 thermal-sensors = <&tsens0 4>; 3697 3698 trips { 3699 cpu3_alert0: trip-point0 { 3700 temperature = <90000>; 3701 hysteresis = <2000>; 3702 type = "passive"; 3703 }; 3704 3705 cpu3_alert1: trip-point1 { 3706 temperature = <95000>; 3707 hysteresis = <2000>; 3708 type = "passive"; 3709 }; 3710 3711 cpu3_crit: cpu-crit { 3712 temperature = <110000>; 3713 hysteresis = <0>; 3714 type = "critical"; 3715 }; 3716 }; 3717 3718 cooling-maps { 3719 map0 { 3720 trip = <&cpu3_alert0>; 3721 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3722 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3723 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3724 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3725 }; 3726 map1 { 3727 trip = <&cpu3_alert1>; 3728 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3729 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3730 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3731 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3732 }; 3733 }; 3734 }; 3735 3736 cpu4-thermal { 3737 polling-delay-passive = <250>; 3738 polling-delay = <0>; 3739 3740 thermal-sensors = <&tsens0 7>; 3741 3742 trips { 3743 cpu4_alert0: trip-point0 { 3744 temperature = <90000>; 3745 hysteresis = <2000>; 3746 type = "passive"; 3747 }; 3748 3749 cpu4_alert1: trip-point1 { 3750 temperature = <95000>; 3751 hysteresis = <2000>; 3752 type = "passive"; 3753 }; 3754 3755 cpu4_crit: cpu-crit { 3756 temperature = <110000>; 3757 hysteresis = <0>; 3758 type = "critical"; 3759 }; 3760 }; 3761 3762 cooling-maps { 3763 map0 { 3764 trip = <&cpu4_alert0>; 3765 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3766 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3767 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3768 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3769 }; 3770 map1 { 3771 trip = <&cpu4_alert1>; 3772 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3773 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3774 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3775 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3776 }; 3777 }; 3778 }; 3779 3780 cpu5-thermal { 3781 polling-delay-passive = <250>; 3782 polling-delay = <0>; 3783 3784 thermal-sensors = <&tsens0 8>; 3785 3786 trips { 3787 cpu5_alert0: trip-point0 { 3788 temperature = <90000>; 3789 hysteresis = <2000>; 3790 type = "passive"; 3791 }; 3792 3793 cpu5_alert1: trip-point1 { 3794 temperature = <95000>; 3795 hysteresis = <2000>; 3796 type = "passive"; 3797 }; 3798 3799 cpu5_crit: cpu-crit { 3800 temperature = <110000>; 3801 hysteresis = <0>; 3802 type = "critical"; 3803 }; 3804 }; 3805 3806 cooling-maps { 3807 map0 { 3808 trip = <&cpu5_alert0>; 3809 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3810 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3811 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3812 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3813 }; 3814 map1 { 3815 trip = <&cpu5_alert1>; 3816 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3817 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3818 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3819 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3820 }; 3821 }; 3822 }; 3823 3824 cpu6-thermal { 3825 polling-delay-passive = <250>; 3826 polling-delay = <0>; 3827 3828 thermal-sensors = <&tsens0 9>; 3829 3830 trips { 3831 cpu6_alert0: trip-point0 { 3832 temperature = <90000>; 3833 hysteresis = <2000>; 3834 type = "passive"; 3835 }; 3836 3837 cpu6_alert1: trip-point1 { 3838 temperature = <95000>; 3839 hysteresis = <2000>; 3840 type = "passive"; 3841 }; 3842 3843 cpu6_crit: cpu-crit { 3844 temperature = <110000>; 3845 hysteresis = <0>; 3846 type = "critical"; 3847 }; 3848 }; 3849 3850 cooling-maps { 3851 map0 { 3852 trip = <&cpu6_alert0>; 3853 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3854 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3855 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3856 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3857 }; 3858 map1 { 3859 trip = <&cpu6_alert1>; 3860 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3861 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3862 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3863 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3864 }; 3865 }; 3866 }; 3867 3868 cpu7-thermal { 3869 polling-delay-passive = <250>; 3870 polling-delay = <0>; 3871 3872 thermal-sensors = <&tsens0 10>; 3873 3874 trips { 3875 cpu7_alert0: trip-point0 { 3876 temperature = <90000>; 3877 hysteresis = <2000>; 3878 type = "passive"; 3879 }; 3880 3881 cpu7_alert1: trip-point1 { 3882 temperature = <95000>; 3883 hysteresis = <2000>; 3884 type = "passive"; 3885 }; 3886 3887 cpu7_crit: cpu-crit { 3888 temperature = <110000>; 3889 hysteresis = <0>; 3890 type = "critical"; 3891 }; 3892 }; 3893 3894 cooling-maps { 3895 map0 { 3896 trip = <&cpu7_alert0>; 3897 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3898 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3899 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3900 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3901 }; 3902 map1 { 3903 trip = <&cpu7_alert1>; 3904 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3905 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3906 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3907 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3908 }; 3909 }; 3910 }; 3911 3912 cpu8-thermal { 3913 polling-delay-passive = <250>; 3914 polling-delay = <0>; 3915 3916 thermal-sensors = <&tsens0 11>; 3917 3918 trips { 3919 cpu8_alert0: trip-point0 { 3920 temperature = <90000>; 3921 hysteresis = <2000>; 3922 type = "passive"; 3923 }; 3924 3925 cpu8_alert1: trip-point1 { 3926 temperature = <95000>; 3927 hysteresis = <2000>; 3928 type = "passive"; 3929 }; 3930 3931 cpu8_crit: cpu-crit { 3932 temperature = <110000>; 3933 hysteresis = <0>; 3934 type = "critical"; 3935 }; 3936 }; 3937 3938 cooling-maps { 3939 map0 { 3940 trip = <&cpu8_alert0>; 3941 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3942 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3943 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3944 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3945 }; 3946 map1 { 3947 trip = <&cpu8_alert1>; 3948 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3949 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3950 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3951 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3952 }; 3953 }; 3954 }; 3955 3956 cpu9-thermal { 3957 polling-delay-passive = <250>; 3958 polling-delay = <0>; 3959 3960 thermal-sensors = <&tsens0 12>; 3961 3962 trips { 3963 cpu9_alert0: trip-point0 { 3964 temperature = <90000>; 3965 hysteresis = <2000>; 3966 type = "passive"; 3967 }; 3968 3969 cpu9_alert1: trip-point1 { 3970 temperature = <95000>; 3971 hysteresis = <2000>; 3972 type = "passive"; 3973 }; 3974 3975 cpu9_crit: cpu-crit { 3976 temperature = <110000>; 3977 hysteresis = <0>; 3978 type = "critical"; 3979 }; 3980 }; 3981 3982 cooling-maps { 3983 map0 { 3984 trip = <&cpu9_alert0>; 3985 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3986 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3987 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3988 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3989 }; 3990 map1 { 3991 trip = <&cpu9_alert1>; 3992 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3993 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3994 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3995 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3996 }; 3997 }; 3998 }; 3999 4000 cpu10-thermal { 4001 polling-delay-passive = <250>; 4002 polling-delay = <0>; 4003 4004 thermal-sensors = <&tsens0 13>; 4005 4006 trips { 4007 cpu10_alert0: trip-point0 { 4008 temperature = <90000>; 4009 hysteresis = <2000>; 4010 type = "passive"; 4011 }; 4012 4013 cpu10_alert1: trip-point1 { 4014 temperature = <95000>; 4015 hysteresis = <2000>; 4016 type = "passive"; 4017 }; 4018 4019 cpu10_crit: cpu-crit { 4020 temperature = <110000>; 4021 hysteresis = <0>; 4022 type = "critical"; 4023 }; 4024 }; 4025 4026 cooling-maps { 4027 map0 { 4028 trip = <&cpu10_alert0>; 4029 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4030 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4031 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4032 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4033 }; 4034 map1 { 4035 trip = <&cpu10_alert1>; 4036 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4037 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4038 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4039 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4040 }; 4041 }; 4042 }; 4043 4044 cpu11-thermal { 4045 polling-delay-passive = <250>; 4046 polling-delay = <0>; 4047 4048 thermal-sensors = <&tsens0 14>; 4049 4050 trips { 4051 cpu11_alert0: trip-point0 { 4052 temperature = <90000>; 4053 hysteresis = <2000>; 4054 type = "passive"; 4055 }; 4056 4057 cpu11_alert1: trip-point1 { 4058 temperature = <95000>; 4059 hysteresis = <2000>; 4060 type = "passive"; 4061 }; 4062 4063 cpu11_crit: cpu-crit { 4064 temperature = <110000>; 4065 hysteresis = <0>; 4066 type = "critical"; 4067 }; 4068 }; 4069 4070 cooling-maps { 4071 map0 { 4072 trip = <&cpu11_alert0>; 4073 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4074 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4075 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4076 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4077 }; 4078 map1 { 4079 trip = <&cpu11_alert1>; 4080 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4081 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4082 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4083 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4084 }; 4085 }; 4086 }; 4087 4088 aoss0-thermal { 4089 polling-delay-passive = <0>; 4090 polling-delay = <0>; 4091 4092 thermal-sensors = <&tsens0 0>; 4093 4094 trips { 4095 aoss0_alert0: trip-point0 { 4096 temperature = <90000>; 4097 hysteresis = <2000>; 4098 type = "hot"; 4099 }; 4100 4101 aoss0_crit: aoss0-crit { 4102 temperature = <110000>; 4103 hysteresis = <0>; 4104 type = "critical"; 4105 }; 4106 }; 4107 }; 4108 4109 aoss1-thermal { 4110 polling-delay-passive = <0>; 4111 polling-delay = <0>; 4112 4113 thermal-sensors = <&tsens1 0>; 4114 4115 trips { 4116 aoss1_alert0: trip-point0 { 4117 temperature = <90000>; 4118 hysteresis = <2000>; 4119 type = "hot"; 4120 }; 4121 4122 aoss1_crit: aoss1-crit { 4123 temperature = <110000>; 4124 hysteresis = <0>; 4125 type = "critical"; 4126 }; 4127 }; 4128 }; 4129 4130 cpuss0-thermal { 4131 polling-delay-passive = <0>; 4132 polling-delay = <0>; 4133 4134 thermal-sensors = <&tsens0 5>; 4135 4136 trips { 4137 cpuss0_alert0: trip-point0 { 4138 temperature = <90000>; 4139 hysteresis = <2000>; 4140 type = "hot"; 4141 }; 4142 cpuss0_crit: cluster0-crit { 4143 temperature = <110000>; 4144 hysteresis = <0>; 4145 type = "critical"; 4146 }; 4147 }; 4148 }; 4149 4150 cpuss1-thermal { 4151 polling-delay-passive = <0>; 4152 polling-delay = <0>; 4153 4154 thermal-sensors = <&tsens0 6>; 4155 4156 trips { 4157 cpuss1_alert0: trip-point0 { 4158 temperature = <90000>; 4159 hysteresis = <2000>; 4160 type = "hot"; 4161 }; 4162 cpuss1_crit: cluster0-crit { 4163 temperature = <110000>; 4164 hysteresis = <0>; 4165 type = "critical"; 4166 }; 4167 }; 4168 }; 4169 4170 gpuss0-thermal { 4171 polling-delay-passive = <100>; 4172 polling-delay = <0>; 4173 4174 thermal-sensors = <&tsens1 1>; 4175 4176 trips { 4177 gpuss0_alert0: trip-point0 { 4178 temperature = <95000>; 4179 hysteresis = <2000>; 4180 type = "passive"; 4181 }; 4182 4183 gpuss0_crit: gpuss0-crit { 4184 temperature = <110000>; 4185 hysteresis = <0>; 4186 type = "critical"; 4187 }; 4188 }; 4189 4190 cooling-maps { 4191 map0 { 4192 trip = <&gpuss0_alert0>; 4193 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4194 }; 4195 }; 4196 }; 4197 4198 gpuss1-thermal { 4199 polling-delay-passive = <100>; 4200 polling-delay = <0>; 4201 4202 thermal-sensors = <&tsens1 2>; 4203 4204 trips { 4205 gpuss1_alert0: trip-point0 { 4206 temperature = <95000>; 4207 hysteresis = <2000>; 4208 type = "passive"; 4209 }; 4210 4211 gpuss1_crit: gpuss1-crit { 4212 temperature = <110000>; 4213 hysteresis = <0>; 4214 type = "critical"; 4215 }; 4216 }; 4217 4218 cooling-maps { 4219 map0 { 4220 trip = <&gpuss1_alert0>; 4221 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4222 }; 4223 }; 4224 }; 4225 4226 nspss0-thermal { 4227 polling-delay-passive = <0>; 4228 polling-delay = <0>; 4229 4230 thermal-sensors = <&tsens1 3>; 4231 4232 trips { 4233 nspss0_alert0: trip-point0 { 4234 temperature = <90000>; 4235 hysteresis = <2000>; 4236 type = "hot"; 4237 }; 4238 4239 nspss0_crit: nspss0-crit { 4240 temperature = <110000>; 4241 hysteresis = <0>; 4242 type = "critical"; 4243 }; 4244 }; 4245 }; 4246 4247 nspss1-thermal { 4248 polling-delay-passive = <0>; 4249 polling-delay = <0>; 4250 4251 thermal-sensors = <&tsens1 4>; 4252 4253 trips { 4254 nspss1_alert0: trip-point0 { 4255 temperature = <90000>; 4256 hysteresis = <2000>; 4257 type = "hot"; 4258 }; 4259 4260 nspss1_crit: nspss1-crit { 4261 temperature = <110000>; 4262 hysteresis = <0>; 4263 type = "critical"; 4264 }; 4265 }; 4266 }; 4267 4268 video-thermal { 4269 polling-delay-passive = <0>; 4270 polling-delay = <0>; 4271 4272 thermal-sensors = <&tsens1 5>; 4273 4274 trips { 4275 video_alert0: trip-point0 { 4276 temperature = <90000>; 4277 hysteresis = <2000>; 4278 type = "hot"; 4279 }; 4280 4281 video_crit: video-crit { 4282 temperature = <110000>; 4283 hysteresis = <0>; 4284 type = "critical"; 4285 }; 4286 }; 4287 }; 4288 4289 ddr-thermal { 4290 polling-delay-passive = <0>; 4291 polling-delay = <0>; 4292 4293 thermal-sensors = <&tsens1 6>; 4294 4295 trips { 4296 ddr_alert0: trip-point0 { 4297 temperature = <90000>; 4298 hysteresis = <2000>; 4299 type = "hot"; 4300 }; 4301 4302 ddr_crit: ddr-crit { 4303 temperature = <110000>; 4304 hysteresis = <0>; 4305 type = "critical"; 4306 }; 4307 }; 4308 }; 4309 4310 mdmss0-thermal { 4311 polling-delay-passive = <0>; 4312 polling-delay = <0>; 4313 4314 thermal-sensors = <&tsens1 7>; 4315 4316 trips { 4317 mdmss0_alert0: trip-point0 { 4318 temperature = <90000>; 4319 hysteresis = <2000>; 4320 type = "hot"; 4321 }; 4322 4323 mdmss0_crit: mdmss0-crit { 4324 temperature = <110000>; 4325 hysteresis = <0>; 4326 type = "critical"; 4327 }; 4328 }; 4329 }; 4330 4331 mdmss1-thermal { 4332 polling-delay-passive = <0>; 4333 polling-delay = <0>; 4334 4335 thermal-sensors = <&tsens1 8>; 4336 4337 trips { 4338 mdmss1_alert0: trip-point0 { 4339 temperature = <90000>; 4340 hysteresis = <2000>; 4341 type = "hot"; 4342 }; 4343 4344 mdmss1_crit: mdmss1-crit { 4345 temperature = <110000>; 4346 hysteresis = <0>; 4347 type = "critical"; 4348 }; 4349 }; 4350 }; 4351 4352 mdmss2-thermal { 4353 polling-delay-passive = <0>; 4354 polling-delay = <0>; 4355 4356 thermal-sensors = <&tsens1 9>; 4357 4358 trips { 4359 mdmss2_alert0: trip-point0 { 4360 temperature = <90000>; 4361 hysteresis = <2000>; 4362 type = "hot"; 4363 }; 4364 4365 mdmss2_crit: mdmss2-crit { 4366 temperature = <110000>; 4367 hysteresis = <0>; 4368 type = "critical"; 4369 }; 4370 }; 4371 }; 4372 4373 mdmss3-thermal { 4374 polling-delay-passive = <0>; 4375 polling-delay = <0>; 4376 4377 thermal-sensors = <&tsens1 10>; 4378 4379 trips { 4380 mdmss3_alert0: trip-point0 { 4381 temperature = <90000>; 4382 hysteresis = <2000>; 4383 type = "hot"; 4384 }; 4385 4386 mdmss3_crit: mdmss3-crit { 4387 temperature = <110000>; 4388 hysteresis = <0>; 4389 type = "critical"; 4390 }; 4391 }; 4392 }; 4393 4394 camera0-thermal { 4395 polling-delay-passive = <0>; 4396 polling-delay = <0>; 4397 4398 thermal-sensors = <&tsens1 11>; 4399 4400 trips { 4401 camera0_alert0: trip-point0 { 4402 temperature = <90000>; 4403 hysteresis = <2000>; 4404 type = "hot"; 4405 }; 4406 4407 camera0_crit: camera0-crit { 4408 temperature = <110000>; 4409 hysteresis = <0>; 4410 type = "critical"; 4411 }; 4412 }; 4413 }; 4414 }; 4415 4416 timer { 4417 compatible = "arm,armv8-timer"; 4418 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 4419 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 4420 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 4421 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 4422 }; 4423}; 4424