1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7280.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sc7280.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/reset/qcom,sdm845-aoss.h> 20#include <dt-bindings/reset/qcom,sdm845-pdc.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 chosen { }; 31 32 aliases { 33 i2c0 = &i2c0; 34 i2c1 = &i2c1; 35 i2c2 = &i2c2; 36 i2c3 = &i2c3; 37 i2c4 = &i2c4; 38 i2c5 = &i2c5; 39 i2c6 = &i2c6; 40 i2c7 = &i2c7; 41 i2c8 = &i2c8; 42 i2c9 = &i2c9; 43 i2c10 = &i2c10; 44 i2c11 = &i2c11; 45 i2c12 = &i2c12; 46 i2c13 = &i2c13; 47 i2c14 = &i2c14; 48 i2c15 = &i2c15; 49 mmc1 = &sdhc_1; 50 mmc2 = &sdhc_2; 51 spi0 = &spi0; 52 spi1 = &spi1; 53 spi2 = &spi2; 54 spi3 = &spi3; 55 spi4 = &spi4; 56 spi5 = &spi5; 57 spi6 = &spi6; 58 spi7 = &spi7; 59 spi8 = &spi8; 60 spi9 = &spi9; 61 spi10 = &spi10; 62 spi11 = &spi11; 63 spi12 = &spi12; 64 spi13 = &spi13; 65 spi14 = &spi14; 66 spi15 = &spi15; 67 }; 68 69 clocks { 70 xo_board: xo-board { 71 compatible = "fixed-clock"; 72 clock-frequency = <76800000>; 73 #clock-cells = <0>; 74 }; 75 76 sleep_clk: sleep-clk { 77 compatible = "fixed-clock"; 78 clock-frequency = <32000>; 79 #clock-cells = <0>; 80 }; 81 }; 82 83 reserved-memory { 84 #address-cells = <2>; 85 #size-cells = <2>; 86 ranges; 87 88 hyp_mem: memory@80000000 { 89 reg = <0x0 0x80000000 0x0 0x600000>; 90 no-map; 91 }; 92 93 xbl_mem: memory@80600000 { 94 reg = <0x0 0x80600000 0x0 0x200000>; 95 no-map; 96 }; 97 98 aop_mem: memory@80800000 { 99 reg = <0x0 0x80800000 0x0 0x60000>; 100 no-map; 101 }; 102 103 aop_cmd_db_mem: memory@80860000 { 104 reg = <0x0 0x80860000 0x0 0x20000>; 105 compatible = "qcom,cmd-db"; 106 no-map; 107 }; 108 109 reserved_xbl_uefi_log: memory@80880000 { 110 reg = <0x0 0x80884000 0x0 0x10000>; 111 no-map; 112 }; 113 114 sec_apps_mem: memory@808ff000 { 115 reg = <0x0 0x808ff000 0x0 0x1000>; 116 no-map; 117 }; 118 119 smem_mem: memory@80900000 { 120 reg = <0x0 0x80900000 0x0 0x200000>; 121 no-map; 122 }; 123 124 cpucp_mem: memory@80b00000 { 125 no-map; 126 reg = <0x0 0x80b00000 0x0 0x100000>; 127 }; 128 129 wlan_fw_mem: memory@80c00000 { 130 reg = <0x0 0x80c00000 0x0 0xc00000>; 131 no-map; 132 }; 133 134 video_mem: memory@8b200000 { 135 reg = <0x0 0x8b200000 0x0 0x500000>; 136 no-map; 137 }; 138 139 ipa_fw_mem: memory@8b700000 { 140 reg = <0 0x8b700000 0 0x10000>; 141 no-map; 142 }; 143 144 rmtfs_mem: memory@9c900000 { 145 compatible = "qcom,rmtfs-mem"; 146 reg = <0x0 0x9c900000 0x0 0x280000>; 147 no-map; 148 149 qcom,client-id = <1>; 150 qcom,vmid = <15>; 151 }; 152 }; 153 154 cpus { 155 #address-cells = <2>; 156 #size-cells = <0>; 157 158 CPU0: cpu@0 { 159 device_type = "cpu"; 160 compatible = "arm,kryo"; 161 reg = <0x0 0x0>; 162 enable-method = "psci"; 163 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 164 &LITTLE_CPU_SLEEP_1 165 &CLUSTER_SLEEP_0>; 166 next-level-cache = <&L2_0>; 167 operating-points-v2 = <&cpu0_opp_table>; 168 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 169 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 170 qcom,freq-domain = <&cpufreq_hw 0>; 171 #cooling-cells = <2>; 172 L2_0: l2-cache { 173 compatible = "cache"; 174 next-level-cache = <&L3_0>; 175 L3_0: l3-cache { 176 compatible = "cache"; 177 }; 178 }; 179 }; 180 181 CPU1: cpu@100 { 182 device_type = "cpu"; 183 compatible = "arm,kryo"; 184 reg = <0x0 0x100>; 185 enable-method = "psci"; 186 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 187 &LITTLE_CPU_SLEEP_1 188 &CLUSTER_SLEEP_0>; 189 next-level-cache = <&L2_100>; 190 operating-points-v2 = <&cpu0_opp_table>; 191 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 192 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 193 qcom,freq-domain = <&cpufreq_hw 0>; 194 #cooling-cells = <2>; 195 L2_100: l2-cache { 196 compatible = "cache"; 197 next-level-cache = <&L3_0>; 198 }; 199 }; 200 201 CPU2: cpu@200 { 202 device_type = "cpu"; 203 compatible = "arm,kryo"; 204 reg = <0x0 0x200>; 205 enable-method = "psci"; 206 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 207 &LITTLE_CPU_SLEEP_1 208 &CLUSTER_SLEEP_0>; 209 next-level-cache = <&L2_200>; 210 operating-points-v2 = <&cpu0_opp_table>; 211 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 212 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 213 qcom,freq-domain = <&cpufreq_hw 0>; 214 #cooling-cells = <2>; 215 L2_200: l2-cache { 216 compatible = "cache"; 217 next-level-cache = <&L3_0>; 218 }; 219 }; 220 221 CPU3: cpu@300 { 222 device_type = "cpu"; 223 compatible = "arm,kryo"; 224 reg = <0x0 0x300>; 225 enable-method = "psci"; 226 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 227 &LITTLE_CPU_SLEEP_1 228 &CLUSTER_SLEEP_0>; 229 next-level-cache = <&L2_300>; 230 operating-points-v2 = <&cpu0_opp_table>; 231 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 232 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 233 qcom,freq-domain = <&cpufreq_hw 0>; 234 #cooling-cells = <2>; 235 L2_300: l2-cache { 236 compatible = "cache"; 237 next-level-cache = <&L3_0>; 238 }; 239 }; 240 241 CPU4: cpu@400 { 242 device_type = "cpu"; 243 compatible = "arm,kryo"; 244 reg = <0x0 0x400>; 245 enable-method = "psci"; 246 cpu-idle-states = <&BIG_CPU_SLEEP_0 247 &BIG_CPU_SLEEP_1 248 &CLUSTER_SLEEP_0>; 249 next-level-cache = <&L2_400>; 250 operating-points-v2 = <&cpu4_opp_table>; 251 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 252 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 253 qcom,freq-domain = <&cpufreq_hw 1>; 254 #cooling-cells = <2>; 255 L2_400: l2-cache { 256 compatible = "cache"; 257 next-level-cache = <&L3_0>; 258 }; 259 }; 260 261 CPU5: cpu@500 { 262 device_type = "cpu"; 263 compatible = "arm,kryo"; 264 reg = <0x0 0x500>; 265 enable-method = "psci"; 266 cpu-idle-states = <&BIG_CPU_SLEEP_0 267 &BIG_CPU_SLEEP_1 268 &CLUSTER_SLEEP_0>; 269 next-level-cache = <&L2_500>; 270 operating-points-v2 = <&cpu4_opp_table>; 271 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 272 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 273 qcom,freq-domain = <&cpufreq_hw 1>; 274 #cooling-cells = <2>; 275 L2_500: l2-cache { 276 compatible = "cache"; 277 next-level-cache = <&L3_0>; 278 }; 279 }; 280 281 CPU6: cpu@600 { 282 device_type = "cpu"; 283 compatible = "arm,kryo"; 284 reg = <0x0 0x600>; 285 enable-method = "psci"; 286 cpu-idle-states = <&BIG_CPU_SLEEP_0 287 &BIG_CPU_SLEEP_1 288 &CLUSTER_SLEEP_0>; 289 next-level-cache = <&L2_600>; 290 operating-points-v2 = <&cpu4_opp_table>; 291 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 292 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 293 qcom,freq-domain = <&cpufreq_hw 1>; 294 #cooling-cells = <2>; 295 L2_600: l2-cache { 296 compatible = "cache"; 297 next-level-cache = <&L3_0>; 298 }; 299 }; 300 301 CPU7: cpu@700 { 302 device_type = "cpu"; 303 compatible = "arm,kryo"; 304 reg = <0x0 0x700>; 305 enable-method = "psci"; 306 cpu-idle-states = <&BIG_CPU_SLEEP_0 307 &BIG_CPU_SLEEP_1 308 &CLUSTER_SLEEP_0>; 309 next-level-cache = <&L2_700>; 310 operating-points-v2 = <&cpu7_opp_table>; 311 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 312 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 313 qcom,freq-domain = <&cpufreq_hw 2>; 314 #cooling-cells = <2>; 315 L2_700: l2-cache { 316 compatible = "cache"; 317 next-level-cache = <&L3_0>; 318 }; 319 }; 320 321 cpu-map { 322 cluster0 { 323 core0 { 324 cpu = <&CPU0>; 325 }; 326 327 core1 { 328 cpu = <&CPU1>; 329 }; 330 331 core2 { 332 cpu = <&CPU2>; 333 }; 334 335 core3 { 336 cpu = <&CPU3>; 337 }; 338 339 core4 { 340 cpu = <&CPU4>; 341 }; 342 343 core5 { 344 cpu = <&CPU5>; 345 }; 346 347 core6 { 348 cpu = <&CPU6>; 349 }; 350 351 core7 { 352 cpu = <&CPU7>; 353 }; 354 }; 355 }; 356 357 idle-states { 358 entry-method = "psci"; 359 360 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 361 compatible = "arm,idle-state"; 362 idle-state-name = "little-power-down"; 363 arm,psci-suspend-param = <0x40000003>; 364 entry-latency-us = <549>; 365 exit-latency-us = <901>; 366 min-residency-us = <1774>; 367 local-timer-stop; 368 }; 369 370 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 371 compatible = "arm,idle-state"; 372 idle-state-name = "little-rail-power-down"; 373 arm,psci-suspend-param = <0x40000004>; 374 entry-latency-us = <702>; 375 exit-latency-us = <915>; 376 min-residency-us = <4001>; 377 local-timer-stop; 378 }; 379 380 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 381 compatible = "arm,idle-state"; 382 idle-state-name = "big-power-down"; 383 arm,psci-suspend-param = <0x40000003>; 384 entry-latency-us = <523>; 385 exit-latency-us = <1244>; 386 min-residency-us = <2207>; 387 local-timer-stop; 388 }; 389 390 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 391 compatible = "arm,idle-state"; 392 idle-state-name = "big-rail-power-down"; 393 arm,psci-suspend-param = <0x40000004>; 394 entry-latency-us = <526>; 395 exit-latency-us = <1854>; 396 min-residency-us = <5555>; 397 local-timer-stop; 398 }; 399 400 CLUSTER_SLEEP_0: cluster-sleep-0 { 401 compatible = "arm,idle-state"; 402 idle-state-name = "cluster-power-down"; 403 arm,psci-suspend-param = <0x40003444>; 404 entry-latency-us = <3263>; 405 exit-latency-us = <6562>; 406 min-residency-us = <9926>; 407 local-timer-stop; 408 }; 409 }; 410 }; 411 412 cpu0_opp_table: cpu0-opp-table { 413 compatible = "operating-points-v2"; 414 opp-shared; 415 416 cpu0_opp_300mhz: opp-300000000 { 417 opp-hz = /bits/ 64 <300000000>; 418 opp-peak-kBps = <800000 9600000>; 419 }; 420 421 cpu0_opp_691mhz: opp-691200000 { 422 opp-hz = /bits/ 64 <691200000>; 423 opp-peak-kBps = <800000 17817600>; 424 }; 425 426 cpu0_opp_806mhz: opp-806400000 { 427 opp-hz = /bits/ 64 <806400000>; 428 opp-peak-kBps = <800000 20889600>; 429 }; 430 431 cpu0_opp_941mhz: opp-940800000 { 432 opp-hz = /bits/ 64 <940800000>; 433 opp-peak-kBps = <1804000 24576000>; 434 }; 435 436 cpu0_opp_1152mhz: opp-1152000000 { 437 opp-hz = /bits/ 64 <1152000000>; 438 opp-peak-kBps = <2188000 27033600>; 439 }; 440 441 cpu0_opp_1325mhz: opp-1324800000 { 442 opp-hz = /bits/ 64 <1324800000>; 443 opp-peak-kBps = <2188000 33792000>; 444 }; 445 446 cpu0_opp_1517mhz: opp-1516800000 { 447 opp-hz = /bits/ 64 <1516800000>; 448 opp-peak-kBps = <3072000 38092800>; 449 }; 450 451 cpu0_opp_1651mhz: opp-1651200000 { 452 opp-hz = /bits/ 64 <1651200000>; 453 opp-peak-kBps = <3072000 41779200>; 454 }; 455 456 cpu0_opp_1805mhz: opp-1804800000 { 457 opp-hz = /bits/ 64 <1804800000>; 458 opp-peak-kBps = <4068000 48537600>; 459 }; 460 461 cpu0_opp_1958mhz: opp-1958400000 { 462 opp-hz = /bits/ 64 <1958400000>; 463 opp-peak-kBps = <4068000 48537600>; 464 }; 465 466 cpu0_opp_2016mhz: opp-2016000000 { 467 opp-hz = /bits/ 64 <2016000000>; 468 opp-peak-kBps = <6220000 48537600>; 469 }; 470 }; 471 472 cpu4_opp_table: cpu4-opp-table { 473 compatible = "operating-points-v2"; 474 opp-shared; 475 476 cpu4_opp_691mhz: opp-691200000 { 477 opp-hz = /bits/ 64 <691200000>; 478 opp-peak-kBps = <1804000 9600000>; 479 }; 480 481 cpu4_opp_941mhz: opp-940800000 { 482 opp-hz = /bits/ 64 <940800000>; 483 opp-peak-kBps = <2188000 17817600>; 484 }; 485 486 cpu4_opp_1229mhz: opp-1228800000 { 487 opp-hz = /bits/ 64 <1228800000>; 488 opp-peak-kBps = <4068000 24576000>; 489 }; 490 491 cpu4_opp_1344mhz: opp-1344000000 { 492 opp-hz = /bits/ 64 <1344000000>; 493 opp-peak-kBps = <4068000 24576000>; 494 }; 495 496 cpu4_opp_1517mhz: opp-1516800000 { 497 opp-hz = /bits/ 64 <1516800000>; 498 opp-peak-kBps = <4068000 24576000>; 499 }; 500 501 cpu4_opp_1651mhz: opp-1651200000 { 502 opp-hz = /bits/ 64 <1651200000>; 503 opp-peak-kBps = <6220000 38092800>; 504 }; 505 506 cpu4_opp_1901mhz: opp-1900800000 { 507 opp-hz = /bits/ 64 <1900800000>; 508 opp-peak-kBps = <6220000 44851200>; 509 }; 510 511 cpu4_opp_2054mhz: opp-2054400000 { 512 opp-hz = /bits/ 64 <2054400000>; 513 opp-peak-kBps = <6220000 44851200>; 514 }; 515 516 cpu4_opp_2112mhz: opp-2112000000 { 517 opp-hz = /bits/ 64 <2112000000>; 518 opp-peak-kBps = <6220000 44851200>; 519 }; 520 521 cpu4_opp_2131mhz: opp-2131200000 { 522 opp-hz = /bits/ 64 <2131200000>; 523 opp-peak-kBps = <6220000 44851200>; 524 }; 525 526 cpu4_opp_2208mhz: opp-2208000000 { 527 opp-hz = /bits/ 64 <2208000000>; 528 opp-peak-kBps = <6220000 44851200>; 529 }; 530 531 cpu4_opp_2400mhz: opp-2400000000 { 532 opp-hz = /bits/ 64 <2400000000>; 533 opp-peak-kBps = <8532000 48537600>; 534 }; 535 536 cpu4_opp_2611mhz: opp-2611200000 { 537 opp-hz = /bits/ 64 <2611200000>; 538 opp-peak-kBps = <8532000 48537600>; 539 }; 540 }; 541 542 cpu7_opp_table: cpu7-opp-table { 543 compatible = "operating-points-v2"; 544 opp-shared; 545 546 cpu7_opp_806mhz: opp-806400000 { 547 opp-hz = /bits/ 64 <806400000>; 548 opp-peak-kBps = <1804000 9600000>; 549 }; 550 551 cpu7_opp_1056mhz: opp-1056000000 { 552 opp-hz = /bits/ 64 <1056000000>; 553 opp-peak-kBps = <2188000 17817600>; 554 }; 555 556 cpu7_opp_1325mhz: opp-1324800000 { 557 opp-hz = /bits/ 64 <1324800000>; 558 opp-peak-kBps = <4068000 24576000>; 559 }; 560 561 cpu7_opp_1517mhz: opp-1516800000 { 562 opp-hz = /bits/ 64 <1516800000>; 563 opp-peak-kBps = <4068000 24576000>; 564 }; 565 566 cpu7_opp_1766mhz: opp-1766400000 { 567 opp-hz = /bits/ 64 <1766400000>; 568 opp-peak-kBps = <6220000 38092800>; 569 }; 570 571 cpu7_opp_1862mhz: opp-1862400000 { 572 opp-hz = /bits/ 64 <1862400000>; 573 opp-peak-kBps = <6220000 38092800>; 574 }; 575 576 cpu7_opp_2035mhz: opp-2035200000 { 577 opp-hz = /bits/ 64 <2035200000>; 578 opp-peak-kBps = <6220000 38092800>; 579 }; 580 581 cpu7_opp_2112mhz: opp-2112000000 { 582 opp-hz = /bits/ 64 <2112000000>; 583 opp-peak-kBps = <6220000 44851200>; 584 }; 585 586 cpu7_opp_2208mhz: opp-2208000000 { 587 opp-hz = /bits/ 64 <2208000000>; 588 opp-peak-kBps = <6220000 44851200>; 589 }; 590 591 cpu7_opp_2381mhz: opp-2380800000 { 592 opp-hz = /bits/ 64 <2380800000>; 593 opp-peak-kBps = <6832000 44851200>; 594 }; 595 596 cpu7_opp_2400mhz: opp-2400000000 { 597 opp-hz = /bits/ 64 <2400000000>; 598 opp-peak-kBps = <8532000 48537600>; 599 }; 600 601 cpu7_opp_2515mhz: opp-2515200000 { 602 opp-hz = /bits/ 64 <2515200000>; 603 opp-peak-kBps = <8532000 48537600>; 604 }; 605 606 cpu7_opp_2707mhz: opp-2707200000 { 607 opp-hz = /bits/ 64 <2707200000>; 608 opp-peak-kBps = <8532000 48537600>; 609 }; 610 611 cpu7_opp_3014mhz: opp-3014400000 { 612 opp-hz = /bits/ 64 <3014400000>; 613 opp-peak-kBps = <8532000 48537600>; 614 }; 615 }; 616 617 memory@80000000 { 618 device_type = "memory"; 619 /* We expect the bootloader to fill in the size */ 620 reg = <0 0x80000000 0 0>; 621 }; 622 623 firmware { 624 scm { 625 compatible = "qcom,scm-sc7280", "qcom,scm"; 626 }; 627 }; 628 629 clk_virt: interconnect { 630 compatible = "qcom,sc7280-clk-virt"; 631 #interconnect-cells = <2>; 632 qcom,bcm-voters = <&apps_bcm_voter>; 633 }; 634 635 smem { 636 compatible = "qcom,smem"; 637 memory-region = <&smem_mem>; 638 hwlocks = <&tcsr_mutex 3>; 639 }; 640 641 smp2p-adsp { 642 compatible = "qcom,smp2p"; 643 qcom,smem = <443>, <429>; 644 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 645 IPCC_MPROC_SIGNAL_SMP2P 646 IRQ_TYPE_EDGE_RISING>; 647 mboxes = <&ipcc IPCC_CLIENT_LPASS 648 IPCC_MPROC_SIGNAL_SMP2P>; 649 650 qcom,local-pid = <0>; 651 qcom,remote-pid = <2>; 652 653 adsp_smp2p_out: master-kernel { 654 qcom,entry-name = "master-kernel"; 655 #qcom,smem-state-cells = <1>; 656 }; 657 658 adsp_smp2p_in: slave-kernel { 659 qcom,entry-name = "slave-kernel"; 660 interrupt-controller; 661 #interrupt-cells = <2>; 662 }; 663 }; 664 665 smp2p-cdsp { 666 compatible = "qcom,smp2p"; 667 qcom,smem = <94>, <432>; 668 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 669 IPCC_MPROC_SIGNAL_SMP2P 670 IRQ_TYPE_EDGE_RISING>; 671 mboxes = <&ipcc IPCC_CLIENT_CDSP 672 IPCC_MPROC_SIGNAL_SMP2P>; 673 674 qcom,local-pid = <0>; 675 qcom,remote-pid = <5>; 676 677 cdsp_smp2p_out: master-kernel { 678 qcom,entry-name = "master-kernel"; 679 #qcom,smem-state-cells = <1>; 680 }; 681 682 cdsp_smp2p_in: slave-kernel { 683 qcom,entry-name = "slave-kernel"; 684 interrupt-controller; 685 #interrupt-cells = <2>; 686 }; 687 }; 688 689 smp2p-mpss { 690 compatible = "qcom,smp2p"; 691 qcom,smem = <435>, <428>; 692 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 693 IPCC_MPROC_SIGNAL_SMP2P 694 IRQ_TYPE_EDGE_RISING>; 695 mboxes = <&ipcc IPCC_CLIENT_MPSS 696 IPCC_MPROC_SIGNAL_SMP2P>; 697 698 qcom,local-pid = <0>; 699 qcom,remote-pid = <1>; 700 701 modem_smp2p_out: master-kernel { 702 qcom,entry-name = "master-kernel"; 703 #qcom,smem-state-cells = <1>; 704 }; 705 706 modem_smp2p_in: slave-kernel { 707 qcom,entry-name = "slave-kernel"; 708 interrupt-controller; 709 #interrupt-cells = <2>; 710 }; 711 712 ipa_smp2p_out: ipa-ap-to-modem { 713 qcom,entry-name = "ipa"; 714 #qcom,smem-state-cells = <1>; 715 }; 716 717 ipa_smp2p_in: ipa-modem-to-ap { 718 qcom,entry-name = "ipa"; 719 interrupt-controller; 720 #interrupt-cells = <2>; 721 }; 722 }; 723 724 smp2p-wpss { 725 compatible = "qcom,smp2p"; 726 qcom,smem = <617>, <616>; 727 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 728 IPCC_MPROC_SIGNAL_SMP2P 729 IRQ_TYPE_EDGE_RISING>; 730 mboxes = <&ipcc IPCC_CLIENT_WPSS 731 IPCC_MPROC_SIGNAL_SMP2P>; 732 733 qcom,local-pid = <0>; 734 qcom,remote-pid = <13>; 735 736 wpss_smp2p_out: master-kernel { 737 qcom,entry-name = "master-kernel"; 738 #qcom,smem-state-cells = <1>; 739 }; 740 741 wpss_smp2p_in: slave-kernel { 742 qcom,entry-name = "slave-kernel"; 743 interrupt-controller; 744 #interrupt-cells = <2>; 745 }; 746 }; 747 748 pmu { 749 compatible = "arm,armv8-pmuv3"; 750 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 751 }; 752 753 psci { 754 compatible = "arm,psci-1.0"; 755 method = "smc"; 756 }; 757 758 qspi_opp_table: qspi-opp-table { 759 compatible = "operating-points-v2"; 760 761 opp-75000000 { 762 opp-hz = /bits/ 64 <75000000>; 763 required-opps = <&rpmhpd_opp_low_svs>; 764 }; 765 766 opp-150000000 { 767 opp-hz = /bits/ 64 <150000000>; 768 required-opps = <&rpmhpd_opp_svs>; 769 }; 770 771 opp-200000000 { 772 opp-hz = /bits/ 64 <200000000>; 773 required-opps = <&rpmhpd_opp_svs_l1>; 774 }; 775 776 opp-300000000 { 777 opp-hz = /bits/ 64 <300000000>; 778 required-opps = <&rpmhpd_opp_nom>; 779 }; 780 }; 781 782 qup_opp_table: qup-opp-table { 783 compatible = "operating-points-v2"; 784 785 opp-75000000 { 786 opp-hz = /bits/ 64 <75000000>; 787 required-opps = <&rpmhpd_opp_low_svs>; 788 }; 789 790 opp-100000000 { 791 opp-hz = /bits/ 64 <100000000>; 792 required-opps = <&rpmhpd_opp_svs>; 793 }; 794 795 opp-128000000 { 796 opp-hz = /bits/ 64 <128000000>; 797 required-opps = <&rpmhpd_opp_nom>; 798 }; 799 }; 800 801 soc: soc@0 { 802 #address-cells = <2>; 803 #size-cells = <2>; 804 ranges = <0 0 0 0 0x10 0>; 805 dma-ranges = <0 0 0 0 0x10 0>; 806 compatible = "simple-bus"; 807 808 gcc: clock-controller@100000 { 809 compatible = "qcom,gcc-sc7280"; 810 reg = <0 0x00100000 0 0x1f0000>; 811 clocks = <&rpmhcc RPMH_CXO_CLK>, 812 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 813 <0>, <&pcie1_lane 0>, 814 <0>, <0>, <0>, <0>; 815 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 816 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 817 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 818 "ufs_phy_tx_symbol_0_clk", 819 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 820 #clock-cells = <1>; 821 #reset-cells = <1>; 822 #power-domain-cells = <1>; 823 }; 824 825 ipcc: mailbox@408000 { 826 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 827 reg = <0 0x00408000 0 0x1000>; 828 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 829 interrupt-controller; 830 #interrupt-cells = <3>; 831 #mbox-cells = <2>; 832 }; 833 834 qfprom: efuse@784000 { 835 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 836 reg = <0 0x00784000 0 0xa20>, 837 <0 0x00780000 0 0xa20>, 838 <0 0x00782000 0 0x120>, 839 <0 0x00786000 0 0x1fff>; 840 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 841 clock-names = "core"; 842 power-domains = <&rpmhpd SC7280_MX>; 843 #address-cells = <1>; 844 #size-cells = <1>; 845 }; 846 847 sdhc_1: sdhci@7c4000 { 848 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 849 pinctrl-names = "default", "sleep"; 850 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 851 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 852 status = "disabled"; 853 854 reg = <0 0x007c4000 0 0x1000>, 855 <0 0x007c5000 0 0x1000>; 856 reg-names = "hc", "cqhci"; 857 858 iommus = <&apps_smmu 0xc0 0x0>; 859 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 861 interrupt-names = "hc_irq", "pwr_irq"; 862 863 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 864 <&gcc GCC_SDCC1_AHB_CLK>, 865 <&rpmhcc RPMH_CXO_CLK>; 866 clock-names = "core", "iface", "xo"; 867 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 868 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 869 interconnect-names = "sdhc-ddr","cpu-sdhc"; 870 power-domains = <&rpmhpd SC7280_CX>; 871 operating-points-v2 = <&sdhc1_opp_table>; 872 873 bus-width = <8>; 874 supports-cqe; 875 876 qcom,dll-config = <0x0007642c>; 877 qcom,ddr-config = <0x80040868>; 878 879 mmc-ddr-1_8v; 880 mmc-hs200-1_8v; 881 mmc-hs400-1_8v; 882 mmc-hs400-enhanced-strobe; 883 884 sdhc1_opp_table: opp-table { 885 compatible = "operating-points-v2"; 886 887 opp-100000000 { 888 opp-hz = /bits/ 64 <100000000>; 889 required-opps = <&rpmhpd_opp_low_svs>; 890 opp-peak-kBps = <1800000 400000>; 891 opp-avg-kBps = <100000 0>; 892 }; 893 894 opp-384000000 { 895 opp-hz = /bits/ 64 <384000000>; 896 required-opps = <&rpmhpd_opp_nom>; 897 opp-peak-kBps = <5400000 1600000>; 898 opp-avg-kBps = <390000 0>; 899 }; 900 }; 901 902 }; 903 904 qupv3_id_0: geniqup@9c0000 { 905 compatible = "qcom,geni-se-qup"; 906 reg = <0 0x009c0000 0 0x2000>; 907 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 908 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 909 clock-names = "m-ahb", "s-ahb"; 910 #address-cells = <2>; 911 #size-cells = <2>; 912 ranges; 913 iommus = <&apps_smmu 0x123 0x0>; 914 status = "disabled"; 915 916 i2c0: i2c@980000 { 917 compatible = "qcom,geni-i2c"; 918 reg = <0 0x00980000 0 0x4000>; 919 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 920 clock-names = "se"; 921 pinctrl-names = "default"; 922 pinctrl-0 = <&qup_i2c0_data_clk>; 923 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 924 #address-cells = <1>; 925 #size-cells = <0>; 926 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 927 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 928 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 929 interconnect-names = "qup-core", "qup-config", 930 "qup-memory"; 931 status = "disabled"; 932 }; 933 934 spi0: spi@980000 { 935 compatible = "qcom,geni-spi"; 936 reg = <0 0x00980000 0 0x4000>; 937 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 938 clock-names = "se"; 939 pinctrl-names = "default"; 940 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 941 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 942 #address-cells = <1>; 943 #size-cells = <0>; 944 power-domains = <&rpmhpd SC7280_CX>; 945 operating-points-v2 = <&qup_opp_table>; 946 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 947 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 948 interconnect-names = "qup-core", "qup-config"; 949 status = "disabled"; 950 }; 951 952 uart0: serial@980000 { 953 compatible = "qcom,geni-uart"; 954 reg = <0 0x00980000 0 0x4000>; 955 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 956 clock-names = "se"; 957 pinctrl-names = "default"; 958 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 959 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 960 power-domains = <&rpmhpd SC7280_CX>; 961 operating-points-v2 = <&qup_opp_table>; 962 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 963 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 964 interconnect-names = "qup-core", "qup-config"; 965 status = "disabled"; 966 }; 967 968 i2c1: i2c@984000 { 969 compatible = "qcom,geni-i2c"; 970 reg = <0 0x00984000 0 0x4000>; 971 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 972 clock-names = "se"; 973 pinctrl-names = "default"; 974 pinctrl-0 = <&qup_i2c1_data_clk>; 975 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 976 #address-cells = <1>; 977 #size-cells = <0>; 978 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 979 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 980 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 981 interconnect-names = "qup-core", "qup-config", 982 "qup-memory"; 983 status = "disabled"; 984 }; 985 986 spi1: spi@984000 { 987 compatible = "qcom,geni-spi"; 988 reg = <0 0x00984000 0 0x4000>; 989 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 990 clock-names = "se"; 991 pinctrl-names = "default"; 992 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 993 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 994 #address-cells = <1>; 995 #size-cells = <0>; 996 power-domains = <&rpmhpd SC7280_CX>; 997 operating-points-v2 = <&qup_opp_table>; 998 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 999 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1000 interconnect-names = "qup-core", "qup-config"; 1001 status = "disabled"; 1002 }; 1003 1004 uart1: serial@984000 { 1005 compatible = "qcom,geni-uart"; 1006 reg = <0 0x00984000 0 0x4000>; 1007 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1008 clock-names = "se"; 1009 pinctrl-names = "default"; 1010 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1011 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1012 power-domains = <&rpmhpd SC7280_CX>; 1013 operating-points-v2 = <&qup_opp_table>; 1014 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1015 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1016 interconnect-names = "qup-core", "qup-config"; 1017 status = "disabled"; 1018 }; 1019 1020 i2c2: i2c@988000 { 1021 compatible = "qcom,geni-i2c"; 1022 reg = <0 0x00988000 0 0x4000>; 1023 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1024 clock-names = "se"; 1025 pinctrl-names = "default"; 1026 pinctrl-0 = <&qup_i2c2_data_clk>; 1027 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1031 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1032 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1033 interconnect-names = "qup-core", "qup-config", 1034 "qup-memory"; 1035 status = "disabled"; 1036 }; 1037 1038 spi2: spi@988000 { 1039 compatible = "qcom,geni-spi"; 1040 reg = <0 0x00988000 0 0x4000>; 1041 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1042 clock-names = "se"; 1043 pinctrl-names = "default"; 1044 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1045 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 power-domains = <&rpmhpd SC7280_CX>; 1049 operating-points-v2 = <&qup_opp_table>; 1050 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1051 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1052 interconnect-names = "qup-core", "qup-config"; 1053 status = "disabled"; 1054 }; 1055 1056 uart2: serial@988000 { 1057 compatible = "qcom,geni-uart"; 1058 reg = <0 0x00988000 0 0x4000>; 1059 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1060 clock-names = "se"; 1061 pinctrl-names = "default"; 1062 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1063 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1064 power-domains = <&rpmhpd SC7280_CX>; 1065 operating-points-v2 = <&qup_opp_table>; 1066 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1067 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1068 interconnect-names = "qup-core", "qup-config"; 1069 status = "disabled"; 1070 }; 1071 1072 i2c3: i2c@98c000 { 1073 compatible = "qcom,geni-i2c"; 1074 reg = <0 0x0098c000 0 0x4000>; 1075 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1076 clock-names = "se"; 1077 pinctrl-names = "default"; 1078 pinctrl-0 = <&qup_i2c3_data_clk>; 1079 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1083 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1084 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1085 interconnect-names = "qup-core", "qup-config", 1086 "qup-memory"; 1087 status = "disabled"; 1088 }; 1089 1090 spi3: spi@98c000 { 1091 compatible = "qcom,geni-spi"; 1092 reg = <0 0x0098c000 0 0x4000>; 1093 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1094 clock-names = "se"; 1095 pinctrl-names = "default"; 1096 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1097 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 power-domains = <&rpmhpd SC7280_CX>; 1101 operating-points-v2 = <&qup_opp_table>; 1102 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1103 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1104 interconnect-names = "qup-core", "qup-config"; 1105 status = "disabled"; 1106 }; 1107 1108 uart3: serial@98c000 { 1109 compatible = "qcom,geni-uart"; 1110 reg = <0 0x0098c000 0 0x4000>; 1111 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1112 clock-names = "se"; 1113 pinctrl-names = "default"; 1114 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1115 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1116 power-domains = <&rpmhpd SC7280_CX>; 1117 operating-points-v2 = <&qup_opp_table>; 1118 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1119 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1120 interconnect-names = "qup-core", "qup-config"; 1121 status = "disabled"; 1122 }; 1123 1124 i2c4: i2c@990000 { 1125 compatible = "qcom,geni-i2c"; 1126 reg = <0 0x00990000 0 0x4000>; 1127 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1128 clock-names = "se"; 1129 pinctrl-names = "default"; 1130 pinctrl-0 = <&qup_i2c4_data_clk>; 1131 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1135 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1136 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1137 interconnect-names = "qup-core", "qup-config", 1138 "qup-memory"; 1139 status = "disabled"; 1140 }; 1141 1142 spi4: spi@990000 { 1143 compatible = "qcom,geni-spi"; 1144 reg = <0 0x00990000 0 0x4000>; 1145 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1146 clock-names = "se"; 1147 pinctrl-names = "default"; 1148 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1149 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1150 #address-cells = <1>; 1151 #size-cells = <0>; 1152 power-domains = <&rpmhpd SC7280_CX>; 1153 operating-points-v2 = <&qup_opp_table>; 1154 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1155 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1156 interconnect-names = "qup-core", "qup-config"; 1157 status = "disabled"; 1158 }; 1159 1160 uart4: serial@990000 { 1161 compatible = "qcom,geni-uart"; 1162 reg = <0 0x00990000 0 0x4000>; 1163 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1164 clock-names = "se"; 1165 pinctrl-names = "default"; 1166 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1167 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1168 power-domains = <&rpmhpd SC7280_CX>; 1169 operating-points-v2 = <&qup_opp_table>; 1170 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1171 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1172 interconnect-names = "qup-core", "qup-config"; 1173 status = "disabled"; 1174 }; 1175 1176 i2c5: i2c@994000 { 1177 compatible = "qcom,geni-i2c"; 1178 reg = <0 0x00994000 0 0x4000>; 1179 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1180 clock-names = "se"; 1181 pinctrl-names = "default"; 1182 pinctrl-0 = <&qup_i2c5_data_clk>; 1183 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1184 #address-cells = <1>; 1185 #size-cells = <0>; 1186 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1187 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1188 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1189 interconnect-names = "qup-core", "qup-config", 1190 "qup-memory"; 1191 status = "disabled"; 1192 }; 1193 1194 spi5: spi@994000 { 1195 compatible = "qcom,geni-spi"; 1196 reg = <0 0x00994000 0 0x4000>; 1197 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1198 clock-names = "se"; 1199 pinctrl-names = "default"; 1200 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1201 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1202 #address-cells = <1>; 1203 #size-cells = <0>; 1204 power-domains = <&rpmhpd SC7280_CX>; 1205 operating-points-v2 = <&qup_opp_table>; 1206 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1207 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1208 interconnect-names = "qup-core", "qup-config"; 1209 status = "disabled"; 1210 }; 1211 1212 uart5: serial@994000 { 1213 compatible = "qcom,geni-uart"; 1214 reg = <0 0x00994000 0 0x4000>; 1215 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1216 clock-names = "se"; 1217 pinctrl-names = "default"; 1218 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1219 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1220 power-domains = <&rpmhpd SC7280_CX>; 1221 operating-points-v2 = <&qup_opp_table>; 1222 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1223 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1224 interconnect-names = "qup-core", "qup-config"; 1225 status = "disabled"; 1226 }; 1227 1228 i2c6: i2c@998000 { 1229 compatible = "qcom,geni-i2c"; 1230 reg = <0 0x00998000 0 0x4000>; 1231 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1232 clock-names = "se"; 1233 pinctrl-names = "default"; 1234 pinctrl-0 = <&qup_i2c6_data_clk>; 1235 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1236 #address-cells = <1>; 1237 #size-cells = <0>; 1238 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1239 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1240 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1241 interconnect-names = "qup-core", "qup-config", 1242 "qup-memory"; 1243 status = "disabled"; 1244 }; 1245 1246 spi6: spi@998000 { 1247 compatible = "qcom,geni-spi"; 1248 reg = <0 0x00998000 0 0x4000>; 1249 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1250 clock-names = "se"; 1251 pinctrl-names = "default"; 1252 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1253 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 power-domains = <&rpmhpd SC7280_CX>; 1257 operating-points-v2 = <&qup_opp_table>; 1258 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1259 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1260 interconnect-names = "qup-core", "qup-config"; 1261 status = "disabled"; 1262 }; 1263 1264 uart6: serial@998000 { 1265 compatible = "qcom,geni-uart"; 1266 reg = <0 0x00998000 0 0x4000>; 1267 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1268 clock-names = "se"; 1269 pinctrl-names = "default"; 1270 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1271 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1272 power-domains = <&rpmhpd SC7280_CX>; 1273 operating-points-v2 = <&qup_opp_table>; 1274 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1275 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1276 interconnect-names = "qup-core", "qup-config"; 1277 status = "disabled"; 1278 }; 1279 1280 i2c7: i2c@99c000 { 1281 compatible = "qcom,geni-i2c"; 1282 reg = <0 0x0099c000 0 0x4000>; 1283 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1284 clock-names = "se"; 1285 pinctrl-names = "default"; 1286 pinctrl-0 = <&qup_i2c7_data_clk>; 1287 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1288 #address-cells = <1>; 1289 #size-cells = <0>; 1290 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1291 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1292 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1293 interconnect-names = "qup-core", "qup-config", 1294 "qup-memory"; 1295 status = "disabled"; 1296 }; 1297 1298 spi7: spi@99c000 { 1299 compatible = "qcom,geni-spi"; 1300 reg = <0 0x0099c000 0 0x4000>; 1301 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1302 clock-names = "se"; 1303 pinctrl-names = "default"; 1304 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1305 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1306 #address-cells = <1>; 1307 #size-cells = <0>; 1308 power-domains = <&rpmhpd SC7280_CX>; 1309 operating-points-v2 = <&qup_opp_table>; 1310 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1311 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1312 interconnect-names = "qup-core", "qup-config"; 1313 status = "disabled"; 1314 }; 1315 1316 uart7: serial@99c000 { 1317 compatible = "qcom,geni-uart"; 1318 reg = <0 0x0099c000 0 0x4000>; 1319 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1320 clock-names = "se"; 1321 pinctrl-names = "default"; 1322 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1323 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1324 power-domains = <&rpmhpd SC7280_CX>; 1325 operating-points-v2 = <&qup_opp_table>; 1326 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1327 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1328 interconnect-names = "qup-core", "qup-config"; 1329 status = "disabled"; 1330 }; 1331 }; 1332 1333 qupv3_id_1: geniqup@ac0000 { 1334 compatible = "qcom,geni-se-qup"; 1335 reg = <0 0x00ac0000 0 0x2000>; 1336 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1337 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1338 clock-names = "m-ahb", "s-ahb"; 1339 #address-cells = <2>; 1340 #size-cells = <2>; 1341 ranges; 1342 iommus = <&apps_smmu 0x43 0x0>; 1343 status = "disabled"; 1344 1345 i2c8: i2c@a80000 { 1346 compatible = "qcom,geni-i2c"; 1347 reg = <0 0x00a80000 0 0x4000>; 1348 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1349 clock-names = "se"; 1350 pinctrl-names = "default"; 1351 pinctrl-0 = <&qup_i2c8_data_clk>; 1352 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1353 #address-cells = <1>; 1354 #size-cells = <0>; 1355 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1356 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1357 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1358 interconnect-names = "qup-core", "qup-config", 1359 "qup-memory"; 1360 status = "disabled"; 1361 }; 1362 1363 spi8: spi@a80000 { 1364 compatible = "qcom,geni-spi"; 1365 reg = <0 0x00a80000 0 0x4000>; 1366 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1367 clock-names = "se"; 1368 pinctrl-names = "default"; 1369 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1370 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1371 #address-cells = <1>; 1372 #size-cells = <0>; 1373 power-domains = <&rpmhpd SC7280_CX>; 1374 operating-points-v2 = <&qup_opp_table>; 1375 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1376 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1377 interconnect-names = "qup-core", "qup-config"; 1378 status = "disabled"; 1379 }; 1380 1381 uart8: serial@a80000 { 1382 compatible = "qcom,geni-uart"; 1383 reg = <0 0x00a80000 0 0x4000>; 1384 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1385 clock-names = "se"; 1386 pinctrl-names = "default"; 1387 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1388 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1389 power-domains = <&rpmhpd SC7280_CX>; 1390 operating-points-v2 = <&qup_opp_table>; 1391 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1392 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1393 interconnect-names = "qup-core", "qup-config"; 1394 status = "disabled"; 1395 }; 1396 1397 i2c9: i2c@a84000 { 1398 compatible = "qcom,geni-i2c"; 1399 reg = <0 0x00a84000 0 0x4000>; 1400 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1401 clock-names = "se"; 1402 pinctrl-names = "default"; 1403 pinctrl-0 = <&qup_i2c9_data_clk>; 1404 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1405 #address-cells = <1>; 1406 #size-cells = <0>; 1407 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1408 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1409 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1410 interconnect-names = "qup-core", "qup-config", 1411 "qup-memory"; 1412 status = "disabled"; 1413 }; 1414 1415 spi9: spi@a84000 { 1416 compatible = "qcom,geni-spi"; 1417 reg = <0 0x00a84000 0 0x4000>; 1418 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1419 clock-names = "se"; 1420 pinctrl-names = "default"; 1421 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1422 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1423 #address-cells = <1>; 1424 #size-cells = <0>; 1425 power-domains = <&rpmhpd SC7280_CX>; 1426 operating-points-v2 = <&qup_opp_table>; 1427 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1428 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1429 interconnect-names = "qup-core", "qup-config"; 1430 status = "disabled"; 1431 }; 1432 1433 uart9: serial@a84000 { 1434 compatible = "qcom,geni-uart"; 1435 reg = <0 0x00a84000 0 0x4000>; 1436 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1437 clock-names = "se"; 1438 pinctrl-names = "default"; 1439 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1440 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1441 power-domains = <&rpmhpd SC7280_CX>; 1442 operating-points-v2 = <&qup_opp_table>; 1443 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1444 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1445 interconnect-names = "qup-core", "qup-config"; 1446 status = "disabled"; 1447 }; 1448 1449 i2c10: i2c@a88000 { 1450 compatible = "qcom,geni-i2c"; 1451 reg = <0 0x00a88000 0 0x4000>; 1452 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1453 clock-names = "se"; 1454 pinctrl-names = "default"; 1455 pinctrl-0 = <&qup_i2c10_data_clk>; 1456 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1457 #address-cells = <1>; 1458 #size-cells = <0>; 1459 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1460 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1461 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1462 interconnect-names = "qup-core", "qup-config", 1463 "qup-memory"; 1464 status = "disabled"; 1465 }; 1466 1467 spi10: spi@a88000 { 1468 compatible = "qcom,geni-spi"; 1469 reg = <0 0x00a88000 0 0x4000>; 1470 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1471 clock-names = "se"; 1472 pinctrl-names = "default"; 1473 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1474 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1475 #address-cells = <1>; 1476 #size-cells = <0>; 1477 power-domains = <&rpmhpd SC7280_CX>; 1478 operating-points-v2 = <&qup_opp_table>; 1479 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1480 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1481 interconnect-names = "qup-core", "qup-config"; 1482 status = "disabled"; 1483 }; 1484 1485 uart10: serial@a88000 { 1486 compatible = "qcom,geni-uart"; 1487 reg = <0 0x00a88000 0 0x4000>; 1488 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1489 clock-names = "se"; 1490 pinctrl-names = "default"; 1491 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1492 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1493 power-domains = <&rpmhpd SC7280_CX>; 1494 operating-points-v2 = <&qup_opp_table>; 1495 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1496 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1497 interconnect-names = "qup-core", "qup-config"; 1498 status = "disabled"; 1499 }; 1500 1501 i2c11: i2c@a8c000 { 1502 compatible = "qcom,geni-i2c"; 1503 reg = <0 0x00a8c000 0 0x4000>; 1504 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1505 clock-names = "se"; 1506 pinctrl-names = "default"; 1507 pinctrl-0 = <&qup_i2c11_data_clk>; 1508 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1509 #address-cells = <1>; 1510 #size-cells = <0>; 1511 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1512 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1513 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1514 interconnect-names = "qup-core", "qup-config", 1515 "qup-memory"; 1516 status = "disabled"; 1517 }; 1518 1519 spi11: spi@a8c000 { 1520 compatible = "qcom,geni-spi"; 1521 reg = <0 0x00a8c000 0 0x4000>; 1522 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1523 clock-names = "se"; 1524 pinctrl-names = "default"; 1525 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1526 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1527 #address-cells = <1>; 1528 #size-cells = <0>; 1529 power-domains = <&rpmhpd SC7280_CX>; 1530 operating-points-v2 = <&qup_opp_table>; 1531 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1532 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1533 interconnect-names = "qup-core", "qup-config"; 1534 status = "disabled"; 1535 }; 1536 1537 uart11: serial@a8c000 { 1538 compatible = "qcom,geni-uart"; 1539 reg = <0 0x00a8c000 0 0x4000>; 1540 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1541 clock-names = "se"; 1542 pinctrl-names = "default"; 1543 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1544 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1545 power-domains = <&rpmhpd SC7280_CX>; 1546 operating-points-v2 = <&qup_opp_table>; 1547 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1548 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1549 interconnect-names = "qup-core", "qup-config"; 1550 status = "disabled"; 1551 }; 1552 1553 i2c12: i2c@a90000 { 1554 compatible = "qcom,geni-i2c"; 1555 reg = <0 0x00a90000 0 0x4000>; 1556 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1557 clock-names = "se"; 1558 pinctrl-names = "default"; 1559 pinctrl-0 = <&qup_i2c12_data_clk>; 1560 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1561 #address-cells = <1>; 1562 #size-cells = <0>; 1563 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1564 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1565 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1566 interconnect-names = "qup-core", "qup-config", 1567 "qup-memory"; 1568 status = "disabled"; 1569 }; 1570 1571 spi12: spi@a90000 { 1572 compatible = "qcom,geni-spi"; 1573 reg = <0 0x00a90000 0 0x4000>; 1574 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1575 clock-names = "se"; 1576 pinctrl-names = "default"; 1577 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1578 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1579 #address-cells = <1>; 1580 #size-cells = <0>; 1581 power-domains = <&rpmhpd SC7280_CX>; 1582 operating-points-v2 = <&qup_opp_table>; 1583 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1584 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1585 interconnect-names = "qup-core", "qup-config"; 1586 status = "disabled"; 1587 }; 1588 1589 uart12: serial@a90000 { 1590 compatible = "qcom,geni-uart"; 1591 reg = <0 0x00a90000 0 0x4000>; 1592 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1593 clock-names = "se"; 1594 pinctrl-names = "default"; 1595 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1596 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1597 power-domains = <&rpmhpd SC7280_CX>; 1598 operating-points-v2 = <&qup_opp_table>; 1599 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1600 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1601 interconnect-names = "qup-core", "qup-config"; 1602 status = "disabled"; 1603 }; 1604 1605 i2c13: i2c@a94000 { 1606 compatible = "qcom,geni-i2c"; 1607 reg = <0 0x00a94000 0 0x4000>; 1608 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1609 clock-names = "se"; 1610 pinctrl-names = "default"; 1611 pinctrl-0 = <&qup_i2c13_data_clk>; 1612 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1613 #address-cells = <1>; 1614 #size-cells = <0>; 1615 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1616 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1617 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1618 interconnect-names = "qup-core", "qup-config", 1619 "qup-memory"; 1620 status = "disabled"; 1621 }; 1622 1623 spi13: spi@a94000 { 1624 compatible = "qcom,geni-spi"; 1625 reg = <0 0x00a94000 0 0x4000>; 1626 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1627 clock-names = "se"; 1628 pinctrl-names = "default"; 1629 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1630 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1631 #address-cells = <1>; 1632 #size-cells = <0>; 1633 power-domains = <&rpmhpd SC7280_CX>; 1634 operating-points-v2 = <&qup_opp_table>; 1635 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1636 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1637 interconnect-names = "qup-core", "qup-config"; 1638 status = "disabled"; 1639 }; 1640 1641 uart13: serial@a94000 { 1642 compatible = "qcom,geni-uart"; 1643 reg = <0 0x00a94000 0 0x4000>; 1644 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1645 clock-names = "se"; 1646 pinctrl-names = "default"; 1647 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1648 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1649 power-domains = <&rpmhpd SC7280_CX>; 1650 operating-points-v2 = <&qup_opp_table>; 1651 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1652 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1653 interconnect-names = "qup-core", "qup-config"; 1654 status = "disabled"; 1655 }; 1656 1657 i2c14: i2c@a98000 { 1658 compatible = "qcom,geni-i2c"; 1659 reg = <0 0x00a98000 0 0x4000>; 1660 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1661 clock-names = "se"; 1662 pinctrl-names = "default"; 1663 pinctrl-0 = <&qup_i2c14_data_clk>; 1664 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1665 #address-cells = <1>; 1666 #size-cells = <0>; 1667 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1668 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1669 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1670 interconnect-names = "qup-core", "qup-config", 1671 "qup-memory"; 1672 status = "disabled"; 1673 }; 1674 1675 spi14: spi@a98000 { 1676 compatible = "qcom,geni-spi"; 1677 reg = <0 0x00a98000 0 0x4000>; 1678 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1679 clock-names = "se"; 1680 pinctrl-names = "default"; 1681 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1682 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1683 #address-cells = <1>; 1684 #size-cells = <0>; 1685 power-domains = <&rpmhpd SC7280_CX>; 1686 operating-points-v2 = <&qup_opp_table>; 1687 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1688 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1689 interconnect-names = "qup-core", "qup-config"; 1690 status = "disabled"; 1691 }; 1692 1693 uart14: serial@a98000 { 1694 compatible = "qcom,geni-uart"; 1695 reg = <0 0x00a98000 0 0x4000>; 1696 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1697 clock-names = "se"; 1698 pinctrl-names = "default"; 1699 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1700 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1701 power-domains = <&rpmhpd SC7280_CX>; 1702 operating-points-v2 = <&qup_opp_table>; 1703 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1704 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1705 interconnect-names = "qup-core", "qup-config"; 1706 status = "disabled"; 1707 }; 1708 1709 i2c15: i2c@a9c000 { 1710 compatible = "qcom,geni-i2c"; 1711 reg = <0 0x00a9c000 0 0x4000>; 1712 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1713 clock-names = "se"; 1714 pinctrl-names = "default"; 1715 pinctrl-0 = <&qup_i2c15_data_clk>; 1716 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1717 #address-cells = <1>; 1718 #size-cells = <0>; 1719 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1720 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1721 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1722 interconnect-names = "qup-core", "qup-config", 1723 "qup-memory"; 1724 status = "disabled"; 1725 }; 1726 1727 spi15: spi@a9c000 { 1728 compatible = "qcom,geni-spi"; 1729 reg = <0 0x00a9c000 0 0x4000>; 1730 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1731 clock-names = "se"; 1732 pinctrl-names = "default"; 1733 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1734 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1735 #address-cells = <1>; 1736 #size-cells = <0>; 1737 power-domains = <&rpmhpd SC7280_CX>; 1738 operating-points-v2 = <&qup_opp_table>; 1739 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1740 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1741 interconnect-names = "qup-core", "qup-config"; 1742 status = "disabled"; 1743 }; 1744 1745 uart15: serial@a9c000 { 1746 compatible = "qcom,geni-uart"; 1747 reg = <0 0x00a9c000 0 0x4000>; 1748 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1749 clock-names = "se"; 1750 pinctrl-names = "default"; 1751 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1752 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1753 power-domains = <&rpmhpd SC7280_CX>; 1754 operating-points-v2 = <&qup_opp_table>; 1755 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1756 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1757 interconnect-names = "qup-core", "qup-config"; 1758 status = "disabled"; 1759 }; 1760 }; 1761 1762 cnoc2: interconnect@1500000 { 1763 reg = <0 0x01500000 0 0x1000>; 1764 compatible = "qcom,sc7280-cnoc2"; 1765 #interconnect-cells = <2>; 1766 qcom,bcm-voters = <&apps_bcm_voter>; 1767 }; 1768 1769 cnoc3: interconnect@1502000 { 1770 reg = <0 0x01502000 0 0x1000>; 1771 compatible = "qcom,sc7280-cnoc3"; 1772 #interconnect-cells = <2>; 1773 qcom,bcm-voters = <&apps_bcm_voter>; 1774 }; 1775 1776 mc_virt: interconnect@1580000 { 1777 reg = <0 0x01580000 0 0x4>; 1778 compatible = "qcom,sc7280-mc-virt"; 1779 #interconnect-cells = <2>; 1780 qcom,bcm-voters = <&apps_bcm_voter>; 1781 }; 1782 1783 system_noc: interconnect@1680000 { 1784 reg = <0 0x01680000 0 0x15480>; 1785 compatible = "qcom,sc7280-system-noc"; 1786 #interconnect-cells = <2>; 1787 qcom,bcm-voters = <&apps_bcm_voter>; 1788 }; 1789 1790 aggre1_noc: interconnect@16e0000 { 1791 compatible = "qcom,sc7280-aggre1-noc"; 1792 reg = <0 0x016e0000 0 0x1c080>; 1793 #interconnect-cells = <2>; 1794 qcom,bcm-voters = <&apps_bcm_voter>; 1795 }; 1796 1797 aggre2_noc: interconnect@1700000 { 1798 reg = <0 0x01700000 0 0x2b080>; 1799 compatible = "qcom,sc7280-aggre2-noc"; 1800 #interconnect-cells = <2>; 1801 qcom,bcm-voters = <&apps_bcm_voter>; 1802 }; 1803 1804 mmss_noc: interconnect@1740000 { 1805 reg = <0 0x01740000 0 0x1e080>; 1806 compatible = "qcom,sc7280-mmss-noc"; 1807 #interconnect-cells = <2>; 1808 qcom,bcm-voters = <&apps_bcm_voter>; 1809 }; 1810 1811 pcie1: pci@1c08000 { 1812 compatible = "qcom,pcie-sc7280"; 1813 reg = <0 0x01c08000 0 0x3000>, 1814 <0 0x40000000 0 0xf1d>, 1815 <0 0x40000f20 0 0xa8>, 1816 <0 0x40001000 0 0x1000>, 1817 <0 0x40100000 0 0x100000>; 1818 1819 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1820 device_type = "pci"; 1821 linux,pci-domain = <1>; 1822 bus-range = <0x00 0xff>; 1823 num-lanes = <2>; 1824 1825 #address-cells = <3>; 1826 #size-cells = <2>; 1827 1828 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1829 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1830 1831 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1832 interrupt-names = "msi"; 1833 #interrupt-cells = <1>; 1834 interrupt-map-mask = <0 0 0 0x7>; 1835 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 1836 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 1837 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 1838 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 1839 1840 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1841 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1842 <&pcie1_lane 0>, 1843 <&rpmhcc RPMH_CXO_CLK>, 1844 <&gcc GCC_PCIE_1_AUX_CLK>, 1845 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1846 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1847 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1848 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1849 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1850 <&gcc GCC_DDRSS_PCIE_SF_CLK>; 1851 1852 clock-names = "pipe", 1853 "pipe_mux", 1854 "phy_pipe", 1855 "ref", 1856 "aux", 1857 "cfg", 1858 "bus_master", 1859 "bus_slave", 1860 "slave_q2a", 1861 "tbu", 1862 "ddrss_sf_tbu"; 1863 1864 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1865 assigned-clock-rates = <19200000>; 1866 1867 resets = <&gcc GCC_PCIE_1_BCR>; 1868 reset-names = "pci"; 1869 1870 power-domains = <&gcc GCC_PCIE_1_GDSC>; 1871 1872 phys = <&pcie1_lane>; 1873 phy-names = "pciephy"; 1874 1875 pinctrl-names = "default"; 1876 pinctrl-0 = <&pcie1_clkreq_n>; 1877 1878 iommus = <&apps_smmu 0x1c80 0x1>; 1879 1880 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1881 <0x100 &apps_smmu 0x1c81 0x1>; 1882 1883 status = "disabled"; 1884 }; 1885 1886 pcie1_phy: phy@1c0e000 { 1887 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1888 reg = <0 0x01c0e000 0 0x1c0>; 1889 #address-cells = <2>; 1890 #size-cells = <2>; 1891 ranges; 1892 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1893 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1894 <&gcc GCC_PCIE_CLKREF_EN>, 1895 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1896 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1897 1898 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1899 reset-names = "phy"; 1900 1901 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1902 assigned-clock-rates = <100000000>; 1903 1904 status = "disabled"; 1905 1906 pcie1_lane: lanes@1c0e200 { 1907 reg = <0 0x01c0e200 0 0x170>, 1908 <0 0x01c0e400 0 0x200>, 1909 <0 0x01c0ea00 0 0x1f0>, 1910 <0 0x01c0e600 0 0x170>, 1911 <0 0x01c0e800 0 0x200>, 1912 <0 0x01c0ee00 0 0xf4>; 1913 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1914 clock-names = "pipe0"; 1915 1916 #phy-cells = <0>; 1917 #clock-cells = <1>; 1918 clock-output-names = "pcie_1_pipe_clk"; 1919 }; 1920 }; 1921 1922 ipa: ipa@1e40000 { 1923 compatible = "qcom,sc7280-ipa"; 1924 1925 iommus = <&apps_smmu 0x480 0x0>, 1926 <&apps_smmu 0x482 0x0>; 1927 reg = <0 0x1e40000 0 0x8000>, 1928 <0 0x1e50000 0 0x4ad0>, 1929 <0 0x1e04000 0 0x23000>; 1930 reg-names = "ipa-reg", 1931 "ipa-shared", 1932 "gsi"; 1933 1934 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 1935 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1936 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1937 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1938 interrupt-names = "ipa", 1939 "gsi", 1940 "ipa-clock-query", 1941 "ipa-setup-ready"; 1942 1943 clocks = <&rpmhcc RPMH_IPA_CLK>; 1944 clock-names = "core"; 1945 1946 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1947 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 1948 interconnect-names = "memory", 1949 "config"; 1950 1951 qcom,qmp = <&aoss_qmp>; 1952 1953 qcom,smem-states = <&ipa_smp2p_out 0>, 1954 <&ipa_smp2p_out 1>; 1955 qcom,smem-state-names = "ipa-clock-enabled-valid", 1956 "ipa-clock-enabled"; 1957 1958 status = "disabled"; 1959 }; 1960 1961 tcsr_mutex: hwlock@1f40000 { 1962 compatible = "qcom,tcsr-mutex", "syscon"; 1963 reg = <0 0x01f40000 0 0x40000>; 1964 #hwlock-cells = <1>; 1965 }; 1966 1967 tcsr: syscon@1fc0000 { 1968 compatible = "qcom,sc7280-tcsr", "syscon"; 1969 reg = <0 0x01fc0000 0 0x30000>; 1970 }; 1971 1972 lpasscc: lpasscc@3000000 { 1973 compatible = "qcom,sc7280-lpasscc"; 1974 reg = <0 0x03000000 0 0x40>, 1975 <0 0x03c04000 0 0x4>, 1976 <0 0x03389000 0 0x24>; 1977 reg-names = "qdsp6ss", "top_cc", "cc"; 1978 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 1979 clock-names = "iface"; 1980 #clock-cells = <1>; 1981 }; 1982 1983 lpass_ag_noc: interconnect@3c40000 { 1984 reg = <0 0x03c40000 0 0xf080>; 1985 compatible = "qcom,sc7280-lpass-ag-noc"; 1986 #interconnect-cells = <2>; 1987 qcom,bcm-voters = <&apps_bcm_voter>; 1988 }; 1989 1990 gpu: gpu@3d00000 { 1991 compatible = "qcom,adreno-635.0", "qcom,adreno"; 1992 reg = <0 0x03d00000 0 0x40000>, 1993 <0 0x03d9e000 0 0x1000>, 1994 <0 0x03d61000 0 0x800>; 1995 reg-names = "kgsl_3d0_reg_memory", 1996 "cx_mem", 1997 "cx_dbgc"; 1998 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1999 iommus = <&adreno_smmu 0 0x401>; 2000 operating-points-v2 = <&gpu_opp_table>; 2001 qcom,gmu = <&gmu>; 2002 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2003 interconnect-names = "gfx-mem"; 2004 #cooling-cells = <2>; 2005 2006 gpu_opp_table: opp-table { 2007 compatible = "operating-points-v2"; 2008 2009 opp-315000000 { 2010 opp-hz = /bits/ 64 <315000000>; 2011 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2012 opp-peak-kBps = <1804000>; 2013 }; 2014 2015 opp-450000000 { 2016 opp-hz = /bits/ 64 <450000000>; 2017 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2018 opp-peak-kBps = <4068000>; 2019 }; 2020 2021 opp-550000000 { 2022 opp-hz = /bits/ 64 <550000000>; 2023 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2024 opp-peak-kBps = <6832000>; 2025 }; 2026 }; 2027 }; 2028 2029 gmu: gmu@3d6a000 { 2030 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2031 reg = <0 0x03d6a000 0 0x34000>, 2032 <0 0x3de0000 0 0x10000>, 2033 <0 0x0b290000 0 0x10000>; 2034 reg-names = "gmu", "rscc", "gmu_pdc"; 2035 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2036 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2037 interrupt-names = "hfi", "gmu"; 2038 clocks = <&gpucc 5>, 2039 <&gpucc 8>, 2040 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2041 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2042 <&gpucc 2>, 2043 <&gpucc 15>, 2044 <&gpucc 11>; 2045 clock-names = "gmu", 2046 "cxo", 2047 "axi", 2048 "memnoc", 2049 "ahb", 2050 "hub", 2051 "smmu_vote"; 2052 power-domains = <&gpucc 0>, 2053 <&gpucc 1>; 2054 power-domain-names = "cx", 2055 "gx"; 2056 iommus = <&adreno_smmu 5 0x400>; 2057 operating-points-v2 = <&gmu_opp_table>; 2058 2059 gmu_opp_table: opp-table { 2060 compatible = "operating-points-v2"; 2061 2062 opp-200000000 { 2063 opp-hz = /bits/ 64 <200000000>; 2064 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2065 }; 2066 }; 2067 }; 2068 2069 gpucc: clock-controller@3d90000 { 2070 compatible = "qcom,sc7280-gpucc"; 2071 reg = <0 0x03d90000 0 0x9000>; 2072 clocks = <&rpmhcc RPMH_CXO_CLK>, 2073 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2074 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2075 clock-names = "bi_tcxo", 2076 "gcc_gpu_gpll0_clk_src", 2077 "gcc_gpu_gpll0_div_clk_src"; 2078 #clock-cells = <1>; 2079 #reset-cells = <1>; 2080 #power-domain-cells = <1>; 2081 }; 2082 2083 adreno_smmu: iommu@3da0000 { 2084 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2085 reg = <0 0x03da0000 0 0x20000>; 2086 #iommu-cells = <2>; 2087 #global-interrupts = <2>; 2088 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2089 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2090 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2091 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2092 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2093 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2094 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2095 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2096 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2097 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2098 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2099 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2100 2101 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2102 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2103 <&gpucc 2>, 2104 <&gpucc 11>, 2105 <&gpucc 5>, 2106 <&gpucc 15>, 2107 <&gpucc 13>; 2108 clock-names = "gcc_gpu_memnoc_gfx_clk", 2109 "gcc_gpu_snoc_dvm_gfx_clk", 2110 "gpu_cc_ahb_clk", 2111 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2112 "gpu_cc_cx_gmu_clk", 2113 "gpu_cc_hub_cx_int_clk", 2114 "gpu_cc_hub_aon_clk"; 2115 2116 power-domains = <&gpucc 0>; 2117 }; 2118 2119 remoteproc_mpss: remoteproc@4080000 { 2120 compatible = "qcom,sc7280-mpss-pas"; 2121 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2122 reg-names = "qdsp6", "rmb"; 2123 2124 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2125 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2126 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2127 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2128 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2129 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2130 interrupt-names = "wdog", "fatal", "ready", "handover", 2131 "stop-ack", "shutdown-ack"; 2132 2133 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2134 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 2135 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2136 <&rpmhcc RPMH_PKA_CLK>, 2137 <&rpmhcc RPMH_CXO_CLK>; 2138 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 2139 2140 power-domains = <&rpmhpd SC7280_CX>, 2141 <&rpmhpd SC7280_MSS>; 2142 power-domain-names = "cx", "mss"; 2143 2144 memory-region = <&mpss_mem>; 2145 2146 qcom,qmp = <&aoss_qmp>; 2147 2148 qcom,smem-states = <&modem_smp2p_out 0>; 2149 qcom,smem-state-names = "stop"; 2150 2151 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2152 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2153 reset-names = "mss_restart", "pdc_reset"; 2154 2155 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; 2156 qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>; 2157 qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>; 2158 2159 status = "disabled"; 2160 2161 glink-edge { 2162 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2163 IPCC_MPROC_SIGNAL_GLINK_QMP 2164 IRQ_TYPE_EDGE_RISING>; 2165 mboxes = <&ipcc IPCC_CLIENT_MPSS 2166 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2167 label = "modem"; 2168 qcom,remote-pid = <1>; 2169 }; 2170 }; 2171 2172 stm@6002000 { 2173 compatible = "arm,coresight-stm", "arm,primecell"; 2174 reg = <0 0x06002000 0 0x1000>, 2175 <0 0x16280000 0 0x180000>; 2176 reg-names = "stm-base", "stm-stimulus-base"; 2177 2178 clocks = <&aoss_qmp>; 2179 clock-names = "apb_pclk"; 2180 2181 out-ports { 2182 port { 2183 stm_out: endpoint { 2184 remote-endpoint = <&funnel0_in7>; 2185 }; 2186 }; 2187 }; 2188 }; 2189 2190 funnel@6041000 { 2191 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2192 reg = <0 0x06041000 0 0x1000>; 2193 2194 clocks = <&aoss_qmp>; 2195 clock-names = "apb_pclk"; 2196 2197 out-ports { 2198 port { 2199 funnel0_out: endpoint { 2200 remote-endpoint = <&merge_funnel_in0>; 2201 }; 2202 }; 2203 }; 2204 2205 in-ports { 2206 #address-cells = <1>; 2207 #size-cells = <0>; 2208 2209 port@7 { 2210 reg = <7>; 2211 funnel0_in7: endpoint { 2212 remote-endpoint = <&stm_out>; 2213 }; 2214 }; 2215 }; 2216 }; 2217 2218 funnel@6042000 { 2219 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2220 reg = <0 0x06042000 0 0x1000>; 2221 2222 clocks = <&aoss_qmp>; 2223 clock-names = "apb_pclk"; 2224 2225 out-ports { 2226 port { 2227 funnel1_out: endpoint { 2228 remote-endpoint = <&merge_funnel_in1>; 2229 }; 2230 }; 2231 }; 2232 2233 in-ports { 2234 #address-cells = <1>; 2235 #size-cells = <0>; 2236 2237 port@4 { 2238 reg = <4>; 2239 funnel1_in4: endpoint { 2240 remote-endpoint = <&apss_merge_funnel_out>; 2241 }; 2242 }; 2243 }; 2244 }; 2245 2246 funnel@6045000 { 2247 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2248 reg = <0 0x06045000 0 0x1000>; 2249 2250 clocks = <&aoss_qmp>; 2251 clock-names = "apb_pclk"; 2252 2253 out-ports { 2254 port { 2255 merge_funnel_out: endpoint { 2256 remote-endpoint = <&swao_funnel_in>; 2257 }; 2258 }; 2259 }; 2260 2261 in-ports { 2262 #address-cells = <1>; 2263 #size-cells = <0>; 2264 2265 port@0 { 2266 reg = <0>; 2267 merge_funnel_in0: endpoint { 2268 remote-endpoint = <&funnel0_out>; 2269 }; 2270 }; 2271 2272 port@1 { 2273 reg = <1>; 2274 merge_funnel_in1: endpoint { 2275 remote-endpoint = <&funnel1_out>; 2276 }; 2277 }; 2278 }; 2279 }; 2280 2281 replicator@6046000 { 2282 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2283 reg = <0 0x06046000 0 0x1000>; 2284 2285 clocks = <&aoss_qmp>; 2286 clock-names = "apb_pclk"; 2287 2288 out-ports { 2289 port { 2290 replicator_out: endpoint { 2291 remote-endpoint = <&etr_in>; 2292 }; 2293 }; 2294 }; 2295 2296 in-ports { 2297 port { 2298 replicator_in: endpoint { 2299 remote-endpoint = <&swao_replicator_out>; 2300 }; 2301 }; 2302 }; 2303 }; 2304 2305 etr@6048000 { 2306 compatible = "arm,coresight-tmc", "arm,primecell"; 2307 reg = <0 0x06048000 0 0x1000>; 2308 iommus = <&apps_smmu 0x04c0 0>; 2309 2310 clocks = <&aoss_qmp>; 2311 clock-names = "apb_pclk"; 2312 arm,scatter-gather; 2313 2314 in-ports { 2315 port { 2316 etr_in: endpoint { 2317 remote-endpoint = <&replicator_out>; 2318 }; 2319 }; 2320 }; 2321 }; 2322 2323 funnel@6b04000 { 2324 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2325 reg = <0 0x06b04000 0 0x1000>; 2326 2327 clocks = <&aoss_qmp>; 2328 clock-names = "apb_pclk"; 2329 2330 out-ports { 2331 port { 2332 swao_funnel_out: endpoint { 2333 remote-endpoint = <&etf_in>; 2334 }; 2335 }; 2336 }; 2337 2338 in-ports { 2339 #address-cells = <1>; 2340 #size-cells = <0>; 2341 2342 port@7 { 2343 reg = <7>; 2344 swao_funnel_in: endpoint { 2345 remote-endpoint = <&merge_funnel_out>; 2346 }; 2347 }; 2348 }; 2349 }; 2350 2351 etf@6b05000 { 2352 compatible = "arm,coresight-tmc", "arm,primecell"; 2353 reg = <0 0x06b05000 0 0x1000>; 2354 2355 clocks = <&aoss_qmp>; 2356 clock-names = "apb_pclk"; 2357 2358 out-ports { 2359 port { 2360 etf_out: endpoint { 2361 remote-endpoint = <&swao_replicator_in>; 2362 }; 2363 }; 2364 }; 2365 2366 in-ports { 2367 port { 2368 etf_in: endpoint { 2369 remote-endpoint = <&swao_funnel_out>; 2370 }; 2371 }; 2372 }; 2373 }; 2374 2375 replicator@6b06000 { 2376 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2377 reg = <0 0x06b06000 0 0x1000>; 2378 2379 clocks = <&aoss_qmp>; 2380 clock-names = "apb_pclk"; 2381 qcom,replicator-loses-context; 2382 2383 out-ports { 2384 port { 2385 swao_replicator_out: endpoint { 2386 remote-endpoint = <&replicator_in>; 2387 }; 2388 }; 2389 }; 2390 2391 in-ports { 2392 port { 2393 swao_replicator_in: endpoint { 2394 remote-endpoint = <&etf_out>; 2395 }; 2396 }; 2397 }; 2398 }; 2399 2400 etm@7040000 { 2401 compatible = "arm,coresight-etm4x", "arm,primecell"; 2402 reg = <0 0x07040000 0 0x1000>; 2403 2404 cpu = <&CPU0>; 2405 2406 clocks = <&aoss_qmp>; 2407 clock-names = "apb_pclk"; 2408 arm,coresight-loses-context-with-cpu; 2409 qcom,skip-power-up; 2410 2411 out-ports { 2412 port { 2413 etm0_out: endpoint { 2414 remote-endpoint = <&apss_funnel_in0>; 2415 }; 2416 }; 2417 }; 2418 }; 2419 2420 etm@7140000 { 2421 compatible = "arm,coresight-etm4x", "arm,primecell"; 2422 reg = <0 0x07140000 0 0x1000>; 2423 2424 cpu = <&CPU1>; 2425 2426 clocks = <&aoss_qmp>; 2427 clock-names = "apb_pclk"; 2428 arm,coresight-loses-context-with-cpu; 2429 qcom,skip-power-up; 2430 2431 out-ports { 2432 port { 2433 etm1_out: endpoint { 2434 remote-endpoint = <&apss_funnel_in1>; 2435 }; 2436 }; 2437 }; 2438 }; 2439 2440 etm@7240000 { 2441 compatible = "arm,coresight-etm4x", "arm,primecell"; 2442 reg = <0 0x07240000 0 0x1000>; 2443 2444 cpu = <&CPU2>; 2445 2446 clocks = <&aoss_qmp>; 2447 clock-names = "apb_pclk"; 2448 arm,coresight-loses-context-with-cpu; 2449 qcom,skip-power-up; 2450 2451 out-ports { 2452 port { 2453 etm2_out: endpoint { 2454 remote-endpoint = <&apss_funnel_in2>; 2455 }; 2456 }; 2457 }; 2458 }; 2459 2460 etm@7340000 { 2461 compatible = "arm,coresight-etm4x", "arm,primecell"; 2462 reg = <0 0x07340000 0 0x1000>; 2463 2464 cpu = <&CPU3>; 2465 2466 clocks = <&aoss_qmp>; 2467 clock-names = "apb_pclk"; 2468 arm,coresight-loses-context-with-cpu; 2469 qcom,skip-power-up; 2470 2471 out-ports { 2472 port { 2473 etm3_out: endpoint { 2474 remote-endpoint = <&apss_funnel_in3>; 2475 }; 2476 }; 2477 }; 2478 }; 2479 2480 etm@7440000 { 2481 compatible = "arm,coresight-etm4x", "arm,primecell"; 2482 reg = <0 0x07440000 0 0x1000>; 2483 2484 cpu = <&CPU4>; 2485 2486 clocks = <&aoss_qmp>; 2487 clock-names = "apb_pclk"; 2488 arm,coresight-loses-context-with-cpu; 2489 qcom,skip-power-up; 2490 2491 out-ports { 2492 port { 2493 etm4_out: endpoint { 2494 remote-endpoint = <&apss_funnel_in4>; 2495 }; 2496 }; 2497 }; 2498 }; 2499 2500 etm@7540000 { 2501 compatible = "arm,coresight-etm4x", "arm,primecell"; 2502 reg = <0 0x07540000 0 0x1000>; 2503 2504 cpu = <&CPU5>; 2505 2506 clocks = <&aoss_qmp>; 2507 clock-names = "apb_pclk"; 2508 arm,coresight-loses-context-with-cpu; 2509 qcom,skip-power-up; 2510 2511 out-ports { 2512 port { 2513 etm5_out: endpoint { 2514 remote-endpoint = <&apss_funnel_in5>; 2515 }; 2516 }; 2517 }; 2518 }; 2519 2520 etm@7640000 { 2521 compatible = "arm,coresight-etm4x", "arm,primecell"; 2522 reg = <0 0x07640000 0 0x1000>; 2523 2524 cpu = <&CPU6>; 2525 2526 clocks = <&aoss_qmp>; 2527 clock-names = "apb_pclk"; 2528 arm,coresight-loses-context-with-cpu; 2529 qcom,skip-power-up; 2530 2531 out-ports { 2532 port { 2533 etm6_out: endpoint { 2534 remote-endpoint = <&apss_funnel_in6>; 2535 }; 2536 }; 2537 }; 2538 }; 2539 2540 etm@7740000 { 2541 compatible = "arm,coresight-etm4x", "arm,primecell"; 2542 reg = <0 0x07740000 0 0x1000>; 2543 2544 cpu = <&CPU7>; 2545 2546 clocks = <&aoss_qmp>; 2547 clock-names = "apb_pclk"; 2548 arm,coresight-loses-context-with-cpu; 2549 qcom,skip-power-up; 2550 2551 out-ports { 2552 port { 2553 etm7_out: endpoint { 2554 remote-endpoint = <&apss_funnel_in7>; 2555 }; 2556 }; 2557 }; 2558 }; 2559 2560 funnel@7800000 { /* APSS Funnel */ 2561 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2562 reg = <0 0x07800000 0 0x1000>; 2563 2564 clocks = <&aoss_qmp>; 2565 clock-names = "apb_pclk"; 2566 2567 out-ports { 2568 port { 2569 apss_funnel_out: endpoint { 2570 remote-endpoint = <&apss_merge_funnel_in>; 2571 }; 2572 }; 2573 }; 2574 2575 in-ports { 2576 #address-cells = <1>; 2577 #size-cells = <0>; 2578 2579 port@0 { 2580 reg = <0>; 2581 apss_funnel_in0: endpoint { 2582 remote-endpoint = <&etm0_out>; 2583 }; 2584 }; 2585 2586 port@1 { 2587 reg = <1>; 2588 apss_funnel_in1: endpoint { 2589 remote-endpoint = <&etm1_out>; 2590 }; 2591 }; 2592 2593 port@2 { 2594 reg = <2>; 2595 apss_funnel_in2: endpoint { 2596 remote-endpoint = <&etm2_out>; 2597 }; 2598 }; 2599 2600 port@3 { 2601 reg = <3>; 2602 apss_funnel_in3: endpoint { 2603 remote-endpoint = <&etm3_out>; 2604 }; 2605 }; 2606 2607 port@4 { 2608 reg = <4>; 2609 apss_funnel_in4: endpoint { 2610 remote-endpoint = <&etm4_out>; 2611 }; 2612 }; 2613 2614 port@5 { 2615 reg = <5>; 2616 apss_funnel_in5: endpoint { 2617 remote-endpoint = <&etm5_out>; 2618 }; 2619 }; 2620 2621 port@6 { 2622 reg = <6>; 2623 apss_funnel_in6: endpoint { 2624 remote-endpoint = <&etm6_out>; 2625 }; 2626 }; 2627 2628 port@7 { 2629 reg = <7>; 2630 apss_funnel_in7: endpoint { 2631 remote-endpoint = <&etm7_out>; 2632 }; 2633 }; 2634 }; 2635 }; 2636 2637 funnel@7810000 { 2638 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2639 reg = <0 0x07810000 0 0x1000>; 2640 2641 clocks = <&aoss_qmp>; 2642 clock-names = "apb_pclk"; 2643 2644 out-ports { 2645 port { 2646 apss_merge_funnel_out: endpoint { 2647 remote-endpoint = <&funnel1_in4>; 2648 }; 2649 }; 2650 }; 2651 2652 in-ports { 2653 port { 2654 apss_merge_funnel_in: endpoint { 2655 remote-endpoint = <&apss_funnel_out>; 2656 }; 2657 }; 2658 }; 2659 }; 2660 2661 sdhc_2: sdhci@8804000 { 2662 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 2663 pinctrl-names = "default", "sleep"; 2664 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 2665 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 2666 status = "disabled"; 2667 2668 reg = <0 0x08804000 0 0x1000>; 2669 2670 iommus = <&apps_smmu 0x100 0x0>; 2671 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2672 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2673 interrupt-names = "hc_irq", "pwr_irq"; 2674 2675 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2676 <&gcc GCC_SDCC2_AHB_CLK>, 2677 <&rpmhcc RPMH_CXO_CLK>; 2678 clock-names = "core", "iface", "xo"; 2679 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2680 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 2681 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2682 power-domains = <&rpmhpd SC7280_CX>; 2683 operating-points-v2 = <&sdhc2_opp_table>; 2684 2685 bus-width = <4>; 2686 2687 qcom,dll-config = <0x0007642c>; 2688 2689 sdhc2_opp_table: opp-table { 2690 compatible = "operating-points-v2"; 2691 2692 opp-100000000 { 2693 opp-hz = /bits/ 64 <100000000>; 2694 required-opps = <&rpmhpd_opp_low_svs>; 2695 opp-peak-kBps = <1800000 400000>; 2696 opp-avg-kBps = <100000 0>; 2697 }; 2698 2699 opp-202000000 { 2700 opp-hz = /bits/ 64 <202000000>; 2701 required-opps = <&rpmhpd_opp_nom>; 2702 opp-peak-kBps = <5400000 1600000>; 2703 opp-avg-kBps = <200000 0>; 2704 }; 2705 }; 2706 2707 }; 2708 2709 usb_1_hsphy: phy@88e3000 { 2710 compatible = "qcom,sc7280-usb-hs-phy", 2711 "qcom,usb-snps-hs-7nm-phy"; 2712 reg = <0 0x088e3000 0 0x400>; 2713 status = "disabled"; 2714 #phy-cells = <0>; 2715 2716 clocks = <&rpmhcc RPMH_CXO_CLK>; 2717 clock-names = "ref"; 2718 2719 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2720 }; 2721 2722 usb_2_hsphy: phy@88e4000 { 2723 compatible = "qcom,sc7280-usb-hs-phy", 2724 "qcom,usb-snps-hs-7nm-phy"; 2725 reg = <0 0x088e4000 0 0x400>; 2726 status = "disabled"; 2727 #phy-cells = <0>; 2728 2729 clocks = <&rpmhcc RPMH_CXO_CLK>; 2730 clock-names = "ref"; 2731 2732 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2733 }; 2734 2735 usb_1_qmpphy: phy-wrapper@88e9000 { 2736 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 2737 "qcom,sm8250-qmp-usb3-dp-phy"; 2738 reg = <0 0x088e9000 0 0x200>, 2739 <0 0x088e8000 0 0x40>, 2740 <0 0x088ea000 0 0x200>; 2741 status = "disabled"; 2742 #address-cells = <2>; 2743 #size-cells = <2>; 2744 ranges; 2745 2746 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2747 <&rpmhcc RPMH_CXO_CLK>, 2748 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2749 clock-names = "aux", "ref_clk_src", "com_aux"; 2750 2751 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2752 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2753 reset-names = "phy", "common"; 2754 2755 usb_1_ssphy: usb3-phy@88e9200 { 2756 reg = <0 0x088e9200 0 0x200>, 2757 <0 0x088e9400 0 0x200>, 2758 <0 0x088e9c00 0 0x400>, 2759 <0 0x088e9600 0 0x200>, 2760 <0 0x088e9800 0 0x200>, 2761 <0 0x088e9a00 0 0x100>; 2762 #clock-cells = <0>; 2763 #phy-cells = <0>; 2764 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2765 clock-names = "pipe0"; 2766 clock-output-names = "usb3_phy_pipe_clk_src"; 2767 }; 2768 2769 dp_phy: dp-phy@88ea200 { 2770 reg = <0 0x088ea200 0 0x200>, 2771 <0 0x088ea400 0 0x200>, 2772 <0 0x088eaa00 0 0x200>, 2773 <0 0x088ea600 0 0x200>, 2774 <0 0x088ea800 0 0x200>; 2775 #phy-cells = <0>; 2776 #clock-cells = <1>; 2777 }; 2778 }; 2779 2780 usb_2: usb@8cf8800 { 2781 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2782 reg = <0 0x08cf8800 0 0x400>; 2783 status = "disabled"; 2784 #address-cells = <2>; 2785 #size-cells = <2>; 2786 ranges; 2787 dma-ranges; 2788 2789 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2790 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2791 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2792 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2793 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 2794 clock-names = "cfg_noc", 2795 "core", 2796 "iface", 2797 "sleep", 2798 "mock_utmi"; 2799 2800 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2801 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2802 assigned-clock-rates = <19200000>, <200000000>; 2803 2804 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2805 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 2806 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 2807 interrupt-names = "hs_phy_irq", 2808 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2809 2810 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 2811 2812 resets = <&gcc GCC_USB30_SEC_BCR>; 2813 2814 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 2815 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 2816 interconnect-names = "usb-ddr", "apps-usb"; 2817 2818 usb_2_dwc3: usb@8c00000 { 2819 compatible = "snps,dwc3"; 2820 reg = <0 0x08c00000 0 0xe000>; 2821 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2822 iommus = <&apps_smmu 0xa0 0x0>; 2823 snps,dis_u2_susphy_quirk; 2824 snps,dis_enblslpm_quirk; 2825 phys = <&usb_2_hsphy>; 2826 phy-names = "usb2-phy"; 2827 maximum-speed = "high-speed"; 2828 usb-role-switch; 2829 port { 2830 usb2_role_switch: endpoint { 2831 remote-endpoint = <&eud_ep>; 2832 }; 2833 }; 2834 }; 2835 }; 2836 2837 qspi: spi@88dc000 { 2838 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 2839 reg = <0 0x088dc000 0 0x1000>; 2840 #address-cells = <1>; 2841 #size-cells = <0>; 2842 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2843 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2844 <&gcc GCC_QSPI_CORE_CLK>; 2845 clock-names = "iface", "core"; 2846 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2847 &cnoc2 SLAVE_QSPI_0 0>; 2848 interconnect-names = "qspi-config"; 2849 power-domains = <&rpmhpd SC7280_CX>; 2850 operating-points-v2 = <&qspi_opp_table>; 2851 status = "disabled"; 2852 }; 2853 2854 dc_noc: interconnect@90e0000 { 2855 reg = <0 0x090e0000 0 0x5080>; 2856 compatible = "qcom,sc7280-dc-noc"; 2857 #interconnect-cells = <2>; 2858 qcom,bcm-voters = <&apps_bcm_voter>; 2859 }; 2860 2861 gem_noc: interconnect@9100000 { 2862 reg = <0 0x9100000 0 0xe2200>; 2863 compatible = "qcom,sc7280-gem-noc"; 2864 #interconnect-cells = <2>; 2865 qcom,bcm-voters = <&apps_bcm_voter>; 2866 }; 2867 2868 system-cache-controller@9200000 { 2869 compatible = "qcom,sc7280-llcc"; 2870 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 2871 reg-names = "llcc_base", "llcc_broadcast_base"; 2872 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2873 }; 2874 2875 eud: eud@88e0000 { 2876 compatible = "qcom,sc7280-eud","qcom,eud"; 2877 reg = <0 0x88e0000 0 0x2000>, 2878 <0 0x88e2000 0 0x1000>; 2879 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 2880 ports { 2881 port@0 { 2882 eud_ep: endpoint { 2883 remote-endpoint = <&usb2_role_switch>; 2884 }; 2885 }; 2886 port@1 { 2887 eud_con: endpoint { 2888 remote-endpoint = <&con_eud>; 2889 }; 2890 }; 2891 }; 2892 }; 2893 2894 eud_typec: connector { 2895 compatible = "usb-c-connector"; 2896 ports { 2897 port@0 { 2898 con_eud: endpoint { 2899 remote-endpoint = <&eud_con>; 2900 }; 2901 }; 2902 }; 2903 }; 2904 2905 nsp_noc: interconnect@a0c0000 { 2906 reg = <0 0x0a0c0000 0 0x10000>; 2907 compatible = "qcom,sc7280-nsp-noc"; 2908 #interconnect-cells = <2>; 2909 qcom,bcm-voters = <&apps_bcm_voter>; 2910 }; 2911 2912 usb_1: usb@a6f8800 { 2913 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2914 reg = <0 0x0a6f8800 0 0x400>; 2915 status = "disabled"; 2916 #address-cells = <2>; 2917 #size-cells = <2>; 2918 ranges; 2919 dma-ranges; 2920 2921 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2922 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2923 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2924 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2925 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2926 clock-names = "cfg_noc", 2927 "core", 2928 "iface", 2929 "sleep", 2930 "mock_utmi"; 2931 2932 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2933 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2934 assigned-clock-rates = <19200000>, <200000000>; 2935 2936 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2937 <&pdc 17 IRQ_TYPE_EDGE_BOTH>, 2938 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2939 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>; 2940 interrupt-names = "hs_phy_irq", 2941 "ss_phy_irq", 2942 "dm_hs_phy_irq", 2943 "dp_hs_phy_irq"; 2944 2945 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 2946 2947 resets = <&gcc GCC_USB30_PRIM_BCR>; 2948 2949 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2950 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 2951 interconnect-names = "usb-ddr", "apps-usb"; 2952 2953 usb_1_dwc3: usb@a600000 { 2954 compatible = "snps,dwc3"; 2955 reg = <0 0x0a600000 0 0xe000>; 2956 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2957 iommus = <&apps_smmu 0xe0 0x0>; 2958 snps,dis_u2_susphy_quirk; 2959 snps,dis_enblslpm_quirk; 2960 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2961 phy-names = "usb2-phy", "usb3-phy"; 2962 maximum-speed = "super-speed"; 2963 }; 2964 }; 2965 2966 venus: video-codec@aa00000 { 2967 compatible = "qcom,sc7280-venus"; 2968 reg = <0 0x0aa00000 0 0xd0600>; 2969 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2970 2971 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 2972 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 2973 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2974 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 2975 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 2976 clock-names = "core", "bus", "iface", 2977 "vcodec_core", "vcodec_bus"; 2978 2979 power-domains = <&videocc MVSC_GDSC>, 2980 <&videocc MVS0_GDSC>, 2981 <&rpmhpd SC7280_CX>; 2982 power-domain-names = "venus", "vcodec0", "cx"; 2983 operating-points-v2 = <&venus_opp_table>; 2984 2985 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 2986 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 2987 interconnect-names = "cpu-cfg", "video-mem"; 2988 2989 iommus = <&apps_smmu 0x2180 0x20>, 2990 <&apps_smmu 0x2184 0x20>; 2991 memory-region = <&video_mem>; 2992 2993 video-decoder { 2994 compatible = "venus-decoder"; 2995 }; 2996 2997 video-encoder { 2998 compatible = "venus-encoder"; 2999 }; 3000 3001 video-firmware { 3002 iommus = <&apps_smmu 0x21a2 0x0>; 3003 }; 3004 3005 venus_opp_table: venus-opp-table { 3006 compatible = "operating-points-v2"; 3007 3008 opp-133330000 { 3009 opp-hz = /bits/ 64 <133330000>; 3010 required-opps = <&rpmhpd_opp_low_svs>; 3011 }; 3012 3013 opp-240000000 { 3014 opp-hz = /bits/ 64 <240000000>; 3015 required-opps = <&rpmhpd_opp_svs>; 3016 }; 3017 3018 opp-335000000 { 3019 opp-hz = /bits/ 64 <335000000>; 3020 required-opps = <&rpmhpd_opp_svs_l1>; 3021 }; 3022 3023 opp-424000000 { 3024 opp-hz = /bits/ 64 <424000000>; 3025 required-opps = <&rpmhpd_opp_nom>; 3026 }; 3027 3028 opp-460000048 { 3029 opp-hz = /bits/ 64 <460000048>; 3030 required-opps = <&rpmhpd_opp_turbo>; 3031 }; 3032 }; 3033 3034 }; 3035 3036 videocc: clock-controller@aaf0000 { 3037 compatible = "qcom,sc7280-videocc"; 3038 reg = <0 0xaaf0000 0 0x10000>; 3039 clocks = <&rpmhcc RPMH_CXO_CLK>, 3040 <&rpmhcc RPMH_CXO_CLK_A>; 3041 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3042 #clock-cells = <1>; 3043 #reset-cells = <1>; 3044 #power-domain-cells = <1>; 3045 }; 3046 3047 camcc: clock-controller@ad00000 { 3048 compatible = "qcom,sc7280-camcc"; 3049 reg = <0 0x0ad00000 0 0x10000>; 3050 clocks = <&rpmhcc RPMH_CXO_CLK>, 3051 <&rpmhcc RPMH_CXO_CLK_A>, 3052 <&sleep_clk>; 3053 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3054 #clock-cells = <1>; 3055 #reset-cells = <1>; 3056 #power-domain-cells = <1>; 3057 }; 3058 3059 dispcc: clock-controller@af00000 { 3060 compatible = "qcom,sc7280-dispcc"; 3061 reg = <0 0xaf00000 0 0x20000>; 3062 clocks = <&rpmhcc RPMH_CXO_CLK>, 3063 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3064 <&mdss_dsi_phy 0>, 3065 <&mdss_dsi_phy 1>, 3066 <&dp_phy 0>, 3067 <&dp_phy 1>, 3068 <&mdss_edp_phy 0>, 3069 <&mdss_edp_phy 1>; 3070 clock-names = "bi_tcxo", 3071 "gcc_disp_gpll0_clk", 3072 "dsi0_phy_pll_out_byteclk", 3073 "dsi0_phy_pll_out_dsiclk", 3074 "dp_phy_pll_link_clk", 3075 "dp_phy_pll_vco_div_clk", 3076 "edp_phy_pll_link_clk", 3077 "edp_phy_pll_vco_div_clk"; 3078 #clock-cells = <1>; 3079 #reset-cells = <1>; 3080 #power-domain-cells = <1>; 3081 }; 3082 3083 mdss: display-subsystem@ae00000 { 3084 compatible = "qcom,sc7280-mdss"; 3085 reg = <0 0x0ae00000 0 0x1000>; 3086 reg-names = "mdss"; 3087 3088 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3089 3090 clocks = <&gcc GCC_DISP_AHB_CLK>, 3091 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3092 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3093 clock-names = "iface", 3094 "ahb", 3095 "core"; 3096 3097 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 3098 assigned-clock-rates = <300000000>; 3099 3100 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3101 interrupt-controller; 3102 #interrupt-cells = <1>; 3103 3104 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3105 interconnect-names = "mdp0-mem"; 3106 3107 iommus = <&apps_smmu 0x900 0x402>; 3108 3109 #address-cells = <2>; 3110 #size-cells = <2>; 3111 ranges; 3112 3113 status = "disabled"; 3114 3115 mdss_mdp: display-controller@ae01000 { 3116 compatible = "qcom,sc7280-dpu"; 3117 reg = <0 0x0ae01000 0 0x8f030>, 3118 <0 0x0aeb0000 0 0x2008>; 3119 reg-names = "mdp", "vbif"; 3120 3121 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3122 <&gcc GCC_DISP_SF_AXI_CLK>, 3123 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3124 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3125 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3126 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3127 clock-names = "bus", 3128 "nrt_bus", 3129 "iface", 3130 "lut", 3131 "core", 3132 "vsync"; 3133 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 3134 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3135 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3136 assigned-clock-rates = <300000000>, 3137 <19200000>, 3138 <19200000>; 3139 operating-points-v2 = <&mdp_opp_table>; 3140 power-domains = <&rpmhpd SC7280_CX>; 3141 3142 interrupt-parent = <&mdss>; 3143 interrupts = <0>; 3144 3145 status = "disabled"; 3146 3147 ports { 3148 #address-cells = <1>; 3149 #size-cells = <0>; 3150 3151 port@0 { 3152 reg = <0>; 3153 dpu_intf1_out: endpoint { 3154 remote-endpoint = <&dsi0_in>; 3155 }; 3156 }; 3157 3158 port@1 { 3159 reg = <1>; 3160 dpu_intf5_out: endpoint { 3161 remote-endpoint = <&edp_in>; 3162 }; 3163 }; 3164 3165 port@2 { 3166 reg = <2>; 3167 dpu_intf0_out: endpoint { 3168 remote-endpoint = <&dp_in>; 3169 }; 3170 }; 3171 }; 3172 3173 mdp_opp_table: opp-table { 3174 compatible = "operating-points-v2"; 3175 3176 opp-200000000 { 3177 opp-hz = /bits/ 64 <200000000>; 3178 required-opps = <&rpmhpd_opp_low_svs>; 3179 }; 3180 3181 opp-300000000 { 3182 opp-hz = /bits/ 64 <300000000>; 3183 required-opps = <&rpmhpd_opp_svs>; 3184 }; 3185 3186 opp-380000000 { 3187 opp-hz = /bits/ 64 <380000000>; 3188 required-opps = <&rpmhpd_opp_svs_l1>; 3189 }; 3190 3191 opp-506666667 { 3192 opp-hz = /bits/ 64 <506666667>; 3193 required-opps = <&rpmhpd_opp_nom>; 3194 }; 3195 }; 3196 }; 3197 3198 mdss_dsi: dsi@ae94000 { 3199 compatible = "qcom,mdss-dsi-ctrl"; 3200 reg = <0 0x0ae94000 0 0x400>; 3201 reg-names = "dsi_ctrl"; 3202 3203 interrupt-parent = <&mdss>; 3204 interrupts = <4>; 3205 3206 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3207 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3208 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3209 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3210 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3211 <&gcc GCC_DISP_HF_AXI_CLK>; 3212 clock-names = "byte", 3213 "byte_intf", 3214 "pixel", 3215 "core", 3216 "iface", 3217 "bus"; 3218 3219 operating-points-v2 = <&dsi_opp_table>; 3220 power-domains = <&rpmhpd SC7280_CX>; 3221 3222 phys = <&mdss_dsi_phy>; 3223 phy-names = "dsi"; 3224 3225 #address-cells = <1>; 3226 #size-cells = <0>; 3227 3228 status = "disabled"; 3229 3230 ports { 3231 #address-cells = <1>; 3232 #size-cells = <0>; 3233 3234 port@0 { 3235 reg = <0>; 3236 dsi0_in: endpoint { 3237 remote-endpoint = <&dpu_intf1_out>; 3238 }; 3239 }; 3240 3241 port@1 { 3242 reg = <1>; 3243 dsi0_out: endpoint { 3244 }; 3245 }; 3246 }; 3247 3248 dsi_opp_table: opp-table { 3249 compatible = "operating-points-v2"; 3250 3251 opp-187500000 { 3252 opp-hz = /bits/ 64 <187500000>; 3253 required-opps = <&rpmhpd_opp_low_svs>; 3254 }; 3255 3256 opp-300000000 { 3257 opp-hz = /bits/ 64 <300000000>; 3258 required-opps = <&rpmhpd_opp_svs>; 3259 }; 3260 3261 opp-358000000 { 3262 opp-hz = /bits/ 64 <358000000>; 3263 required-opps = <&rpmhpd_opp_svs_l1>; 3264 }; 3265 }; 3266 }; 3267 3268 mdss_dsi_phy: phy@ae94400 { 3269 compatible = "qcom,sc7280-dsi-phy-7nm"; 3270 reg = <0 0x0ae94400 0 0x200>, 3271 <0 0x0ae94600 0 0x280>, 3272 <0 0x0ae94900 0 0x280>; 3273 reg-names = "dsi_phy", 3274 "dsi_phy_lane", 3275 "dsi_pll"; 3276 3277 #clock-cells = <1>; 3278 #phy-cells = <0>; 3279 3280 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3281 <&rpmhcc RPMH_CXO_CLK>; 3282 clock-names = "iface", "ref"; 3283 3284 status = "disabled"; 3285 }; 3286 3287 mdss_edp: edp@aea0000 { 3288 compatible = "qcom,sc7280-edp"; 3289 pinctrl-names = "default"; 3290 pinctrl-0 = <&edp_hot_plug_det>; 3291 3292 reg = <0 0xaea0000 0 0x200>, 3293 <0 0xaea0200 0 0x200>, 3294 <0 0xaea0400 0 0xc00>, 3295 <0 0xaea1000 0 0x400>; 3296 3297 interrupt-parent = <&mdss>; 3298 interrupts = <14>; 3299 3300 clocks = <&rpmhcc RPMH_CXO_CLK>, 3301 <&gcc GCC_EDP_CLKREF_EN>, 3302 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3303 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3304 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 3305 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 3306 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 3307 clock-names = "core_xo", 3308 "core_ref", 3309 "core_iface", 3310 "core_aux", 3311 "ctrl_link", 3312 "ctrl_link_iface", 3313 "stream_pixel"; 3314 #clock-cells = <1>; 3315 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 3316 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 3317 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 3318 3319 phys = <&mdss_edp_phy>; 3320 phy-names = "dp"; 3321 3322 operating-points-v2 = <&edp_opp_table>; 3323 power-domains = <&rpmhpd SC7280_CX>; 3324 3325 #address-cells = <1>; 3326 #size-cells = <0>; 3327 3328 status = "disabled"; 3329 3330 ports { 3331 #address-cells = <1>; 3332 #size-cells = <0>; 3333 3334 port@0 { 3335 reg = <0>; 3336 edp_in: endpoint { 3337 remote-endpoint = <&dpu_intf5_out>; 3338 }; 3339 }; 3340 3341 port@1 { 3342 reg = <1>; 3343 edp_out: endpoint { }; 3344 }; 3345 }; 3346 3347 edp_opp_table: opp-table { 3348 compatible = "operating-points-v2"; 3349 3350 opp-160000000 { 3351 opp-hz = /bits/ 64 <160000000>; 3352 required-opps = <&rpmhpd_opp_low_svs>; 3353 }; 3354 3355 opp-270000000 { 3356 opp-hz = /bits/ 64 <270000000>; 3357 required-opps = <&rpmhpd_opp_svs>; 3358 }; 3359 3360 opp-540000000 { 3361 opp-hz = /bits/ 64 <540000000>; 3362 required-opps = <&rpmhpd_opp_nom>; 3363 }; 3364 3365 opp-810000000 { 3366 opp-hz = /bits/ 64 <810000000>; 3367 required-opps = <&rpmhpd_opp_nom>; 3368 }; 3369 }; 3370 }; 3371 3372 mdss_edp_phy: phy@aec2a00 { 3373 compatible = "qcom,sc7280-edp-phy"; 3374 3375 reg = <0 0xaec2a00 0 0x19c>, 3376 <0 0xaec2200 0 0xa0>, 3377 <0 0xaec2600 0 0xa0>, 3378 <0 0xaec2000 0 0x1c0>; 3379 3380 clocks = <&rpmhcc RPMH_CXO_CLK>, 3381 <&gcc GCC_EDP_CLKREF_EN>; 3382 clock-names = "aux", 3383 "cfg_ahb"; 3384 3385 #clock-cells = <1>; 3386 #phy-cells = <0>; 3387 3388 status = "disabled"; 3389 }; 3390 3391 mdss_dp: displayport-controller@ae90000 { 3392 compatible = "qcom,sc7280-dp"; 3393 3394 reg = <0 0x0ae90000 0 0x1400>; 3395 3396 interrupt-parent = <&mdss>; 3397 interrupts = <12>; 3398 3399 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3400 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3401 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3402 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3403 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3404 clock-names = "core_iface", 3405 "core_aux", 3406 "ctrl_link", 3407 "ctrl_link_iface", 3408 "stream_pixel"; 3409 #clock-cells = <1>; 3410 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3411 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3412 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 3413 phys = <&dp_phy>; 3414 phy-names = "dp"; 3415 3416 operating-points-v2 = <&dp_opp_table>; 3417 power-domains = <&rpmhpd SC7280_CX>; 3418 3419 #sound-dai-cells = <0>; 3420 3421 status = "disabled"; 3422 3423 ports { 3424 #address-cells = <1>; 3425 #size-cells = <0>; 3426 3427 port@0 { 3428 reg = <0>; 3429 dp_in: endpoint { 3430 remote-endpoint = <&dpu_intf0_out>; 3431 }; 3432 }; 3433 3434 port@1 { 3435 reg = <1>; 3436 dp_out: endpoint { }; 3437 }; 3438 }; 3439 3440 dp_opp_table: opp-table { 3441 compatible = "operating-points-v2"; 3442 3443 opp-160000000 { 3444 opp-hz = /bits/ 64 <160000000>; 3445 required-opps = <&rpmhpd_opp_low_svs>; 3446 }; 3447 3448 opp-270000000 { 3449 opp-hz = /bits/ 64 <270000000>; 3450 required-opps = <&rpmhpd_opp_svs>; 3451 }; 3452 3453 opp-540000000 { 3454 opp-hz = /bits/ 64 <540000000>; 3455 required-opps = <&rpmhpd_opp_svs_l1>; 3456 }; 3457 3458 opp-810000000 { 3459 opp-hz = /bits/ 64 <810000000>; 3460 required-opps = <&rpmhpd_opp_nom>; 3461 }; 3462 }; 3463 }; 3464 }; 3465 3466 pdc: interrupt-controller@b220000 { 3467 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 3468 reg = <0 0x0b220000 0 0x30000>; 3469 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 3470 <55 306 4>, <59 312 3>, <62 374 2>, 3471 <64 434 2>, <66 438 3>, <69 86 1>, 3472 <70 520 54>, <124 609 31>, <155 63 1>, 3473 <156 716 12>; 3474 #interrupt-cells = <2>; 3475 interrupt-parent = <&intc>; 3476 interrupt-controller; 3477 }; 3478 3479 pdc_reset: reset-controller@b5e0000 { 3480 compatible = "qcom,sc7280-pdc-global"; 3481 reg = <0 0x0b5e0000 0 0x20000>; 3482 #reset-cells = <1>; 3483 }; 3484 3485 tsens0: thermal-sensor@c263000 { 3486 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3487 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3488 <0 0x0c222000 0 0x1ff>; /* SROT */ 3489 #qcom,sensors = <15>; 3490 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3491 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3492 interrupt-names = "uplow","critical"; 3493 #thermal-sensor-cells = <1>; 3494 }; 3495 3496 tsens1: thermal-sensor@c265000 { 3497 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3498 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3499 <0 0x0c223000 0 0x1ff>; /* SROT */ 3500 #qcom,sensors = <12>; 3501 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3502 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3503 interrupt-names = "uplow","critical"; 3504 #thermal-sensor-cells = <1>; 3505 }; 3506 3507 aoss_reset: reset-controller@c2a0000 { 3508 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 3509 reg = <0 0x0c2a0000 0 0x31000>; 3510 #reset-cells = <1>; 3511 }; 3512 3513 aoss_qmp: power-controller@c300000 { 3514 compatible = "qcom,sc7280-aoss-qmp"; 3515 reg = <0 0x0c300000 0 0x400>; 3516 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3517 IPCC_MPROC_SIGNAL_GLINK_QMP 3518 IRQ_TYPE_EDGE_RISING>; 3519 mboxes = <&ipcc IPCC_CLIENT_AOP 3520 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3521 3522 #clock-cells = <0>; 3523 }; 3524 3525 sram@c3f0000 { 3526 compatible = "qcom,rpmh-stats"; 3527 reg = <0 0x0c3f0000 0 0x400>; 3528 }; 3529 3530 spmi_bus: spmi@c440000 { 3531 compatible = "qcom,spmi-pmic-arb"; 3532 reg = <0 0x0c440000 0 0x1100>, 3533 <0 0x0c600000 0 0x2000000>, 3534 <0 0x0e600000 0 0x100000>, 3535 <0 0x0e700000 0 0xa0000>, 3536 <0 0x0c40a000 0 0x26000>; 3537 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3538 interrupt-names = "periph_irq"; 3539 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3540 qcom,ee = <0>; 3541 qcom,channel = <0>; 3542 #address-cells = <1>; 3543 #size-cells = <1>; 3544 interrupt-controller; 3545 #interrupt-cells = <4>; 3546 }; 3547 3548 tlmm: pinctrl@f100000 { 3549 compatible = "qcom,sc7280-pinctrl"; 3550 reg = <0 0x0f100000 0 0x300000>; 3551 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3552 gpio-controller; 3553 #gpio-cells = <2>; 3554 interrupt-controller; 3555 #interrupt-cells = <2>; 3556 gpio-ranges = <&tlmm 0 0 175>; 3557 wakeup-parent = <&pdc>; 3558 3559 dp_hot_plug_det: dp-hot-plug-det { 3560 pins = "gpio47"; 3561 function = "dp_hot"; 3562 }; 3563 3564 edp_hot_plug_det: edp-hot-plug-det { 3565 pins = "gpio60"; 3566 function = "edp_hot"; 3567 }; 3568 3569 pcie1_clkreq_n: pcie1-clkreq-n { 3570 pins = "gpio79"; 3571 function = "pcie1_clkreqn"; 3572 }; 3573 3574 qspi_clk: qspi-clk { 3575 pins = "gpio14"; 3576 function = "qspi_clk"; 3577 }; 3578 3579 qspi_cs0: qspi-cs0 { 3580 pins = "gpio15"; 3581 function = "qspi_cs"; 3582 }; 3583 3584 qspi_cs1: qspi-cs1 { 3585 pins = "gpio19"; 3586 function = "qspi_cs"; 3587 }; 3588 3589 qspi_data01: qspi-data01 { 3590 pins = "gpio12", "gpio13"; 3591 function = "qspi_data"; 3592 }; 3593 3594 qspi_data12: qspi-data12 { 3595 pins = "gpio16", "gpio17"; 3596 function = "qspi_data"; 3597 }; 3598 3599 qup_i2c0_data_clk: qup-i2c0-data-clk { 3600 pins = "gpio0", "gpio1"; 3601 function = "qup00"; 3602 }; 3603 3604 qup_i2c1_data_clk: qup-i2c1-data-clk { 3605 pins = "gpio4", "gpio5"; 3606 function = "qup01"; 3607 }; 3608 3609 qup_i2c2_data_clk: qup-i2c2-data-clk { 3610 pins = "gpio8", "gpio9"; 3611 function = "qup02"; 3612 }; 3613 3614 qup_i2c3_data_clk: qup-i2c3-data-clk { 3615 pins = "gpio12", "gpio13"; 3616 function = "qup03"; 3617 }; 3618 3619 qup_i2c4_data_clk: qup-i2c4-data-clk { 3620 pins = "gpio16", "gpio17"; 3621 function = "qup04"; 3622 }; 3623 3624 qup_i2c5_data_clk: qup-i2c5-data-clk { 3625 pins = "gpio20", "gpio21"; 3626 function = "qup05"; 3627 }; 3628 3629 qup_i2c6_data_clk: qup-i2c6-data-clk { 3630 pins = "gpio24", "gpio25"; 3631 function = "qup06"; 3632 }; 3633 3634 qup_i2c7_data_clk: qup-i2c7-data-clk { 3635 pins = "gpio28", "gpio29"; 3636 function = "qup07"; 3637 }; 3638 3639 qup_i2c8_data_clk: qup-i2c8-data-clk { 3640 pins = "gpio32", "gpio33"; 3641 function = "qup10"; 3642 }; 3643 3644 qup_i2c9_data_clk: qup-i2c9-data-clk { 3645 pins = "gpio36", "gpio37"; 3646 function = "qup11"; 3647 }; 3648 3649 qup_i2c10_data_clk: qup-i2c10-data-clk { 3650 pins = "gpio40", "gpio41"; 3651 function = "qup12"; 3652 }; 3653 3654 qup_i2c11_data_clk: qup-i2c11-data-clk { 3655 pins = "gpio44", "gpio45"; 3656 function = "qup13"; 3657 }; 3658 3659 qup_i2c12_data_clk: qup-i2c12-data-clk { 3660 pins = "gpio48", "gpio49"; 3661 function = "qup14"; 3662 }; 3663 3664 qup_i2c13_data_clk: qup-i2c13-data-clk { 3665 pins = "gpio52", "gpio53"; 3666 function = "qup15"; 3667 }; 3668 3669 qup_i2c14_data_clk: qup-i2c14-data-clk { 3670 pins = "gpio56", "gpio57"; 3671 function = "qup16"; 3672 }; 3673 3674 qup_i2c15_data_clk: qup-i2c15-data-clk { 3675 pins = "gpio60", "gpio61"; 3676 function = "qup17"; 3677 }; 3678 3679 qup_spi0_data_clk: qup-spi0-data-clk { 3680 pins = "gpio0", "gpio1", "gpio2"; 3681 function = "qup00"; 3682 }; 3683 3684 qup_spi0_cs: qup-spi0-cs { 3685 pins = "gpio3"; 3686 function = "qup00"; 3687 }; 3688 3689 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 3690 pins = "gpio3"; 3691 function = "gpio"; 3692 }; 3693 3694 qup_spi1_data_clk: qup-spi1-data-clk { 3695 pins = "gpio4", "gpio5", "gpio6"; 3696 function = "qup01"; 3697 }; 3698 3699 qup_spi1_cs: qup-spi1-cs { 3700 pins = "gpio7"; 3701 function = "qup01"; 3702 }; 3703 3704 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 3705 pins = "gpio7"; 3706 function = "gpio"; 3707 }; 3708 3709 qup_spi2_data_clk: qup-spi2-data-clk { 3710 pins = "gpio8", "gpio9", "gpio10"; 3711 function = "qup02"; 3712 }; 3713 3714 qup_spi2_cs: qup-spi2-cs { 3715 pins = "gpio11"; 3716 function = "qup02"; 3717 }; 3718 3719 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 3720 pins = "gpio11"; 3721 function = "gpio"; 3722 }; 3723 3724 qup_spi3_data_clk: qup-spi3-data-clk { 3725 pins = "gpio12", "gpio13", "gpio14"; 3726 function = "qup03"; 3727 }; 3728 3729 qup_spi3_cs: qup-spi3-cs { 3730 pins = "gpio15"; 3731 function = "qup03"; 3732 }; 3733 3734 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 3735 pins = "gpio15"; 3736 function = "gpio"; 3737 }; 3738 3739 qup_spi4_data_clk: qup-spi4-data-clk { 3740 pins = "gpio16", "gpio17", "gpio18"; 3741 function = "qup04"; 3742 }; 3743 3744 qup_spi4_cs: qup-spi4-cs { 3745 pins = "gpio19"; 3746 function = "qup04"; 3747 }; 3748 3749 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 3750 pins = "gpio19"; 3751 function = "gpio"; 3752 }; 3753 3754 qup_spi5_data_clk: qup-spi5-data-clk { 3755 pins = "gpio20", "gpio21", "gpio22"; 3756 function = "qup05"; 3757 }; 3758 3759 qup_spi5_cs: qup-spi5-cs { 3760 pins = "gpio23"; 3761 function = "qup05"; 3762 }; 3763 3764 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 3765 pins = "gpio23"; 3766 function = "gpio"; 3767 }; 3768 3769 qup_spi6_data_clk: qup-spi6-data-clk { 3770 pins = "gpio24", "gpio25", "gpio26"; 3771 function = "qup06"; 3772 }; 3773 3774 qup_spi6_cs: qup-spi6-cs { 3775 pins = "gpio27"; 3776 function = "qup06"; 3777 }; 3778 3779 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3780 pins = "gpio27"; 3781 function = "gpio"; 3782 }; 3783 3784 qup_spi7_data_clk: qup-spi7-data-clk { 3785 pins = "gpio28", "gpio29", "gpio30"; 3786 function = "qup07"; 3787 }; 3788 3789 qup_spi7_cs: qup-spi7-cs { 3790 pins = "gpio31"; 3791 function = "qup07"; 3792 }; 3793 3794 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3795 pins = "gpio31"; 3796 function = "gpio"; 3797 }; 3798 3799 qup_spi8_data_clk: qup-spi8-data-clk { 3800 pins = "gpio32", "gpio33", "gpio34"; 3801 function = "qup10"; 3802 }; 3803 3804 qup_spi8_cs: qup-spi8-cs { 3805 pins = "gpio35"; 3806 function = "qup10"; 3807 }; 3808 3809 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 3810 pins = "gpio35"; 3811 function = "gpio"; 3812 }; 3813 3814 qup_spi9_data_clk: qup-spi9-data-clk { 3815 pins = "gpio36", "gpio37", "gpio38"; 3816 function = "qup11"; 3817 }; 3818 3819 qup_spi9_cs: qup-spi9-cs { 3820 pins = "gpio39"; 3821 function = "qup11"; 3822 }; 3823 3824 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 3825 pins = "gpio39"; 3826 function = "gpio"; 3827 }; 3828 3829 qup_spi10_data_clk: qup-spi10-data-clk { 3830 pins = "gpio40", "gpio41", "gpio42"; 3831 function = "qup12"; 3832 }; 3833 3834 qup_spi10_cs: qup-spi10-cs { 3835 pins = "gpio43"; 3836 function = "qup12"; 3837 }; 3838 3839 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 3840 pins = "gpio43"; 3841 function = "gpio"; 3842 }; 3843 3844 qup_spi11_data_clk: qup-spi11-data-clk { 3845 pins = "gpio44", "gpio45", "gpio46"; 3846 function = "qup13"; 3847 }; 3848 3849 qup_spi11_cs: qup-spi11-cs { 3850 pins = "gpio47"; 3851 function = "qup13"; 3852 }; 3853 3854 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 3855 pins = "gpio47"; 3856 function = "gpio"; 3857 }; 3858 3859 qup_spi12_data_clk: qup-spi12-data-clk { 3860 pins = "gpio48", "gpio49", "gpio50"; 3861 function = "qup14"; 3862 }; 3863 3864 qup_spi12_cs: qup-spi12-cs { 3865 pins = "gpio51"; 3866 function = "qup14"; 3867 }; 3868 3869 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 3870 pins = "gpio51"; 3871 function = "gpio"; 3872 }; 3873 3874 qup_spi13_data_clk: qup-spi13-data-clk { 3875 pins = "gpio52", "gpio53", "gpio54"; 3876 function = "qup15"; 3877 }; 3878 3879 qup_spi13_cs: qup-spi13-cs { 3880 pins = "gpio55"; 3881 function = "qup15"; 3882 }; 3883 3884 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 3885 pins = "gpio55"; 3886 function = "gpio"; 3887 }; 3888 3889 qup_spi14_data_clk: qup-spi14-data-clk { 3890 pins = "gpio56", "gpio57", "gpio58"; 3891 function = "qup16"; 3892 }; 3893 3894 qup_spi14_cs: qup-spi14-cs { 3895 pins = "gpio59"; 3896 function = "qup16"; 3897 }; 3898 3899 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 3900 pins = "gpio59"; 3901 function = "gpio"; 3902 }; 3903 3904 qup_spi15_data_clk: qup-spi15-data-clk { 3905 pins = "gpio60", "gpio61", "gpio62"; 3906 function = "qup17"; 3907 }; 3908 3909 qup_spi15_cs: qup-spi15-cs { 3910 pins = "gpio63"; 3911 function = "qup17"; 3912 }; 3913 3914 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 3915 pins = "gpio63"; 3916 function = "gpio"; 3917 }; 3918 3919 qup_uart0_cts: qup-uart0-cts { 3920 pins = "gpio0"; 3921 function = "qup00"; 3922 }; 3923 3924 qup_uart0_rts: qup-uart0-rts { 3925 pins = "gpio1"; 3926 function = "qup00"; 3927 }; 3928 3929 qup_uart0_tx: qup-uart0-tx { 3930 pins = "gpio2"; 3931 function = "qup00"; 3932 }; 3933 3934 qup_uart0_rx: qup-uart0-rx { 3935 pins = "gpio3"; 3936 function = "qup00"; 3937 }; 3938 3939 qup_uart1_cts: qup-uart1-cts { 3940 pins = "gpio4"; 3941 function = "qup01"; 3942 }; 3943 3944 qup_uart1_rts: qup-uart1-rts { 3945 pins = "gpio5"; 3946 function = "qup01"; 3947 }; 3948 3949 qup_uart1_tx: qup-uart1-tx { 3950 pins = "gpio6"; 3951 function = "qup01"; 3952 }; 3953 3954 qup_uart1_rx: qup-uart1-rx { 3955 pins = "gpio7"; 3956 function = "qup01"; 3957 }; 3958 3959 qup_uart2_cts: qup-uart2-cts { 3960 pins = "gpio8"; 3961 function = "qup02"; 3962 }; 3963 3964 qup_uart2_rts: qup-uart2-rts { 3965 pins = "gpio9"; 3966 function = "qup02"; 3967 }; 3968 3969 qup_uart2_tx: qup-uart2-tx { 3970 pins = "gpio10"; 3971 function = "qup02"; 3972 }; 3973 3974 qup_uart2_rx: qup-uart2-rx { 3975 pins = "gpio11"; 3976 function = "qup02"; 3977 }; 3978 3979 qup_uart3_cts: qup-uart3-cts { 3980 pins = "gpio12"; 3981 function = "qup03"; 3982 }; 3983 3984 qup_uart3_rts: qup-uart3-rts { 3985 pins = "gpio13"; 3986 function = "qup03"; 3987 }; 3988 3989 qup_uart3_tx: qup-uart3-tx { 3990 pins = "gpio14"; 3991 function = "qup03"; 3992 }; 3993 3994 qup_uart3_rx: qup-uart3-rx { 3995 pins = "gpio15"; 3996 function = "qup03"; 3997 }; 3998 3999 qup_uart4_cts: qup-uart4-cts { 4000 pins = "gpio16"; 4001 function = "qup04"; 4002 }; 4003 4004 qup_uart4_rts: qup-uart4-rts { 4005 pins = "gpio17"; 4006 function = "qup04"; 4007 }; 4008 4009 qup_uart4_tx: qup-uart4-tx { 4010 pins = "gpio18"; 4011 function = "qup04"; 4012 }; 4013 4014 qup_uart4_rx: qup-uart4-rx { 4015 pins = "gpio19"; 4016 function = "qup04"; 4017 }; 4018 4019 qup_uart5_cts: qup-uart5-cts { 4020 pins = "gpio20"; 4021 function = "qup05"; 4022 }; 4023 4024 qup_uart5_rts: qup-uart5-rts { 4025 pins = "gpio21"; 4026 function = "qup05"; 4027 }; 4028 4029 qup_uart5_tx: qup-uart5-tx { 4030 pins = "gpio22"; 4031 function = "qup05"; 4032 }; 4033 4034 qup_uart5_rx: qup-uart5-rx { 4035 pins = "gpio23"; 4036 function = "qup05"; 4037 }; 4038 4039 qup_uart6_cts: qup-uart6-cts { 4040 pins = "gpio24"; 4041 function = "qup06"; 4042 }; 4043 4044 qup_uart6_rts: qup-uart6-rts { 4045 pins = "gpio25"; 4046 function = "qup06"; 4047 }; 4048 4049 qup_uart6_tx: qup-uart6-tx { 4050 pins = "gpio26"; 4051 function = "qup06"; 4052 }; 4053 4054 qup_uart6_rx: qup-uart6-rx { 4055 pins = "gpio27"; 4056 function = "qup06"; 4057 }; 4058 4059 qup_uart7_cts: qup-uart7-cts { 4060 pins = "gpio28"; 4061 function = "qup07"; 4062 }; 4063 4064 qup_uart7_rts: qup-uart7-rts { 4065 pins = "gpio29"; 4066 function = "qup07"; 4067 }; 4068 4069 qup_uart7_tx: qup-uart7-tx { 4070 pins = "gpio30"; 4071 function = "qup07"; 4072 }; 4073 4074 qup_uart7_rx: qup-uart7-rx { 4075 pins = "gpio31"; 4076 function = "qup07"; 4077 }; 4078 4079 qup_uart8_cts: qup-uart8-cts { 4080 pins = "gpio32"; 4081 function = "qup10"; 4082 }; 4083 4084 qup_uart8_rts: qup-uart8-rts { 4085 pins = "gpio33"; 4086 function = "qup10"; 4087 }; 4088 4089 qup_uart8_tx: qup-uart8-tx { 4090 pins = "gpio34"; 4091 function = "qup10"; 4092 }; 4093 4094 qup_uart8_rx: qup-uart8-rx { 4095 pins = "gpio35"; 4096 function = "qup10"; 4097 }; 4098 4099 qup_uart9_cts: qup-uart9-cts { 4100 pins = "gpio36"; 4101 function = "qup11"; 4102 }; 4103 4104 qup_uart9_rts: qup-uart9-rts { 4105 pins = "gpio37"; 4106 function = "qup11"; 4107 }; 4108 4109 qup_uart9_tx: qup-uart9-tx { 4110 pins = "gpio38"; 4111 function = "qup11"; 4112 }; 4113 4114 qup_uart9_rx: qup-uart9-rx { 4115 pins = "gpio39"; 4116 function = "qup11"; 4117 }; 4118 4119 qup_uart10_cts: qup-uart10-cts { 4120 pins = "gpio40"; 4121 function = "qup12"; 4122 }; 4123 4124 qup_uart10_rts: qup-uart10-rts { 4125 pins = "gpio41"; 4126 function = "qup12"; 4127 }; 4128 4129 qup_uart10_tx: qup-uart10-tx { 4130 pins = "gpio42"; 4131 function = "qup12"; 4132 }; 4133 4134 qup_uart10_rx: qup-uart10-rx { 4135 pins = "gpio43"; 4136 function = "qup12"; 4137 }; 4138 4139 qup_uart11_cts: qup-uart11-cts { 4140 pins = "gpio44"; 4141 function = "qup13"; 4142 }; 4143 4144 qup_uart11_rts: qup-uart11-rts { 4145 pins = "gpio45"; 4146 function = "qup13"; 4147 }; 4148 4149 qup_uart11_tx: qup-uart11-tx { 4150 pins = "gpio46"; 4151 function = "qup13"; 4152 }; 4153 4154 qup_uart11_rx: qup-uart11-rx { 4155 pins = "gpio47"; 4156 function = "qup13"; 4157 }; 4158 4159 qup_uart12_cts: qup-uart12-cts { 4160 pins = "gpio48"; 4161 function = "qup14"; 4162 }; 4163 4164 qup_uart12_rts: qup-uart12-rts { 4165 pins = "gpio49"; 4166 function = "qup14"; 4167 }; 4168 4169 qup_uart12_tx: qup-uart12-tx { 4170 pins = "gpio50"; 4171 function = "qup14"; 4172 }; 4173 4174 qup_uart12_rx: qup-uart12-rx { 4175 pins = "gpio51"; 4176 function = "qup14"; 4177 }; 4178 4179 qup_uart13_cts: qup-uart13-cts { 4180 pins = "gpio52"; 4181 function = "qup15"; 4182 }; 4183 4184 qup_uart13_rts: qup-uart13-rts { 4185 pins = "gpio53"; 4186 function = "qup15"; 4187 }; 4188 4189 qup_uart13_tx: qup-uart13-tx { 4190 pins = "gpio54"; 4191 function = "qup15"; 4192 }; 4193 4194 qup_uart13_rx: qup-uart13-rx { 4195 pins = "gpio55"; 4196 function = "qup15"; 4197 }; 4198 4199 qup_uart14_cts: qup-uart14-cts { 4200 pins = "gpio56"; 4201 function = "qup16"; 4202 }; 4203 4204 qup_uart14_rts: qup-uart14-rts { 4205 pins = "gpio57"; 4206 function = "qup16"; 4207 }; 4208 4209 qup_uart14_tx: qup-uart14-tx { 4210 pins = "gpio58"; 4211 function = "qup16"; 4212 }; 4213 4214 qup_uart14_rx: qup-uart14-rx { 4215 pins = "gpio59"; 4216 function = "qup16"; 4217 }; 4218 4219 qup_uart15_cts: qup-uart15-cts { 4220 pins = "gpio60"; 4221 function = "qup17"; 4222 }; 4223 4224 qup_uart15_rts: qup-uart15-rts { 4225 pins = "gpio61"; 4226 function = "qup17"; 4227 }; 4228 4229 qup_uart15_tx: qup-uart15-tx { 4230 pins = "gpio62"; 4231 function = "qup17"; 4232 }; 4233 4234 qup_uart15_rx: qup-uart15-rx { 4235 pins = "gpio63"; 4236 function = "qup17"; 4237 }; 4238 4239 sdc1_clk: sdc1-clk { 4240 pins = "sdc1_clk"; 4241 }; 4242 4243 sdc1_cmd: sdc1-cmd { 4244 pins = "sdc1_cmd"; 4245 }; 4246 4247 sdc1_data: sdc1-data { 4248 pins = "sdc1_data"; 4249 }; 4250 4251 sdc1_rclk: sdc1-rclk { 4252 pins = "sdc1_rclk"; 4253 }; 4254 4255 sdc1_clk_sleep: sdc1-clk-sleep { 4256 pins = "sdc1_clk"; 4257 drive-strength = <2>; 4258 bias-bus-hold; 4259 }; 4260 4261 sdc1_cmd_sleep: sdc1-cmd-sleep { 4262 pins = "sdc1_cmd"; 4263 drive-strength = <2>; 4264 bias-bus-hold; 4265 }; 4266 4267 sdc1_data_sleep: sdc1-data-sleep { 4268 pins = "sdc1_data"; 4269 drive-strength = <2>; 4270 bias-bus-hold; 4271 }; 4272 4273 sdc1_rclk_sleep: sdc1-rclk-sleep { 4274 pins = "sdc1_rclk"; 4275 drive-strength = <2>; 4276 bias-bus-hold; 4277 }; 4278 4279 sdc2_clk: sdc2-clk { 4280 pins = "sdc2_clk"; 4281 }; 4282 4283 sdc2_cmd: sdc2-cmd { 4284 pins = "sdc2_cmd"; 4285 }; 4286 4287 sdc2_data: sdc2-data { 4288 pins = "sdc2_data"; 4289 }; 4290 4291 sdc2_clk_sleep: sdc2-clk-sleep { 4292 pins = "sdc2_clk"; 4293 drive-strength = <2>; 4294 bias-bus-hold; 4295 }; 4296 4297 sdc2_cmd_sleep: sdc2-cmd-sleep { 4298 pins = "sdc2_cmd"; 4299 drive-strength = <2>; 4300 bias-bus-hold; 4301 }; 4302 4303 sdc2_data_sleep: sdc2-data-sleep { 4304 pins = "sdc2_data"; 4305 drive-strength = <2>; 4306 bias-bus-hold; 4307 }; 4308 }; 4309 4310 imem@146a5000 { 4311 compatible = "qcom,sc7280-imem", "syscon"; 4312 reg = <0 0x146a5000 0 0x6000>; 4313 4314 #address-cells = <1>; 4315 #size-cells = <1>; 4316 4317 ranges = <0 0 0x146a5000 0x6000>; 4318 4319 pil-reloc@594c { 4320 compatible = "qcom,pil-reloc-info"; 4321 reg = <0x594c 0xc8>; 4322 }; 4323 }; 4324 4325 apps_smmu: iommu@15000000 { 4326 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 4327 reg = <0 0x15000000 0 0x100000>; 4328 #iommu-cells = <2>; 4329 #global-interrupts = <1>; 4330 dma-coherent; 4331 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4332 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 4333 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4334 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4335 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4336 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4337 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4338 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4339 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4340 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4341 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4342 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4343 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4344 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4345 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4346 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4347 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4348 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4349 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4350 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4351 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4352 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4353 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4354 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4355 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4356 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4357 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4358 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4359 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4360 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4361 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4362 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4363 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4364 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4365 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4366 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4367 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4368 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4369 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4370 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4371 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4372 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4373 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4374 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4375 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4376 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4377 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4378 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4379 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4380 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4381 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4382 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4383 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4384 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4385 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4386 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4387 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4388 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4389 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4390 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4391 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4392 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4393 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4394 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4395 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4396 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4397 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4398 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4399 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4400 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4401 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4402 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4403 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4404 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4405 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4406 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4407 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4408 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4409 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4410 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4411 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 4412 }; 4413 4414 intc: interrupt-controller@17a00000 { 4415 compatible = "arm,gic-v3"; 4416 #address-cells = <2>; 4417 #size-cells = <2>; 4418 ranges; 4419 #interrupt-cells = <3>; 4420 interrupt-controller; 4421 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 4422 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 4423 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 4424 4425 gic-its@17a40000 { 4426 compatible = "arm,gic-v3-its"; 4427 msi-controller; 4428 #msi-cells = <1>; 4429 reg = <0 0x17a40000 0 0x20000>; 4430 status = "disabled"; 4431 }; 4432 }; 4433 4434 watchdog@17c10000 { 4435 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 4436 reg = <0 0x17c10000 0 0x1000>; 4437 clocks = <&sleep_clk>; 4438 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4439 }; 4440 4441 timer@17c20000 { 4442 #address-cells = <2>; 4443 #size-cells = <2>; 4444 ranges; 4445 compatible = "arm,armv7-timer-mem"; 4446 reg = <0 0x17c20000 0 0x1000>; 4447 4448 frame@17c21000 { 4449 frame-number = <0>; 4450 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4451 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4452 reg = <0 0x17c21000 0 0x1000>, 4453 <0 0x17c22000 0 0x1000>; 4454 }; 4455 4456 frame@17c23000 { 4457 frame-number = <1>; 4458 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4459 reg = <0 0x17c23000 0 0x1000>; 4460 status = "disabled"; 4461 }; 4462 4463 frame@17c25000 { 4464 frame-number = <2>; 4465 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4466 reg = <0 0x17c25000 0 0x1000>; 4467 status = "disabled"; 4468 }; 4469 4470 frame@17c27000 { 4471 frame-number = <3>; 4472 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4473 reg = <0 0x17c27000 0 0x1000>; 4474 status = "disabled"; 4475 }; 4476 4477 frame@17c29000 { 4478 frame-number = <4>; 4479 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4480 reg = <0 0x17c29000 0 0x1000>; 4481 status = "disabled"; 4482 }; 4483 4484 frame@17c2b000 { 4485 frame-number = <5>; 4486 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4487 reg = <0 0x17c2b000 0 0x1000>; 4488 status = "disabled"; 4489 }; 4490 4491 frame@17c2d000 { 4492 frame-number = <6>; 4493 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4494 reg = <0 0x17c2d000 0 0x1000>; 4495 status = "disabled"; 4496 }; 4497 }; 4498 4499 apps_rsc: rsc@18200000 { 4500 compatible = "qcom,rpmh-rsc"; 4501 reg = <0 0x18200000 0 0x10000>, 4502 <0 0x18210000 0 0x10000>, 4503 <0 0x18220000 0 0x10000>; 4504 reg-names = "drv-0", "drv-1", "drv-2"; 4505 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4506 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4507 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4508 qcom,tcs-offset = <0xd00>; 4509 qcom,drv-id = <2>; 4510 qcom,tcs-config = <ACTIVE_TCS 2>, 4511 <SLEEP_TCS 3>, 4512 <WAKE_TCS 3>, 4513 <CONTROL_TCS 1>; 4514 4515 apps_bcm_voter: bcm-voter { 4516 compatible = "qcom,bcm-voter"; 4517 }; 4518 4519 rpmhpd: power-controller { 4520 compatible = "qcom,sc7280-rpmhpd"; 4521 #power-domain-cells = <1>; 4522 operating-points-v2 = <&rpmhpd_opp_table>; 4523 4524 rpmhpd_opp_table: opp-table { 4525 compatible = "operating-points-v2"; 4526 4527 rpmhpd_opp_ret: opp1 { 4528 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4529 }; 4530 4531 rpmhpd_opp_low_svs: opp2 { 4532 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4533 }; 4534 4535 rpmhpd_opp_svs: opp3 { 4536 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4537 }; 4538 4539 rpmhpd_opp_svs_l1: opp4 { 4540 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4541 }; 4542 4543 rpmhpd_opp_svs_l2: opp5 { 4544 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4545 }; 4546 4547 rpmhpd_opp_nom: opp6 { 4548 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4549 }; 4550 4551 rpmhpd_opp_nom_l1: opp7 { 4552 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4553 }; 4554 4555 rpmhpd_opp_turbo: opp8 { 4556 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4557 }; 4558 4559 rpmhpd_opp_turbo_l1: opp9 { 4560 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4561 }; 4562 }; 4563 }; 4564 4565 rpmhcc: clock-controller { 4566 compatible = "qcom,sc7280-rpmh-clk"; 4567 clocks = <&xo_board>; 4568 clock-names = "xo"; 4569 #clock-cells = <1>; 4570 }; 4571 }; 4572 4573 epss_l3: interconnect@18590000 { 4574 compatible = "qcom,sc7280-epss-l3"; 4575 reg = <0 0x18590000 0 0x1000>; 4576 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4577 clock-names = "xo", "alternate"; 4578 #interconnect-cells = <1>; 4579 }; 4580 4581 cpufreq_hw: cpufreq@18591000 { 4582 compatible = "qcom,cpufreq-epss"; 4583 reg = <0 0x18591000 0 0x1000>, 4584 <0 0x18592000 0 0x1000>, 4585 <0 0x18593000 0 0x1000>; 4586 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4587 clock-names = "xo", "alternate"; 4588 #freq-domain-cells = <1>; 4589 }; 4590 }; 4591 4592 thermal_zones: thermal-zones { 4593 cpu0-thermal { 4594 polling-delay-passive = <250>; 4595 polling-delay = <0>; 4596 4597 thermal-sensors = <&tsens0 1>; 4598 4599 trips { 4600 cpu0_alert0: trip-point0 { 4601 temperature = <90000>; 4602 hysteresis = <2000>; 4603 type = "passive"; 4604 }; 4605 4606 cpu0_alert1: trip-point1 { 4607 temperature = <95000>; 4608 hysteresis = <2000>; 4609 type = "passive"; 4610 }; 4611 4612 cpu0_crit: cpu-crit { 4613 temperature = <110000>; 4614 hysteresis = <0>; 4615 type = "critical"; 4616 }; 4617 }; 4618 4619 cooling-maps { 4620 map0 { 4621 trip = <&cpu0_alert0>; 4622 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4623 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4624 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4625 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4626 }; 4627 map1 { 4628 trip = <&cpu0_alert1>; 4629 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4630 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4631 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4632 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4633 }; 4634 }; 4635 }; 4636 4637 cpu1-thermal { 4638 polling-delay-passive = <250>; 4639 polling-delay = <0>; 4640 4641 thermal-sensors = <&tsens0 2>; 4642 4643 trips { 4644 cpu1_alert0: trip-point0 { 4645 temperature = <90000>; 4646 hysteresis = <2000>; 4647 type = "passive"; 4648 }; 4649 4650 cpu1_alert1: trip-point1 { 4651 temperature = <95000>; 4652 hysteresis = <2000>; 4653 type = "passive"; 4654 }; 4655 4656 cpu1_crit: cpu-crit { 4657 temperature = <110000>; 4658 hysteresis = <0>; 4659 type = "critical"; 4660 }; 4661 }; 4662 4663 cooling-maps { 4664 map0 { 4665 trip = <&cpu1_alert0>; 4666 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4667 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4668 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4669 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4670 }; 4671 map1 { 4672 trip = <&cpu1_alert1>; 4673 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4674 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4675 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4676 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4677 }; 4678 }; 4679 }; 4680 4681 cpu2-thermal { 4682 polling-delay-passive = <250>; 4683 polling-delay = <0>; 4684 4685 thermal-sensors = <&tsens0 3>; 4686 4687 trips { 4688 cpu2_alert0: trip-point0 { 4689 temperature = <90000>; 4690 hysteresis = <2000>; 4691 type = "passive"; 4692 }; 4693 4694 cpu2_alert1: trip-point1 { 4695 temperature = <95000>; 4696 hysteresis = <2000>; 4697 type = "passive"; 4698 }; 4699 4700 cpu2_crit: cpu-crit { 4701 temperature = <110000>; 4702 hysteresis = <0>; 4703 type = "critical"; 4704 }; 4705 }; 4706 4707 cooling-maps { 4708 map0 { 4709 trip = <&cpu2_alert0>; 4710 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4711 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4712 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4713 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4714 }; 4715 map1 { 4716 trip = <&cpu2_alert1>; 4717 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4718 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4719 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4720 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4721 }; 4722 }; 4723 }; 4724 4725 cpu3-thermal { 4726 polling-delay-passive = <250>; 4727 polling-delay = <0>; 4728 4729 thermal-sensors = <&tsens0 4>; 4730 4731 trips { 4732 cpu3_alert0: trip-point0 { 4733 temperature = <90000>; 4734 hysteresis = <2000>; 4735 type = "passive"; 4736 }; 4737 4738 cpu3_alert1: trip-point1 { 4739 temperature = <95000>; 4740 hysteresis = <2000>; 4741 type = "passive"; 4742 }; 4743 4744 cpu3_crit: cpu-crit { 4745 temperature = <110000>; 4746 hysteresis = <0>; 4747 type = "critical"; 4748 }; 4749 }; 4750 4751 cooling-maps { 4752 map0 { 4753 trip = <&cpu3_alert0>; 4754 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4755 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4756 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4757 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4758 }; 4759 map1 { 4760 trip = <&cpu3_alert1>; 4761 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4762 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4763 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4764 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4765 }; 4766 }; 4767 }; 4768 4769 cpu4-thermal { 4770 polling-delay-passive = <250>; 4771 polling-delay = <0>; 4772 4773 thermal-sensors = <&tsens0 7>; 4774 4775 trips { 4776 cpu4_alert0: trip-point0 { 4777 temperature = <90000>; 4778 hysteresis = <2000>; 4779 type = "passive"; 4780 }; 4781 4782 cpu4_alert1: trip-point1 { 4783 temperature = <95000>; 4784 hysteresis = <2000>; 4785 type = "passive"; 4786 }; 4787 4788 cpu4_crit: cpu-crit { 4789 temperature = <110000>; 4790 hysteresis = <0>; 4791 type = "critical"; 4792 }; 4793 }; 4794 4795 cooling-maps { 4796 map0 { 4797 trip = <&cpu4_alert0>; 4798 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4799 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4800 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4801 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4802 }; 4803 map1 { 4804 trip = <&cpu4_alert1>; 4805 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4806 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4807 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4808 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4809 }; 4810 }; 4811 }; 4812 4813 cpu5-thermal { 4814 polling-delay-passive = <250>; 4815 polling-delay = <0>; 4816 4817 thermal-sensors = <&tsens0 8>; 4818 4819 trips { 4820 cpu5_alert0: trip-point0 { 4821 temperature = <90000>; 4822 hysteresis = <2000>; 4823 type = "passive"; 4824 }; 4825 4826 cpu5_alert1: trip-point1 { 4827 temperature = <95000>; 4828 hysteresis = <2000>; 4829 type = "passive"; 4830 }; 4831 4832 cpu5_crit: cpu-crit { 4833 temperature = <110000>; 4834 hysteresis = <0>; 4835 type = "critical"; 4836 }; 4837 }; 4838 4839 cooling-maps { 4840 map0 { 4841 trip = <&cpu5_alert0>; 4842 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4843 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4844 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4845 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4846 }; 4847 map1 { 4848 trip = <&cpu5_alert1>; 4849 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4850 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4851 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4852 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4853 }; 4854 }; 4855 }; 4856 4857 cpu6-thermal { 4858 polling-delay-passive = <250>; 4859 polling-delay = <0>; 4860 4861 thermal-sensors = <&tsens0 9>; 4862 4863 trips { 4864 cpu6_alert0: trip-point0 { 4865 temperature = <90000>; 4866 hysteresis = <2000>; 4867 type = "passive"; 4868 }; 4869 4870 cpu6_alert1: trip-point1 { 4871 temperature = <95000>; 4872 hysteresis = <2000>; 4873 type = "passive"; 4874 }; 4875 4876 cpu6_crit: cpu-crit { 4877 temperature = <110000>; 4878 hysteresis = <0>; 4879 type = "critical"; 4880 }; 4881 }; 4882 4883 cooling-maps { 4884 map0 { 4885 trip = <&cpu6_alert0>; 4886 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4887 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4888 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4889 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4890 }; 4891 map1 { 4892 trip = <&cpu6_alert1>; 4893 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4894 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4895 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4896 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4897 }; 4898 }; 4899 }; 4900 4901 cpu7-thermal { 4902 polling-delay-passive = <250>; 4903 polling-delay = <0>; 4904 4905 thermal-sensors = <&tsens0 10>; 4906 4907 trips { 4908 cpu7_alert0: trip-point0 { 4909 temperature = <90000>; 4910 hysteresis = <2000>; 4911 type = "passive"; 4912 }; 4913 4914 cpu7_alert1: trip-point1 { 4915 temperature = <95000>; 4916 hysteresis = <2000>; 4917 type = "passive"; 4918 }; 4919 4920 cpu7_crit: cpu-crit { 4921 temperature = <110000>; 4922 hysteresis = <0>; 4923 type = "critical"; 4924 }; 4925 }; 4926 4927 cooling-maps { 4928 map0 { 4929 trip = <&cpu7_alert0>; 4930 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4931 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4932 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4933 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4934 }; 4935 map1 { 4936 trip = <&cpu7_alert1>; 4937 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4938 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4939 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4940 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4941 }; 4942 }; 4943 }; 4944 4945 cpu8-thermal { 4946 polling-delay-passive = <250>; 4947 polling-delay = <0>; 4948 4949 thermal-sensors = <&tsens0 11>; 4950 4951 trips { 4952 cpu8_alert0: trip-point0 { 4953 temperature = <90000>; 4954 hysteresis = <2000>; 4955 type = "passive"; 4956 }; 4957 4958 cpu8_alert1: trip-point1 { 4959 temperature = <95000>; 4960 hysteresis = <2000>; 4961 type = "passive"; 4962 }; 4963 4964 cpu8_crit: cpu-crit { 4965 temperature = <110000>; 4966 hysteresis = <0>; 4967 type = "critical"; 4968 }; 4969 }; 4970 4971 cooling-maps { 4972 map0 { 4973 trip = <&cpu8_alert0>; 4974 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4975 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4976 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4977 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4978 }; 4979 map1 { 4980 trip = <&cpu8_alert1>; 4981 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4982 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4983 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4984 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4985 }; 4986 }; 4987 }; 4988 4989 cpu9-thermal { 4990 polling-delay-passive = <250>; 4991 polling-delay = <0>; 4992 4993 thermal-sensors = <&tsens0 12>; 4994 4995 trips { 4996 cpu9_alert0: trip-point0 { 4997 temperature = <90000>; 4998 hysteresis = <2000>; 4999 type = "passive"; 5000 }; 5001 5002 cpu9_alert1: trip-point1 { 5003 temperature = <95000>; 5004 hysteresis = <2000>; 5005 type = "passive"; 5006 }; 5007 5008 cpu9_crit: cpu-crit { 5009 temperature = <110000>; 5010 hysteresis = <0>; 5011 type = "critical"; 5012 }; 5013 }; 5014 5015 cooling-maps { 5016 map0 { 5017 trip = <&cpu9_alert0>; 5018 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5019 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5020 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5021 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5022 }; 5023 map1 { 5024 trip = <&cpu9_alert1>; 5025 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5026 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5027 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5028 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5029 }; 5030 }; 5031 }; 5032 5033 cpu10-thermal { 5034 polling-delay-passive = <250>; 5035 polling-delay = <0>; 5036 5037 thermal-sensors = <&tsens0 13>; 5038 5039 trips { 5040 cpu10_alert0: trip-point0 { 5041 temperature = <90000>; 5042 hysteresis = <2000>; 5043 type = "passive"; 5044 }; 5045 5046 cpu10_alert1: trip-point1 { 5047 temperature = <95000>; 5048 hysteresis = <2000>; 5049 type = "passive"; 5050 }; 5051 5052 cpu10_crit: cpu-crit { 5053 temperature = <110000>; 5054 hysteresis = <0>; 5055 type = "critical"; 5056 }; 5057 }; 5058 5059 cooling-maps { 5060 map0 { 5061 trip = <&cpu10_alert0>; 5062 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5063 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5064 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5065 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5066 }; 5067 map1 { 5068 trip = <&cpu10_alert1>; 5069 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5070 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5071 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5072 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5073 }; 5074 }; 5075 }; 5076 5077 cpu11-thermal { 5078 polling-delay-passive = <250>; 5079 polling-delay = <0>; 5080 5081 thermal-sensors = <&tsens0 14>; 5082 5083 trips { 5084 cpu11_alert0: trip-point0 { 5085 temperature = <90000>; 5086 hysteresis = <2000>; 5087 type = "passive"; 5088 }; 5089 5090 cpu11_alert1: trip-point1 { 5091 temperature = <95000>; 5092 hysteresis = <2000>; 5093 type = "passive"; 5094 }; 5095 5096 cpu11_crit: cpu-crit { 5097 temperature = <110000>; 5098 hysteresis = <0>; 5099 type = "critical"; 5100 }; 5101 }; 5102 5103 cooling-maps { 5104 map0 { 5105 trip = <&cpu11_alert0>; 5106 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5107 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5108 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5109 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5110 }; 5111 map1 { 5112 trip = <&cpu11_alert1>; 5113 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5114 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5115 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5116 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5117 }; 5118 }; 5119 }; 5120 5121 aoss0-thermal { 5122 polling-delay-passive = <0>; 5123 polling-delay = <0>; 5124 5125 thermal-sensors = <&tsens0 0>; 5126 5127 trips { 5128 aoss0_alert0: trip-point0 { 5129 temperature = <90000>; 5130 hysteresis = <2000>; 5131 type = "hot"; 5132 }; 5133 5134 aoss0_crit: aoss0-crit { 5135 temperature = <110000>; 5136 hysteresis = <0>; 5137 type = "critical"; 5138 }; 5139 }; 5140 }; 5141 5142 aoss1-thermal { 5143 polling-delay-passive = <0>; 5144 polling-delay = <0>; 5145 5146 thermal-sensors = <&tsens1 0>; 5147 5148 trips { 5149 aoss1_alert0: trip-point0 { 5150 temperature = <90000>; 5151 hysteresis = <2000>; 5152 type = "hot"; 5153 }; 5154 5155 aoss1_crit: aoss1-crit { 5156 temperature = <110000>; 5157 hysteresis = <0>; 5158 type = "critical"; 5159 }; 5160 }; 5161 }; 5162 5163 cpuss0-thermal { 5164 polling-delay-passive = <0>; 5165 polling-delay = <0>; 5166 5167 thermal-sensors = <&tsens0 5>; 5168 5169 trips { 5170 cpuss0_alert0: trip-point0 { 5171 temperature = <90000>; 5172 hysteresis = <2000>; 5173 type = "hot"; 5174 }; 5175 cpuss0_crit: cluster0-crit { 5176 temperature = <110000>; 5177 hysteresis = <0>; 5178 type = "critical"; 5179 }; 5180 }; 5181 }; 5182 5183 cpuss1-thermal { 5184 polling-delay-passive = <0>; 5185 polling-delay = <0>; 5186 5187 thermal-sensors = <&tsens0 6>; 5188 5189 trips { 5190 cpuss1_alert0: trip-point0 { 5191 temperature = <90000>; 5192 hysteresis = <2000>; 5193 type = "hot"; 5194 }; 5195 cpuss1_crit: cluster0-crit { 5196 temperature = <110000>; 5197 hysteresis = <0>; 5198 type = "critical"; 5199 }; 5200 }; 5201 }; 5202 5203 gpuss0-thermal { 5204 polling-delay-passive = <100>; 5205 polling-delay = <0>; 5206 5207 thermal-sensors = <&tsens1 1>; 5208 5209 trips { 5210 gpuss0_alert0: trip-point0 { 5211 temperature = <95000>; 5212 hysteresis = <2000>; 5213 type = "passive"; 5214 }; 5215 5216 gpuss0_crit: gpuss0-crit { 5217 temperature = <110000>; 5218 hysteresis = <0>; 5219 type = "critical"; 5220 }; 5221 }; 5222 5223 cooling-maps { 5224 map0 { 5225 trip = <&gpuss0_alert0>; 5226 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5227 }; 5228 }; 5229 }; 5230 5231 gpuss1-thermal { 5232 polling-delay-passive = <100>; 5233 polling-delay = <0>; 5234 5235 thermal-sensors = <&tsens1 2>; 5236 5237 trips { 5238 gpuss1_alert0: trip-point0 { 5239 temperature = <95000>; 5240 hysteresis = <2000>; 5241 type = "passive"; 5242 }; 5243 5244 gpuss1_crit: gpuss1-crit { 5245 temperature = <110000>; 5246 hysteresis = <0>; 5247 type = "critical"; 5248 }; 5249 }; 5250 5251 cooling-maps { 5252 map0 { 5253 trip = <&gpuss1_alert0>; 5254 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5255 }; 5256 }; 5257 }; 5258 5259 nspss0-thermal { 5260 polling-delay-passive = <0>; 5261 polling-delay = <0>; 5262 5263 thermal-sensors = <&tsens1 3>; 5264 5265 trips { 5266 nspss0_alert0: trip-point0 { 5267 temperature = <90000>; 5268 hysteresis = <2000>; 5269 type = "hot"; 5270 }; 5271 5272 nspss0_crit: nspss0-crit { 5273 temperature = <110000>; 5274 hysteresis = <0>; 5275 type = "critical"; 5276 }; 5277 }; 5278 }; 5279 5280 nspss1-thermal { 5281 polling-delay-passive = <0>; 5282 polling-delay = <0>; 5283 5284 thermal-sensors = <&tsens1 4>; 5285 5286 trips { 5287 nspss1_alert0: trip-point0 { 5288 temperature = <90000>; 5289 hysteresis = <2000>; 5290 type = "hot"; 5291 }; 5292 5293 nspss1_crit: nspss1-crit { 5294 temperature = <110000>; 5295 hysteresis = <0>; 5296 type = "critical"; 5297 }; 5298 }; 5299 }; 5300 5301 video-thermal { 5302 polling-delay-passive = <0>; 5303 polling-delay = <0>; 5304 5305 thermal-sensors = <&tsens1 5>; 5306 5307 trips { 5308 video_alert0: trip-point0 { 5309 temperature = <90000>; 5310 hysteresis = <2000>; 5311 type = "hot"; 5312 }; 5313 5314 video_crit: video-crit { 5315 temperature = <110000>; 5316 hysteresis = <0>; 5317 type = "critical"; 5318 }; 5319 }; 5320 }; 5321 5322 ddr-thermal { 5323 polling-delay-passive = <0>; 5324 polling-delay = <0>; 5325 5326 thermal-sensors = <&tsens1 6>; 5327 5328 trips { 5329 ddr_alert0: trip-point0 { 5330 temperature = <90000>; 5331 hysteresis = <2000>; 5332 type = "hot"; 5333 }; 5334 5335 ddr_crit: ddr-crit { 5336 temperature = <110000>; 5337 hysteresis = <0>; 5338 type = "critical"; 5339 }; 5340 }; 5341 }; 5342 5343 mdmss0-thermal { 5344 polling-delay-passive = <0>; 5345 polling-delay = <0>; 5346 5347 thermal-sensors = <&tsens1 7>; 5348 5349 trips { 5350 mdmss0_alert0: trip-point0 { 5351 temperature = <90000>; 5352 hysteresis = <2000>; 5353 type = "hot"; 5354 }; 5355 5356 mdmss0_crit: mdmss0-crit { 5357 temperature = <110000>; 5358 hysteresis = <0>; 5359 type = "critical"; 5360 }; 5361 }; 5362 }; 5363 5364 mdmss1-thermal { 5365 polling-delay-passive = <0>; 5366 polling-delay = <0>; 5367 5368 thermal-sensors = <&tsens1 8>; 5369 5370 trips { 5371 mdmss1_alert0: trip-point0 { 5372 temperature = <90000>; 5373 hysteresis = <2000>; 5374 type = "hot"; 5375 }; 5376 5377 mdmss1_crit: mdmss1-crit { 5378 temperature = <110000>; 5379 hysteresis = <0>; 5380 type = "critical"; 5381 }; 5382 }; 5383 }; 5384 5385 mdmss2-thermal { 5386 polling-delay-passive = <0>; 5387 polling-delay = <0>; 5388 5389 thermal-sensors = <&tsens1 9>; 5390 5391 trips { 5392 mdmss2_alert0: trip-point0 { 5393 temperature = <90000>; 5394 hysteresis = <2000>; 5395 type = "hot"; 5396 }; 5397 5398 mdmss2_crit: mdmss2-crit { 5399 temperature = <110000>; 5400 hysteresis = <0>; 5401 type = "critical"; 5402 }; 5403 }; 5404 }; 5405 5406 mdmss3-thermal { 5407 polling-delay-passive = <0>; 5408 polling-delay = <0>; 5409 5410 thermal-sensors = <&tsens1 10>; 5411 5412 trips { 5413 mdmss3_alert0: trip-point0 { 5414 temperature = <90000>; 5415 hysteresis = <2000>; 5416 type = "hot"; 5417 }; 5418 5419 mdmss3_crit: mdmss3-crit { 5420 temperature = <110000>; 5421 hysteresis = <0>; 5422 type = "critical"; 5423 }; 5424 }; 5425 }; 5426 5427 camera0-thermal { 5428 polling-delay-passive = <0>; 5429 polling-delay = <0>; 5430 5431 thermal-sensors = <&tsens1 11>; 5432 5433 trips { 5434 camera0_alert0: trip-point0 { 5435 temperature = <90000>; 5436 hysteresis = <2000>; 5437 type = "hot"; 5438 }; 5439 5440 camera0_crit: camera0-crit { 5441 temperature = <110000>; 5442 hysteresis = <0>; 5443 type = "critical"; 5444 }; 5445 }; 5446 }; 5447 }; 5448 5449 timer { 5450 compatible = "arm,armv8-timer"; 5451 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 5452 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 5453 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 5454 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 5455 }; 5456}; 5457