1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-sc7280.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/interconnect/qcom,sc7280.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/mailbox/qcom-ipcc.h> 13#include <dt-bindings/power/qcom-aoss-qmp.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/reset/qcom,sdm845-aoss.h> 16#include <dt-bindings/reset/qcom,sdm845-pdc.h> 17#include <dt-bindings/soc/qcom,rpmh-rsc.h> 18#include <dt-bindings/thermal/thermal.h> 19 20/ { 21 interrupt-parent = <&intc>; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 chosen { }; 27 28 aliases { 29 mmc1 = &sdhc_1; 30 mmc2 = &sdhc_2; 31 }; 32 33 clocks { 34 xo_board: xo-board { 35 compatible = "fixed-clock"; 36 clock-frequency = <76800000>; 37 #clock-cells = <0>; 38 }; 39 40 sleep_clk: sleep-clk { 41 compatible = "fixed-clock"; 42 clock-frequency = <32000>; 43 #clock-cells = <0>; 44 }; 45 }; 46 47 reserved-memory { 48 #address-cells = <2>; 49 #size-cells = <2>; 50 ranges; 51 52 aop_mem: memory@80800000 { 53 reg = <0x0 0x80800000 0x0 0x60000>; 54 no-map; 55 }; 56 57 aop_cmd_db_mem: memory@80860000 { 58 reg = <0x0 0x80860000 0x0 0x20000>; 59 compatible = "qcom,cmd-db"; 60 no-map; 61 }; 62 63 smem_mem: memory@80900000 { 64 reg = <0x0 0x80900000 0x0 0x200000>; 65 no-map; 66 }; 67 68 cpucp_mem: memory@80b00000 { 69 no-map; 70 reg = <0x0 0x80b00000 0x0 0x100000>; 71 }; 72 73 ipa_fw_mem: memory@8b700000 { 74 reg = <0 0x8b700000 0 0x10000>; 75 no-map; 76 }; 77 }; 78 79 cpus { 80 #address-cells = <2>; 81 #size-cells = <0>; 82 83 CPU0: cpu@0 { 84 device_type = "cpu"; 85 compatible = "arm,kryo"; 86 reg = <0x0 0x0>; 87 enable-method = "psci"; 88 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 89 &LITTLE_CPU_SLEEP_1 90 &CLUSTER_SLEEP_0>; 91 next-level-cache = <&L2_0>; 92 qcom,freq-domain = <&cpufreq_hw 0>; 93 #cooling-cells = <2>; 94 L2_0: l2-cache { 95 compatible = "cache"; 96 next-level-cache = <&L3_0>; 97 L3_0: l3-cache { 98 compatible = "cache"; 99 }; 100 }; 101 }; 102 103 CPU1: cpu@100 { 104 device_type = "cpu"; 105 compatible = "arm,kryo"; 106 reg = <0x0 0x100>; 107 enable-method = "psci"; 108 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 109 &LITTLE_CPU_SLEEP_1 110 &CLUSTER_SLEEP_0>; 111 next-level-cache = <&L2_100>; 112 qcom,freq-domain = <&cpufreq_hw 0>; 113 #cooling-cells = <2>; 114 L2_100: l2-cache { 115 compatible = "cache"; 116 next-level-cache = <&L3_0>; 117 }; 118 }; 119 120 CPU2: cpu@200 { 121 device_type = "cpu"; 122 compatible = "arm,kryo"; 123 reg = <0x0 0x200>; 124 enable-method = "psci"; 125 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 126 &LITTLE_CPU_SLEEP_1 127 &CLUSTER_SLEEP_0>; 128 next-level-cache = <&L2_200>; 129 qcom,freq-domain = <&cpufreq_hw 0>; 130 #cooling-cells = <2>; 131 L2_200: l2-cache { 132 compatible = "cache"; 133 next-level-cache = <&L3_0>; 134 }; 135 }; 136 137 CPU3: cpu@300 { 138 device_type = "cpu"; 139 compatible = "arm,kryo"; 140 reg = <0x0 0x300>; 141 enable-method = "psci"; 142 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 143 &LITTLE_CPU_SLEEP_1 144 &CLUSTER_SLEEP_0>; 145 next-level-cache = <&L2_300>; 146 qcom,freq-domain = <&cpufreq_hw 0>; 147 #cooling-cells = <2>; 148 L2_300: l2-cache { 149 compatible = "cache"; 150 next-level-cache = <&L3_0>; 151 }; 152 }; 153 154 CPU4: cpu@400 { 155 device_type = "cpu"; 156 compatible = "arm,kryo"; 157 reg = <0x0 0x400>; 158 enable-method = "psci"; 159 cpu-idle-states = <&BIG_CPU_SLEEP_0 160 &BIG_CPU_SLEEP_1 161 &CLUSTER_SLEEP_0>; 162 next-level-cache = <&L2_400>; 163 qcom,freq-domain = <&cpufreq_hw 1>; 164 #cooling-cells = <2>; 165 L2_400: l2-cache { 166 compatible = "cache"; 167 next-level-cache = <&L3_0>; 168 }; 169 }; 170 171 CPU5: cpu@500 { 172 device_type = "cpu"; 173 compatible = "arm,kryo"; 174 reg = <0x0 0x500>; 175 enable-method = "psci"; 176 cpu-idle-states = <&BIG_CPU_SLEEP_0 177 &BIG_CPU_SLEEP_1 178 &CLUSTER_SLEEP_0>; 179 next-level-cache = <&L2_500>; 180 qcom,freq-domain = <&cpufreq_hw 1>; 181 #cooling-cells = <2>; 182 L2_500: l2-cache { 183 compatible = "cache"; 184 next-level-cache = <&L3_0>; 185 }; 186 }; 187 188 CPU6: cpu@600 { 189 device_type = "cpu"; 190 compatible = "arm,kryo"; 191 reg = <0x0 0x600>; 192 enable-method = "psci"; 193 cpu-idle-states = <&BIG_CPU_SLEEP_0 194 &BIG_CPU_SLEEP_1 195 &CLUSTER_SLEEP_0>; 196 next-level-cache = <&L2_600>; 197 qcom,freq-domain = <&cpufreq_hw 1>; 198 #cooling-cells = <2>; 199 L2_600: l2-cache { 200 compatible = "cache"; 201 next-level-cache = <&L3_0>; 202 }; 203 }; 204 205 CPU7: cpu@700 { 206 device_type = "cpu"; 207 compatible = "arm,kryo"; 208 reg = <0x0 0x700>; 209 enable-method = "psci"; 210 cpu-idle-states = <&BIG_CPU_SLEEP_0 211 &BIG_CPU_SLEEP_1 212 &CLUSTER_SLEEP_0>; 213 next-level-cache = <&L2_700>; 214 qcom,freq-domain = <&cpufreq_hw 2>; 215 #cooling-cells = <2>; 216 L2_700: l2-cache { 217 compatible = "cache"; 218 next-level-cache = <&L3_0>; 219 }; 220 }; 221 222 idle-states { 223 entry-method = "psci"; 224 225 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 226 compatible = "arm,idle-state"; 227 idle-state-name = "little-power-down"; 228 arm,psci-suspend-param = <0x40000003>; 229 entry-latency-us = <549>; 230 exit-latency-us = <901>; 231 min-residency-us = <1774>; 232 local-timer-stop; 233 }; 234 235 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 236 compatible = "arm,idle-state"; 237 idle-state-name = "little-rail-power-down"; 238 arm,psci-suspend-param = <0x40000004>; 239 entry-latency-us = <702>; 240 exit-latency-us = <915>; 241 min-residency-us = <4001>; 242 local-timer-stop; 243 }; 244 245 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 246 compatible = "arm,idle-state"; 247 idle-state-name = "big-power-down"; 248 arm,psci-suspend-param = <0x40000003>; 249 entry-latency-us = <523>; 250 exit-latency-us = <1244>; 251 min-residency-us = <2207>; 252 local-timer-stop; 253 }; 254 255 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 256 compatible = "arm,idle-state"; 257 idle-state-name = "big-rail-power-down"; 258 arm,psci-suspend-param = <0x40000004>; 259 entry-latency-us = <526>; 260 exit-latency-us = <1854>; 261 min-residency-us = <5555>; 262 local-timer-stop; 263 }; 264 265 CLUSTER_SLEEP_0: cluster-sleep-0 { 266 compatible = "arm,idle-state"; 267 idle-state-name = "cluster-power-down"; 268 arm,psci-suspend-param = <0x40003444>; 269 entry-latency-us = <3263>; 270 exit-latency-us = <6562>; 271 min-residency-us = <9926>; 272 local-timer-stop; 273 }; 274 }; 275 }; 276 277 memory@80000000 { 278 device_type = "memory"; 279 /* We expect the bootloader to fill in the size */ 280 reg = <0 0x80000000 0 0>; 281 }; 282 283 firmware { 284 scm { 285 compatible = "qcom,scm-sc7280", "qcom,scm"; 286 }; 287 }; 288 289 clk_virt: interconnect { 290 compatible = "qcom,sc7280-clk-virt"; 291 #interconnect-cells = <2>; 292 qcom,bcm-voters = <&apps_bcm_voter>; 293 }; 294 295 smem { 296 compatible = "qcom,smem"; 297 memory-region = <&smem_mem>; 298 hwlocks = <&tcsr_mutex 3>; 299 }; 300 301 smp2p-adsp { 302 compatible = "qcom,smp2p"; 303 qcom,smem = <443>, <429>; 304 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 305 IPCC_MPROC_SIGNAL_SMP2P 306 IRQ_TYPE_EDGE_RISING>; 307 mboxes = <&ipcc IPCC_CLIENT_LPASS 308 IPCC_MPROC_SIGNAL_SMP2P>; 309 310 qcom,local-pid = <0>; 311 qcom,remote-pid = <2>; 312 313 adsp_smp2p_out: master-kernel { 314 qcom,entry-name = "master-kernel"; 315 #qcom,smem-state-cells = <1>; 316 }; 317 318 adsp_smp2p_in: slave-kernel { 319 qcom,entry-name = "slave-kernel"; 320 interrupt-controller; 321 #interrupt-cells = <2>; 322 }; 323 }; 324 325 smp2p-cdsp { 326 compatible = "qcom,smp2p"; 327 qcom,smem = <94>, <432>; 328 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 329 IPCC_MPROC_SIGNAL_SMP2P 330 IRQ_TYPE_EDGE_RISING>; 331 mboxes = <&ipcc IPCC_CLIENT_CDSP 332 IPCC_MPROC_SIGNAL_SMP2P>; 333 334 qcom,local-pid = <0>; 335 qcom,remote-pid = <5>; 336 337 cdsp_smp2p_out: master-kernel { 338 qcom,entry-name = "master-kernel"; 339 #qcom,smem-state-cells = <1>; 340 }; 341 342 cdsp_smp2p_in: slave-kernel { 343 qcom,entry-name = "slave-kernel"; 344 interrupt-controller; 345 #interrupt-cells = <2>; 346 }; 347 }; 348 349 smp2p-mpss { 350 compatible = "qcom,smp2p"; 351 qcom,smem = <435>, <428>; 352 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 353 IPCC_MPROC_SIGNAL_SMP2P 354 IRQ_TYPE_EDGE_RISING>; 355 mboxes = <&ipcc IPCC_CLIENT_MPSS 356 IPCC_MPROC_SIGNAL_SMP2P>; 357 358 qcom,local-pid = <0>; 359 qcom,remote-pid = <1>; 360 361 modem_smp2p_out: master-kernel { 362 qcom,entry-name = "master-kernel"; 363 #qcom,smem-state-cells = <1>; 364 }; 365 366 modem_smp2p_in: slave-kernel { 367 qcom,entry-name = "slave-kernel"; 368 interrupt-controller; 369 #interrupt-cells = <2>; 370 }; 371 372 ipa_smp2p_out: ipa-ap-to-modem { 373 qcom,entry-name = "ipa"; 374 #qcom,smem-state-cells = <1>; 375 }; 376 377 ipa_smp2p_in: ipa-modem-to-ap { 378 qcom,entry-name = "ipa"; 379 interrupt-controller; 380 #interrupt-cells = <2>; 381 }; 382 }; 383 384 smp2p-wpss { 385 compatible = "qcom,smp2p"; 386 qcom,smem = <617>, <616>; 387 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 388 IPCC_MPROC_SIGNAL_SMP2P 389 IRQ_TYPE_EDGE_RISING>; 390 mboxes = <&ipcc IPCC_CLIENT_WPSS 391 IPCC_MPROC_SIGNAL_SMP2P>; 392 393 qcom,local-pid = <0>; 394 qcom,remote-pid = <13>; 395 396 wpss_smp2p_out: master-kernel { 397 qcom,entry-name = "master-kernel"; 398 #qcom,smem-state-cells = <1>; 399 }; 400 401 wpss_smp2p_in: slave-kernel { 402 qcom,entry-name = "slave-kernel"; 403 interrupt-controller; 404 #interrupt-cells = <2>; 405 }; 406 }; 407 408 pmu { 409 compatible = "arm,armv8-pmuv3"; 410 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 411 }; 412 413 psci { 414 compatible = "arm,psci-1.0"; 415 method = "smc"; 416 }; 417 418 soc: soc@0 { 419 #address-cells = <2>; 420 #size-cells = <2>; 421 ranges = <0 0 0 0 0x10 0>; 422 dma-ranges = <0 0 0 0 0x10 0>; 423 compatible = "simple-bus"; 424 425 gcc: clock-controller@100000 { 426 compatible = "qcom,gcc-sc7280"; 427 reg = <0 0x00100000 0 0x1f0000>; 428 clocks = <&rpmhcc RPMH_CXO_CLK>, 429 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 430 <0>, <0>, <0>, <0>, <0>, <0>; 431 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 432 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 433 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 434 "ufs_phy_tx_symbol_0_clk", 435 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 436 #clock-cells = <1>; 437 #reset-cells = <1>; 438 #power-domain-cells = <1>; 439 }; 440 441 ipcc: mailbox@408000 { 442 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 443 reg = <0 0x00408000 0 0x1000>; 444 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 445 interrupt-controller; 446 #interrupt-cells = <3>; 447 #mbox-cells = <2>; 448 }; 449 450 qfprom: efuse@784000 { 451 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 452 reg = <0 0x00784000 0 0xa20>, 453 <0 0x00780000 0 0xa20>, 454 <0 0x00782000 0 0x120>, 455 <0 0x00786000 0 0x1fff>; 456 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 457 clock-names = "core"; 458 power-domains = <&rpmhpd SC7280_MX>; 459 #address-cells = <1>; 460 #size-cells = <1>; 461 }; 462 463 sdhc_1: sdhci@7c4000 { 464 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 465 status = "disabled"; 466 467 reg = <0 0x007c4000 0 0x1000>, 468 <0 0x007c5000 0 0x1000>; 469 reg-names = "hc", "cqhci"; 470 471 iommus = <&apps_smmu 0xc0 0x0>; 472 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 474 interrupt-names = "hc_irq", "pwr_irq"; 475 476 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 477 <&gcc GCC_SDCC1_AHB_CLK>, 478 <&rpmhcc RPMH_CXO_CLK>; 479 clock-names = "core", "iface", "xo"; 480 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 481 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 482 interconnect-names = "sdhc-ddr","cpu-sdhc"; 483 power-domains = <&rpmhpd SC7280_CX>; 484 operating-points-v2 = <&sdhc1_opp_table>; 485 486 bus-width = <8>; 487 supports-cqe; 488 489 qcom,dll-config = <0x0007642c>; 490 qcom,ddr-config = <0x80040868>; 491 492 mmc-ddr-1_8v; 493 mmc-hs200-1_8v; 494 mmc-hs400-1_8v; 495 mmc-hs400-enhanced-strobe; 496 497 sdhc1_opp_table: opp-table { 498 compatible = "operating-points-v2"; 499 500 opp-100000000 { 501 opp-hz = /bits/ 64 <100000000>; 502 required-opps = <&rpmhpd_opp_low_svs>; 503 opp-peak-kBps = <1800000 400000>; 504 opp-avg-kBps = <100000 0>; 505 }; 506 507 opp-384000000 { 508 opp-hz = /bits/ 64 <384000000>; 509 required-opps = <&rpmhpd_opp_nom>; 510 opp-peak-kBps = <5400000 1600000>; 511 opp-avg-kBps = <390000 0>; 512 }; 513 }; 514 515 }; 516 517 qupv3_id_0: geniqup@9c0000 { 518 compatible = "qcom,geni-se-qup"; 519 reg = <0 0x009c0000 0 0x2000>; 520 clock-names = "m-ahb", "s-ahb"; 521 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 522 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 523 #address-cells = <2>; 524 #size-cells = <2>; 525 ranges; 526 status = "disabled"; 527 528 uart5: serial@994000 { 529 compatible = "qcom,geni-debug-uart"; 530 reg = <0 0x00994000 0 0x4000>; 531 clock-names = "se"; 532 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 533 pinctrl-names = "default"; 534 pinctrl-0 = <&qup_uart5_default>; 535 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 536 status = "disabled"; 537 }; 538 }; 539 540 cnoc2: interconnect@1500000 { 541 reg = <0 0x01500000 0 0x1000>; 542 compatible = "qcom,sc7280-cnoc2"; 543 #interconnect-cells = <2>; 544 qcom,bcm-voters = <&apps_bcm_voter>; 545 }; 546 547 cnoc3: interconnect@1502000 { 548 reg = <0 0x01502000 0 0x1000>; 549 compatible = "qcom,sc7280-cnoc3"; 550 #interconnect-cells = <2>; 551 qcom,bcm-voters = <&apps_bcm_voter>; 552 }; 553 554 mc_virt: interconnect@1580000 { 555 reg = <0 0x01580000 0 0x4>; 556 compatible = "qcom,sc7280-mc-virt"; 557 #interconnect-cells = <2>; 558 qcom,bcm-voters = <&apps_bcm_voter>; 559 }; 560 561 system_noc: interconnect@1680000 { 562 reg = <0 0x01680000 0 0x15480>; 563 compatible = "qcom,sc7280-system-noc"; 564 #interconnect-cells = <2>; 565 qcom,bcm-voters = <&apps_bcm_voter>; 566 }; 567 568 aggre1_noc: interconnect@16e0000 { 569 compatible = "qcom,sc7280-aggre1-noc"; 570 reg = <0 0x016e0000 0 0x1c080>; 571 #interconnect-cells = <2>; 572 qcom,bcm-voters = <&apps_bcm_voter>; 573 }; 574 575 aggre2_noc: interconnect@1700000 { 576 reg = <0 0x01700000 0 0x2b080>; 577 compatible = "qcom,sc7280-aggre2-noc"; 578 #interconnect-cells = <2>; 579 qcom,bcm-voters = <&apps_bcm_voter>; 580 }; 581 582 mmss_noc: interconnect@1740000 { 583 reg = <0 0x01740000 0 0x1e080>; 584 compatible = "qcom,sc7280-mmss-noc"; 585 #interconnect-cells = <2>; 586 qcom,bcm-voters = <&apps_bcm_voter>; 587 }; 588 589 ipa: ipa@1e40000 { 590 compatible = "qcom,sc7280-ipa"; 591 592 iommus = <&apps_smmu 0x480 0x0>, 593 <&apps_smmu 0x482 0x0>; 594 reg = <0 0x1e40000 0 0x8000>, 595 <0 0x1e50000 0 0x4ad0>, 596 <0 0x1e04000 0 0x23000>; 597 reg-names = "ipa-reg", 598 "ipa-shared", 599 "gsi"; 600 601 interrupts-extended = <&intc 0 654 IRQ_TYPE_EDGE_RISING>, 602 <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, 603 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 604 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 605 interrupt-names = "ipa", 606 "gsi", 607 "ipa-clock-query", 608 "ipa-setup-ready"; 609 610 clocks = <&rpmhcc RPMH_IPA_CLK>; 611 clock-names = "core"; 612 613 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 614 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 615 interconnect-names = "memory", 616 "config"; 617 618 qcom,smem-states = <&ipa_smp2p_out 0>, 619 <&ipa_smp2p_out 1>; 620 qcom,smem-state-names = "ipa-clock-enabled-valid", 621 "ipa-clock-enabled"; 622 623 status = "disabled"; 624 }; 625 626 tcsr_mutex: hwlock@1f40000 { 627 compatible = "qcom,tcsr-mutex", "syscon"; 628 reg = <0 0x01f40000 0 0x40000>; 629 #hwlock-cells = <1>; 630 }; 631 632 lpasscc: lpasscc@3000000 { 633 compatible = "qcom,sc7280-lpasscc"; 634 reg = <0 0x03000000 0 0x40>, 635 <0 0x03c04000 0 0x4>, 636 <0 0x03389000 0 0x24>; 637 reg-names = "qdsp6ss", "top_cc", "cc"; 638 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 639 clock-names = "iface"; 640 #clock-cells = <1>; 641 }; 642 643 lpass_ag_noc: interconnect@3c40000 { 644 reg = <0 0x03c40000 0 0xf080>; 645 compatible = "qcom,sc7280-lpass-ag-noc"; 646 #interconnect-cells = <2>; 647 qcom,bcm-voters = <&apps_bcm_voter>; 648 }; 649 650 gpucc: clock-controller@3d90000 { 651 compatible = "qcom,sc7280-gpucc"; 652 reg = <0 0x03d90000 0 0x9000>; 653 clocks = <&rpmhcc RPMH_CXO_CLK>, 654 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 655 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 656 clock-names = "bi_tcxo", 657 "gcc_gpu_gpll0_clk_src", 658 "gcc_gpu_gpll0_div_clk_src"; 659 #clock-cells = <1>; 660 #reset-cells = <1>; 661 #power-domain-cells = <1>; 662 }; 663 664 stm@6002000 { 665 compatible = "arm,coresight-stm", "arm,primecell"; 666 reg = <0 0x06002000 0 0x1000>, 667 <0 0x16280000 0 0x180000>; 668 reg-names = "stm-base", "stm-stimulus-base"; 669 670 clocks = <&aoss_qmp>; 671 clock-names = "apb_pclk"; 672 673 out-ports { 674 port { 675 stm_out: endpoint { 676 remote-endpoint = <&funnel0_in7>; 677 }; 678 }; 679 }; 680 }; 681 682 funnel@6041000 { 683 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 684 reg = <0 0x06041000 0 0x1000>; 685 686 clocks = <&aoss_qmp>; 687 clock-names = "apb_pclk"; 688 689 out-ports { 690 port { 691 funnel0_out: endpoint { 692 remote-endpoint = <&merge_funnel_in0>; 693 }; 694 }; 695 }; 696 697 in-ports { 698 #address-cells = <1>; 699 #size-cells = <0>; 700 701 port@7 { 702 reg = <7>; 703 funnel0_in7: endpoint { 704 remote-endpoint = <&stm_out>; 705 }; 706 }; 707 }; 708 }; 709 710 funnel@6042000 { 711 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 712 reg = <0 0x06042000 0 0x1000>; 713 714 clocks = <&aoss_qmp>; 715 clock-names = "apb_pclk"; 716 717 out-ports { 718 port { 719 funnel1_out: endpoint { 720 remote-endpoint = <&merge_funnel_in1>; 721 }; 722 }; 723 }; 724 725 in-ports { 726 #address-cells = <1>; 727 #size-cells = <0>; 728 729 port@4 { 730 reg = <4>; 731 funnel1_in4: endpoint { 732 remote-endpoint = <&apss_merge_funnel_out>; 733 }; 734 }; 735 }; 736 }; 737 738 funnel@6045000 { 739 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 740 reg = <0 0x06045000 0 0x1000>; 741 742 clocks = <&aoss_qmp>; 743 clock-names = "apb_pclk"; 744 745 out-ports { 746 port { 747 merge_funnel_out: endpoint { 748 remote-endpoint = <&swao_funnel_in>; 749 }; 750 }; 751 }; 752 753 in-ports { 754 #address-cells = <1>; 755 #size-cells = <0>; 756 757 port@0 { 758 reg = <0>; 759 merge_funnel_in0: endpoint { 760 remote-endpoint = <&funnel0_out>; 761 }; 762 }; 763 764 port@1 { 765 reg = <1>; 766 merge_funnel_in1: endpoint { 767 remote-endpoint = <&funnel1_out>; 768 }; 769 }; 770 }; 771 }; 772 773 replicator@6046000 { 774 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 775 reg = <0 0x06046000 0 0x1000>; 776 777 clocks = <&aoss_qmp>; 778 clock-names = "apb_pclk"; 779 780 out-ports { 781 port { 782 replicator_out: endpoint { 783 remote-endpoint = <&etr_in>; 784 }; 785 }; 786 }; 787 788 in-ports { 789 port { 790 replicator_in: endpoint { 791 remote-endpoint = <&swao_replicator_out>; 792 }; 793 }; 794 }; 795 }; 796 797 etr@6048000 { 798 compatible = "arm,coresight-tmc", "arm,primecell"; 799 reg = <0 0x06048000 0 0x1000>; 800 iommus = <&apps_smmu 0x04c0 0>; 801 802 clocks = <&aoss_qmp>; 803 clock-names = "apb_pclk"; 804 arm,scatter-gather; 805 806 in-ports { 807 port { 808 etr_in: endpoint { 809 remote-endpoint = <&replicator_out>; 810 }; 811 }; 812 }; 813 }; 814 815 funnel@6b04000 { 816 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 817 reg = <0 0x06b04000 0 0x1000>; 818 819 clocks = <&aoss_qmp>; 820 clock-names = "apb_pclk"; 821 822 out-ports { 823 port { 824 swao_funnel_out: endpoint { 825 remote-endpoint = <&etf_in>; 826 }; 827 }; 828 }; 829 830 in-ports { 831 #address-cells = <1>; 832 #size-cells = <0>; 833 834 port@7 { 835 reg = <7>; 836 swao_funnel_in: endpoint { 837 remote-endpoint = <&merge_funnel_out>; 838 }; 839 }; 840 }; 841 }; 842 843 etf@6b05000 { 844 compatible = "arm,coresight-tmc", "arm,primecell"; 845 reg = <0 0x06b05000 0 0x1000>; 846 847 clocks = <&aoss_qmp>; 848 clock-names = "apb_pclk"; 849 850 out-ports { 851 port { 852 etf_out: endpoint { 853 remote-endpoint = <&swao_replicator_in>; 854 }; 855 }; 856 }; 857 858 in-ports { 859 port { 860 etf_in: endpoint { 861 remote-endpoint = <&swao_funnel_out>; 862 }; 863 }; 864 }; 865 }; 866 867 replicator@6b06000 { 868 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 869 reg = <0 0x06b06000 0 0x1000>; 870 871 clocks = <&aoss_qmp>; 872 clock-names = "apb_pclk"; 873 qcom,replicator-loses-context; 874 875 out-ports { 876 port { 877 swao_replicator_out: endpoint { 878 remote-endpoint = <&replicator_in>; 879 }; 880 }; 881 }; 882 883 in-ports { 884 port { 885 swao_replicator_in: endpoint { 886 remote-endpoint = <&etf_out>; 887 }; 888 }; 889 }; 890 }; 891 892 etm@7040000 { 893 compatible = "arm,coresight-etm4x", "arm,primecell"; 894 reg = <0 0x07040000 0 0x1000>; 895 896 cpu = <&CPU0>; 897 898 clocks = <&aoss_qmp>; 899 clock-names = "apb_pclk"; 900 arm,coresight-loses-context-with-cpu; 901 qcom,skip-power-up; 902 903 out-ports { 904 port { 905 etm0_out: endpoint { 906 remote-endpoint = <&apss_funnel_in0>; 907 }; 908 }; 909 }; 910 }; 911 912 etm@7140000 { 913 compatible = "arm,coresight-etm4x", "arm,primecell"; 914 reg = <0 0x07140000 0 0x1000>; 915 916 cpu = <&CPU1>; 917 918 clocks = <&aoss_qmp>; 919 clock-names = "apb_pclk"; 920 arm,coresight-loses-context-with-cpu; 921 qcom,skip-power-up; 922 923 out-ports { 924 port { 925 etm1_out: endpoint { 926 remote-endpoint = <&apss_funnel_in1>; 927 }; 928 }; 929 }; 930 }; 931 932 etm@7240000 { 933 compatible = "arm,coresight-etm4x", "arm,primecell"; 934 reg = <0 0x07240000 0 0x1000>; 935 936 cpu = <&CPU2>; 937 938 clocks = <&aoss_qmp>; 939 clock-names = "apb_pclk"; 940 arm,coresight-loses-context-with-cpu; 941 qcom,skip-power-up; 942 943 out-ports { 944 port { 945 etm2_out: endpoint { 946 remote-endpoint = <&apss_funnel_in2>; 947 }; 948 }; 949 }; 950 }; 951 952 etm@7340000 { 953 compatible = "arm,coresight-etm4x", "arm,primecell"; 954 reg = <0 0x07340000 0 0x1000>; 955 956 cpu = <&CPU3>; 957 958 clocks = <&aoss_qmp>; 959 clock-names = "apb_pclk"; 960 arm,coresight-loses-context-with-cpu; 961 qcom,skip-power-up; 962 963 out-ports { 964 port { 965 etm3_out: endpoint { 966 remote-endpoint = <&apss_funnel_in3>; 967 }; 968 }; 969 }; 970 }; 971 972 etm@7440000 { 973 compatible = "arm,coresight-etm4x", "arm,primecell"; 974 reg = <0 0x07440000 0 0x1000>; 975 976 cpu = <&CPU4>; 977 978 clocks = <&aoss_qmp>; 979 clock-names = "apb_pclk"; 980 arm,coresight-loses-context-with-cpu; 981 qcom,skip-power-up; 982 983 out-ports { 984 port { 985 etm4_out: endpoint { 986 remote-endpoint = <&apss_funnel_in4>; 987 }; 988 }; 989 }; 990 }; 991 992 etm@7540000 { 993 compatible = "arm,coresight-etm4x", "arm,primecell"; 994 reg = <0 0x07540000 0 0x1000>; 995 996 cpu = <&CPU5>; 997 998 clocks = <&aoss_qmp>; 999 clock-names = "apb_pclk"; 1000 arm,coresight-loses-context-with-cpu; 1001 qcom,skip-power-up; 1002 1003 out-ports { 1004 port { 1005 etm5_out: endpoint { 1006 remote-endpoint = <&apss_funnel_in5>; 1007 }; 1008 }; 1009 }; 1010 }; 1011 1012 etm@7640000 { 1013 compatible = "arm,coresight-etm4x", "arm,primecell"; 1014 reg = <0 0x07640000 0 0x1000>; 1015 1016 cpu = <&CPU6>; 1017 1018 clocks = <&aoss_qmp>; 1019 clock-names = "apb_pclk"; 1020 arm,coresight-loses-context-with-cpu; 1021 qcom,skip-power-up; 1022 1023 out-ports { 1024 port { 1025 etm6_out: endpoint { 1026 remote-endpoint = <&apss_funnel_in6>; 1027 }; 1028 }; 1029 }; 1030 }; 1031 1032 etm@7740000 { 1033 compatible = "arm,coresight-etm4x", "arm,primecell"; 1034 reg = <0 0x07740000 0 0x1000>; 1035 1036 cpu = <&CPU7>; 1037 1038 clocks = <&aoss_qmp>; 1039 clock-names = "apb_pclk"; 1040 arm,coresight-loses-context-with-cpu; 1041 qcom,skip-power-up; 1042 1043 out-ports { 1044 port { 1045 etm7_out: endpoint { 1046 remote-endpoint = <&apss_funnel_in7>; 1047 }; 1048 }; 1049 }; 1050 }; 1051 1052 funnel@7800000 { /* APSS Funnel */ 1053 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1054 reg = <0 0x07800000 0 0x1000>; 1055 1056 clocks = <&aoss_qmp>; 1057 clock-names = "apb_pclk"; 1058 1059 out-ports { 1060 port { 1061 apss_funnel_out: endpoint { 1062 remote-endpoint = <&apss_merge_funnel_in>; 1063 }; 1064 }; 1065 }; 1066 1067 in-ports { 1068 #address-cells = <1>; 1069 #size-cells = <0>; 1070 1071 port@0 { 1072 reg = <0>; 1073 apss_funnel_in0: endpoint { 1074 remote-endpoint = <&etm0_out>; 1075 }; 1076 }; 1077 1078 port@1 { 1079 reg = <1>; 1080 apss_funnel_in1: endpoint { 1081 remote-endpoint = <&etm1_out>; 1082 }; 1083 }; 1084 1085 port@2 { 1086 reg = <2>; 1087 apss_funnel_in2: endpoint { 1088 remote-endpoint = <&etm2_out>; 1089 }; 1090 }; 1091 1092 port@3 { 1093 reg = <3>; 1094 apss_funnel_in3: endpoint { 1095 remote-endpoint = <&etm3_out>; 1096 }; 1097 }; 1098 1099 port@4 { 1100 reg = <4>; 1101 apss_funnel_in4: endpoint { 1102 remote-endpoint = <&etm4_out>; 1103 }; 1104 }; 1105 1106 port@5 { 1107 reg = <5>; 1108 apss_funnel_in5: endpoint { 1109 remote-endpoint = <&etm5_out>; 1110 }; 1111 }; 1112 1113 port@6 { 1114 reg = <6>; 1115 apss_funnel_in6: endpoint { 1116 remote-endpoint = <&etm6_out>; 1117 }; 1118 }; 1119 1120 port@7 { 1121 reg = <7>; 1122 apss_funnel_in7: endpoint { 1123 remote-endpoint = <&etm7_out>; 1124 }; 1125 }; 1126 }; 1127 }; 1128 1129 funnel@7810000 { 1130 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1131 reg = <0 0x07810000 0 0x1000>; 1132 1133 clocks = <&aoss_qmp>; 1134 clock-names = "apb_pclk"; 1135 1136 out-ports { 1137 port { 1138 apss_merge_funnel_out: endpoint { 1139 remote-endpoint = <&funnel1_in4>; 1140 }; 1141 }; 1142 }; 1143 1144 in-ports { 1145 port { 1146 apss_merge_funnel_in: endpoint { 1147 remote-endpoint = <&apss_funnel_out>; 1148 }; 1149 }; 1150 }; 1151 }; 1152 1153 sdhc_2: sdhci@8804000 { 1154 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 1155 status = "disabled"; 1156 1157 reg = <0 0x08804000 0 0x1000>; 1158 1159 iommus = <&apps_smmu 0x100 0x0>; 1160 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1162 interrupt-names = "hc_irq", "pwr_irq"; 1163 1164 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 1165 <&gcc GCC_SDCC2_AHB_CLK>, 1166 <&rpmhcc RPMH_CXO_CLK>; 1167 clock-names = "core", "iface", "xo"; 1168 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 1169 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 1170 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1171 power-domains = <&rpmhpd SC7280_CX>; 1172 operating-points-v2 = <&sdhc2_opp_table>; 1173 1174 bus-width = <4>; 1175 1176 qcom,dll-config = <0x0007642c>; 1177 1178 sdhc2_opp_table: opp-table { 1179 compatible = "operating-points-v2"; 1180 1181 opp-100000000 { 1182 opp-hz = /bits/ 64 <100000000>; 1183 required-opps = <&rpmhpd_opp_low_svs>; 1184 opp-peak-kBps = <1800000 400000>; 1185 opp-avg-kBps = <100000 0>; 1186 }; 1187 1188 opp-202000000 { 1189 opp-hz = /bits/ 64 <202000000>; 1190 required-opps = <&rpmhpd_opp_nom>; 1191 opp-peak-kBps = <5400000 1600000>; 1192 opp-avg-kBps = <200000 0>; 1193 }; 1194 }; 1195 1196 }; 1197 1198 usb_1_hsphy: phy@88e3000 { 1199 compatible = "qcom,sc7280-usb-hs-phy", 1200 "qcom,usb-snps-hs-7nm-phy"; 1201 reg = <0 0x088e3000 0 0x400>; 1202 status = "disabled"; 1203 #phy-cells = <0>; 1204 1205 clocks = <&rpmhcc RPMH_CXO_CLK>; 1206 clock-names = "ref"; 1207 1208 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1209 }; 1210 1211 usb_2_hsphy: phy@88e4000 { 1212 compatible = "qcom,sc7280-usb-hs-phy", 1213 "qcom,usb-snps-hs-7nm-phy"; 1214 reg = <0 0x088e4000 0 0x400>; 1215 status = "disabled"; 1216 #phy-cells = <0>; 1217 1218 clocks = <&rpmhcc RPMH_CXO_CLK>; 1219 clock-names = "ref"; 1220 1221 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1222 }; 1223 1224 usb_1_qmpphy: phy-wrapper@88e9000 { 1225 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 1226 "qcom,sm8250-qmp-usb3-dp-phy"; 1227 reg = <0 0x088e9000 0 0x200>, 1228 <0 0x088e8000 0 0x40>, 1229 <0 0x088ea000 0 0x200>; 1230 status = "disabled"; 1231 #address-cells = <2>; 1232 #size-cells = <2>; 1233 ranges; 1234 1235 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1236 <&rpmhcc RPMH_CXO_CLK>, 1237 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1238 clock-names = "aux", "ref_clk_src", "com_aux"; 1239 1240 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 1241 <&gcc GCC_USB3_PHY_PRIM_BCR>; 1242 reset-names = "phy", "common"; 1243 1244 usb_1_ssphy: usb3-phy@88e9200 { 1245 reg = <0 0x088e9200 0 0x200>, 1246 <0 0x088e9400 0 0x200>, 1247 <0 0x088e9c00 0 0x400>, 1248 <0 0x088e9600 0 0x200>, 1249 <0 0x088e9800 0 0x200>, 1250 <0 0x088e9a00 0 0x100>; 1251 #clock-cells = <0>; 1252 #phy-cells = <0>; 1253 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1254 clock-names = "pipe0"; 1255 clock-output-names = "usb3_phy_pipe_clk_src"; 1256 }; 1257 1258 dp_phy: dp-phy@88ea200 { 1259 reg = <0 0x088ea200 0 0x200>, 1260 <0 0x088ea400 0 0x200>, 1261 <0 0x088eaa00 0 0x200>, 1262 <0 0x088ea600 0 0x200>, 1263 <0 0x088ea800 0 0x200>; 1264 #phy-cells = <0>; 1265 #clock-cells = <1>; 1266 }; 1267 }; 1268 1269 usb_2: usb@8cf8800 { 1270 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 1271 reg = <0 0x08cf8800 0 0x400>; 1272 status = "disabled"; 1273 #address-cells = <2>; 1274 #size-cells = <2>; 1275 ranges; 1276 dma-ranges; 1277 1278 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 1279 <&gcc GCC_USB30_SEC_MASTER_CLK>, 1280 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 1281 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1282 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 1283 clock-names = "cfg_noc", "core", "iface","mock_utmi", 1284 "sleep"; 1285 1286 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1287 <&gcc GCC_USB30_SEC_MASTER_CLK>; 1288 assigned-clock-rates = <19200000>, <200000000>; 1289 1290 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1291 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 1292 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 1293 interrupt-names = "hs_phy_irq", 1294 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1295 1296 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 1297 1298 resets = <&gcc GCC_USB30_SEC_BCR>; 1299 1300 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 1301 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 1302 interconnect-names = "usb-ddr", "apps-usb"; 1303 1304 usb_2_dwc3: usb@8c00000 { 1305 compatible = "snps,dwc3"; 1306 reg = <0 0x08c00000 0 0xe000>; 1307 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1308 iommus = <&apps_smmu 0xa0 0x0>; 1309 snps,dis_u2_susphy_quirk; 1310 snps,dis_enblslpm_quirk; 1311 phys = <&usb_2_hsphy>; 1312 phy-names = "usb2-phy"; 1313 maximum-speed = "high-speed"; 1314 }; 1315 }; 1316 1317 dc_noc: interconnect@90e0000 { 1318 reg = <0 0x090e0000 0 0x5080>; 1319 compatible = "qcom,sc7280-dc-noc"; 1320 #interconnect-cells = <2>; 1321 qcom,bcm-voters = <&apps_bcm_voter>; 1322 }; 1323 1324 gem_noc: interconnect@9100000 { 1325 reg = <0 0x9100000 0 0xe2200>; 1326 compatible = "qcom,sc7280-gem-noc"; 1327 #interconnect-cells = <2>; 1328 qcom,bcm-voters = <&apps_bcm_voter>; 1329 }; 1330 1331 system-cache-controller@9200000 { 1332 compatible = "qcom,sc7280-llcc"; 1333 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 1334 reg-names = "llcc_base", "llcc_broadcast_base"; 1335 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1336 }; 1337 1338 nsp_noc: interconnect@a0c0000 { 1339 reg = <0 0x0a0c0000 0 0x10000>; 1340 compatible = "qcom,sc7280-nsp-noc"; 1341 #interconnect-cells = <2>; 1342 qcom,bcm-voters = <&apps_bcm_voter>; 1343 }; 1344 1345 usb_1: usb@a6f8800 { 1346 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 1347 reg = <0 0x0a6f8800 0 0x400>; 1348 status = "disabled"; 1349 #address-cells = <2>; 1350 #size-cells = <2>; 1351 ranges; 1352 dma-ranges; 1353 1354 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1355 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1356 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1357 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1358 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 1359 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1360 "sleep"; 1361 1362 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1363 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1364 assigned-clock-rates = <19200000>, <200000000>; 1365 1366 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1367 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1368 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1369 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 1370 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 1371 "dm_hs_phy_irq", "ss_phy_irq"; 1372 1373 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1374 1375 resets = <&gcc GCC_USB30_PRIM_BCR>; 1376 1377 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 1378 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 1379 interconnect-names = "usb-ddr", "apps-usb"; 1380 1381 usb_1_dwc3: usb@a600000 { 1382 compatible = "snps,dwc3"; 1383 reg = <0 0x0a600000 0 0xe000>; 1384 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1385 iommus = <&apps_smmu 0xe0 0x0>; 1386 snps,dis_u2_susphy_quirk; 1387 snps,dis_enblslpm_quirk; 1388 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1389 phy-names = "usb2-phy", "usb3-phy"; 1390 maximum-speed = "super-speed"; 1391 }; 1392 }; 1393 1394 videocc: clock-controller@aaf0000 { 1395 compatible = "qcom,sc7280-videocc"; 1396 reg = <0 0xaaf0000 0 0x10000>; 1397 clocks = <&rpmhcc RPMH_CXO_CLK>, 1398 <&rpmhcc RPMH_CXO_CLK_A>; 1399 clock-names = "bi_tcxo", "bi_tcxo_ao"; 1400 #clock-cells = <1>; 1401 #reset-cells = <1>; 1402 #power-domain-cells = <1>; 1403 }; 1404 1405 dispcc: clock-controller@af00000 { 1406 compatible = "qcom,sc7280-dispcc"; 1407 reg = <0 0xaf00000 0 0x20000>; 1408 clocks = <&rpmhcc RPMH_CXO_CLK>, 1409 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 1410 <0>, <0>, <0>, <0>, <0>, <0>; 1411 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 1412 "dsi0_phy_pll_out_byteclk", 1413 "dsi0_phy_pll_out_dsiclk", 1414 "dp_phy_pll_link_clk", 1415 "dp_phy_pll_vco_div_clk", 1416 "edp_phy_pll_link_clk", 1417 "edp_phy_pll_vco_div_clk"; 1418 #clock-cells = <1>; 1419 #reset-cells = <1>; 1420 #power-domain-cells = <1>; 1421 }; 1422 1423 pdc: interrupt-controller@b220000 { 1424 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 1425 reg = <0 0x0b220000 0 0x30000>; 1426 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 1427 <55 306 4>, <59 312 3>, <62 374 2>, 1428 <64 434 2>, <66 438 3>, <69 86 1>, 1429 <70 520 54>, <124 609 31>, <155 63 1>, 1430 <156 716 12>; 1431 #interrupt-cells = <2>; 1432 interrupt-parent = <&intc>; 1433 interrupt-controller; 1434 }; 1435 1436 pdc_reset: reset-controller@b5e0000 { 1437 compatible = "qcom,sc7280-pdc-global"; 1438 reg = <0 0x0b5e0000 0 0x20000>; 1439 #reset-cells = <1>; 1440 }; 1441 1442 tsens0: thermal-sensor@c263000 { 1443 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 1444 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1445 <0 0x0c222000 0 0x1ff>; /* SROT */ 1446 #qcom,sensors = <15>; 1447 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1449 interrupt-names = "uplow","critical"; 1450 #thermal-sensor-cells = <1>; 1451 }; 1452 1453 tsens1: thermal-sensor@c265000 { 1454 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 1455 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1456 <0 0x0c223000 0 0x1ff>; /* SROT */ 1457 #qcom,sensors = <12>; 1458 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1460 interrupt-names = "uplow","critical"; 1461 #thermal-sensor-cells = <1>; 1462 }; 1463 1464 aoss_reset: reset-controller@c2a0000 { 1465 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 1466 reg = <0 0x0c2a0000 0 0x31000>; 1467 #reset-cells = <1>; 1468 }; 1469 1470 aoss_qmp: power-controller@c300000 { 1471 compatible = "qcom,sc7280-aoss-qmp"; 1472 reg = <0 0x0c300000 0 0x100000>; 1473 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 1474 IPCC_MPROC_SIGNAL_GLINK_QMP 1475 IRQ_TYPE_EDGE_RISING>; 1476 mboxes = <&ipcc IPCC_CLIENT_AOP 1477 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1478 1479 #clock-cells = <0>; 1480 #power-domain-cells = <1>; 1481 }; 1482 1483 spmi_bus: spmi@c440000 { 1484 compatible = "qcom,spmi-pmic-arb"; 1485 reg = <0 0x0c440000 0 0x1100>, 1486 <0 0x0c600000 0 0x2000000>, 1487 <0 0x0e600000 0 0x100000>, 1488 <0 0x0e700000 0 0xa0000>, 1489 <0 0x0c40a000 0 0x26000>; 1490 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1491 interrupt-names = "periph_irq"; 1492 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1493 qcom,ee = <0>; 1494 qcom,channel = <0>; 1495 #address-cells = <1>; 1496 #size-cells = <1>; 1497 interrupt-controller; 1498 #interrupt-cells = <4>; 1499 }; 1500 1501 tlmm: pinctrl@f100000 { 1502 compatible = "qcom,sc7280-pinctrl"; 1503 reg = <0 0x0f100000 0 0x300000>; 1504 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1505 gpio-controller; 1506 #gpio-cells = <2>; 1507 interrupt-controller; 1508 #interrupt-cells = <2>; 1509 gpio-ranges = <&tlmm 0 0 175>; 1510 wakeup-parent = <&pdc>; 1511 1512 qup_uart5_default: qup-uart5-default { 1513 pins = "gpio46", "gpio47"; 1514 function = "qup13"; 1515 }; 1516 1517 sdc1_on: sdc1-on { 1518 clk { 1519 pins = "sdc1_clk"; 1520 }; 1521 1522 cmd { 1523 pins = "sdc1_cmd"; 1524 }; 1525 1526 data { 1527 pins = "sdc1_data"; 1528 }; 1529 1530 rclk { 1531 pins = "sdc1_rclk"; 1532 }; 1533 }; 1534 1535 sdc1_off: sdc1-off { 1536 clk { 1537 pins = "sdc1_clk"; 1538 drive-strength = <2>; 1539 bias-bus-hold; 1540 }; 1541 1542 cmd { 1543 pins = "sdc1_cmd"; 1544 drive-strength = <2>; 1545 bias-bus-hold; 1546 }; 1547 1548 data { 1549 pins = "sdc1_data"; 1550 drive-strength = <2>; 1551 bias-bus-hold; 1552 }; 1553 1554 rclk { 1555 pins = "sdc1_rclk"; 1556 bias-bus-hold; 1557 }; 1558 }; 1559 1560 sdc2_on: sdc2-on { 1561 clk { 1562 pins = "sdc2_clk"; 1563 }; 1564 1565 cmd { 1566 pins = "sdc2_cmd"; 1567 }; 1568 1569 data { 1570 pins = "sdc2_data"; 1571 }; 1572 1573 sd-cd { 1574 pins = "gpio91"; 1575 }; 1576 }; 1577 1578 sdc2_off: sdc2-off { 1579 clk { 1580 pins = "sdc2_clk"; 1581 drive-strength = <2>; 1582 bias-bus-hold; 1583 }; 1584 1585 cmd { 1586 pins ="sdc2_cmd"; 1587 drive-strength = <2>; 1588 bias-bus-hold; 1589 }; 1590 1591 data { 1592 pins ="sdc2_data"; 1593 drive-strength = <2>; 1594 bias-bus-hold; 1595 }; 1596 }; 1597 }; 1598 1599 apps_smmu: iommu@15000000 { 1600 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 1601 reg = <0 0x15000000 0 0x100000>; 1602 #iommu-cells = <2>; 1603 #global-interrupts = <1>; 1604 dma-coherent; 1605 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1617 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1621 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1622 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1623 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1626 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1651 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1652 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1655 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1656 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1657 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1658 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1659 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1660 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1661 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1662 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1663 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1665 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1666 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1667 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1668 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1669 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1670 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1672 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1673 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1674 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1675 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1676 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1677 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1680 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1681 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1682 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1683 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1684 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1685 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1686 }; 1687 1688 intc: interrupt-controller@17a00000 { 1689 compatible = "arm,gic-v3"; 1690 #address-cells = <2>; 1691 #size-cells = <2>; 1692 ranges; 1693 #interrupt-cells = <3>; 1694 interrupt-controller; 1695 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 1696 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 1697 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 1698 1699 gic-its@17a40000 { 1700 compatible = "arm,gic-v3-its"; 1701 msi-controller; 1702 #msi-cells = <1>; 1703 reg = <0 0x17a40000 0 0x20000>; 1704 status = "disabled"; 1705 }; 1706 }; 1707 1708 watchdog@17c10000 { 1709 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 1710 reg = <0 0x17c10000 0 0x1000>; 1711 clocks = <&sleep_clk>; 1712 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1713 }; 1714 1715 timer@17c20000 { 1716 #address-cells = <2>; 1717 #size-cells = <2>; 1718 ranges; 1719 compatible = "arm,armv7-timer-mem"; 1720 reg = <0 0x17c20000 0 0x1000>; 1721 1722 frame@17c21000 { 1723 frame-number = <0>; 1724 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1726 reg = <0 0x17c21000 0 0x1000>, 1727 <0 0x17c22000 0 0x1000>; 1728 }; 1729 1730 frame@17c23000 { 1731 frame-number = <1>; 1732 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1733 reg = <0 0x17c23000 0 0x1000>; 1734 status = "disabled"; 1735 }; 1736 1737 frame@17c25000 { 1738 frame-number = <2>; 1739 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1740 reg = <0 0x17c25000 0 0x1000>; 1741 status = "disabled"; 1742 }; 1743 1744 frame@17c27000 { 1745 frame-number = <3>; 1746 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1747 reg = <0 0x17c27000 0 0x1000>; 1748 status = "disabled"; 1749 }; 1750 1751 frame@17c29000 { 1752 frame-number = <4>; 1753 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1754 reg = <0 0x17c29000 0 0x1000>; 1755 status = "disabled"; 1756 }; 1757 1758 frame@17c2b000 { 1759 frame-number = <5>; 1760 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1761 reg = <0 0x17c2b000 0 0x1000>; 1762 status = "disabled"; 1763 }; 1764 1765 frame@17c2d000 { 1766 frame-number = <6>; 1767 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1768 reg = <0 0x17c2d000 0 0x1000>; 1769 status = "disabled"; 1770 }; 1771 }; 1772 1773 apps_rsc: rsc@18200000 { 1774 compatible = "qcom,rpmh-rsc"; 1775 reg = <0 0x18200000 0 0x10000>, 1776 <0 0x18210000 0 0x10000>, 1777 <0 0x18220000 0 0x10000>; 1778 reg-names = "drv-0", "drv-1", "drv-2"; 1779 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1782 qcom,tcs-offset = <0xd00>; 1783 qcom,drv-id = <2>; 1784 qcom,tcs-config = <ACTIVE_TCS 2>, 1785 <SLEEP_TCS 3>, 1786 <WAKE_TCS 3>, 1787 <CONTROL_TCS 1>; 1788 1789 apps_bcm_voter: bcm-voter { 1790 compatible = "qcom,bcm-voter"; 1791 }; 1792 1793 rpmhpd: power-controller { 1794 compatible = "qcom,sc7280-rpmhpd"; 1795 #power-domain-cells = <1>; 1796 operating-points-v2 = <&rpmhpd_opp_table>; 1797 1798 rpmhpd_opp_table: opp-table { 1799 compatible = "operating-points-v2"; 1800 1801 rpmhpd_opp_ret: opp1 { 1802 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1803 }; 1804 1805 rpmhpd_opp_low_svs: opp2 { 1806 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1807 }; 1808 1809 rpmhpd_opp_svs: opp3 { 1810 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1811 }; 1812 1813 rpmhpd_opp_svs_l1: opp4 { 1814 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1815 }; 1816 1817 rpmhpd_opp_svs_l2: opp5 { 1818 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1819 }; 1820 1821 rpmhpd_opp_nom: opp6 { 1822 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1823 }; 1824 1825 rpmhpd_opp_nom_l1: opp7 { 1826 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1827 }; 1828 1829 rpmhpd_opp_turbo: opp8 { 1830 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1831 }; 1832 1833 rpmhpd_opp_turbo_l1: opp9 { 1834 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1835 }; 1836 }; 1837 }; 1838 1839 rpmhcc: clock-controller { 1840 compatible = "qcom,sc7280-rpmh-clk"; 1841 clocks = <&xo_board>; 1842 clock-names = "xo"; 1843 #clock-cells = <1>; 1844 }; 1845 }; 1846 1847 cpufreq_hw: cpufreq@18591000 { 1848 compatible = "qcom,cpufreq-epss"; 1849 reg = <0 0x18591100 0 0x900>, 1850 <0 0x18592100 0 0x900>, 1851 <0 0x18593100 0 0x900>; 1852 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 1853 clock-names = "xo", "alternate"; 1854 #freq-domain-cells = <1>; 1855 }; 1856 }; 1857 1858 thermal_zones: thermal-zones { 1859 cpu0-thermal { 1860 polling-delay-passive = <250>; 1861 polling-delay = <0>; 1862 1863 thermal-sensors = <&tsens0 1>; 1864 1865 trips { 1866 cpu0_alert0: trip-point0 { 1867 temperature = <90000>; 1868 hysteresis = <2000>; 1869 type = "passive"; 1870 }; 1871 1872 cpu0_alert1: trip-point1 { 1873 temperature = <95000>; 1874 hysteresis = <2000>; 1875 type = "passive"; 1876 }; 1877 1878 cpu0_crit: cpu-crit { 1879 temperature = <110000>; 1880 hysteresis = <0>; 1881 type = "critical"; 1882 }; 1883 }; 1884 1885 cooling-maps { 1886 map0 { 1887 trip = <&cpu0_alert0>; 1888 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1889 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1890 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1891 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1892 }; 1893 map1 { 1894 trip = <&cpu0_alert1>; 1895 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1896 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1897 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1898 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1899 }; 1900 }; 1901 }; 1902 1903 cpu1-thermal { 1904 polling-delay-passive = <250>; 1905 polling-delay = <0>; 1906 1907 thermal-sensors = <&tsens0 2>; 1908 1909 trips { 1910 cpu1_alert0: trip-point0 { 1911 temperature = <90000>; 1912 hysteresis = <2000>; 1913 type = "passive"; 1914 }; 1915 1916 cpu1_alert1: trip-point1 { 1917 temperature = <95000>; 1918 hysteresis = <2000>; 1919 type = "passive"; 1920 }; 1921 1922 cpu1_crit: cpu-crit { 1923 temperature = <110000>; 1924 hysteresis = <0>; 1925 type = "critical"; 1926 }; 1927 }; 1928 1929 cooling-maps { 1930 map0 { 1931 trip = <&cpu1_alert0>; 1932 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1933 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1934 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1935 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1936 }; 1937 map1 { 1938 trip = <&cpu1_alert1>; 1939 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1940 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1941 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1942 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1943 }; 1944 }; 1945 }; 1946 1947 cpu2-thermal { 1948 polling-delay-passive = <250>; 1949 polling-delay = <0>; 1950 1951 thermal-sensors = <&tsens0 3>; 1952 1953 trips { 1954 cpu2_alert0: trip-point0 { 1955 temperature = <90000>; 1956 hysteresis = <2000>; 1957 type = "passive"; 1958 }; 1959 1960 cpu2_alert1: trip-point1 { 1961 temperature = <95000>; 1962 hysteresis = <2000>; 1963 type = "passive"; 1964 }; 1965 1966 cpu2_crit: cpu-crit { 1967 temperature = <110000>; 1968 hysteresis = <0>; 1969 type = "critical"; 1970 }; 1971 }; 1972 1973 cooling-maps { 1974 map0 { 1975 trip = <&cpu2_alert0>; 1976 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1977 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1978 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1979 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1980 }; 1981 map1 { 1982 trip = <&cpu2_alert1>; 1983 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1984 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1985 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1986 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1987 }; 1988 }; 1989 }; 1990 1991 cpu3-thermal { 1992 polling-delay-passive = <250>; 1993 polling-delay = <0>; 1994 1995 thermal-sensors = <&tsens0 4>; 1996 1997 trips { 1998 cpu3_alert0: trip-point0 { 1999 temperature = <90000>; 2000 hysteresis = <2000>; 2001 type = "passive"; 2002 }; 2003 2004 cpu3_alert1: trip-point1 { 2005 temperature = <95000>; 2006 hysteresis = <2000>; 2007 type = "passive"; 2008 }; 2009 2010 cpu3_crit: cpu-crit { 2011 temperature = <110000>; 2012 hysteresis = <0>; 2013 type = "critical"; 2014 }; 2015 }; 2016 2017 cooling-maps { 2018 map0 { 2019 trip = <&cpu3_alert0>; 2020 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2021 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2022 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2023 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2024 }; 2025 map1 { 2026 trip = <&cpu3_alert1>; 2027 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2028 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2029 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2030 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2031 }; 2032 }; 2033 }; 2034 2035 cpu4-thermal { 2036 polling-delay-passive = <250>; 2037 polling-delay = <0>; 2038 2039 thermal-sensors = <&tsens0 7>; 2040 2041 trips { 2042 cpu4_alert0: trip-point0 { 2043 temperature = <90000>; 2044 hysteresis = <2000>; 2045 type = "passive"; 2046 }; 2047 2048 cpu4_alert1: trip-point1 { 2049 temperature = <95000>; 2050 hysteresis = <2000>; 2051 type = "passive"; 2052 }; 2053 2054 cpu4_crit: cpu-crit { 2055 temperature = <110000>; 2056 hysteresis = <0>; 2057 type = "critical"; 2058 }; 2059 }; 2060 2061 cooling-maps { 2062 map0 { 2063 trip = <&cpu4_alert0>; 2064 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2065 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2066 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2067 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2068 }; 2069 map1 { 2070 trip = <&cpu4_alert1>; 2071 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2072 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2073 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2074 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2075 }; 2076 }; 2077 }; 2078 2079 cpu5-thermal { 2080 polling-delay-passive = <250>; 2081 polling-delay = <0>; 2082 2083 thermal-sensors = <&tsens0 8>; 2084 2085 trips { 2086 cpu5_alert0: trip-point0 { 2087 temperature = <90000>; 2088 hysteresis = <2000>; 2089 type = "passive"; 2090 }; 2091 2092 cpu5_alert1: trip-point1 { 2093 temperature = <95000>; 2094 hysteresis = <2000>; 2095 type = "passive"; 2096 }; 2097 2098 cpu5_crit: cpu-crit { 2099 temperature = <110000>; 2100 hysteresis = <0>; 2101 type = "critical"; 2102 }; 2103 }; 2104 2105 cooling-maps { 2106 map0 { 2107 trip = <&cpu5_alert0>; 2108 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2109 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2110 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2111 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2112 }; 2113 map1 { 2114 trip = <&cpu5_alert1>; 2115 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2116 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2117 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2118 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2119 }; 2120 }; 2121 }; 2122 2123 cpu6-thermal { 2124 polling-delay-passive = <250>; 2125 polling-delay = <0>; 2126 2127 thermal-sensors = <&tsens0 9>; 2128 2129 trips { 2130 cpu6_alert0: trip-point0 { 2131 temperature = <90000>; 2132 hysteresis = <2000>; 2133 type = "passive"; 2134 }; 2135 2136 cpu6_alert1: trip-point1 { 2137 temperature = <95000>; 2138 hysteresis = <2000>; 2139 type = "passive"; 2140 }; 2141 2142 cpu6_crit: cpu-crit { 2143 temperature = <110000>; 2144 hysteresis = <0>; 2145 type = "critical"; 2146 }; 2147 }; 2148 2149 cooling-maps { 2150 map0 { 2151 trip = <&cpu6_alert0>; 2152 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2153 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2154 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2155 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2156 }; 2157 map1 { 2158 trip = <&cpu6_alert1>; 2159 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2160 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2161 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2162 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2163 }; 2164 }; 2165 }; 2166 2167 cpu7-thermal { 2168 polling-delay-passive = <250>; 2169 polling-delay = <0>; 2170 2171 thermal-sensors = <&tsens0 10>; 2172 2173 trips { 2174 cpu7_alert0: trip-point0 { 2175 temperature = <90000>; 2176 hysteresis = <2000>; 2177 type = "passive"; 2178 }; 2179 2180 cpu7_alert1: trip-point1 { 2181 temperature = <95000>; 2182 hysteresis = <2000>; 2183 type = "passive"; 2184 }; 2185 2186 cpu7_crit: cpu-crit { 2187 temperature = <110000>; 2188 hysteresis = <0>; 2189 type = "critical"; 2190 }; 2191 }; 2192 2193 cooling-maps { 2194 map0 { 2195 trip = <&cpu7_alert0>; 2196 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2197 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2198 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2199 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2200 }; 2201 map1 { 2202 trip = <&cpu7_alert1>; 2203 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2204 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2205 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2206 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2207 }; 2208 }; 2209 }; 2210 2211 cpu8-thermal { 2212 polling-delay-passive = <250>; 2213 polling-delay = <0>; 2214 2215 thermal-sensors = <&tsens0 11>; 2216 2217 trips { 2218 cpu8_alert0: trip-point0 { 2219 temperature = <90000>; 2220 hysteresis = <2000>; 2221 type = "passive"; 2222 }; 2223 2224 cpu8_alert1: trip-point1 { 2225 temperature = <95000>; 2226 hysteresis = <2000>; 2227 type = "passive"; 2228 }; 2229 2230 cpu8_crit: cpu-crit { 2231 temperature = <110000>; 2232 hysteresis = <0>; 2233 type = "critical"; 2234 }; 2235 }; 2236 2237 cooling-maps { 2238 map0 { 2239 trip = <&cpu8_alert0>; 2240 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2241 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2242 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2243 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2244 }; 2245 map1 { 2246 trip = <&cpu8_alert1>; 2247 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2248 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2249 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2250 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2251 }; 2252 }; 2253 }; 2254 2255 cpu9-thermal { 2256 polling-delay-passive = <250>; 2257 polling-delay = <0>; 2258 2259 thermal-sensors = <&tsens0 12>; 2260 2261 trips { 2262 cpu9_alert0: trip-point0 { 2263 temperature = <90000>; 2264 hysteresis = <2000>; 2265 type = "passive"; 2266 }; 2267 2268 cpu9_alert1: trip-point1 { 2269 temperature = <95000>; 2270 hysteresis = <2000>; 2271 type = "passive"; 2272 }; 2273 2274 cpu9_crit: cpu-crit { 2275 temperature = <110000>; 2276 hysteresis = <0>; 2277 type = "critical"; 2278 }; 2279 }; 2280 2281 cooling-maps { 2282 map0 { 2283 trip = <&cpu9_alert0>; 2284 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2285 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2286 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2287 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2288 }; 2289 map1 { 2290 trip = <&cpu9_alert1>; 2291 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2292 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2293 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2294 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2295 }; 2296 }; 2297 }; 2298 2299 cpu10-thermal { 2300 polling-delay-passive = <250>; 2301 polling-delay = <0>; 2302 2303 thermal-sensors = <&tsens0 13>; 2304 2305 trips { 2306 cpu10_alert0: trip-point0 { 2307 temperature = <90000>; 2308 hysteresis = <2000>; 2309 type = "passive"; 2310 }; 2311 2312 cpu10_alert1: trip-point1 { 2313 temperature = <95000>; 2314 hysteresis = <2000>; 2315 type = "passive"; 2316 }; 2317 2318 cpu10_crit: cpu-crit { 2319 temperature = <110000>; 2320 hysteresis = <0>; 2321 type = "critical"; 2322 }; 2323 }; 2324 2325 cooling-maps { 2326 map0 { 2327 trip = <&cpu10_alert0>; 2328 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2329 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2330 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2331 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2332 }; 2333 map1 { 2334 trip = <&cpu10_alert1>; 2335 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2336 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2337 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2338 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2339 }; 2340 }; 2341 }; 2342 2343 cpu11-thermal { 2344 polling-delay-passive = <250>; 2345 polling-delay = <0>; 2346 2347 thermal-sensors = <&tsens0 14>; 2348 2349 trips { 2350 cpu11_alert0: trip-point0 { 2351 temperature = <90000>; 2352 hysteresis = <2000>; 2353 type = "passive"; 2354 }; 2355 2356 cpu11_alert1: trip-point1 { 2357 temperature = <95000>; 2358 hysteresis = <2000>; 2359 type = "passive"; 2360 }; 2361 2362 cpu11_crit: cpu-crit { 2363 temperature = <110000>; 2364 hysteresis = <0>; 2365 type = "critical"; 2366 }; 2367 }; 2368 2369 cooling-maps { 2370 map0 { 2371 trip = <&cpu11_alert0>; 2372 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2373 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2374 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2375 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2376 }; 2377 map1 { 2378 trip = <&cpu11_alert1>; 2379 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2380 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2381 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2382 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2383 }; 2384 }; 2385 }; 2386 2387 aoss0-thermal { 2388 polling-delay-passive = <0>; 2389 polling-delay = <0>; 2390 2391 thermal-sensors = <&tsens0 0>; 2392 2393 trips { 2394 aoss0_alert0: trip-point0 { 2395 temperature = <90000>; 2396 hysteresis = <2000>; 2397 type = "hot"; 2398 }; 2399 2400 aoss0_crit: aoss0-crit { 2401 temperature = <110000>; 2402 hysteresis = <0>; 2403 type = "critical"; 2404 }; 2405 }; 2406 }; 2407 2408 aoss1-thermal { 2409 polling-delay-passive = <0>; 2410 polling-delay = <0>; 2411 2412 thermal-sensors = <&tsens1 0>; 2413 2414 trips { 2415 aoss1_alert0: trip-point0 { 2416 temperature = <90000>; 2417 hysteresis = <2000>; 2418 type = "hot"; 2419 }; 2420 2421 aoss1_crit: aoss1-crit { 2422 temperature = <110000>; 2423 hysteresis = <0>; 2424 type = "critical"; 2425 }; 2426 }; 2427 }; 2428 2429 cpuss0-thermal { 2430 polling-delay-passive = <0>; 2431 polling-delay = <0>; 2432 2433 thermal-sensors = <&tsens0 5>; 2434 2435 trips { 2436 cpuss0_alert0: trip-point0 { 2437 temperature = <90000>; 2438 hysteresis = <2000>; 2439 type = "hot"; 2440 }; 2441 cpuss0_crit: cluster0-crit { 2442 temperature = <110000>; 2443 hysteresis = <0>; 2444 type = "critical"; 2445 }; 2446 }; 2447 }; 2448 2449 cpuss1-thermal { 2450 polling-delay-passive = <0>; 2451 polling-delay = <0>; 2452 2453 thermal-sensors = <&tsens0 6>; 2454 2455 trips { 2456 cpuss1_alert0: trip-point0 { 2457 temperature = <90000>; 2458 hysteresis = <2000>; 2459 type = "hot"; 2460 }; 2461 cpuss1_crit: cluster0-crit { 2462 temperature = <110000>; 2463 hysteresis = <0>; 2464 type = "critical"; 2465 }; 2466 }; 2467 }; 2468 2469 gpuss0-thermal { 2470 polling-delay-passive = <0>; 2471 polling-delay = <0>; 2472 2473 thermal-sensors = <&tsens1 1>; 2474 2475 trips { 2476 gpuss0_alert0: trip-point0 { 2477 temperature = <90000>; 2478 hysteresis = <2000>; 2479 type = "hot"; 2480 }; 2481 2482 gpuss0_crit: gpuss0-crit { 2483 temperature = <110000>; 2484 hysteresis = <0>; 2485 type = "critical"; 2486 }; 2487 }; 2488 }; 2489 2490 gpuss1-thermal { 2491 polling-delay-passive = <0>; 2492 polling-delay = <0>; 2493 2494 thermal-sensors = <&tsens1 2>; 2495 2496 trips { 2497 gpuss1_alert0: trip-point0 { 2498 temperature = <90000>; 2499 hysteresis = <2000>; 2500 type = "hot"; 2501 }; 2502 2503 gpuss1_crit: gpuss1-crit { 2504 temperature = <110000>; 2505 hysteresis = <0>; 2506 type = "critical"; 2507 }; 2508 }; 2509 }; 2510 2511 nspss0-thermal { 2512 polling-delay-passive = <0>; 2513 polling-delay = <0>; 2514 2515 thermal-sensors = <&tsens1 3>; 2516 2517 trips { 2518 nspss0_alert0: trip-point0 { 2519 temperature = <90000>; 2520 hysteresis = <2000>; 2521 type = "hot"; 2522 }; 2523 2524 nspss0_crit: nspss0-crit { 2525 temperature = <110000>; 2526 hysteresis = <0>; 2527 type = "critical"; 2528 }; 2529 }; 2530 }; 2531 2532 nspss1-thermal { 2533 polling-delay-passive = <0>; 2534 polling-delay = <0>; 2535 2536 thermal-sensors = <&tsens1 4>; 2537 2538 trips { 2539 nspss1_alert0: trip-point0 { 2540 temperature = <90000>; 2541 hysteresis = <2000>; 2542 type = "hot"; 2543 }; 2544 2545 nspss1_crit: nspss1-crit { 2546 temperature = <110000>; 2547 hysteresis = <0>; 2548 type = "critical"; 2549 }; 2550 }; 2551 }; 2552 2553 video-thermal { 2554 polling-delay-passive = <0>; 2555 polling-delay = <0>; 2556 2557 thermal-sensors = <&tsens1 5>; 2558 2559 trips { 2560 video_alert0: trip-point0 { 2561 temperature = <90000>; 2562 hysteresis = <2000>; 2563 type = "hot"; 2564 }; 2565 2566 video_crit: video-crit { 2567 temperature = <110000>; 2568 hysteresis = <0>; 2569 type = "critical"; 2570 }; 2571 }; 2572 }; 2573 2574 ddr-thermal { 2575 polling-delay-passive = <0>; 2576 polling-delay = <0>; 2577 2578 thermal-sensors = <&tsens1 6>; 2579 2580 trips { 2581 ddr_alert0: trip-point0 { 2582 temperature = <90000>; 2583 hysteresis = <2000>; 2584 type = "hot"; 2585 }; 2586 2587 ddr_crit: ddr-crit { 2588 temperature = <110000>; 2589 hysteresis = <0>; 2590 type = "critical"; 2591 }; 2592 }; 2593 }; 2594 2595 mdmss0-thermal { 2596 polling-delay-passive = <0>; 2597 polling-delay = <0>; 2598 2599 thermal-sensors = <&tsens1 7>; 2600 2601 trips { 2602 mdmss0_alert0: trip-point0 { 2603 temperature = <90000>; 2604 hysteresis = <2000>; 2605 type = "hot"; 2606 }; 2607 2608 mdmss0_crit: mdmss0-crit { 2609 temperature = <110000>; 2610 hysteresis = <0>; 2611 type = "critical"; 2612 }; 2613 }; 2614 }; 2615 2616 mdmss1-thermal { 2617 polling-delay-passive = <0>; 2618 polling-delay = <0>; 2619 2620 thermal-sensors = <&tsens1 8>; 2621 2622 trips { 2623 mdmss1_alert0: trip-point0 { 2624 temperature = <90000>; 2625 hysteresis = <2000>; 2626 type = "hot"; 2627 }; 2628 2629 mdmss1_crit: mdmss1-crit { 2630 temperature = <110000>; 2631 hysteresis = <0>; 2632 type = "critical"; 2633 }; 2634 }; 2635 }; 2636 2637 mdmss2-thermal { 2638 polling-delay-passive = <0>; 2639 polling-delay = <0>; 2640 2641 thermal-sensors = <&tsens1 9>; 2642 2643 trips { 2644 mdmss2_alert0: trip-point0 { 2645 temperature = <90000>; 2646 hysteresis = <2000>; 2647 type = "hot"; 2648 }; 2649 2650 mdmss2_crit: mdmss2-crit { 2651 temperature = <110000>; 2652 hysteresis = <0>; 2653 type = "critical"; 2654 }; 2655 }; 2656 }; 2657 2658 mdmss3-thermal { 2659 polling-delay-passive = <0>; 2660 polling-delay = <0>; 2661 2662 thermal-sensors = <&tsens1 10>; 2663 2664 trips { 2665 mdmss3_alert0: trip-point0 { 2666 temperature = <90000>; 2667 hysteresis = <2000>; 2668 type = "hot"; 2669 }; 2670 2671 mdmss3_crit: mdmss3-crit { 2672 temperature = <110000>; 2673 hysteresis = <0>; 2674 type = "critical"; 2675 }; 2676 }; 2677 }; 2678 2679 camera0-thermal { 2680 polling-delay-passive = <0>; 2681 polling-delay = <0>; 2682 2683 thermal-sensors = <&tsens1 11>; 2684 2685 trips { 2686 camera0_alert0: trip-point0 { 2687 temperature = <90000>; 2688 hysteresis = <2000>; 2689 type = "hot"; 2690 }; 2691 2692 camera0_crit: camera0-crit { 2693 temperature = <110000>; 2694 hysteresis = <0>; 2695 type = "critical"; 2696 }; 2697 }; 2698 }; 2699 }; 2700 2701 timer { 2702 compatible = "arm,armv8-timer"; 2703 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 2704 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 2705 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 2706 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 2707 }; 2708}; 2709