1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-sc7280.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/mailbox/qcom-ipcc.h> 12#include <dt-bindings/power/qcom-aoss-qmp.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/soc/qcom,rpmh-rsc.h> 15#include <dt-bindings/thermal/thermal.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 chosen { }; 24 25 clocks { 26 xo_board: xo-board { 27 compatible = "fixed-clock"; 28 clock-frequency = <76800000>; 29 #clock-cells = <0>; 30 }; 31 32 sleep_clk: sleep-clk { 33 compatible = "fixed-clock"; 34 clock-frequency = <32000>; 35 #clock-cells = <0>; 36 }; 37 }; 38 39 reserved-memory { 40 #address-cells = <2>; 41 #size-cells = <2>; 42 ranges; 43 44 aop_mem: memory@80800000 { 45 reg = <0x0 0x80800000 0x0 0x60000>; 46 no-map; 47 }; 48 49 aop_cmd_db_mem: memory@80860000 { 50 reg = <0x0 0x80860000 0x0 0x20000>; 51 compatible = "qcom,cmd-db"; 52 no-map; 53 }; 54 55 cpucp_mem: memory@80b00000 { 56 no-map; 57 reg = <0x0 0x80b00000 0x0 0x100000>; 58 }; 59 }; 60 61 cpus { 62 #address-cells = <2>; 63 #size-cells = <0>; 64 65 CPU0: cpu@0 { 66 device_type = "cpu"; 67 compatible = "arm,kryo"; 68 reg = <0x0 0x0>; 69 enable-method = "psci"; 70 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 71 &LITTLE_CPU_SLEEP_1 72 &CLUSTER_SLEEP_0>; 73 next-level-cache = <&L2_0>; 74 qcom,freq-domain = <&cpufreq_hw 0>; 75 #cooling-cells = <2>; 76 L2_0: l2-cache { 77 compatible = "cache"; 78 next-level-cache = <&L3_0>; 79 L3_0: l3-cache { 80 compatible = "cache"; 81 }; 82 }; 83 }; 84 85 CPU1: cpu@100 { 86 device_type = "cpu"; 87 compatible = "arm,kryo"; 88 reg = <0x0 0x100>; 89 enable-method = "psci"; 90 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 91 &LITTLE_CPU_SLEEP_1 92 &CLUSTER_SLEEP_0>; 93 next-level-cache = <&L2_100>; 94 qcom,freq-domain = <&cpufreq_hw 0>; 95 #cooling-cells = <2>; 96 L2_100: l2-cache { 97 compatible = "cache"; 98 next-level-cache = <&L3_0>; 99 }; 100 }; 101 102 CPU2: cpu@200 { 103 device_type = "cpu"; 104 compatible = "arm,kryo"; 105 reg = <0x0 0x200>; 106 enable-method = "psci"; 107 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 108 &LITTLE_CPU_SLEEP_1 109 &CLUSTER_SLEEP_0>; 110 next-level-cache = <&L2_200>; 111 qcom,freq-domain = <&cpufreq_hw 0>; 112 #cooling-cells = <2>; 113 L2_200: l2-cache { 114 compatible = "cache"; 115 next-level-cache = <&L3_0>; 116 }; 117 }; 118 119 CPU3: cpu@300 { 120 device_type = "cpu"; 121 compatible = "arm,kryo"; 122 reg = <0x0 0x300>; 123 enable-method = "psci"; 124 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 125 &LITTLE_CPU_SLEEP_1 126 &CLUSTER_SLEEP_0>; 127 next-level-cache = <&L2_300>; 128 qcom,freq-domain = <&cpufreq_hw 0>; 129 #cooling-cells = <2>; 130 L2_300: l2-cache { 131 compatible = "cache"; 132 next-level-cache = <&L3_0>; 133 }; 134 }; 135 136 CPU4: cpu@400 { 137 device_type = "cpu"; 138 compatible = "arm,kryo"; 139 reg = <0x0 0x400>; 140 enable-method = "psci"; 141 cpu-idle-states = <&BIG_CPU_SLEEP_0 142 &BIG_CPU_SLEEP_1 143 &CLUSTER_SLEEP_0>; 144 next-level-cache = <&L2_400>; 145 qcom,freq-domain = <&cpufreq_hw 1>; 146 #cooling-cells = <2>; 147 L2_400: l2-cache { 148 compatible = "cache"; 149 next-level-cache = <&L3_0>; 150 }; 151 }; 152 153 CPU5: cpu@500 { 154 device_type = "cpu"; 155 compatible = "arm,kryo"; 156 reg = <0x0 0x500>; 157 enable-method = "psci"; 158 cpu-idle-states = <&BIG_CPU_SLEEP_0 159 &BIG_CPU_SLEEP_1 160 &CLUSTER_SLEEP_0>; 161 next-level-cache = <&L2_500>; 162 qcom,freq-domain = <&cpufreq_hw 1>; 163 #cooling-cells = <2>; 164 L2_500: l2-cache { 165 compatible = "cache"; 166 next-level-cache = <&L3_0>; 167 }; 168 }; 169 170 CPU6: cpu@600 { 171 device_type = "cpu"; 172 compatible = "arm,kryo"; 173 reg = <0x0 0x600>; 174 enable-method = "psci"; 175 cpu-idle-states = <&BIG_CPU_SLEEP_0 176 &BIG_CPU_SLEEP_1 177 &CLUSTER_SLEEP_0>; 178 next-level-cache = <&L2_600>; 179 qcom,freq-domain = <&cpufreq_hw 1>; 180 #cooling-cells = <2>; 181 L2_600: l2-cache { 182 compatible = "cache"; 183 next-level-cache = <&L3_0>; 184 }; 185 }; 186 187 CPU7: cpu@700 { 188 device_type = "cpu"; 189 compatible = "arm,kryo"; 190 reg = <0x0 0x700>; 191 enable-method = "psci"; 192 cpu-idle-states = <&BIG_CPU_SLEEP_0 193 &BIG_CPU_SLEEP_1 194 &CLUSTER_SLEEP_0>; 195 next-level-cache = <&L2_700>; 196 qcom,freq-domain = <&cpufreq_hw 1>; 197 #cooling-cells = <2>; 198 L2_700: l2-cache { 199 compatible = "cache"; 200 next-level-cache = <&L3_0>; 201 }; 202 }; 203 204 idle-states { 205 entry-method = "psci"; 206 207 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 208 compatible = "arm,idle-state"; 209 idle-state-name = "little-power-down"; 210 arm,psci-suspend-param = <0x40000003>; 211 entry-latency-us = <549>; 212 exit-latency-us = <901>; 213 min-residency-us = <1774>; 214 local-timer-stop; 215 }; 216 217 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 218 compatible = "arm,idle-state"; 219 idle-state-name = "little-rail-power-down"; 220 arm,psci-suspend-param = <0x40000004>; 221 entry-latency-us = <702>; 222 exit-latency-us = <915>; 223 min-residency-us = <4001>; 224 local-timer-stop; 225 }; 226 227 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 228 compatible = "arm,idle-state"; 229 idle-state-name = "big-power-down"; 230 arm,psci-suspend-param = <0x40000003>; 231 entry-latency-us = <523>; 232 exit-latency-us = <1244>; 233 min-residency-us = <2207>; 234 local-timer-stop; 235 }; 236 237 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 238 compatible = "arm,idle-state"; 239 idle-state-name = "big-rail-power-down"; 240 arm,psci-suspend-param = <0x40000004>; 241 entry-latency-us = <526>; 242 exit-latency-us = <1854>; 243 min-residency-us = <5555>; 244 local-timer-stop; 245 }; 246 247 CLUSTER_SLEEP_0: cluster-sleep-0 { 248 compatible = "arm,idle-state"; 249 idle-state-name = "cluster-power-down"; 250 arm,psci-suspend-param = <0x40003444>; 251 entry-latency-us = <3263>; 252 exit-latency-us = <6562>; 253 min-residency-us = <9926>; 254 local-timer-stop; 255 }; 256 }; 257 }; 258 259 memory@80000000 { 260 device_type = "memory"; 261 /* We expect the bootloader to fill in the size */ 262 reg = <0 0x80000000 0 0>; 263 }; 264 265 firmware { 266 scm { 267 compatible = "qcom,scm-sc7280", "qcom,scm"; 268 }; 269 }; 270 271 pmu { 272 compatible = "arm,armv8-pmuv3"; 273 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 274 }; 275 276 psci { 277 compatible = "arm,psci-1.0"; 278 method = "smc"; 279 }; 280 281 soc: soc@0 { 282 #address-cells = <2>; 283 #size-cells = <2>; 284 ranges = <0 0 0 0 0x10 0>; 285 dma-ranges = <0 0 0 0 0x10 0>; 286 compatible = "simple-bus"; 287 288 gcc: clock-controller@100000 { 289 compatible = "qcom,gcc-sc7280"; 290 reg = <0 0x00100000 0 0x1f0000>; 291 clocks = <&rpmhcc RPMH_CXO_CLK>, 292 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 293 <0>, <0>, <0>, <0>, <0>, <0>; 294 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 295 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 296 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 297 "ufs_phy_tx_symbol_0_clk", 298 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 299 #clock-cells = <1>; 300 #reset-cells = <1>; 301 #power-domain-cells = <1>; 302 }; 303 304 ipcc: mailbox@408000 { 305 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 306 reg = <0 0x00408000 0 0x1000>; 307 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 308 interrupt-controller; 309 #interrupt-cells = <3>; 310 #mbox-cells = <2>; 311 }; 312 313 qupv3_id_0: geniqup@9c0000 { 314 compatible = "qcom,geni-se-qup"; 315 reg = <0 0x009c0000 0 0x2000>; 316 clock-names = "m-ahb", "s-ahb"; 317 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 318 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 319 #address-cells = <2>; 320 #size-cells = <2>; 321 ranges; 322 status = "disabled"; 323 324 uart5: serial@994000 { 325 compatible = "qcom,geni-debug-uart"; 326 reg = <0 0x00994000 0 0x4000>; 327 clock-names = "se"; 328 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&qup_uart5_default>; 331 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 332 status = "disabled"; 333 }; 334 }; 335 336 lpasscc: lpasscc@3000000 { 337 compatible = "qcom,sc7280-lpasscc"; 338 reg = <0 0x03000000 0 0x40>, 339 <0 0x03c04000 0 0x4>, 340 <0 0x03389000 0 0x24>; 341 reg-names = "qdsp6ss", "top_cc", "cc"; 342 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 343 clock-names = "iface"; 344 #clock-cells = <1>; 345 }; 346 347 gpucc: clock-controller@3d90000 { 348 compatible = "qcom,sc7280-gpucc"; 349 reg = <0 0x03d90000 0 0x9000>; 350 clocks = <&rpmhcc RPMH_CXO_CLK>, 351 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 352 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 353 clock-names = "bi_tcxo", 354 "gcc_gpu_gpll0_clk_src", 355 "gcc_gpu_gpll0_div_clk_src"; 356 #clock-cells = <1>; 357 #reset-cells = <1>; 358 #power-domain-cells = <1>; 359 }; 360 361 stm@6002000 { 362 compatible = "arm,coresight-stm", "arm,primecell"; 363 reg = <0 0x06002000 0 0x1000>, 364 <0 0x16280000 0 0x180000>; 365 reg-names = "stm-base", "stm-stimulus-base"; 366 367 clocks = <&aoss_qmp>; 368 clock-names = "apb_pclk"; 369 370 out-ports { 371 port { 372 stm_out: endpoint { 373 remote-endpoint = <&funnel0_in7>; 374 }; 375 }; 376 }; 377 }; 378 379 funnel@6041000 { 380 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 381 reg = <0 0x06041000 0 0x1000>; 382 383 clocks = <&aoss_qmp>; 384 clock-names = "apb_pclk"; 385 386 out-ports { 387 port { 388 funnel0_out: endpoint { 389 remote-endpoint = <&merge_funnel_in0>; 390 }; 391 }; 392 }; 393 394 in-ports { 395 #address-cells = <1>; 396 #size-cells = <0>; 397 398 port@7 { 399 reg = <7>; 400 funnel0_in7: endpoint { 401 remote-endpoint = <&stm_out>; 402 }; 403 }; 404 }; 405 }; 406 407 funnel@6042000 { 408 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 409 reg = <0 0x06042000 0 0x1000>; 410 411 clocks = <&aoss_qmp>; 412 clock-names = "apb_pclk"; 413 414 out-ports { 415 port { 416 funnel1_out: endpoint { 417 remote-endpoint = <&merge_funnel_in1>; 418 }; 419 }; 420 }; 421 422 in-ports { 423 #address-cells = <1>; 424 #size-cells = <0>; 425 426 port@4 { 427 reg = <4>; 428 funnel1_in4: endpoint { 429 remote-endpoint = <&apss_merge_funnel_out>; 430 }; 431 }; 432 }; 433 }; 434 435 funnel@6045000 { 436 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 437 reg = <0 0x06045000 0 0x1000>; 438 439 clocks = <&aoss_qmp>; 440 clock-names = "apb_pclk"; 441 442 out-ports { 443 port { 444 merge_funnel_out: endpoint { 445 remote-endpoint = <&swao_funnel_in>; 446 }; 447 }; 448 }; 449 450 in-ports { 451 #address-cells = <1>; 452 #size-cells = <0>; 453 454 port@0 { 455 reg = <0>; 456 merge_funnel_in0: endpoint { 457 remote-endpoint = <&funnel0_out>; 458 }; 459 }; 460 461 port@1 { 462 reg = <1>; 463 merge_funnel_in1: endpoint { 464 remote-endpoint = <&funnel1_out>; 465 }; 466 }; 467 }; 468 }; 469 470 replicator@6046000 { 471 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 472 reg = <0 0x06046000 0 0x1000>; 473 474 clocks = <&aoss_qmp>; 475 clock-names = "apb_pclk"; 476 477 out-ports { 478 port { 479 replicator_out: endpoint { 480 remote-endpoint = <&etr_in>; 481 }; 482 }; 483 }; 484 485 in-ports { 486 port { 487 replicator_in: endpoint { 488 remote-endpoint = <&swao_replicator_out>; 489 }; 490 }; 491 }; 492 }; 493 494 etr@6048000 { 495 compatible = "arm,coresight-tmc", "arm,primecell"; 496 reg = <0 0x06048000 0 0x1000>; 497 iommus = <&apps_smmu 0x04c0 0>; 498 499 clocks = <&aoss_qmp>; 500 clock-names = "apb_pclk"; 501 arm,scatter-gather; 502 503 in-ports { 504 port { 505 etr_in: endpoint { 506 remote-endpoint = <&replicator_out>; 507 }; 508 }; 509 }; 510 }; 511 512 funnel@6b04000 { 513 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 514 reg = <0 0x06b04000 0 0x1000>; 515 516 clocks = <&aoss_qmp>; 517 clock-names = "apb_pclk"; 518 519 out-ports { 520 port { 521 swao_funnel_out: endpoint { 522 remote-endpoint = <&etf_in>; 523 }; 524 }; 525 }; 526 527 in-ports { 528 #address-cells = <1>; 529 #size-cells = <0>; 530 531 port@7 { 532 reg = <7>; 533 swao_funnel_in: endpoint { 534 remote-endpoint = <&merge_funnel_out>; 535 }; 536 }; 537 }; 538 }; 539 540 etf@6b05000 { 541 compatible = "arm,coresight-tmc", "arm,primecell"; 542 reg = <0 0x06b05000 0 0x1000>; 543 544 clocks = <&aoss_qmp>; 545 clock-names = "apb_pclk"; 546 547 out-ports { 548 port { 549 etf_out: endpoint { 550 remote-endpoint = <&swao_replicator_in>; 551 }; 552 }; 553 }; 554 555 in-ports { 556 port { 557 etf_in: endpoint { 558 remote-endpoint = <&swao_funnel_out>; 559 }; 560 }; 561 }; 562 }; 563 564 replicator@6b06000 { 565 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 566 reg = <0 0x06b06000 0 0x1000>; 567 568 clocks = <&aoss_qmp>; 569 clock-names = "apb_pclk"; 570 qcom,replicator-loses-context; 571 572 out-ports { 573 port { 574 swao_replicator_out: endpoint { 575 remote-endpoint = <&replicator_in>; 576 }; 577 }; 578 }; 579 580 in-ports { 581 port { 582 swao_replicator_in: endpoint { 583 remote-endpoint = <&etf_out>; 584 }; 585 }; 586 }; 587 }; 588 589 etm@7040000 { 590 compatible = "arm,coresight-etm4x", "arm,primecell"; 591 reg = <0 0x07040000 0 0x1000>; 592 593 cpu = <&CPU0>; 594 595 clocks = <&aoss_qmp>; 596 clock-names = "apb_pclk"; 597 arm,coresight-loses-context-with-cpu; 598 qcom,skip-power-up; 599 600 out-ports { 601 port { 602 etm0_out: endpoint { 603 remote-endpoint = <&apss_funnel_in0>; 604 }; 605 }; 606 }; 607 }; 608 609 etm@7140000 { 610 compatible = "arm,coresight-etm4x", "arm,primecell"; 611 reg = <0 0x07140000 0 0x1000>; 612 613 cpu = <&CPU1>; 614 615 clocks = <&aoss_qmp>; 616 clock-names = "apb_pclk"; 617 arm,coresight-loses-context-with-cpu; 618 qcom,skip-power-up; 619 620 out-ports { 621 port { 622 etm1_out: endpoint { 623 remote-endpoint = <&apss_funnel_in1>; 624 }; 625 }; 626 }; 627 }; 628 629 etm@7240000 { 630 compatible = "arm,coresight-etm4x", "arm,primecell"; 631 reg = <0 0x07240000 0 0x1000>; 632 633 cpu = <&CPU2>; 634 635 clocks = <&aoss_qmp>; 636 clock-names = "apb_pclk"; 637 arm,coresight-loses-context-with-cpu; 638 qcom,skip-power-up; 639 640 out-ports { 641 port { 642 etm2_out: endpoint { 643 remote-endpoint = <&apss_funnel_in2>; 644 }; 645 }; 646 }; 647 }; 648 649 etm@7340000 { 650 compatible = "arm,coresight-etm4x", "arm,primecell"; 651 reg = <0 0x07340000 0 0x1000>; 652 653 cpu = <&CPU3>; 654 655 clocks = <&aoss_qmp>; 656 clock-names = "apb_pclk"; 657 arm,coresight-loses-context-with-cpu; 658 qcom,skip-power-up; 659 660 out-ports { 661 port { 662 etm3_out: endpoint { 663 remote-endpoint = <&apss_funnel_in3>; 664 }; 665 }; 666 }; 667 }; 668 669 etm@7440000 { 670 compatible = "arm,coresight-etm4x", "arm,primecell"; 671 reg = <0 0x07440000 0 0x1000>; 672 673 cpu = <&CPU4>; 674 675 clocks = <&aoss_qmp>; 676 clock-names = "apb_pclk"; 677 arm,coresight-loses-context-with-cpu; 678 qcom,skip-power-up; 679 680 out-ports { 681 port { 682 etm4_out: endpoint { 683 remote-endpoint = <&apss_funnel_in4>; 684 }; 685 }; 686 }; 687 }; 688 689 etm@7540000 { 690 compatible = "arm,coresight-etm4x", "arm,primecell"; 691 reg = <0 0x07540000 0 0x1000>; 692 693 cpu = <&CPU5>; 694 695 clocks = <&aoss_qmp>; 696 clock-names = "apb_pclk"; 697 arm,coresight-loses-context-with-cpu; 698 qcom,skip-power-up; 699 700 out-ports { 701 port { 702 etm5_out: endpoint { 703 remote-endpoint = <&apss_funnel_in5>; 704 }; 705 }; 706 }; 707 }; 708 709 etm@7640000 { 710 compatible = "arm,coresight-etm4x", "arm,primecell"; 711 reg = <0 0x07640000 0 0x1000>; 712 713 cpu = <&CPU6>; 714 715 clocks = <&aoss_qmp>; 716 clock-names = "apb_pclk"; 717 arm,coresight-loses-context-with-cpu; 718 qcom,skip-power-up; 719 720 out-ports { 721 port { 722 etm6_out: endpoint { 723 remote-endpoint = <&apss_funnel_in6>; 724 }; 725 }; 726 }; 727 }; 728 729 etm@7740000 { 730 compatible = "arm,coresight-etm4x", "arm,primecell"; 731 reg = <0 0x07740000 0 0x1000>; 732 733 cpu = <&CPU7>; 734 735 clocks = <&aoss_qmp>; 736 clock-names = "apb_pclk"; 737 arm,coresight-loses-context-with-cpu; 738 qcom,skip-power-up; 739 740 out-ports { 741 port { 742 etm7_out: endpoint { 743 remote-endpoint = <&apss_funnel_in7>; 744 }; 745 }; 746 }; 747 }; 748 749 funnel@7800000 { /* APSS Funnel */ 750 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 751 reg = <0 0x07800000 0 0x1000>; 752 753 clocks = <&aoss_qmp>; 754 clock-names = "apb_pclk"; 755 756 out-ports { 757 port { 758 apss_funnel_out: endpoint { 759 remote-endpoint = <&apss_merge_funnel_in>; 760 }; 761 }; 762 }; 763 764 in-ports { 765 #address-cells = <1>; 766 #size-cells = <0>; 767 768 port@0 { 769 reg = <0>; 770 apss_funnel_in0: endpoint { 771 remote-endpoint = <&etm0_out>; 772 }; 773 }; 774 775 port@1 { 776 reg = <1>; 777 apss_funnel_in1: endpoint { 778 remote-endpoint = <&etm1_out>; 779 }; 780 }; 781 782 port@2 { 783 reg = <2>; 784 apss_funnel_in2: endpoint { 785 remote-endpoint = <&etm2_out>; 786 }; 787 }; 788 789 port@3 { 790 reg = <3>; 791 apss_funnel_in3: endpoint { 792 remote-endpoint = <&etm3_out>; 793 }; 794 }; 795 796 port@4 { 797 reg = <4>; 798 apss_funnel_in4: endpoint { 799 remote-endpoint = <&etm4_out>; 800 }; 801 }; 802 803 port@5 { 804 reg = <5>; 805 apss_funnel_in5: endpoint { 806 remote-endpoint = <&etm5_out>; 807 }; 808 }; 809 810 port@6 { 811 reg = <6>; 812 apss_funnel_in6: endpoint { 813 remote-endpoint = <&etm6_out>; 814 }; 815 }; 816 817 port@7 { 818 reg = <7>; 819 apss_funnel_in7: endpoint { 820 remote-endpoint = <&etm7_out>; 821 }; 822 }; 823 }; 824 }; 825 826 funnel@7810000 { 827 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 828 reg = <0 0x07810000 0 0x1000>; 829 830 clocks = <&aoss_qmp>; 831 clock-names = "apb_pclk"; 832 833 out-ports { 834 port { 835 apss_merge_funnel_out: endpoint { 836 remote-endpoint = <&funnel1_in4>; 837 }; 838 }; 839 }; 840 841 in-ports { 842 port { 843 apss_merge_funnel_in: endpoint { 844 remote-endpoint = <&apss_funnel_out>; 845 }; 846 }; 847 }; 848 }; 849 850 system-cache-controller@9200000 { 851 compatible = "qcom,sc7280-llcc"; 852 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 853 reg-names = "llcc_base", "llcc_broadcast_base"; 854 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 855 }; 856 857 videocc: clock-controller@aaf0000 { 858 compatible = "qcom,sc7280-videocc"; 859 reg = <0 0xaaf0000 0 0x10000>; 860 clocks = <&rpmhcc RPMH_CXO_CLK>, 861 <&rpmhcc RPMH_CXO_CLK_A>; 862 clock-names = "bi_tcxo", "bi_tcxo_ao"; 863 #clock-cells = <1>; 864 #reset-cells = <1>; 865 #power-domain-cells = <1>; 866 }; 867 868 dispcc: clock-controller@af00000 { 869 compatible = "qcom,sc7280-dispcc"; 870 reg = <0 0xaf00000 0 0x20000>; 871 clocks = <&rpmhcc RPMH_CXO_CLK>, 872 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 873 <0>, <0>, <0>, <0>, <0>, <0>; 874 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 875 "dsi0_phy_pll_out_byteclk", 876 "dsi0_phy_pll_out_dsiclk", 877 "dp_phy_pll_link_clk", 878 "dp_phy_pll_vco_div_clk", 879 "edp_phy_pll_link_clk", 880 "edp_phy_pll_vco_div_clk"; 881 #clock-cells = <1>; 882 #reset-cells = <1>; 883 #power-domain-cells = <1>; 884 }; 885 886 pdc: interrupt-controller@b220000 { 887 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 888 reg = <0 0x0b220000 0 0x30000>; 889 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 890 <55 306 4>, <59 312 3>, <62 374 2>, 891 <64 434 2>, <66 438 3>, <69 86 1>, 892 <70 520 54>, <124 609 31>, <155 63 1>, 893 <156 716 12>; 894 #interrupt-cells = <2>; 895 interrupt-parent = <&intc>; 896 interrupt-controller; 897 }; 898 899 tsens0: thermal-sensor@c263000 { 900 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 901 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 902 <0 0x0c222000 0 0x1ff>; /* SROT */ 903 #qcom,sensors = <15>; 904 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 906 interrupt-names = "uplow","critical"; 907 #thermal-sensor-cells = <1>; 908 }; 909 910 tsens1: thermal-sensor@c265000 { 911 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 912 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 913 <0 0x0c223000 0 0x1ff>; /* SROT */ 914 #qcom,sensors = <12>; 915 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 917 interrupt-names = "uplow","critical"; 918 #thermal-sensor-cells = <1>; 919 }; 920 921 aoss_qmp: power-controller@c300000 { 922 compatible = "qcom,sc7280-aoss-qmp"; 923 reg = <0 0x0c300000 0 0x100000>; 924 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 925 IPCC_MPROC_SIGNAL_GLINK_QMP 926 IRQ_TYPE_EDGE_RISING>; 927 mboxes = <&ipcc IPCC_CLIENT_AOP 928 IPCC_MPROC_SIGNAL_GLINK_QMP>; 929 930 #clock-cells = <0>; 931 #power-domain-cells = <1>; 932 }; 933 934 spmi_bus: spmi@c440000 { 935 compatible = "qcom,spmi-pmic-arb"; 936 reg = <0 0x0c440000 0 0x1100>, 937 <0 0x0c600000 0 0x2000000>, 938 <0 0x0e600000 0 0x100000>, 939 <0 0x0e700000 0 0xa0000>, 940 <0 0x0c40a000 0 0x26000>; 941 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 942 interrupt-names = "periph_irq"; 943 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 944 qcom,ee = <0>; 945 qcom,channel = <0>; 946 #address-cells = <1>; 947 #size-cells = <1>; 948 interrupt-controller; 949 #interrupt-cells = <4>; 950 }; 951 952 tlmm: pinctrl@f100000 { 953 compatible = "qcom,sc7280-pinctrl"; 954 reg = <0 0x0f100000 0 0x300000>; 955 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 956 gpio-controller; 957 #gpio-cells = <2>; 958 interrupt-controller; 959 #interrupt-cells = <2>; 960 gpio-ranges = <&tlmm 0 0 175>; 961 wakeup-parent = <&pdc>; 962 963 qup_uart5_default: qup-uart5-default { 964 pins = "gpio46", "gpio47"; 965 function = "qup13"; 966 }; 967 }; 968 969 apps_smmu: iommu@15000000 { 970 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 971 reg = <0 0x15000000 0 0x100000>; 972 #iommu-cells = <2>; 973 #global-interrupts = <1>; 974 dma-coherent; 975 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 978 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 979 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 982 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1002 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1003 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1004 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1005 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1006 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1007 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1008 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1009 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1010 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1011 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1012 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1013 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1014 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1015 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1016 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1017 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1018 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1019 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1020 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1021 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1023 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1024 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1035 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1036 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1037 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1038 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1039 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1040 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1041 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1042 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1043 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1044 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1045 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1046 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1047 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1048 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1049 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1050 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1054 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1056 }; 1057 1058 intc: interrupt-controller@17a00000 { 1059 compatible = "arm,gic-v3"; 1060 #address-cells = <2>; 1061 #size-cells = <2>; 1062 ranges; 1063 #interrupt-cells = <3>; 1064 interrupt-controller; 1065 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 1066 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 1067 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 1068 1069 gic-its@17a40000 { 1070 compatible = "arm,gic-v3-its"; 1071 msi-controller; 1072 #msi-cells = <1>; 1073 reg = <0 0x17a40000 0 0x20000>; 1074 status = "disabled"; 1075 }; 1076 }; 1077 1078 watchdog@17c10000 { 1079 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 1080 reg = <0 0x17c10000 0 0x1000>; 1081 clocks = <&sleep_clk>; 1082 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1083 }; 1084 1085 timer@17c20000 { 1086 #address-cells = <2>; 1087 #size-cells = <2>; 1088 ranges; 1089 compatible = "arm,armv7-timer-mem"; 1090 reg = <0 0x17c20000 0 0x1000>; 1091 1092 frame@17c21000 { 1093 frame-number = <0>; 1094 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1095 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1096 reg = <0 0x17c21000 0 0x1000>, 1097 <0 0x17c22000 0 0x1000>; 1098 }; 1099 1100 frame@17c23000 { 1101 frame-number = <1>; 1102 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1103 reg = <0 0x17c23000 0 0x1000>; 1104 status = "disabled"; 1105 }; 1106 1107 frame@17c25000 { 1108 frame-number = <2>; 1109 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1110 reg = <0 0x17c25000 0 0x1000>; 1111 status = "disabled"; 1112 }; 1113 1114 frame@17c27000 { 1115 frame-number = <3>; 1116 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1117 reg = <0 0x17c27000 0 0x1000>; 1118 status = "disabled"; 1119 }; 1120 1121 frame@17c29000 { 1122 frame-number = <4>; 1123 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1124 reg = <0 0x17c29000 0 0x1000>; 1125 status = "disabled"; 1126 }; 1127 1128 frame@17c2b000 { 1129 frame-number = <5>; 1130 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1131 reg = <0 0x17c2b000 0 0x1000>; 1132 status = "disabled"; 1133 }; 1134 1135 frame@17c2d000 { 1136 frame-number = <6>; 1137 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1138 reg = <0 0x17c2d000 0 0x1000>; 1139 status = "disabled"; 1140 }; 1141 }; 1142 1143 apps_rsc: rsc@18200000 { 1144 compatible = "qcom,rpmh-rsc"; 1145 reg = <0 0x18200000 0 0x10000>, 1146 <0 0x18210000 0 0x10000>, 1147 <0 0x18220000 0 0x10000>; 1148 reg-names = "drv-0", "drv-1", "drv-2"; 1149 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1152 qcom,tcs-offset = <0xd00>; 1153 qcom,drv-id = <2>; 1154 qcom,tcs-config = <ACTIVE_TCS 2>, 1155 <SLEEP_TCS 3>, 1156 <WAKE_TCS 3>, 1157 <CONTROL_TCS 1>; 1158 1159 rpmhpd: power-controller { 1160 compatible = "qcom,sc7280-rpmhpd"; 1161 #power-domain-cells = <1>; 1162 operating-points-v2 = <&rpmhpd_opp_table>; 1163 1164 rpmhpd_opp_table: opp-table { 1165 compatible = "operating-points-v2"; 1166 1167 rpmhpd_opp_ret: opp1 { 1168 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1169 }; 1170 1171 rpmhpd_opp_low_svs: opp2 { 1172 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1173 }; 1174 1175 rpmhpd_opp_svs: opp3 { 1176 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1177 }; 1178 1179 rpmhpd_opp_svs_l1: opp4 { 1180 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1181 }; 1182 1183 rpmhpd_opp_svs_l2: opp5 { 1184 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1185 }; 1186 1187 rpmhpd_opp_nom: opp6 { 1188 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1189 }; 1190 1191 rpmhpd_opp_nom_l1: opp7 { 1192 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1193 }; 1194 1195 rpmhpd_opp_turbo: opp8 { 1196 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1197 }; 1198 1199 rpmhpd_opp_turbo_l1: opp9 { 1200 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1201 }; 1202 }; 1203 }; 1204 1205 rpmhcc: clock-controller { 1206 compatible = "qcom,sc7280-rpmh-clk"; 1207 clocks = <&xo_board>; 1208 clock-names = "xo"; 1209 #clock-cells = <1>; 1210 }; 1211 }; 1212 1213 cpufreq_hw: cpufreq@18591000 { 1214 compatible = "qcom,cpufreq-epss"; 1215 reg = <0 0x18591000 0 0x1000>, 1216 <0 0x18592000 0 0x1000>, 1217 <0 0x18593000 0 0x1000>; 1218 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 1219 clock-names = "xo", "alternate"; 1220 #freq-domain-cells = <1>; 1221 }; 1222 }; 1223 1224 thermal_zones: thermal-zones { 1225 cpu0-thermal { 1226 polling-delay-passive = <250>; 1227 polling-delay = <0>; 1228 1229 thermal-sensors = <&tsens0 1>; 1230 1231 trips { 1232 cpu0_alert0: trip-point0 { 1233 temperature = <90000>; 1234 hysteresis = <2000>; 1235 type = "passive"; 1236 }; 1237 1238 cpu0_alert1: trip-point1 { 1239 temperature = <95000>; 1240 hysteresis = <2000>; 1241 type = "passive"; 1242 }; 1243 1244 cpu0_crit: cpu-crit { 1245 temperature = <110000>; 1246 hysteresis = <0>; 1247 type = "critical"; 1248 }; 1249 }; 1250 1251 cooling-maps { 1252 map0 { 1253 trip = <&cpu0_alert0>; 1254 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1255 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1256 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1257 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1258 }; 1259 map1 { 1260 trip = <&cpu0_alert1>; 1261 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1262 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1263 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1264 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1265 }; 1266 }; 1267 }; 1268 1269 cpu1-thermal { 1270 polling-delay-passive = <250>; 1271 polling-delay = <0>; 1272 1273 thermal-sensors = <&tsens0 2>; 1274 1275 trips { 1276 cpu1_alert0: trip-point0 { 1277 temperature = <90000>; 1278 hysteresis = <2000>; 1279 type = "passive"; 1280 }; 1281 1282 cpu1_alert1: trip-point1 { 1283 temperature = <95000>; 1284 hysteresis = <2000>; 1285 type = "passive"; 1286 }; 1287 1288 cpu1_crit: cpu-crit { 1289 temperature = <110000>; 1290 hysteresis = <0>; 1291 type = "critical"; 1292 }; 1293 }; 1294 1295 cooling-maps { 1296 map0 { 1297 trip = <&cpu1_alert0>; 1298 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1299 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1300 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1301 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1302 }; 1303 map1 { 1304 trip = <&cpu1_alert1>; 1305 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1306 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1307 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1308 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1309 }; 1310 }; 1311 }; 1312 1313 cpu2-thermal { 1314 polling-delay-passive = <250>; 1315 polling-delay = <0>; 1316 1317 thermal-sensors = <&tsens0 3>; 1318 1319 trips { 1320 cpu2_alert0: trip-point0 { 1321 temperature = <90000>; 1322 hysteresis = <2000>; 1323 type = "passive"; 1324 }; 1325 1326 cpu2_alert1: trip-point1 { 1327 temperature = <95000>; 1328 hysteresis = <2000>; 1329 type = "passive"; 1330 }; 1331 1332 cpu2_crit: cpu-crit { 1333 temperature = <110000>; 1334 hysteresis = <0>; 1335 type = "critical"; 1336 }; 1337 }; 1338 1339 cooling-maps { 1340 map0 { 1341 trip = <&cpu2_alert0>; 1342 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1343 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1344 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1345 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1346 }; 1347 map1 { 1348 trip = <&cpu2_alert1>; 1349 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1350 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1351 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1352 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1353 }; 1354 }; 1355 }; 1356 1357 cpu3-thermal { 1358 polling-delay-passive = <250>; 1359 polling-delay = <0>; 1360 1361 thermal-sensors = <&tsens0 4>; 1362 1363 trips { 1364 cpu3_alert0: trip-point0 { 1365 temperature = <90000>; 1366 hysteresis = <2000>; 1367 type = "passive"; 1368 }; 1369 1370 cpu3_alert1: trip-point1 { 1371 temperature = <95000>; 1372 hysteresis = <2000>; 1373 type = "passive"; 1374 }; 1375 1376 cpu3_crit: cpu-crit { 1377 temperature = <110000>; 1378 hysteresis = <0>; 1379 type = "critical"; 1380 }; 1381 }; 1382 1383 cooling-maps { 1384 map0 { 1385 trip = <&cpu3_alert0>; 1386 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1387 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1388 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1389 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1390 }; 1391 map1 { 1392 trip = <&cpu3_alert1>; 1393 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1394 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1395 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1396 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1397 }; 1398 }; 1399 }; 1400 1401 cpu4-thermal { 1402 polling-delay-passive = <250>; 1403 polling-delay = <0>; 1404 1405 thermal-sensors = <&tsens0 7>; 1406 1407 trips { 1408 cpu4_alert0: trip-point0 { 1409 temperature = <90000>; 1410 hysteresis = <2000>; 1411 type = "passive"; 1412 }; 1413 1414 cpu4_alert1: trip-point1 { 1415 temperature = <95000>; 1416 hysteresis = <2000>; 1417 type = "passive"; 1418 }; 1419 1420 cpu4_crit: cpu-crit { 1421 temperature = <110000>; 1422 hysteresis = <0>; 1423 type = "critical"; 1424 }; 1425 }; 1426 1427 cooling-maps { 1428 map0 { 1429 trip = <&cpu4_alert0>; 1430 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1431 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1432 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1433 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1434 }; 1435 map1 { 1436 trip = <&cpu4_alert1>; 1437 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1438 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1439 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1440 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1441 }; 1442 }; 1443 }; 1444 1445 cpu5-thermal { 1446 polling-delay-passive = <250>; 1447 polling-delay = <0>; 1448 1449 thermal-sensors = <&tsens0 8>; 1450 1451 trips { 1452 cpu5_alert0: trip-point0 { 1453 temperature = <90000>; 1454 hysteresis = <2000>; 1455 type = "passive"; 1456 }; 1457 1458 cpu5_alert1: trip-point1 { 1459 temperature = <95000>; 1460 hysteresis = <2000>; 1461 type = "passive"; 1462 }; 1463 1464 cpu5_crit: cpu-crit { 1465 temperature = <110000>; 1466 hysteresis = <0>; 1467 type = "critical"; 1468 }; 1469 }; 1470 1471 cooling-maps { 1472 map0 { 1473 trip = <&cpu5_alert0>; 1474 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1475 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1476 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1477 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1478 }; 1479 map1 { 1480 trip = <&cpu5_alert1>; 1481 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1482 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1483 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1484 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1485 }; 1486 }; 1487 }; 1488 1489 cpu6-thermal { 1490 polling-delay-passive = <250>; 1491 polling-delay = <0>; 1492 1493 thermal-sensors = <&tsens0 9>; 1494 1495 trips { 1496 cpu6_alert0: trip-point0 { 1497 temperature = <90000>; 1498 hysteresis = <2000>; 1499 type = "passive"; 1500 }; 1501 1502 cpu6_alert1: trip-point1 { 1503 temperature = <95000>; 1504 hysteresis = <2000>; 1505 type = "passive"; 1506 }; 1507 1508 cpu6_crit: cpu-crit { 1509 temperature = <110000>; 1510 hysteresis = <0>; 1511 type = "critical"; 1512 }; 1513 }; 1514 1515 cooling-maps { 1516 map0 { 1517 trip = <&cpu6_alert0>; 1518 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1519 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1520 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1521 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1522 }; 1523 map1 { 1524 trip = <&cpu6_alert1>; 1525 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1526 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1527 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1528 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1529 }; 1530 }; 1531 }; 1532 1533 cpu7-thermal { 1534 polling-delay-passive = <250>; 1535 polling-delay = <0>; 1536 1537 thermal-sensors = <&tsens0 10>; 1538 1539 trips { 1540 cpu7_alert0: trip-point0 { 1541 temperature = <90000>; 1542 hysteresis = <2000>; 1543 type = "passive"; 1544 }; 1545 1546 cpu7_alert1: trip-point1 { 1547 temperature = <95000>; 1548 hysteresis = <2000>; 1549 type = "passive"; 1550 }; 1551 1552 cpu7_crit: cpu-crit { 1553 temperature = <110000>; 1554 hysteresis = <0>; 1555 type = "critical"; 1556 }; 1557 }; 1558 1559 cooling-maps { 1560 map0 { 1561 trip = <&cpu7_alert0>; 1562 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1563 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1564 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1565 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1566 }; 1567 map1 { 1568 trip = <&cpu7_alert1>; 1569 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1570 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1571 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1572 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1573 }; 1574 }; 1575 }; 1576 1577 cpu8-thermal { 1578 polling-delay-passive = <250>; 1579 polling-delay = <0>; 1580 1581 thermal-sensors = <&tsens0 11>; 1582 1583 trips { 1584 cpu8_alert0: trip-point0 { 1585 temperature = <90000>; 1586 hysteresis = <2000>; 1587 type = "passive"; 1588 }; 1589 1590 cpu8_alert1: trip-point1 { 1591 temperature = <95000>; 1592 hysteresis = <2000>; 1593 type = "passive"; 1594 }; 1595 1596 cpu8_crit: cpu-crit { 1597 temperature = <110000>; 1598 hysteresis = <0>; 1599 type = "critical"; 1600 }; 1601 }; 1602 1603 cooling-maps { 1604 map0 { 1605 trip = <&cpu8_alert0>; 1606 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1607 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1608 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1609 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1610 }; 1611 map1 { 1612 trip = <&cpu8_alert1>; 1613 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1614 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1615 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1616 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1617 }; 1618 }; 1619 }; 1620 1621 cpu9-thermal { 1622 polling-delay-passive = <250>; 1623 polling-delay = <0>; 1624 1625 thermal-sensors = <&tsens0 12>; 1626 1627 trips { 1628 cpu9_alert0: trip-point0 { 1629 temperature = <90000>; 1630 hysteresis = <2000>; 1631 type = "passive"; 1632 }; 1633 1634 cpu9_alert1: trip-point1 { 1635 temperature = <95000>; 1636 hysteresis = <2000>; 1637 type = "passive"; 1638 }; 1639 1640 cpu9_crit: cpu-crit { 1641 temperature = <110000>; 1642 hysteresis = <0>; 1643 type = "critical"; 1644 }; 1645 }; 1646 1647 cooling-maps { 1648 map0 { 1649 trip = <&cpu9_alert0>; 1650 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1651 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1652 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1653 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1654 }; 1655 map1 { 1656 trip = <&cpu9_alert1>; 1657 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1658 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1659 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1660 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1661 }; 1662 }; 1663 }; 1664 1665 cpu10-thermal { 1666 polling-delay-passive = <250>; 1667 polling-delay = <0>; 1668 1669 thermal-sensors = <&tsens0 13>; 1670 1671 trips { 1672 cpu10_alert0: trip-point0 { 1673 temperature = <90000>; 1674 hysteresis = <2000>; 1675 type = "passive"; 1676 }; 1677 1678 cpu10_alert1: trip-point1 { 1679 temperature = <95000>; 1680 hysteresis = <2000>; 1681 type = "passive"; 1682 }; 1683 1684 cpu10_crit: cpu-crit { 1685 temperature = <110000>; 1686 hysteresis = <0>; 1687 type = "critical"; 1688 }; 1689 }; 1690 1691 cooling-maps { 1692 map0 { 1693 trip = <&cpu10_alert0>; 1694 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1695 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1696 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1697 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1698 }; 1699 map1 { 1700 trip = <&cpu10_alert1>; 1701 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1702 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1703 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1704 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1705 }; 1706 }; 1707 }; 1708 1709 cpu11-thermal { 1710 polling-delay-passive = <250>; 1711 polling-delay = <0>; 1712 1713 thermal-sensors = <&tsens0 14>; 1714 1715 trips { 1716 cpu11_alert0: trip-point0 { 1717 temperature = <90000>; 1718 hysteresis = <2000>; 1719 type = "passive"; 1720 }; 1721 1722 cpu11_alert1: trip-point1 { 1723 temperature = <95000>; 1724 hysteresis = <2000>; 1725 type = "passive"; 1726 }; 1727 1728 cpu11_crit: cpu-crit { 1729 temperature = <110000>; 1730 hysteresis = <0>; 1731 type = "critical"; 1732 }; 1733 }; 1734 1735 cooling-maps { 1736 map0 { 1737 trip = <&cpu11_alert0>; 1738 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1739 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1740 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1741 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1742 }; 1743 map1 { 1744 trip = <&cpu11_alert1>; 1745 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1746 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1747 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1748 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1749 }; 1750 }; 1751 }; 1752 1753 aoss0-thermal { 1754 polling-delay-passive = <0>; 1755 polling-delay = <0>; 1756 1757 thermal-sensors = <&tsens0 0>; 1758 1759 trips { 1760 aoss0_alert0: trip-point0 { 1761 temperature = <90000>; 1762 hysteresis = <2000>; 1763 type = "hot"; 1764 }; 1765 1766 aoss0_crit: aoss0-crit { 1767 temperature = <110000>; 1768 hysteresis = <0>; 1769 type = "critical"; 1770 }; 1771 }; 1772 }; 1773 1774 aoss1-thermal { 1775 polling-delay-passive = <0>; 1776 polling-delay = <0>; 1777 1778 thermal-sensors = <&tsens1 0>; 1779 1780 trips { 1781 aoss1_alert0: trip-point0 { 1782 temperature = <90000>; 1783 hysteresis = <2000>; 1784 type = "hot"; 1785 }; 1786 1787 aoss1_crit: aoss1-crit { 1788 temperature = <110000>; 1789 hysteresis = <0>; 1790 type = "critical"; 1791 }; 1792 }; 1793 }; 1794 1795 cpuss0-thermal { 1796 polling-delay-passive = <0>; 1797 polling-delay = <0>; 1798 1799 thermal-sensors = <&tsens0 5>; 1800 1801 trips { 1802 cpuss0_alert0: trip-point0 { 1803 temperature = <90000>; 1804 hysteresis = <2000>; 1805 type = "hot"; 1806 }; 1807 cpuss0_crit: cluster0-crit { 1808 temperature = <110000>; 1809 hysteresis = <0>; 1810 type = "critical"; 1811 }; 1812 }; 1813 }; 1814 1815 cpuss1-thermal { 1816 polling-delay-passive = <0>; 1817 polling-delay = <0>; 1818 1819 thermal-sensors = <&tsens0 6>; 1820 1821 trips { 1822 cpuss1_alert0: trip-point0 { 1823 temperature = <90000>; 1824 hysteresis = <2000>; 1825 type = "hot"; 1826 }; 1827 cpuss1_crit: cluster0-crit { 1828 temperature = <110000>; 1829 hysteresis = <0>; 1830 type = "critical"; 1831 }; 1832 }; 1833 }; 1834 1835 gpuss0-thermal { 1836 polling-delay-passive = <0>; 1837 polling-delay = <0>; 1838 1839 thermal-sensors = <&tsens1 1>; 1840 1841 trips { 1842 gpuss0_alert0: trip-point0 { 1843 temperature = <90000>; 1844 hysteresis = <2000>; 1845 type = "hot"; 1846 }; 1847 1848 gpuss0_crit: gpuss0-crit { 1849 temperature = <110000>; 1850 hysteresis = <0>; 1851 type = "critical"; 1852 }; 1853 }; 1854 }; 1855 1856 gpuss1-thermal { 1857 polling-delay-passive = <0>; 1858 polling-delay = <0>; 1859 1860 thermal-sensors = <&tsens1 2>; 1861 1862 trips { 1863 gpuss1_alert0: trip-point0 { 1864 temperature = <90000>; 1865 hysteresis = <2000>; 1866 type = "hot"; 1867 }; 1868 1869 gpuss1_crit: gpuss1-crit { 1870 temperature = <110000>; 1871 hysteresis = <0>; 1872 type = "critical"; 1873 }; 1874 }; 1875 }; 1876 1877 nspss0-thermal { 1878 polling-delay-passive = <0>; 1879 polling-delay = <0>; 1880 1881 thermal-sensors = <&tsens1 3>; 1882 1883 trips { 1884 nspss0_alert0: trip-point0 { 1885 temperature = <90000>; 1886 hysteresis = <2000>; 1887 type = "hot"; 1888 }; 1889 1890 nspss0_crit: nspss0-crit { 1891 temperature = <110000>; 1892 hysteresis = <0>; 1893 type = "critical"; 1894 }; 1895 }; 1896 }; 1897 1898 nspss1-thermal { 1899 polling-delay-passive = <0>; 1900 polling-delay = <0>; 1901 1902 thermal-sensors = <&tsens1 4>; 1903 1904 trips { 1905 nspss1_alert0: trip-point0 { 1906 temperature = <90000>; 1907 hysteresis = <2000>; 1908 type = "hot"; 1909 }; 1910 1911 nspss1_crit: nspss1-crit { 1912 temperature = <110000>; 1913 hysteresis = <0>; 1914 type = "critical"; 1915 }; 1916 }; 1917 }; 1918 1919 video-thermal { 1920 polling-delay-passive = <0>; 1921 polling-delay = <0>; 1922 1923 thermal-sensors = <&tsens1 5>; 1924 1925 trips { 1926 video_alert0: trip-point0 { 1927 temperature = <90000>; 1928 hysteresis = <2000>; 1929 type = "hot"; 1930 }; 1931 1932 video_crit: video-crit { 1933 temperature = <110000>; 1934 hysteresis = <0>; 1935 type = "critical"; 1936 }; 1937 }; 1938 }; 1939 1940 ddr-thermal { 1941 polling-delay-passive = <0>; 1942 polling-delay = <0>; 1943 1944 thermal-sensors = <&tsens1 6>; 1945 1946 trips { 1947 ddr_alert0: trip-point0 { 1948 temperature = <90000>; 1949 hysteresis = <2000>; 1950 type = "hot"; 1951 }; 1952 1953 ddr_crit: ddr-crit { 1954 temperature = <110000>; 1955 hysteresis = <0>; 1956 type = "critical"; 1957 }; 1958 }; 1959 }; 1960 1961 mdmss0-thermal { 1962 polling-delay-passive = <0>; 1963 polling-delay = <0>; 1964 1965 thermal-sensors = <&tsens1 7>; 1966 1967 trips { 1968 mdmss0_alert0: trip-point0 { 1969 temperature = <90000>; 1970 hysteresis = <2000>; 1971 type = "hot"; 1972 }; 1973 1974 mdmss0_crit: mdmss0-crit { 1975 temperature = <110000>; 1976 hysteresis = <0>; 1977 type = "critical"; 1978 }; 1979 }; 1980 }; 1981 1982 mdmss1-thermal { 1983 polling-delay-passive = <0>; 1984 polling-delay = <0>; 1985 1986 thermal-sensors = <&tsens1 8>; 1987 1988 trips { 1989 mdmss1_alert0: trip-point0 { 1990 temperature = <90000>; 1991 hysteresis = <2000>; 1992 type = "hot"; 1993 }; 1994 1995 mdmss1_crit: mdmss1-crit { 1996 temperature = <110000>; 1997 hysteresis = <0>; 1998 type = "critical"; 1999 }; 2000 }; 2001 }; 2002 2003 mdmss2-thermal { 2004 polling-delay-passive = <0>; 2005 polling-delay = <0>; 2006 2007 thermal-sensors = <&tsens1 9>; 2008 2009 trips { 2010 mdmss2_alert0: trip-point0 { 2011 temperature = <90000>; 2012 hysteresis = <2000>; 2013 type = "hot"; 2014 }; 2015 2016 mdmss2_crit: mdmss2-crit { 2017 temperature = <110000>; 2018 hysteresis = <0>; 2019 type = "critical"; 2020 }; 2021 }; 2022 }; 2023 2024 mdmss3-thermal { 2025 polling-delay-passive = <0>; 2026 polling-delay = <0>; 2027 2028 thermal-sensors = <&tsens1 10>; 2029 2030 trips { 2031 mdmss3_alert0: trip-point0 { 2032 temperature = <90000>; 2033 hysteresis = <2000>; 2034 type = "hot"; 2035 }; 2036 2037 mdmss3_crit: mdmss3-crit { 2038 temperature = <110000>; 2039 hysteresis = <0>; 2040 type = "critical"; 2041 }; 2042 }; 2043 }; 2044 2045 camera0-thermal { 2046 polling-delay-passive = <0>; 2047 polling-delay = <0>; 2048 2049 thermal-sensors = <&tsens1 11>; 2050 2051 trips { 2052 camera0_alert0: trip-point0 { 2053 temperature = <90000>; 2054 hysteresis = <2000>; 2055 type = "hot"; 2056 }; 2057 2058 camera0_crit: camera0-crit { 2059 temperature = <110000>; 2060 hysteresis = <0>; 2061 type = "critical"; 2062 }; 2063 }; 2064 }; 2065 }; 2066 2067 timer { 2068 compatible = "arm,armv8-timer"; 2069 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 2070 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 2071 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 2072 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 2073 }; 2074}; 2075