1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7280.h> 13#include <dt-bindings/interconnect/qcom,sc7280.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/reset/qcom,sdm845-aoss.h> 18#include <dt-bindings/reset/qcom,sdm845-pdc.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/thermal/thermal.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 chosen { }; 29 30 aliases { 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 i2c5 = &i2c5; 37 i2c6 = &i2c6; 38 i2c7 = &i2c7; 39 i2c8 = &i2c8; 40 i2c9 = &i2c9; 41 i2c10 = &i2c10; 42 i2c11 = &i2c11; 43 i2c12 = &i2c12; 44 i2c13 = &i2c13; 45 i2c14 = &i2c14; 46 i2c15 = &i2c15; 47 mmc1 = &sdhc_1; 48 mmc2 = &sdhc_2; 49 spi0 = &spi0; 50 spi1 = &spi1; 51 spi2 = &spi2; 52 spi3 = &spi3; 53 spi4 = &spi4; 54 spi5 = &spi5; 55 spi6 = &spi6; 56 spi7 = &spi7; 57 spi8 = &spi8; 58 spi9 = &spi9; 59 spi10 = &spi10; 60 spi11 = &spi11; 61 spi12 = &spi12; 62 spi13 = &spi13; 63 spi14 = &spi14; 64 spi15 = &spi15; 65 }; 66 67 clocks { 68 xo_board: xo-board { 69 compatible = "fixed-clock"; 70 clock-frequency = <76800000>; 71 #clock-cells = <0>; 72 }; 73 74 sleep_clk: sleep-clk { 75 compatible = "fixed-clock"; 76 clock-frequency = <32000>; 77 #clock-cells = <0>; 78 }; 79 }; 80 81 reserved-memory { 82 #address-cells = <2>; 83 #size-cells = <2>; 84 ranges; 85 86 hyp_mem: memory@80000000 { 87 reg = <0x0 0x80000000 0x0 0x600000>; 88 no-map; 89 }; 90 91 xbl_mem: memory@80600000 { 92 reg = <0x0 0x80600000 0x0 0x200000>; 93 no-map; 94 }; 95 96 aop_mem: memory@80800000 { 97 reg = <0x0 0x80800000 0x0 0x60000>; 98 no-map; 99 }; 100 101 aop_cmd_db_mem: memory@80860000 { 102 reg = <0x0 0x80860000 0x0 0x20000>; 103 compatible = "qcom,cmd-db"; 104 no-map; 105 }; 106 107 reserved_xbl_uefi_log: memory@80880000 { 108 reg = <0x0 0x80884000 0x0 0x10000>; 109 no-map; 110 }; 111 112 sec_apps_mem: memory@808ff000 { 113 reg = <0x0 0x808ff000 0x0 0x1000>; 114 no-map; 115 }; 116 117 smem_mem: memory@80900000 { 118 reg = <0x0 0x80900000 0x0 0x200000>; 119 no-map; 120 }; 121 122 cpucp_mem: memory@80b00000 { 123 no-map; 124 reg = <0x0 0x80b00000 0x0 0x100000>; 125 }; 126 127 wlan_fw_mem: memory@80c00000 { 128 reg = <0x0 0x80c00000 0x0 0xc00000>; 129 no-map; 130 }; 131 132 ipa_fw_mem: memory@8b700000 { 133 reg = <0 0x8b700000 0 0x10000>; 134 no-map; 135 }; 136 137 rmtfs_mem: memory@9c900000 { 138 compatible = "qcom,rmtfs-mem"; 139 reg = <0x0 0x9c900000 0x0 0x280000>; 140 no-map; 141 142 qcom,client-id = <1>; 143 qcom,vmid = <15>; 144 }; 145 }; 146 147 cpus { 148 #address-cells = <2>; 149 #size-cells = <0>; 150 151 CPU0: cpu@0 { 152 device_type = "cpu"; 153 compatible = "arm,kryo"; 154 reg = <0x0 0x0>; 155 enable-method = "psci"; 156 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 157 &LITTLE_CPU_SLEEP_1 158 &CLUSTER_SLEEP_0>; 159 next-level-cache = <&L2_0>; 160 qcom,freq-domain = <&cpufreq_hw 0>; 161 #cooling-cells = <2>; 162 L2_0: l2-cache { 163 compatible = "cache"; 164 next-level-cache = <&L3_0>; 165 L3_0: l3-cache { 166 compatible = "cache"; 167 }; 168 }; 169 }; 170 171 CPU1: cpu@100 { 172 device_type = "cpu"; 173 compatible = "arm,kryo"; 174 reg = <0x0 0x100>; 175 enable-method = "psci"; 176 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 177 &LITTLE_CPU_SLEEP_1 178 &CLUSTER_SLEEP_0>; 179 next-level-cache = <&L2_100>; 180 qcom,freq-domain = <&cpufreq_hw 0>; 181 #cooling-cells = <2>; 182 L2_100: l2-cache { 183 compatible = "cache"; 184 next-level-cache = <&L3_0>; 185 }; 186 }; 187 188 CPU2: cpu@200 { 189 device_type = "cpu"; 190 compatible = "arm,kryo"; 191 reg = <0x0 0x200>; 192 enable-method = "psci"; 193 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 194 &LITTLE_CPU_SLEEP_1 195 &CLUSTER_SLEEP_0>; 196 next-level-cache = <&L2_200>; 197 qcom,freq-domain = <&cpufreq_hw 0>; 198 #cooling-cells = <2>; 199 L2_200: l2-cache { 200 compatible = "cache"; 201 next-level-cache = <&L3_0>; 202 }; 203 }; 204 205 CPU3: cpu@300 { 206 device_type = "cpu"; 207 compatible = "arm,kryo"; 208 reg = <0x0 0x300>; 209 enable-method = "psci"; 210 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 211 &LITTLE_CPU_SLEEP_1 212 &CLUSTER_SLEEP_0>; 213 next-level-cache = <&L2_300>; 214 qcom,freq-domain = <&cpufreq_hw 0>; 215 #cooling-cells = <2>; 216 L2_300: l2-cache { 217 compatible = "cache"; 218 next-level-cache = <&L3_0>; 219 }; 220 }; 221 222 CPU4: cpu@400 { 223 device_type = "cpu"; 224 compatible = "arm,kryo"; 225 reg = <0x0 0x400>; 226 enable-method = "psci"; 227 cpu-idle-states = <&BIG_CPU_SLEEP_0 228 &BIG_CPU_SLEEP_1 229 &CLUSTER_SLEEP_0>; 230 next-level-cache = <&L2_400>; 231 qcom,freq-domain = <&cpufreq_hw 1>; 232 #cooling-cells = <2>; 233 L2_400: l2-cache { 234 compatible = "cache"; 235 next-level-cache = <&L3_0>; 236 }; 237 }; 238 239 CPU5: cpu@500 { 240 device_type = "cpu"; 241 compatible = "arm,kryo"; 242 reg = <0x0 0x500>; 243 enable-method = "psci"; 244 cpu-idle-states = <&BIG_CPU_SLEEP_0 245 &BIG_CPU_SLEEP_1 246 &CLUSTER_SLEEP_0>; 247 next-level-cache = <&L2_500>; 248 qcom,freq-domain = <&cpufreq_hw 1>; 249 #cooling-cells = <2>; 250 L2_500: l2-cache { 251 compatible = "cache"; 252 next-level-cache = <&L3_0>; 253 }; 254 }; 255 256 CPU6: cpu@600 { 257 device_type = "cpu"; 258 compatible = "arm,kryo"; 259 reg = <0x0 0x600>; 260 enable-method = "psci"; 261 cpu-idle-states = <&BIG_CPU_SLEEP_0 262 &BIG_CPU_SLEEP_1 263 &CLUSTER_SLEEP_0>; 264 next-level-cache = <&L2_600>; 265 qcom,freq-domain = <&cpufreq_hw 1>; 266 #cooling-cells = <2>; 267 L2_600: l2-cache { 268 compatible = "cache"; 269 next-level-cache = <&L3_0>; 270 }; 271 }; 272 273 CPU7: cpu@700 { 274 device_type = "cpu"; 275 compatible = "arm,kryo"; 276 reg = <0x0 0x700>; 277 enable-method = "psci"; 278 cpu-idle-states = <&BIG_CPU_SLEEP_0 279 &BIG_CPU_SLEEP_1 280 &CLUSTER_SLEEP_0>; 281 next-level-cache = <&L2_700>; 282 qcom,freq-domain = <&cpufreq_hw 2>; 283 #cooling-cells = <2>; 284 L2_700: l2-cache { 285 compatible = "cache"; 286 next-level-cache = <&L3_0>; 287 }; 288 }; 289 290 cpu-map { 291 cluster0 { 292 core0 { 293 cpu = <&CPU0>; 294 }; 295 296 core1 { 297 cpu = <&CPU1>; 298 }; 299 300 core2 { 301 cpu = <&CPU2>; 302 }; 303 304 core3 { 305 cpu = <&CPU3>; 306 }; 307 308 core4 { 309 cpu = <&CPU4>; 310 }; 311 312 core5 { 313 cpu = <&CPU5>; 314 }; 315 316 core6 { 317 cpu = <&CPU6>; 318 }; 319 320 core7 { 321 cpu = <&CPU7>; 322 }; 323 }; 324 }; 325 326 idle-states { 327 entry-method = "psci"; 328 329 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 330 compatible = "arm,idle-state"; 331 idle-state-name = "little-power-down"; 332 arm,psci-suspend-param = <0x40000003>; 333 entry-latency-us = <549>; 334 exit-latency-us = <901>; 335 min-residency-us = <1774>; 336 local-timer-stop; 337 }; 338 339 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 340 compatible = "arm,idle-state"; 341 idle-state-name = "little-rail-power-down"; 342 arm,psci-suspend-param = <0x40000004>; 343 entry-latency-us = <702>; 344 exit-latency-us = <915>; 345 min-residency-us = <4001>; 346 local-timer-stop; 347 }; 348 349 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 350 compatible = "arm,idle-state"; 351 idle-state-name = "big-power-down"; 352 arm,psci-suspend-param = <0x40000003>; 353 entry-latency-us = <523>; 354 exit-latency-us = <1244>; 355 min-residency-us = <2207>; 356 local-timer-stop; 357 }; 358 359 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 360 compatible = "arm,idle-state"; 361 idle-state-name = "big-rail-power-down"; 362 arm,psci-suspend-param = <0x40000004>; 363 entry-latency-us = <526>; 364 exit-latency-us = <1854>; 365 min-residency-us = <5555>; 366 local-timer-stop; 367 }; 368 369 CLUSTER_SLEEP_0: cluster-sleep-0 { 370 compatible = "arm,idle-state"; 371 idle-state-name = "cluster-power-down"; 372 arm,psci-suspend-param = <0x40003444>; 373 entry-latency-us = <3263>; 374 exit-latency-us = <6562>; 375 min-residency-us = <9926>; 376 local-timer-stop; 377 }; 378 }; 379 }; 380 381 memory@80000000 { 382 device_type = "memory"; 383 /* We expect the bootloader to fill in the size */ 384 reg = <0 0x80000000 0 0>; 385 }; 386 387 firmware { 388 scm { 389 compatible = "qcom,scm-sc7280", "qcom,scm"; 390 }; 391 }; 392 393 clk_virt: interconnect { 394 compatible = "qcom,sc7280-clk-virt"; 395 #interconnect-cells = <2>; 396 qcom,bcm-voters = <&apps_bcm_voter>; 397 }; 398 399 smem { 400 compatible = "qcom,smem"; 401 memory-region = <&smem_mem>; 402 hwlocks = <&tcsr_mutex 3>; 403 }; 404 405 smp2p-adsp { 406 compatible = "qcom,smp2p"; 407 qcom,smem = <443>, <429>; 408 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 409 IPCC_MPROC_SIGNAL_SMP2P 410 IRQ_TYPE_EDGE_RISING>; 411 mboxes = <&ipcc IPCC_CLIENT_LPASS 412 IPCC_MPROC_SIGNAL_SMP2P>; 413 414 qcom,local-pid = <0>; 415 qcom,remote-pid = <2>; 416 417 adsp_smp2p_out: master-kernel { 418 qcom,entry-name = "master-kernel"; 419 #qcom,smem-state-cells = <1>; 420 }; 421 422 adsp_smp2p_in: slave-kernel { 423 qcom,entry-name = "slave-kernel"; 424 interrupt-controller; 425 #interrupt-cells = <2>; 426 }; 427 }; 428 429 smp2p-cdsp { 430 compatible = "qcom,smp2p"; 431 qcom,smem = <94>, <432>; 432 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 433 IPCC_MPROC_SIGNAL_SMP2P 434 IRQ_TYPE_EDGE_RISING>; 435 mboxes = <&ipcc IPCC_CLIENT_CDSP 436 IPCC_MPROC_SIGNAL_SMP2P>; 437 438 qcom,local-pid = <0>; 439 qcom,remote-pid = <5>; 440 441 cdsp_smp2p_out: master-kernel { 442 qcom,entry-name = "master-kernel"; 443 #qcom,smem-state-cells = <1>; 444 }; 445 446 cdsp_smp2p_in: slave-kernel { 447 qcom,entry-name = "slave-kernel"; 448 interrupt-controller; 449 #interrupt-cells = <2>; 450 }; 451 }; 452 453 smp2p-mpss { 454 compatible = "qcom,smp2p"; 455 qcom,smem = <435>, <428>; 456 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 457 IPCC_MPROC_SIGNAL_SMP2P 458 IRQ_TYPE_EDGE_RISING>; 459 mboxes = <&ipcc IPCC_CLIENT_MPSS 460 IPCC_MPROC_SIGNAL_SMP2P>; 461 462 qcom,local-pid = <0>; 463 qcom,remote-pid = <1>; 464 465 modem_smp2p_out: master-kernel { 466 qcom,entry-name = "master-kernel"; 467 #qcom,smem-state-cells = <1>; 468 }; 469 470 modem_smp2p_in: slave-kernel { 471 qcom,entry-name = "slave-kernel"; 472 interrupt-controller; 473 #interrupt-cells = <2>; 474 }; 475 476 ipa_smp2p_out: ipa-ap-to-modem { 477 qcom,entry-name = "ipa"; 478 #qcom,smem-state-cells = <1>; 479 }; 480 481 ipa_smp2p_in: ipa-modem-to-ap { 482 qcom,entry-name = "ipa"; 483 interrupt-controller; 484 #interrupt-cells = <2>; 485 }; 486 }; 487 488 smp2p-wpss { 489 compatible = "qcom,smp2p"; 490 qcom,smem = <617>, <616>; 491 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 492 IPCC_MPROC_SIGNAL_SMP2P 493 IRQ_TYPE_EDGE_RISING>; 494 mboxes = <&ipcc IPCC_CLIENT_WPSS 495 IPCC_MPROC_SIGNAL_SMP2P>; 496 497 qcom,local-pid = <0>; 498 qcom,remote-pid = <13>; 499 500 wpss_smp2p_out: master-kernel { 501 qcom,entry-name = "master-kernel"; 502 #qcom,smem-state-cells = <1>; 503 }; 504 505 wpss_smp2p_in: slave-kernel { 506 qcom,entry-name = "slave-kernel"; 507 interrupt-controller; 508 #interrupt-cells = <2>; 509 }; 510 }; 511 512 pmu { 513 compatible = "arm,armv8-pmuv3"; 514 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 515 }; 516 517 psci { 518 compatible = "arm,psci-1.0"; 519 method = "smc"; 520 }; 521 522 qspi_opp_table: qspi-opp-table { 523 compatible = "operating-points-v2"; 524 525 opp-75000000 { 526 opp-hz = /bits/ 64 <75000000>; 527 required-opps = <&rpmhpd_opp_low_svs>; 528 }; 529 530 opp-150000000 { 531 opp-hz = /bits/ 64 <150000000>; 532 required-opps = <&rpmhpd_opp_svs>; 533 }; 534 535 opp-200000000 { 536 opp-hz = /bits/ 64 <200000000>; 537 required-opps = <&rpmhpd_opp_svs_l1>; 538 }; 539 540 opp-300000000 { 541 opp-hz = /bits/ 64 <300000000>; 542 required-opps = <&rpmhpd_opp_nom>; 543 }; 544 }; 545 546 qup_opp_table: qup-opp-table { 547 compatible = "operating-points-v2"; 548 549 opp-75000000 { 550 opp-hz = /bits/ 64 <75000000>; 551 required-opps = <&rpmhpd_opp_low_svs>; 552 }; 553 554 opp-100000000 { 555 opp-hz = /bits/ 64 <100000000>; 556 required-opps = <&rpmhpd_opp_svs>; 557 }; 558 559 opp-128000000 { 560 opp-hz = /bits/ 64 <128000000>; 561 required-opps = <&rpmhpd_opp_nom>; 562 }; 563 }; 564 565 soc: soc@0 { 566 #address-cells = <2>; 567 #size-cells = <2>; 568 ranges = <0 0 0 0 0x10 0>; 569 dma-ranges = <0 0 0 0 0x10 0>; 570 compatible = "simple-bus"; 571 572 gcc: clock-controller@100000 { 573 compatible = "qcom,gcc-sc7280"; 574 reg = <0 0x00100000 0 0x1f0000>; 575 clocks = <&rpmhcc RPMH_CXO_CLK>, 576 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 577 <0>, <0>, <0>, <0>, <0>, <0>; 578 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 579 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 580 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 581 "ufs_phy_tx_symbol_0_clk", 582 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 583 #clock-cells = <1>; 584 #reset-cells = <1>; 585 #power-domain-cells = <1>; 586 }; 587 588 ipcc: mailbox@408000 { 589 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 590 reg = <0 0x00408000 0 0x1000>; 591 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 592 interrupt-controller; 593 #interrupt-cells = <3>; 594 #mbox-cells = <2>; 595 }; 596 597 qfprom: efuse@784000 { 598 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 599 reg = <0 0x00784000 0 0xa20>, 600 <0 0x00780000 0 0xa20>, 601 <0 0x00782000 0 0x120>, 602 <0 0x00786000 0 0x1fff>; 603 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 604 clock-names = "core"; 605 power-domains = <&rpmhpd SC7280_MX>; 606 #address-cells = <1>; 607 #size-cells = <1>; 608 }; 609 610 sdhc_1: sdhci@7c4000 { 611 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 612 status = "disabled"; 613 614 reg = <0 0x007c4000 0 0x1000>, 615 <0 0x007c5000 0 0x1000>; 616 reg-names = "hc", "cqhci"; 617 618 iommus = <&apps_smmu 0xc0 0x0>; 619 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 621 interrupt-names = "hc_irq", "pwr_irq"; 622 623 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 624 <&gcc GCC_SDCC1_AHB_CLK>, 625 <&rpmhcc RPMH_CXO_CLK>; 626 clock-names = "core", "iface", "xo"; 627 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 628 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 629 interconnect-names = "sdhc-ddr","cpu-sdhc"; 630 power-domains = <&rpmhpd SC7280_CX>; 631 operating-points-v2 = <&sdhc1_opp_table>; 632 633 bus-width = <8>; 634 supports-cqe; 635 636 qcom,dll-config = <0x0007642c>; 637 qcom,ddr-config = <0x80040868>; 638 639 mmc-ddr-1_8v; 640 mmc-hs200-1_8v; 641 mmc-hs400-1_8v; 642 mmc-hs400-enhanced-strobe; 643 644 sdhc1_opp_table: opp-table { 645 compatible = "operating-points-v2"; 646 647 opp-100000000 { 648 opp-hz = /bits/ 64 <100000000>; 649 required-opps = <&rpmhpd_opp_low_svs>; 650 opp-peak-kBps = <1800000 400000>; 651 opp-avg-kBps = <100000 0>; 652 }; 653 654 opp-384000000 { 655 opp-hz = /bits/ 64 <384000000>; 656 required-opps = <&rpmhpd_opp_nom>; 657 opp-peak-kBps = <5400000 1600000>; 658 opp-avg-kBps = <390000 0>; 659 }; 660 }; 661 662 }; 663 664 qupv3_id_0: geniqup@9c0000 { 665 compatible = "qcom,geni-se-qup"; 666 reg = <0 0x009c0000 0 0x2000>; 667 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 668 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 669 clock-names = "m-ahb", "s-ahb"; 670 #address-cells = <2>; 671 #size-cells = <2>; 672 ranges; 673 iommus = <&apps_smmu 0x123 0x0>; 674 status = "disabled"; 675 676 i2c0: i2c@980000 { 677 compatible = "qcom,geni-i2c"; 678 reg = <0 0x00980000 0 0x4000>; 679 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 680 clock-names = "se"; 681 pinctrl-names = "default"; 682 pinctrl-0 = <&qup_i2c0_data_clk>; 683 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 687 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 688 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 689 interconnect-names = "qup-core", "qup-config", 690 "qup-memory"; 691 status = "disabled"; 692 }; 693 694 spi0: spi@980000 { 695 compatible = "qcom,geni-spi"; 696 reg = <0 0x00980000 0 0x4000>; 697 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 698 clock-names = "se"; 699 pinctrl-names = "default"; 700 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 701 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 702 #address-cells = <1>; 703 #size-cells = <0>; 704 power-domains = <&rpmhpd SC7280_CX>; 705 operating-points-v2 = <&qup_opp_table>; 706 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 707 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 708 interconnect-names = "qup-core", "qup-config"; 709 status = "disabled"; 710 }; 711 712 uart0: serial@980000 { 713 compatible = "qcom,geni-uart"; 714 reg = <0 0x00980000 0 0x4000>; 715 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 716 clock-names = "se"; 717 pinctrl-names = "default"; 718 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 719 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 720 power-domains = <&rpmhpd SC7280_CX>; 721 operating-points-v2 = <&qup_opp_table>; 722 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 723 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 724 interconnect-names = "qup-core", "qup-config"; 725 status = "disabled"; 726 }; 727 728 i2c1: i2c@984000 { 729 compatible = "qcom,geni-i2c"; 730 reg = <0 0x00984000 0 0x4000>; 731 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 732 clock-names = "se"; 733 pinctrl-names = "default"; 734 pinctrl-0 = <&qup_i2c1_data_clk>; 735 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 736 #address-cells = <1>; 737 #size-cells = <0>; 738 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 739 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 740 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 741 interconnect-names = "qup-core", "qup-config", 742 "qup-memory"; 743 status = "disabled"; 744 }; 745 746 spi1: spi@984000 { 747 compatible = "qcom,geni-spi"; 748 reg = <0 0x00984000 0 0x4000>; 749 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 750 clock-names = "se"; 751 pinctrl-names = "default"; 752 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 753 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 754 #address-cells = <1>; 755 #size-cells = <0>; 756 power-domains = <&rpmhpd SC7280_CX>; 757 operating-points-v2 = <&qup_opp_table>; 758 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 759 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 760 interconnect-names = "qup-core", "qup-config"; 761 status = "disabled"; 762 }; 763 764 uart1: serial@984000 { 765 compatible = "qcom,geni-uart"; 766 reg = <0 0x00984000 0 0x4000>; 767 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 768 clock-names = "se"; 769 pinctrl-names = "default"; 770 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 771 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 772 power-domains = <&rpmhpd SC7280_CX>; 773 operating-points-v2 = <&qup_opp_table>; 774 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 775 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 776 interconnect-names = "qup-core", "qup-config"; 777 status = "disabled"; 778 }; 779 780 i2c2: i2c@988000 { 781 compatible = "qcom,geni-i2c"; 782 reg = <0 0x00988000 0 0x4000>; 783 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 784 clock-names = "se"; 785 pinctrl-names = "default"; 786 pinctrl-0 = <&qup_i2c2_data_clk>; 787 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 791 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 792 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 793 interconnect-names = "qup-core", "qup-config", 794 "qup-memory"; 795 status = "disabled"; 796 }; 797 798 spi2: spi@988000 { 799 compatible = "qcom,geni-spi"; 800 reg = <0 0x00988000 0 0x4000>; 801 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 802 clock-names = "se"; 803 pinctrl-names = "default"; 804 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 805 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 power-domains = <&rpmhpd SC7280_CX>; 809 operating-points-v2 = <&qup_opp_table>; 810 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 811 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 812 interconnect-names = "qup-core", "qup-config"; 813 status = "disabled"; 814 }; 815 816 uart2: serial@988000 { 817 compatible = "qcom,geni-uart"; 818 reg = <0 0x00988000 0 0x4000>; 819 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 820 clock-names = "se"; 821 pinctrl-names = "default"; 822 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 823 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 824 power-domains = <&rpmhpd SC7280_CX>; 825 operating-points-v2 = <&qup_opp_table>; 826 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 827 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 828 interconnect-names = "qup-core", "qup-config"; 829 status = "disabled"; 830 }; 831 832 i2c3: i2c@98c000 { 833 compatible = "qcom,geni-i2c"; 834 reg = <0 0x0098c000 0 0x4000>; 835 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 836 clock-names = "se"; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&qup_i2c3_data_clk>; 839 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 843 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 844 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 845 interconnect-names = "qup-core", "qup-config", 846 "qup-memory"; 847 status = "disabled"; 848 }; 849 850 spi3: spi@98c000 { 851 compatible = "qcom,geni-spi"; 852 reg = <0 0x0098c000 0 0x4000>; 853 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 854 clock-names = "se"; 855 pinctrl-names = "default"; 856 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 857 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 858 #address-cells = <1>; 859 #size-cells = <0>; 860 power-domains = <&rpmhpd SC7280_CX>; 861 operating-points-v2 = <&qup_opp_table>; 862 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 863 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 864 interconnect-names = "qup-core", "qup-config"; 865 status = "disabled"; 866 }; 867 868 uart3: serial@98c000 { 869 compatible = "qcom,geni-uart"; 870 reg = <0 0x0098c000 0 0x4000>; 871 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 872 clock-names = "se"; 873 pinctrl-names = "default"; 874 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 875 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 876 power-domains = <&rpmhpd SC7280_CX>; 877 operating-points-v2 = <&qup_opp_table>; 878 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 879 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 880 interconnect-names = "qup-core", "qup-config"; 881 status = "disabled"; 882 }; 883 884 i2c4: i2c@990000 { 885 compatible = "qcom,geni-i2c"; 886 reg = <0 0x00990000 0 0x4000>; 887 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 888 clock-names = "se"; 889 pinctrl-names = "default"; 890 pinctrl-0 = <&qup_i2c4_data_clk>; 891 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 892 #address-cells = <1>; 893 #size-cells = <0>; 894 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 895 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 896 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 897 interconnect-names = "qup-core", "qup-config", 898 "qup-memory"; 899 status = "disabled"; 900 }; 901 902 spi4: spi@990000 { 903 compatible = "qcom,geni-spi"; 904 reg = <0 0x00990000 0 0x4000>; 905 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 906 clock-names = "se"; 907 pinctrl-names = "default"; 908 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 909 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 910 #address-cells = <1>; 911 #size-cells = <0>; 912 power-domains = <&rpmhpd SC7280_CX>; 913 operating-points-v2 = <&qup_opp_table>; 914 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 915 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 916 interconnect-names = "qup-core", "qup-config"; 917 status = "disabled"; 918 }; 919 920 uart4: serial@990000 { 921 compatible = "qcom,geni-uart"; 922 reg = <0 0x00990000 0 0x4000>; 923 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 924 clock-names = "se"; 925 pinctrl-names = "default"; 926 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 927 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 928 power-domains = <&rpmhpd SC7280_CX>; 929 operating-points-v2 = <&qup_opp_table>; 930 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 931 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 932 interconnect-names = "qup-core", "qup-config"; 933 status = "disabled"; 934 }; 935 936 i2c5: i2c@994000 { 937 compatible = "qcom,geni-i2c"; 938 reg = <0 0x00994000 0 0x4000>; 939 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 940 clock-names = "se"; 941 pinctrl-names = "default"; 942 pinctrl-0 = <&qup_i2c5_data_clk>; 943 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 944 #address-cells = <1>; 945 #size-cells = <0>; 946 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 947 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 948 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 949 interconnect-names = "qup-core", "qup-config", 950 "qup-memory"; 951 status = "disabled"; 952 }; 953 954 spi5: spi@994000 { 955 compatible = "qcom,geni-spi"; 956 reg = <0 0x00994000 0 0x4000>; 957 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 958 clock-names = "se"; 959 pinctrl-names = "default"; 960 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 961 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 power-domains = <&rpmhpd SC7280_CX>; 965 operating-points-v2 = <&qup_opp_table>; 966 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 967 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 968 interconnect-names = "qup-core", "qup-config"; 969 status = "disabled"; 970 }; 971 972 uart5: serial@994000 { 973 compatible = "qcom,geni-uart"; 974 reg = <0 0x00994000 0 0x4000>; 975 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 976 clock-names = "se"; 977 pinctrl-names = "default"; 978 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 979 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 980 power-domains = <&rpmhpd SC7280_CX>; 981 operating-points-v2 = <&qup_opp_table>; 982 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 983 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 984 interconnect-names = "qup-core", "qup-config"; 985 status = "disabled"; 986 }; 987 988 i2c6: i2c@998000 { 989 compatible = "qcom,geni-i2c"; 990 reg = <0 0x00998000 0 0x4000>; 991 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 992 clock-names = "se"; 993 pinctrl-names = "default"; 994 pinctrl-0 = <&qup_i2c6_data_clk>; 995 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 996 #address-cells = <1>; 997 #size-cells = <0>; 998 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 999 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1000 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1001 interconnect-names = "qup-core", "qup-config", 1002 "qup-memory"; 1003 status = "disabled"; 1004 }; 1005 1006 spi6: spi@998000 { 1007 compatible = "qcom,geni-spi"; 1008 reg = <0 0x00998000 0 0x4000>; 1009 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1010 clock-names = "se"; 1011 pinctrl-names = "default"; 1012 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1013 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 power-domains = <&rpmhpd SC7280_CX>; 1017 operating-points-v2 = <&qup_opp_table>; 1018 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1019 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1020 interconnect-names = "qup-core", "qup-config"; 1021 status = "disabled"; 1022 }; 1023 1024 uart6: serial@998000 { 1025 compatible = "qcom,geni-uart"; 1026 reg = <0 0x00998000 0 0x4000>; 1027 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1028 clock-names = "se"; 1029 pinctrl-names = "default"; 1030 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1031 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1032 power-domains = <&rpmhpd SC7280_CX>; 1033 operating-points-v2 = <&qup_opp_table>; 1034 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1035 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1036 interconnect-names = "qup-core", "qup-config"; 1037 status = "disabled"; 1038 }; 1039 1040 i2c7: i2c@99c000 { 1041 compatible = "qcom,geni-i2c"; 1042 reg = <0 0x0099c000 0 0x4000>; 1043 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1044 clock-names = "se"; 1045 pinctrl-names = "default"; 1046 pinctrl-0 = <&qup_i2c7_data_clk>; 1047 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1048 #address-cells = <1>; 1049 #size-cells = <0>; 1050 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1051 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1052 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1053 interconnect-names = "qup-core", "qup-config", 1054 "qup-memory"; 1055 status = "disabled"; 1056 }; 1057 1058 spi7: spi@99c000 { 1059 compatible = "qcom,geni-spi"; 1060 reg = <0 0x0099c000 0 0x4000>; 1061 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1062 clock-names = "se"; 1063 pinctrl-names = "default"; 1064 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1065 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1066 #address-cells = <1>; 1067 #size-cells = <0>; 1068 power-domains = <&rpmhpd SC7280_CX>; 1069 operating-points-v2 = <&qup_opp_table>; 1070 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1071 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1072 interconnect-names = "qup-core", "qup-config"; 1073 status = "disabled"; 1074 }; 1075 1076 uart7: serial@99c000 { 1077 compatible = "qcom,geni-uart"; 1078 reg = <0 0x0099c000 0 0x4000>; 1079 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1080 clock-names = "se"; 1081 pinctrl-names = "default"; 1082 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1083 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1084 power-domains = <&rpmhpd SC7280_CX>; 1085 operating-points-v2 = <&qup_opp_table>; 1086 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1087 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1088 interconnect-names = "qup-core", "qup-config"; 1089 status = "disabled"; 1090 }; 1091 }; 1092 1093 qupv3_id_1: geniqup@ac0000 { 1094 compatible = "qcom,geni-se-qup"; 1095 reg = <0 0x00ac0000 0 0x2000>; 1096 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1097 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1098 clock-names = "m-ahb", "s-ahb"; 1099 #address-cells = <2>; 1100 #size-cells = <2>; 1101 ranges; 1102 iommus = <&apps_smmu 0x43 0x0>; 1103 status = "disabled"; 1104 1105 i2c8: i2c@a80000 { 1106 compatible = "qcom,geni-i2c"; 1107 reg = <0 0x00a80000 0 0x4000>; 1108 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1109 clock-names = "se"; 1110 pinctrl-names = "default"; 1111 pinctrl-0 = <&qup_i2c8_data_clk>; 1112 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1116 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1117 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1118 interconnect-names = "qup-core", "qup-config", 1119 "qup-memory"; 1120 status = "disabled"; 1121 }; 1122 1123 spi8: spi@a80000 { 1124 compatible = "qcom,geni-spi"; 1125 reg = <0 0x00a80000 0 0x4000>; 1126 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1127 clock-names = "se"; 1128 pinctrl-names = "default"; 1129 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1130 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 power-domains = <&rpmhpd SC7280_CX>; 1134 operating-points-v2 = <&qup_opp_table>; 1135 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1136 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1137 interconnect-names = "qup-core", "qup-config"; 1138 status = "disabled"; 1139 }; 1140 1141 uart8: serial@a80000 { 1142 compatible = "qcom,geni-uart"; 1143 reg = <0 0x00a80000 0 0x4000>; 1144 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1145 clock-names = "se"; 1146 pinctrl-names = "default"; 1147 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1148 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1149 power-domains = <&rpmhpd SC7280_CX>; 1150 operating-points-v2 = <&qup_opp_table>; 1151 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1152 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1153 interconnect-names = "qup-core", "qup-config"; 1154 status = "disabled"; 1155 }; 1156 1157 i2c9: i2c@a84000 { 1158 compatible = "qcom,geni-i2c"; 1159 reg = <0 0x00a84000 0 0x4000>; 1160 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1161 clock-names = "se"; 1162 pinctrl-names = "default"; 1163 pinctrl-0 = <&qup_i2c9_data_clk>; 1164 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1168 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1169 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1170 interconnect-names = "qup-core", "qup-config", 1171 "qup-memory"; 1172 status = "disabled"; 1173 }; 1174 1175 spi9: spi@a84000 { 1176 compatible = "qcom,geni-spi"; 1177 reg = <0 0x00a84000 0 0x4000>; 1178 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1179 clock-names = "se"; 1180 pinctrl-names = "default"; 1181 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1182 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1183 #address-cells = <1>; 1184 #size-cells = <0>; 1185 power-domains = <&rpmhpd SC7280_CX>; 1186 operating-points-v2 = <&qup_opp_table>; 1187 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1188 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1189 interconnect-names = "qup-core", "qup-config"; 1190 status = "disabled"; 1191 }; 1192 1193 uart9: serial@a84000 { 1194 compatible = "qcom,geni-uart"; 1195 reg = <0 0x00a84000 0 0x4000>; 1196 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1197 clock-names = "se"; 1198 pinctrl-names = "default"; 1199 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1200 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1201 power-domains = <&rpmhpd SC7280_CX>; 1202 operating-points-v2 = <&qup_opp_table>; 1203 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1204 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1205 interconnect-names = "qup-core", "qup-config"; 1206 status = "disabled"; 1207 }; 1208 1209 i2c10: i2c@a88000 { 1210 compatible = "qcom,geni-i2c"; 1211 reg = <0 0x00a88000 0 0x4000>; 1212 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1213 clock-names = "se"; 1214 pinctrl-names = "default"; 1215 pinctrl-0 = <&qup_i2c10_data_clk>; 1216 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1220 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1221 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1222 interconnect-names = "qup-core", "qup-config", 1223 "qup-memory"; 1224 status = "disabled"; 1225 }; 1226 1227 spi10: spi@a88000 { 1228 compatible = "qcom,geni-spi"; 1229 reg = <0 0x00a88000 0 0x4000>; 1230 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1231 clock-names = "se"; 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1234 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1235 #address-cells = <1>; 1236 #size-cells = <0>; 1237 power-domains = <&rpmhpd SC7280_CX>; 1238 operating-points-v2 = <&qup_opp_table>; 1239 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1240 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1241 interconnect-names = "qup-core", "qup-config"; 1242 status = "disabled"; 1243 }; 1244 1245 uart10: serial@a88000 { 1246 compatible = "qcom,geni-uart"; 1247 reg = <0 0x00a88000 0 0x4000>; 1248 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1249 clock-names = "se"; 1250 pinctrl-names = "default"; 1251 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1252 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1253 power-domains = <&rpmhpd SC7280_CX>; 1254 operating-points-v2 = <&qup_opp_table>; 1255 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1256 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1257 interconnect-names = "qup-core", "qup-config"; 1258 status = "disabled"; 1259 }; 1260 1261 i2c11: i2c@a8c000 { 1262 compatible = "qcom,geni-i2c"; 1263 reg = <0 0x00a8c000 0 0x4000>; 1264 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1265 clock-names = "se"; 1266 pinctrl-names = "default"; 1267 pinctrl-0 = <&qup_i2c11_data_clk>; 1268 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1272 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1273 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1274 interconnect-names = "qup-core", "qup-config", 1275 "qup-memory"; 1276 status = "disabled"; 1277 }; 1278 1279 spi11: spi@a8c000 { 1280 compatible = "qcom,geni-spi"; 1281 reg = <0 0x00a8c000 0 0x4000>; 1282 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1283 clock-names = "se"; 1284 pinctrl-names = "default"; 1285 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1286 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1287 #address-cells = <1>; 1288 #size-cells = <0>; 1289 power-domains = <&rpmhpd SC7280_CX>; 1290 operating-points-v2 = <&qup_opp_table>; 1291 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1292 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1293 interconnect-names = "qup-core", "qup-config"; 1294 status = "disabled"; 1295 }; 1296 1297 uart11: serial@a8c000 { 1298 compatible = "qcom,geni-uart"; 1299 reg = <0 0x00a8c000 0 0x4000>; 1300 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1301 clock-names = "se"; 1302 pinctrl-names = "default"; 1303 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1304 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1305 power-domains = <&rpmhpd SC7280_CX>; 1306 operating-points-v2 = <&qup_opp_table>; 1307 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1308 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1309 interconnect-names = "qup-core", "qup-config"; 1310 status = "disabled"; 1311 }; 1312 1313 i2c12: i2c@a90000 { 1314 compatible = "qcom,geni-i2c"; 1315 reg = <0 0x00a90000 0 0x4000>; 1316 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1317 clock-names = "se"; 1318 pinctrl-names = "default"; 1319 pinctrl-0 = <&qup_i2c12_data_clk>; 1320 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1321 #address-cells = <1>; 1322 #size-cells = <0>; 1323 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1324 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1325 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1326 interconnect-names = "qup-core", "qup-config", 1327 "qup-memory"; 1328 status = "disabled"; 1329 }; 1330 1331 spi12: spi@a90000 { 1332 compatible = "qcom,geni-spi"; 1333 reg = <0 0x00a90000 0 0x4000>; 1334 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1335 clock-names = "se"; 1336 pinctrl-names = "default"; 1337 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1338 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1339 #address-cells = <1>; 1340 #size-cells = <0>; 1341 power-domains = <&rpmhpd SC7280_CX>; 1342 operating-points-v2 = <&qup_opp_table>; 1343 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1344 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1345 interconnect-names = "qup-core", "qup-config"; 1346 status = "disabled"; 1347 }; 1348 1349 uart12: serial@a90000 { 1350 compatible = "qcom,geni-uart"; 1351 reg = <0 0x00a90000 0 0x4000>; 1352 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1353 clock-names = "se"; 1354 pinctrl-names = "default"; 1355 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1356 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1357 power-domains = <&rpmhpd SC7280_CX>; 1358 operating-points-v2 = <&qup_opp_table>; 1359 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1360 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1361 interconnect-names = "qup-core", "qup-config"; 1362 status = "disabled"; 1363 }; 1364 1365 i2c13: i2c@a94000 { 1366 compatible = "qcom,geni-i2c"; 1367 reg = <0 0x00a94000 0 0x4000>; 1368 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1369 clock-names = "se"; 1370 pinctrl-names = "default"; 1371 pinctrl-0 = <&qup_i2c13_data_clk>; 1372 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1373 #address-cells = <1>; 1374 #size-cells = <0>; 1375 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1376 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1377 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1378 interconnect-names = "qup-core", "qup-config", 1379 "qup-memory"; 1380 status = "disabled"; 1381 }; 1382 1383 spi13: spi@a94000 { 1384 compatible = "qcom,geni-spi"; 1385 reg = <0 0x00a94000 0 0x4000>; 1386 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1387 clock-names = "se"; 1388 pinctrl-names = "default"; 1389 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1390 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1391 #address-cells = <1>; 1392 #size-cells = <0>; 1393 power-domains = <&rpmhpd SC7280_CX>; 1394 operating-points-v2 = <&qup_opp_table>; 1395 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1396 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1397 interconnect-names = "qup-core", "qup-config"; 1398 status = "disabled"; 1399 }; 1400 1401 uart13: serial@a94000 { 1402 compatible = "qcom,geni-uart"; 1403 reg = <0 0x00a94000 0 0x4000>; 1404 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1405 clock-names = "se"; 1406 pinctrl-names = "default"; 1407 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1408 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1409 power-domains = <&rpmhpd SC7280_CX>; 1410 operating-points-v2 = <&qup_opp_table>; 1411 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1412 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1413 interconnect-names = "qup-core", "qup-config"; 1414 status = "disabled"; 1415 }; 1416 1417 i2c14: i2c@a98000 { 1418 compatible = "qcom,geni-i2c"; 1419 reg = <0 0x00a98000 0 0x4000>; 1420 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1421 clock-names = "se"; 1422 pinctrl-names = "default"; 1423 pinctrl-0 = <&qup_i2c14_data_clk>; 1424 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1425 #address-cells = <1>; 1426 #size-cells = <0>; 1427 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1428 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1429 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1430 interconnect-names = "qup-core", "qup-config", 1431 "qup-memory"; 1432 status = "disabled"; 1433 }; 1434 1435 spi14: spi@a98000 { 1436 compatible = "qcom,geni-spi"; 1437 reg = <0 0x00a98000 0 0x4000>; 1438 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1439 clock-names = "se"; 1440 pinctrl-names = "default"; 1441 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1442 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1443 #address-cells = <1>; 1444 #size-cells = <0>; 1445 power-domains = <&rpmhpd SC7280_CX>; 1446 operating-points-v2 = <&qup_opp_table>; 1447 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1448 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1449 interconnect-names = "qup-core", "qup-config"; 1450 status = "disabled"; 1451 }; 1452 1453 uart14: serial@a98000 { 1454 compatible = "qcom,geni-uart"; 1455 reg = <0 0x00a98000 0 0x4000>; 1456 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1457 clock-names = "se"; 1458 pinctrl-names = "default"; 1459 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1460 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1461 power-domains = <&rpmhpd SC7280_CX>; 1462 operating-points-v2 = <&qup_opp_table>; 1463 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1464 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1465 interconnect-names = "qup-core", "qup-config"; 1466 status = "disabled"; 1467 }; 1468 1469 i2c15: i2c@a9c000 { 1470 compatible = "qcom,geni-i2c"; 1471 reg = <0 0x00a9c000 0 0x4000>; 1472 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1473 clock-names = "se"; 1474 pinctrl-names = "default"; 1475 pinctrl-0 = <&qup_i2c15_data_clk>; 1476 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1477 #address-cells = <1>; 1478 #size-cells = <0>; 1479 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1480 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1481 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1482 interconnect-names = "qup-core", "qup-config", 1483 "qup-memory"; 1484 status = "disabled"; 1485 }; 1486 1487 spi15: spi@a9c000 { 1488 compatible = "qcom,geni-spi"; 1489 reg = <0 0x00a9c000 0 0x4000>; 1490 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1491 clock-names = "se"; 1492 pinctrl-names = "default"; 1493 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1494 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1495 #address-cells = <1>; 1496 #size-cells = <0>; 1497 power-domains = <&rpmhpd SC7280_CX>; 1498 operating-points-v2 = <&qup_opp_table>; 1499 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1500 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1501 interconnect-names = "qup-core", "qup-config"; 1502 status = "disabled"; 1503 }; 1504 1505 uart15: serial@a9c000 { 1506 compatible = "qcom,geni-uart"; 1507 reg = <0 0x00a9c000 0 0x4000>; 1508 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1509 clock-names = "se"; 1510 pinctrl-names = "default"; 1511 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1512 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1513 power-domains = <&rpmhpd SC7280_CX>; 1514 operating-points-v2 = <&qup_opp_table>; 1515 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1516 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1517 interconnect-names = "qup-core", "qup-config"; 1518 status = "disabled"; 1519 }; 1520 }; 1521 1522 cnoc2: interconnect@1500000 { 1523 reg = <0 0x01500000 0 0x1000>; 1524 compatible = "qcom,sc7280-cnoc2"; 1525 #interconnect-cells = <2>; 1526 qcom,bcm-voters = <&apps_bcm_voter>; 1527 }; 1528 1529 cnoc3: interconnect@1502000 { 1530 reg = <0 0x01502000 0 0x1000>; 1531 compatible = "qcom,sc7280-cnoc3"; 1532 #interconnect-cells = <2>; 1533 qcom,bcm-voters = <&apps_bcm_voter>; 1534 }; 1535 1536 mc_virt: interconnect@1580000 { 1537 reg = <0 0x01580000 0 0x4>; 1538 compatible = "qcom,sc7280-mc-virt"; 1539 #interconnect-cells = <2>; 1540 qcom,bcm-voters = <&apps_bcm_voter>; 1541 }; 1542 1543 system_noc: interconnect@1680000 { 1544 reg = <0 0x01680000 0 0x15480>; 1545 compatible = "qcom,sc7280-system-noc"; 1546 #interconnect-cells = <2>; 1547 qcom,bcm-voters = <&apps_bcm_voter>; 1548 }; 1549 1550 aggre1_noc: interconnect@16e0000 { 1551 compatible = "qcom,sc7280-aggre1-noc"; 1552 reg = <0 0x016e0000 0 0x1c080>; 1553 #interconnect-cells = <2>; 1554 qcom,bcm-voters = <&apps_bcm_voter>; 1555 }; 1556 1557 aggre2_noc: interconnect@1700000 { 1558 reg = <0 0x01700000 0 0x2b080>; 1559 compatible = "qcom,sc7280-aggre2-noc"; 1560 #interconnect-cells = <2>; 1561 qcom,bcm-voters = <&apps_bcm_voter>; 1562 }; 1563 1564 mmss_noc: interconnect@1740000 { 1565 reg = <0 0x01740000 0 0x1e080>; 1566 compatible = "qcom,sc7280-mmss-noc"; 1567 #interconnect-cells = <2>; 1568 qcom,bcm-voters = <&apps_bcm_voter>; 1569 }; 1570 1571 pcie1: pci@1c08000 { 1572 compatible = "qcom,pcie-sc7280"; 1573 reg = <0 0x01c08000 0 0x3000>, 1574 <0 0x40000000 0 0xf1d>, 1575 <0 0x40000f20 0 0xa8>, 1576 <0 0x40001000 0 0x1000>, 1577 <0 0x40100000 0 0x100000>; 1578 1579 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1580 device_type = "pci"; 1581 linux,pci-domain = <1>; 1582 bus-range = <0x00 0xff>; 1583 num-lanes = <2>; 1584 1585 #address-cells = <3>; 1586 #size-cells = <2>; 1587 1588 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1589 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1590 1591 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1592 interrupt-names = "msi"; 1593 #interrupt-cells = <1>; 1594 interrupt-map-mask = <0 0 0 0x7>; 1595 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, 1596 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, 1597 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, 1598 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; 1599 1600 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1601 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1602 <&pcie1_lane 0>, 1603 <&rpmhcc RPMH_CXO_CLK>, 1604 <&gcc GCC_PCIE_1_AUX_CLK>, 1605 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1606 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1607 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1608 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1609 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1610 <&gcc GCC_DDRSS_PCIE_SF_CLK>; 1611 1612 clock-names = "pipe", 1613 "pipe_mux", 1614 "phy_pipe", 1615 "ref", 1616 "aux", 1617 "cfg", 1618 "bus_master", 1619 "bus_slave", 1620 "slave_q2a", 1621 "tbu", 1622 "ddrss_sf_tbu"; 1623 1624 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1625 assigned-clock-rates = <19200000>; 1626 1627 resets = <&gcc GCC_PCIE_1_BCR>; 1628 reset-names = "pci"; 1629 1630 power-domains = <&gcc GCC_PCIE_1_GDSC>; 1631 1632 phys = <&pcie1_lane>; 1633 phy-names = "pciephy"; 1634 1635 pinctrl-names = "default"; 1636 pinctrl-0 = <&pcie1_clkreq_n>; 1637 1638 iommus = <&apps_smmu 0x1c80 0x1>; 1639 1640 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1641 <0x100 &apps_smmu 0x1c81 0x1>; 1642 1643 status = "disabled"; 1644 }; 1645 1646 pcie1_phy: phy@1c0e000 { 1647 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1648 reg = <0 0x01c0e000 0 0x1c0>; 1649 #address-cells = <2>; 1650 #size-cells = <2>; 1651 ranges; 1652 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1653 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1654 <&gcc GCC_PCIE_CLKREF_EN>, 1655 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1656 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1657 1658 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1659 reset-names = "phy"; 1660 1661 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1662 assigned-clock-rates = <100000000>; 1663 1664 status = "disabled"; 1665 1666 pcie1_lane: lanes@1c0e200 { 1667 reg = <0 0x01c0e200 0 0x170>, 1668 <0 0x01c0e400 0 0x200>, 1669 <0 0x01c0ea00 0 0x1f0>, 1670 <0 0x01c0e600 0 0x170>, 1671 <0 0x01c0e800 0 0x200>, 1672 <0 0x01c0ee00 0 0xf4>; 1673 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1674 clock-names = "pipe0"; 1675 1676 #phy-cells = <0>; 1677 #clock-cells = <1>; 1678 clock-output-names = "pcie_1_pipe_clk"; 1679 }; 1680 }; 1681 1682 ipa: ipa@1e40000 { 1683 compatible = "qcom,sc7280-ipa"; 1684 1685 iommus = <&apps_smmu 0x480 0x0>, 1686 <&apps_smmu 0x482 0x0>; 1687 reg = <0 0x1e40000 0 0x8000>, 1688 <0 0x1e50000 0 0x4ad0>, 1689 <0 0x1e04000 0 0x23000>; 1690 reg-names = "ipa-reg", 1691 "ipa-shared", 1692 "gsi"; 1693 1694 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 1695 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1696 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1697 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1698 interrupt-names = "ipa", 1699 "gsi", 1700 "ipa-clock-query", 1701 "ipa-setup-ready"; 1702 1703 clocks = <&rpmhcc RPMH_IPA_CLK>; 1704 clock-names = "core"; 1705 1706 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1707 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 1708 interconnect-names = "memory", 1709 "config"; 1710 1711 qcom,smem-states = <&ipa_smp2p_out 0>, 1712 <&ipa_smp2p_out 1>; 1713 qcom,smem-state-names = "ipa-clock-enabled-valid", 1714 "ipa-clock-enabled"; 1715 1716 status = "disabled"; 1717 }; 1718 1719 tcsr_mutex: hwlock@1f40000 { 1720 compatible = "qcom,tcsr-mutex", "syscon"; 1721 reg = <0 0x01f40000 0 0x40000>; 1722 #hwlock-cells = <1>; 1723 }; 1724 1725 tcsr: syscon@1fc0000 { 1726 compatible = "qcom,sc7280-tcsr", "syscon"; 1727 reg = <0 0x01fc0000 0 0x30000>; 1728 }; 1729 1730 lpasscc: lpasscc@3000000 { 1731 compatible = "qcom,sc7280-lpasscc"; 1732 reg = <0 0x03000000 0 0x40>, 1733 <0 0x03c04000 0 0x4>, 1734 <0 0x03389000 0 0x24>; 1735 reg-names = "qdsp6ss", "top_cc", "cc"; 1736 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 1737 clock-names = "iface"; 1738 #clock-cells = <1>; 1739 }; 1740 1741 lpass_ag_noc: interconnect@3c40000 { 1742 reg = <0 0x03c40000 0 0xf080>; 1743 compatible = "qcom,sc7280-lpass-ag-noc"; 1744 #interconnect-cells = <2>; 1745 qcom,bcm-voters = <&apps_bcm_voter>; 1746 }; 1747 1748 gpu: gpu@3d00000 { 1749 compatible = "qcom,adreno-635.0", "qcom,adreno"; 1750 #stream-id-cells = <16>; 1751 reg = <0 0x03d00000 0 0x40000>, 1752 <0 0x03d9e000 0 0x1000>, 1753 <0 0x03d61000 0 0x800>; 1754 reg-names = "kgsl_3d0_reg_memory", 1755 "cx_mem", 1756 "cx_dbgc"; 1757 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1758 iommus = <&adreno_smmu 0 0x401>; 1759 operating-points-v2 = <&gpu_opp_table>; 1760 qcom,gmu = <&gmu>; 1761 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 1762 interconnect-names = "gfx-mem"; 1763 #cooling-cells = <2>; 1764 1765 gpu_opp_table: opp-table { 1766 compatible = "operating-points-v2"; 1767 1768 opp-315000000 { 1769 opp-hz = /bits/ 64 <315000000>; 1770 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1771 opp-peak-kBps = <1804000>; 1772 }; 1773 1774 opp-450000000 { 1775 opp-hz = /bits/ 64 <450000000>; 1776 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1777 opp-peak-kBps = <4068000>; 1778 }; 1779 1780 opp-550000000 { 1781 opp-hz = /bits/ 64 <550000000>; 1782 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1783 opp-peak-kBps = <6832000>; 1784 }; 1785 }; 1786 }; 1787 1788 gmu: gmu@3d69000 { 1789 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 1790 reg = <0 0x03d6a000 0 0x34000>, 1791 <0 0x3de0000 0 0x10000>, 1792 <0 0x0b290000 0 0x10000>; 1793 reg-names = "gmu", "rscc", "gmu_pdc"; 1794 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1796 interrupt-names = "hfi", "gmu"; 1797 clocks = <&gpucc 5>, 1798 <&gpucc 8>, 1799 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1800 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1801 <&gpucc 2>, 1802 <&gpucc 15>, 1803 <&gpucc 11>; 1804 clock-names = "gmu", 1805 "cxo", 1806 "axi", 1807 "memnoc", 1808 "ahb", 1809 "hub", 1810 "smmu_vote"; 1811 power-domains = <&gpucc 0>, 1812 <&gpucc 1>; 1813 power-domain-names = "cx", 1814 "gx"; 1815 iommus = <&adreno_smmu 5 0x400>; 1816 operating-points-v2 = <&gmu_opp_table>; 1817 1818 gmu_opp_table: opp-table { 1819 compatible = "operating-points-v2"; 1820 1821 opp-200000000 { 1822 opp-hz = /bits/ 64 <200000000>; 1823 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1824 }; 1825 }; 1826 }; 1827 1828 gpucc: clock-controller@3d90000 { 1829 compatible = "qcom,sc7280-gpucc"; 1830 reg = <0 0x03d90000 0 0x9000>; 1831 clocks = <&rpmhcc RPMH_CXO_CLK>, 1832 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1833 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1834 clock-names = "bi_tcxo", 1835 "gcc_gpu_gpll0_clk_src", 1836 "gcc_gpu_gpll0_div_clk_src"; 1837 #clock-cells = <1>; 1838 #reset-cells = <1>; 1839 #power-domain-cells = <1>; 1840 }; 1841 1842 adreno_smmu: iommu@3da0000 { 1843 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 1844 reg = <0 0x03da0000 0 0x20000>; 1845 #iommu-cells = <2>; 1846 #global-interrupts = <2>; 1847 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1859 1860 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1861 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1862 <&gpucc 2>, 1863 <&gpucc 11>, 1864 <&gpucc 5>, 1865 <&gpucc 15>, 1866 <&gpucc 13>; 1867 clock-names = "gcc_gpu_memnoc_gfx_clk", 1868 "gcc_gpu_snoc_dvm_gfx_clk", 1869 "gpu_cc_ahb_clk", 1870 "gpu_cc_hlos1_vote_gpu_smmu_clk", 1871 "gpu_cc_cx_gmu_clk", 1872 "gpu_cc_hub_cx_int_clk", 1873 "gpu_cc_hub_aon_clk"; 1874 1875 power-domains = <&gpucc 0>; 1876 }; 1877 1878 remoteproc_mpss: remoteproc@4080000 { 1879 compatible = "qcom,sc7280-mpss-pas"; 1880 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 1881 reg-names = "qdsp6", "rmb"; 1882 1883 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 1884 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1885 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1886 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1887 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1888 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1889 interrupt-names = "wdog", "fatal", "ready", "handover", 1890 "stop-ack", "shutdown-ack"; 1891 1892 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1893 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 1894 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1895 <&rpmhcc RPMH_PKA_CLK>, 1896 <&rpmhcc RPMH_CXO_CLK>; 1897 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 1898 1899 power-domains = <&rpmhpd SC7280_CX>, 1900 <&rpmhpd SC7280_MSS>; 1901 power-domain-names = "cx", "mss"; 1902 1903 memory-region = <&mpss_mem>; 1904 1905 qcom,qmp = <&aoss_qmp>; 1906 1907 qcom,smem-states = <&modem_smp2p_out 0>; 1908 qcom,smem-state-names = "stop"; 1909 1910 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 1911 <&pdc_reset PDC_MODEM_SYNC_RESET>; 1912 reset-names = "mss_restart", "pdc_reset"; 1913 1914 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; 1915 qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>; 1916 qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>; 1917 1918 status = "disabled"; 1919 1920 glink-edge { 1921 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1922 IPCC_MPROC_SIGNAL_GLINK_QMP 1923 IRQ_TYPE_EDGE_RISING>; 1924 mboxes = <&ipcc IPCC_CLIENT_MPSS 1925 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1926 label = "modem"; 1927 qcom,remote-pid = <1>; 1928 }; 1929 }; 1930 1931 stm@6002000 { 1932 compatible = "arm,coresight-stm", "arm,primecell"; 1933 reg = <0 0x06002000 0 0x1000>, 1934 <0 0x16280000 0 0x180000>; 1935 reg-names = "stm-base", "stm-stimulus-base"; 1936 1937 clocks = <&aoss_qmp>; 1938 clock-names = "apb_pclk"; 1939 1940 out-ports { 1941 port { 1942 stm_out: endpoint { 1943 remote-endpoint = <&funnel0_in7>; 1944 }; 1945 }; 1946 }; 1947 }; 1948 1949 funnel@6041000 { 1950 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1951 reg = <0 0x06041000 0 0x1000>; 1952 1953 clocks = <&aoss_qmp>; 1954 clock-names = "apb_pclk"; 1955 1956 out-ports { 1957 port { 1958 funnel0_out: endpoint { 1959 remote-endpoint = <&merge_funnel_in0>; 1960 }; 1961 }; 1962 }; 1963 1964 in-ports { 1965 #address-cells = <1>; 1966 #size-cells = <0>; 1967 1968 port@7 { 1969 reg = <7>; 1970 funnel0_in7: endpoint { 1971 remote-endpoint = <&stm_out>; 1972 }; 1973 }; 1974 }; 1975 }; 1976 1977 funnel@6042000 { 1978 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1979 reg = <0 0x06042000 0 0x1000>; 1980 1981 clocks = <&aoss_qmp>; 1982 clock-names = "apb_pclk"; 1983 1984 out-ports { 1985 port { 1986 funnel1_out: endpoint { 1987 remote-endpoint = <&merge_funnel_in1>; 1988 }; 1989 }; 1990 }; 1991 1992 in-ports { 1993 #address-cells = <1>; 1994 #size-cells = <0>; 1995 1996 port@4 { 1997 reg = <4>; 1998 funnel1_in4: endpoint { 1999 remote-endpoint = <&apss_merge_funnel_out>; 2000 }; 2001 }; 2002 }; 2003 }; 2004 2005 funnel@6045000 { 2006 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2007 reg = <0 0x06045000 0 0x1000>; 2008 2009 clocks = <&aoss_qmp>; 2010 clock-names = "apb_pclk"; 2011 2012 out-ports { 2013 port { 2014 merge_funnel_out: endpoint { 2015 remote-endpoint = <&swao_funnel_in>; 2016 }; 2017 }; 2018 }; 2019 2020 in-ports { 2021 #address-cells = <1>; 2022 #size-cells = <0>; 2023 2024 port@0 { 2025 reg = <0>; 2026 merge_funnel_in0: endpoint { 2027 remote-endpoint = <&funnel0_out>; 2028 }; 2029 }; 2030 2031 port@1 { 2032 reg = <1>; 2033 merge_funnel_in1: endpoint { 2034 remote-endpoint = <&funnel1_out>; 2035 }; 2036 }; 2037 }; 2038 }; 2039 2040 replicator@6046000 { 2041 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2042 reg = <0 0x06046000 0 0x1000>; 2043 2044 clocks = <&aoss_qmp>; 2045 clock-names = "apb_pclk"; 2046 2047 out-ports { 2048 port { 2049 replicator_out: endpoint { 2050 remote-endpoint = <&etr_in>; 2051 }; 2052 }; 2053 }; 2054 2055 in-ports { 2056 port { 2057 replicator_in: endpoint { 2058 remote-endpoint = <&swao_replicator_out>; 2059 }; 2060 }; 2061 }; 2062 }; 2063 2064 etr@6048000 { 2065 compatible = "arm,coresight-tmc", "arm,primecell"; 2066 reg = <0 0x06048000 0 0x1000>; 2067 iommus = <&apps_smmu 0x04c0 0>; 2068 2069 clocks = <&aoss_qmp>; 2070 clock-names = "apb_pclk"; 2071 arm,scatter-gather; 2072 2073 in-ports { 2074 port { 2075 etr_in: endpoint { 2076 remote-endpoint = <&replicator_out>; 2077 }; 2078 }; 2079 }; 2080 }; 2081 2082 funnel@6b04000 { 2083 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2084 reg = <0 0x06b04000 0 0x1000>; 2085 2086 clocks = <&aoss_qmp>; 2087 clock-names = "apb_pclk"; 2088 2089 out-ports { 2090 port { 2091 swao_funnel_out: endpoint { 2092 remote-endpoint = <&etf_in>; 2093 }; 2094 }; 2095 }; 2096 2097 in-ports { 2098 #address-cells = <1>; 2099 #size-cells = <0>; 2100 2101 port@7 { 2102 reg = <7>; 2103 swao_funnel_in: endpoint { 2104 remote-endpoint = <&merge_funnel_out>; 2105 }; 2106 }; 2107 }; 2108 }; 2109 2110 etf@6b05000 { 2111 compatible = "arm,coresight-tmc", "arm,primecell"; 2112 reg = <0 0x06b05000 0 0x1000>; 2113 2114 clocks = <&aoss_qmp>; 2115 clock-names = "apb_pclk"; 2116 2117 out-ports { 2118 port { 2119 etf_out: endpoint { 2120 remote-endpoint = <&swao_replicator_in>; 2121 }; 2122 }; 2123 }; 2124 2125 in-ports { 2126 port { 2127 etf_in: endpoint { 2128 remote-endpoint = <&swao_funnel_out>; 2129 }; 2130 }; 2131 }; 2132 }; 2133 2134 replicator@6b06000 { 2135 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2136 reg = <0 0x06b06000 0 0x1000>; 2137 2138 clocks = <&aoss_qmp>; 2139 clock-names = "apb_pclk"; 2140 qcom,replicator-loses-context; 2141 2142 out-ports { 2143 port { 2144 swao_replicator_out: endpoint { 2145 remote-endpoint = <&replicator_in>; 2146 }; 2147 }; 2148 }; 2149 2150 in-ports { 2151 port { 2152 swao_replicator_in: endpoint { 2153 remote-endpoint = <&etf_out>; 2154 }; 2155 }; 2156 }; 2157 }; 2158 2159 etm@7040000 { 2160 compatible = "arm,coresight-etm4x", "arm,primecell"; 2161 reg = <0 0x07040000 0 0x1000>; 2162 2163 cpu = <&CPU0>; 2164 2165 clocks = <&aoss_qmp>; 2166 clock-names = "apb_pclk"; 2167 arm,coresight-loses-context-with-cpu; 2168 qcom,skip-power-up; 2169 2170 out-ports { 2171 port { 2172 etm0_out: endpoint { 2173 remote-endpoint = <&apss_funnel_in0>; 2174 }; 2175 }; 2176 }; 2177 }; 2178 2179 etm@7140000 { 2180 compatible = "arm,coresight-etm4x", "arm,primecell"; 2181 reg = <0 0x07140000 0 0x1000>; 2182 2183 cpu = <&CPU1>; 2184 2185 clocks = <&aoss_qmp>; 2186 clock-names = "apb_pclk"; 2187 arm,coresight-loses-context-with-cpu; 2188 qcom,skip-power-up; 2189 2190 out-ports { 2191 port { 2192 etm1_out: endpoint { 2193 remote-endpoint = <&apss_funnel_in1>; 2194 }; 2195 }; 2196 }; 2197 }; 2198 2199 etm@7240000 { 2200 compatible = "arm,coresight-etm4x", "arm,primecell"; 2201 reg = <0 0x07240000 0 0x1000>; 2202 2203 cpu = <&CPU2>; 2204 2205 clocks = <&aoss_qmp>; 2206 clock-names = "apb_pclk"; 2207 arm,coresight-loses-context-with-cpu; 2208 qcom,skip-power-up; 2209 2210 out-ports { 2211 port { 2212 etm2_out: endpoint { 2213 remote-endpoint = <&apss_funnel_in2>; 2214 }; 2215 }; 2216 }; 2217 }; 2218 2219 etm@7340000 { 2220 compatible = "arm,coresight-etm4x", "arm,primecell"; 2221 reg = <0 0x07340000 0 0x1000>; 2222 2223 cpu = <&CPU3>; 2224 2225 clocks = <&aoss_qmp>; 2226 clock-names = "apb_pclk"; 2227 arm,coresight-loses-context-with-cpu; 2228 qcom,skip-power-up; 2229 2230 out-ports { 2231 port { 2232 etm3_out: endpoint { 2233 remote-endpoint = <&apss_funnel_in3>; 2234 }; 2235 }; 2236 }; 2237 }; 2238 2239 etm@7440000 { 2240 compatible = "arm,coresight-etm4x", "arm,primecell"; 2241 reg = <0 0x07440000 0 0x1000>; 2242 2243 cpu = <&CPU4>; 2244 2245 clocks = <&aoss_qmp>; 2246 clock-names = "apb_pclk"; 2247 arm,coresight-loses-context-with-cpu; 2248 qcom,skip-power-up; 2249 2250 out-ports { 2251 port { 2252 etm4_out: endpoint { 2253 remote-endpoint = <&apss_funnel_in4>; 2254 }; 2255 }; 2256 }; 2257 }; 2258 2259 etm@7540000 { 2260 compatible = "arm,coresight-etm4x", "arm,primecell"; 2261 reg = <0 0x07540000 0 0x1000>; 2262 2263 cpu = <&CPU5>; 2264 2265 clocks = <&aoss_qmp>; 2266 clock-names = "apb_pclk"; 2267 arm,coresight-loses-context-with-cpu; 2268 qcom,skip-power-up; 2269 2270 out-ports { 2271 port { 2272 etm5_out: endpoint { 2273 remote-endpoint = <&apss_funnel_in5>; 2274 }; 2275 }; 2276 }; 2277 }; 2278 2279 etm@7640000 { 2280 compatible = "arm,coresight-etm4x", "arm,primecell"; 2281 reg = <0 0x07640000 0 0x1000>; 2282 2283 cpu = <&CPU6>; 2284 2285 clocks = <&aoss_qmp>; 2286 clock-names = "apb_pclk"; 2287 arm,coresight-loses-context-with-cpu; 2288 qcom,skip-power-up; 2289 2290 out-ports { 2291 port { 2292 etm6_out: endpoint { 2293 remote-endpoint = <&apss_funnel_in6>; 2294 }; 2295 }; 2296 }; 2297 }; 2298 2299 etm@7740000 { 2300 compatible = "arm,coresight-etm4x", "arm,primecell"; 2301 reg = <0 0x07740000 0 0x1000>; 2302 2303 cpu = <&CPU7>; 2304 2305 clocks = <&aoss_qmp>; 2306 clock-names = "apb_pclk"; 2307 arm,coresight-loses-context-with-cpu; 2308 qcom,skip-power-up; 2309 2310 out-ports { 2311 port { 2312 etm7_out: endpoint { 2313 remote-endpoint = <&apss_funnel_in7>; 2314 }; 2315 }; 2316 }; 2317 }; 2318 2319 funnel@7800000 { /* APSS Funnel */ 2320 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2321 reg = <0 0x07800000 0 0x1000>; 2322 2323 clocks = <&aoss_qmp>; 2324 clock-names = "apb_pclk"; 2325 2326 out-ports { 2327 port { 2328 apss_funnel_out: endpoint { 2329 remote-endpoint = <&apss_merge_funnel_in>; 2330 }; 2331 }; 2332 }; 2333 2334 in-ports { 2335 #address-cells = <1>; 2336 #size-cells = <0>; 2337 2338 port@0 { 2339 reg = <0>; 2340 apss_funnel_in0: endpoint { 2341 remote-endpoint = <&etm0_out>; 2342 }; 2343 }; 2344 2345 port@1 { 2346 reg = <1>; 2347 apss_funnel_in1: endpoint { 2348 remote-endpoint = <&etm1_out>; 2349 }; 2350 }; 2351 2352 port@2 { 2353 reg = <2>; 2354 apss_funnel_in2: endpoint { 2355 remote-endpoint = <&etm2_out>; 2356 }; 2357 }; 2358 2359 port@3 { 2360 reg = <3>; 2361 apss_funnel_in3: endpoint { 2362 remote-endpoint = <&etm3_out>; 2363 }; 2364 }; 2365 2366 port@4 { 2367 reg = <4>; 2368 apss_funnel_in4: endpoint { 2369 remote-endpoint = <&etm4_out>; 2370 }; 2371 }; 2372 2373 port@5 { 2374 reg = <5>; 2375 apss_funnel_in5: endpoint { 2376 remote-endpoint = <&etm5_out>; 2377 }; 2378 }; 2379 2380 port@6 { 2381 reg = <6>; 2382 apss_funnel_in6: endpoint { 2383 remote-endpoint = <&etm6_out>; 2384 }; 2385 }; 2386 2387 port@7 { 2388 reg = <7>; 2389 apss_funnel_in7: endpoint { 2390 remote-endpoint = <&etm7_out>; 2391 }; 2392 }; 2393 }; 2394 }; 2395 2396 funnel@7810000 { 2397 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2398 reg = <0 0x07810000 0 0x1000>; 2399 2400 clocks = <&aoss_qmp>; 2401 clock-names = "apb_pclk"; 2402 2403 out-ports { 2404 port { 2405 apss_merge_funnel_out: endpoint { 2406 remote-endpoint = <&funnel1_in4>; 2407 }; 2408 }; 2409 }; 2410 2411 in-ports { 2412 port { 2413 apss_merge_funnel_in: endpoint { 2414 remote-endpoint = <&apss_funnel_out>; 2415 }; 2416 }; 2417 }; 2418 }; 2419 2420 sdhc_2: sdhci@8804000 { 2421 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 2422 status = "disabled"; 2423 2424 reg = <0 0x08804000 0 0x1000>; 2425 2426 iommus = <&apps_smmu 0x100 0x0>; 2427 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2428 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2429 interrupt-names = "hc_irq", "pwr_irq"; 2430 2431 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2432 <&gcc GCC_SDCC2_AHB_CLK>, 2433 <&rpmhcc RPMH_CXO_CLK>; 2434 clock-names = "core", "iface", "xo"; 2435 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2436 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 2437 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2438 power-domains = <&rpmhpd SC7280_CX>; 2439 operating-points-v2 = <&sdhc2_opp_table>; 2440 2441 bus-width = <4>; 2442 2443 qcom,dll-config = <0x0007642c>; 2444 2445 sdhc2_opp_table: opp-table { 2446 compatible = "operating-points-v2"; 2447 2448 opp-100000000 { 2449 opp-hz = /bits/ 64 <100000000>; 2450 required-opps = <&rpmhpd_opp_low_svs>; 2451 opp-peak-kBps = <1800000 400000>; 2452 opp-avg-kBps = <100000 0>; 2453 }; 2454 2455 opp-202000000 { 2456 opp-hz = /bits/ 64 <202000000>; 2457 required-opps = <&rpmhpd_opp_nom>; 2458 opp-peak-kBps = <5400000 1600000>; 2459 opp-avg-kBps = <200000 0>; 2460 }; 2461 }; 2462 2463 }; 2464 2465 usb_1_hsphy: phy@88e3000 { 2466 compatible = "qcom,sc7280-usb-hs-phy", 2467 "qcom,usb-snps-hs-7nm-phy"; 2468 reg = <0 0x088e3000 0 0x400>; 2469 status = "disabled"; 2470 #phy-cells = <0>; 2471 2472 clocks = <&rpmhcc RPMH_CXO_CLK>; 2473 clock-names = "ref"; 2474 2475 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2476 }; 2477 2478 usb_2_hsphy: phy@88e4000 { 2479 compatible = "qcom,sc7280-usb-hs-phy", 2480 "qcom,usb-snps-hs-7nm-phy"; 2481 reg = <0 0x088e4000 0 0x400>; 2482 status = "disabled"; 2483 #phy-cells = <0>; 2484 2485 clocks = <&rpmhcc RPMH_CXO_CLK>; 2486 clock-names = "ref"; 2487 2488 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2489 }; 2490 2491 usb_1_qmpphy: phy-wrapper@88e9000 { 2492 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 2493 "qcom,sm8250-qmp-usb3-dp-phy"; 2494 reg = <0 0x088e9000 0 0x200>, 2495 <0 0x088e8000 0 0x40>, 2496 <0 0x088ea000 0 0x200>; 2497 status = "disabled"; 2498 #address-cells = <2>; 2499 #size-cells = <2>; 2500 ranges; 2501 2502 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2503 <&rpmhcc RPMH_CXO_CLK>, 2504 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2505 clock-names = "aux", "ref_clk_src", "com_aux"; 2506 2507 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2508 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2509 reset-names = "phy", "common"; 2510 2511 usb_1_ssphy: usb3-phy@88e9200 { 2512 reg = <0 0x088e9200 0 0x200>, 2513 <0 0x088e9400 0 0x200>, 2514 <0 0x088e9c00 0 0x400>, 2515 <0 0x088e9600 0 0x200>, 2516 <0 0x088e9800 0 0x200>, 2517 <0 0x088e9a00 0 0x100>; 2518 #clock-cells = <0>; 2519 #phy-cells = <0>; 2520 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2521 clock-names = "pipe0"; 2522 clock-output-names = "usb3_phy_pipe_clk_src"; 2523 }; 2524 2525 dp_phy: dp-phy@88ea200 { 2526 reg = <0 0x088ea200 0 0x200>, 2527 <0 0x088ea400 0 0x200>, 2528 <0 0x088eaa00 0 0x200>, 2529 <0 0x088ea600 0 0x200>, 2530 <0 0x088ea800 0 0x200>; 2531 #phy-cells = <0>; 2532 #clock-cells = <1>; 2533 }; 2534 }; 2535 2536 usb_2: usb@8cf8800 { 2537 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2538 reg = <0 0x08cf8800 0 0x400>; 2539 status = "disabled"; 2540 #address-cells = <2>; 2541 #size-cells = <2>; 2542 ranges; 2543 dma-ranges; 2544 2545 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2546 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2547 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2548 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2549 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 2550 clock-names = "cfg_noc", "core", "iface","mock_utmi", 2551 "sleep"; 2552 2553 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2554 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2555 assigned-clock-rates = <19200000>, <200000000>; 2556 2557 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2558 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 2559 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 2560 interrupt-names = "hs_phy_irq", 2561 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2562 2563 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 2564 2565 resets = <&gcc GCC_USB30_SEC_BCR>; 2566 2567 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 2568 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 2569 interconnect-names = "usb-ddr", "apps-usb"; 2570 2571 usb_2_dwc3: usb@8c00000 { 2572 compatible = "snps,dwc3"; 2573 reg = <0 0x08c00000 0 0xe000>; 2574 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2575 iommus = <&apps_smmu 0xa0 0x0>; 2576 snps,dis_u2_susphy_quirk; 2577 snps,dis_enblslpm_quirk; 2578 phys = <&usb_2_hsphy>; 2579 phy-names = "usb2-phy"; 2580 maximum-speed = "high-speed"; 2581 }; 2582 }; 2583 2584 qspi: spi@88dc000 { 2585 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 2586 reg = <0 0x088dc000 0 0x1000>; 2587 #address-cells = <1>; 2588 #size-cells = <0>; 2589 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2590 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2591 <&gcc GCC_QSPI_CORE_CLK>; 2592 clock-names = "iface", "core"; 2593 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2594 &cnoc2 SLAVE_QSPI_0 0>; 2595 interconnect-names = "qspi-config"; 2596 power-domains = <&rpmhpd SC7280_CX>; 2597 operating-points-v2 = <&qspi_opp_table>; 2598 status = "disabled"; 2599 }; 2600 2601 dc_noc: interconnect@90e0000 { 2602 reg = <0 0x090e0000 0 0x5080>; 2603 compatible = "qcom,sc7280-dc-noc"; 2604 #interconnect-cells = <2>; 2605 qcom,bcm-voters = <&apps_bcm_voter>; 2606 }; 2607 2608 gem_noc: interconnect@9100000 { 2609 reg = <0 0x9100000 0 0xe2200>; 2610 compatible = "qcom,sc7280-gem-noc"; 2611 #interconnect-cells = <2>; 2612 qcom,bcm-voters = <&apps_bcm_voter>; 2613 }; 2614 2615 system-cache-controller@9200000 { 2616 compatible = "qcom,sc7280-llcc"; 2617 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 2618 reg-names = "llcc_base", "llcc_broadcast_base"; 2619 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2620 }; 2621 2622 nsp_noc: interconnect@a0c0000 { 2623 reg = <0 0x0a0c0000 0 0x10000>; 2624 compatible = "qcom,sc7280-nsp-noc"; 2625 #interconnect-cells = <2>; 2626 qcom,bcm-voters = <&apps_bcm_voter>; 2627 }; 2628 2629 usb_1: usb@a6f8800 { 2630 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2631 reg = <0 0x0a6f8800 0 0x400>; 2632 status = "disabled"; 2633 #address-cells = <2>; 2634 #size-cells = <2>; 2635 ranges; 2636 dma-ranges; 2637 2638 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2639 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2640 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2641 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2642 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2643 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2644 "sleep"; 2645 2646 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2647 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2648 assigned-clock-rates = <19200000>, <200000000>; 2649 2650 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2651 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2652 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2653 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2654 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2655 "dm_hs_phy_irq", "ss_phy_irq"; 2656 2657 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 2658 2659 resets = <&gcc GCC_USB30_PRIM_BCR>; 2660 2661 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2662 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 2663 interconnect-names = "usb-ddr", "apps-usb"; 2664 2665 usb_1_dwc3: usb@a600000 { 2666 compatible = "snps,dwc3"; 2667 reg = <0 0x0a600000 0 0xe000>; 2668 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2669 iommus = <&apps_smmu 0xe0 0x0>; 2670 snps,dis_u2_susphy_quirk; 2671 snps,dis_enblslpm_quirk; 2672 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2673 phy-names = "usb2-phy", "usb3-phy"; 2674 maximum-speed = "super-speed"; 2675 }; 2676 }; 2677 2678 videocc: clock-controller@aaf0000 { 2679 compatible = "qcom,sc7280-videocc"; 2680 reg = <0 0xaaf0000 0 0x10000>; 2681 clocks = <&rpmhcc RPMH_CXO_CLK>, 2682 <&rpmhcc RPMH_CXO_CLK_A>; 2683 clock-names = "bi_tcxo", "bi_tcxo_ao"; 2684 #clock-cells = <1>; 2685 #reset-cells = <1>; 2686 #power-domain-cells = <1>; 2687 }; 2688 2689 dispcc: clock-controller@af00000 { 2690 compatible = "qcom,sc7280-dispcc"; 2691 reg = <0 0xaf00000 0 0x20000>; 2692 clocks = <&rpmhcc RPMH_CXO_CLK>, 2693 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2694 <0>, <0>, <0>, <0>, <0>, <0>; 2695 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 2696 "dsi0_phy_pll_out_byteclk", 2697 "dsi0_phy_pll_out_dsiclk", 2698 "dp_phy_pll_link_clk", 2699 "dp_phy_pll_vco_div_clk", 2700 "edp_phy_pll_link_clk", 2701 "edp_phy_pll_vco_div_clk"; 2702 #clock-cells = <1>; 2703 #reset-cells = <1>; 2704 #power-domain-cells = <1>; 2705 }; 2706 2707 pdc: interrupt-controller@b220000 { 2708 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 2709 reg = <0 0x0b220000 0 0x30000>; 2710 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 2711 <55 306 4>, <59 312 3>, <62 374 2>, 2712 <64 434 2>, <66 438 3>, <69 86 1>, 2713 <70 520 54>, <124 609 31>, <155 63 1>, 2714 <156 716 12>; 2715 #interrupt-cells = <2>; 2716 interrupt-parent = <&intc>; 2717 interrupt-controller; 2718 }; 2719 2720 pdc_reset: reset-controller@b5e0000 { 2721 compatible = "qcom,sc7280-pdc-global"; 2722 reg = <0 0x0b5e0000 0 0x20000>; 2723 #reset-cells = <1>; 2724 }; 2725 2726 tsens0: thermal-sensor@c263000 { 2727 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 2728 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2729 <0 0x0c222000 0 0x1ff>; /* SROT */ 2730 #qcom,sensors = <15>; 2731 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2732 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2733 interrupt-names = "uplow","critical"; 2734 #thermal-sensor-cells = <1>; 2735 }; 2736 2737 tsens1: thermal-sensor@c265000 { 2738 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 2739 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2740 <0 0x0c223000 0 0x1ff>; /* SROT */ 2741 #qcom,sensors = <12>; 2742 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2743 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2744 interrupt-names = "uplow","critical"; 2745 #thermal-sensor-cells = <1>; 2746 }; 2747 2748 aoss_reset: reset-controller@c2a0000 { 2749 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 2750 reg = <0 0x0c2a0000 0 0x31000>; 2751 #reset-cells = <1>; 2752 }; 2753 2754 aoss_qmp: power-controller@c300000 { 2755 compatible = "qcom,sc7280-aoss-qmp"; 2756 reg = <0 0x0c300000 0 0x400>; 2757 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 2758 IPCC_MPROC_SIGNAL_GLINK_QMP 2759 IRQ_TYPE_EDGE_RISING>; 2760 mboxes = <&ipcc IPCC_CLIENT_AOP 2761 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2762 2763 #clock-cells = <0>; 2764 }; 2765 2766 sram@c3f0000 { 2767 compatible = "qcom,rpmh-stats"; 2768 reg = <0 0x0c3f0000 0 0x400>; 2769 }; 2770 2771 spmi_bus: spmi@c440000 { 2772 compatible = "qcom,spmi-pmic-arb"; 2773 reg = <0 0x0c440000 0 0x1100>, 2774 <0 0x0c600000 0 0x2000000>, 2775 <0 0x0e600000 0 0x100000>, 2776 <0 0x0e700000 0 0xa0000>, 2777 <0 0x0c40a000 0 0x26000>; 2778 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2779 interrupt-names = "periph_irq"; 2780 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2781 qcom,ee = <0>; 2782 qcom,channel = <0>; 2783 #address-cells = <1>; 2784 #size-cells = <1>; 2785 interrupt-controller; 2786 #interrupt-cells = <4>; 2787 }; 2788 2789 tlmm: pinctrl@f100000 { 2790 compatible = "qcom,sc7280-pinctrl"; 2791 reg = <0 0x0f100000 0 0x300000>; 2792 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2793 gpio-controller; 2794 #gpio-cells = <2>; 2795 interrupt-controller; 2796 #interrupt-cells = <2>; 2797 gpio-ranges = <&tlmm 0 0 175>; 2798 wakeup-parent = <&pdc>; 2799 2800 pcie1_clkreq_n: pcie1-clkreq-n { 2801 pins = "gpio79"; 2802 function = "pcie1_clkreqn"; 2803 drive-strength = <2>; 2804 bias-pull-up; 2805 }; 2806 2807 qspi_clk: qspi-clk { 2808 pins = "gpio14"; 2809 function = "qspi_clk"; 2810 }; 2811 2812 qspi_cs0: qspi-cs0 { 2813 pins = "gpio15"; 2814 function = "qspi_cs"; 2815 }; 2816 2817 qspi_cs1: qspi-cs1 { 2818 pins = "gpio19"; 2819 function = "qspi_cs"; 2820 }; 2821 2822 qspi_data01: qspi-data01 { 2823 pins = "gpio12", "gpio13"; 2824 function = "qspi_data"; 2825 }; 2826 2827 qspi_data12: qspi-data12 { 2828 pins = "gpio16", "gpio17"; 2829 function = "qspi_data"; 2830 }; 2831 2832 qup_i2c0_data_clk: qup-i2c0-data-clk { 2833 pins = "gpio0", "gpio1"; 2834 function = "qup00"; 2835 }; 2836 2837 qup_i2c1_data_clk: qup-i2c1-data-clk { 2838 pins = "gpio4", "gpio5"; 2839 function = "qup01"; 2840 }; 2841 2842 qup_i2c2_data_clk: qup-i2c2-data-clk { 2843 pins = "gpio8", "gpio9"; 2844 function = "qup02"; 2845 }; 2846 2847 qup_i2c3_data_clk: qup-i2c3-data-clk { 2848 pins = "gpio12", "gpio13"; 2849 function = "qup03"; 2850 }; 2851 2852 qup_i2c4_data_clk: qup-i2c4-data-clk { 2853 pins = "gpio16", "gpio17"; 2854 function = "qup04"; 2855 }; 2856 2857 qup_i2c5_data_clk: qup-i2c5-data-clk { 2858 pins = "gpio20", "gpio21"; 2859 function = "qup05"; 2860 }; 2861 2862 qup_i2c6_data_clk: qup-i2c6-data-clk { 2863 pins = "gpio24", "gpio25"; 2864 function = "qup06"; 2865 }; 2866 2867 qup_i2c7_data_clk: qup-i2c7-data-clk { 2868 pins = "gpio28", "gpio29"; 2869 function = "qup07"; 2870 }; 2871 2872 qup_i2c8_data_clk: qup-i2c8-data-clk { 2873 pins = "gpio32", "gpio33"; 2874 function = "qup10"; 2875 }; 2876 2877 qup_i2c9_data_clk: qup-i2c9-data-clk { 2878 pins = "gpio36", "gpio37"; 2879 function = "qup11"; 2880 }; 2881 2882 qup_i2c10_data_clk: qup-i2c10-data-clk { 2883 pins = "gpio40", "gpio41"; 2884 function = "qup12"; 2885 }; 2886 2887 qup_i2c11_data_clk: qup-i2c11-data-clk { 2888 pins = "gpio44", "gpio45"; 2889 function = "qup13"; 2890 }; 2891 2892 qup_i2c12_data_clk: qup-i2c12-data-clk { 2893 pins = "gpio48", "gpio49"; 2894 function = "qup14"; 2895 }; 2896 2897 qup_i2c13_data_clk: qup-i2c13-data-clk { 2898 pins = "gpio52", "gpio53"; 2899 function = "qup15"; 2900 }; 2901 2902 qup_i2c14_data_clk: qup-i2c14-data-clk { 2903 pins = "gpio56", "gpio57"; 2904 function = "qup16"; 2905 }; 2906 2907 qup_i2c15_data_clk: qup-i2c15-data-clk { 2908 pins = "gpio60", "gpio61"; 2909 function = "qup17"; 2910 }; 2911 2912 qup_spi0_data_clk: qup-spi0-data-clk { 2913 pins = "gpio0", "gpio1", "gpio2"; 2914 function = "qup00"; 2915 }; 2916 2917 qup_spi0_cs: qup-spi0-cs { 2918 pins = "gpio3"; 2919 function = "qup00"; 2920 }; 2921 2922 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 2923 pins = "gpio3"; 2924 function = "gpio"; 2925 }; 2926 2927 qup_spi1_data_clk: qup-spi1-data-clk { 2928 pins = "gpio4", "gpio5", "gpio6"; 2929 function = "qup01"; 2930 }; 2931 2932 qup_spi1_cs: qup-spi1-cs { 2933 pins = "gpio7"; 2934 function = "qup01"; 2935 }; 2936 2937 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 2938 pins = "gpio7"; 2939 function = "gpio"; 2940 }; 2941 2942 qup_spi2_data_clk: qup-spi2-data-clk { 2943 pins = "gpio8", "gpio9", "gpio10"; 2944 function = "qup02"; 2945 }; 2946 2947 qup_spi2_cs: qup-spi2-cs { 2948 pins = "gpio11"; 2949 function = "qup02"; 2950 }; 2951 2952 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 2953 pins = "gpio11"; 2954 function = "gpio"; 2955 }; 2956 2957 qup_spi3_data_clk: qup-spi3-data-clk { 2958 pins = "gpio12", "gpio13", "gpio14"; 2959 function = "qup03"; 2960 }; 2961 2962 qup_spi3_cs: qup-spi3-cs { 2963 pins = "gpio15"; 2964 function = "qup03"; 2965 }; 2966 2967 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 2968 pins = "gpio15"; 2969 function = "gpio"; 2970 }; 2971 2972 qup_spi4_data_clk: qup-spi4-data-clk { 2973 pins = "gpio16", "gpio17", "gpio18"; 2974 function = "qup04"; 2975 }; 2976 2977 qup_spi4_cs: qup-spi4-cs { 2978 pins = "gpio19"; 2979 function = "qup04"; 2980 }; 2981 2982 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 2983 pins = "gpio19"; 2984 function = "gpio"; 2985 }; 2986 2987 qup_spi5_data_clk: qup-spi5-data-clk { 2988 pins = "gpio20", "gpio21", "gpio22"; 2989 function = "qup05"; 2990 }; 2991 2992 qup_spi5_cs: qup-spi5-cs { 2993 pins = "gpio23"; 2994 function = "qup05"; 2995 }; 2996 2997 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 2998 pins = "gpio23"; 2999 function = "gpio"; 3000 }; 3001 3002 qup_spi6_data_clk: qup-spi6-data-clk { 3003 pins = "gpio24", "gpio25", "gpio26"; 3004 function = "qup06"; 3005 }; 3006 3007 qup_spi6_cs: qup-spi6-cs { 3008 pins = "gpio27"; 3009 function = "qup06"; 3010 }; 3011 3012 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3013 pins = "gpio27"; 3014 function = "gpio"; 3015 }; 3016 3017 qup_spi7_data_clk: qup-spi7-data-clk { 3018 pins = "gpio28", "gpio29", "gpio30"; 3019 function = "qup07"; 3020 }; 3021 3022 qup_spi7_cs: qup-spi7-cs { 3023 pins = "gpio31"; 3024 function = "qup07"; 3025 }; 3026 3027 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3028 pins = "gpio31"; 3029 function = "gpio"; 3030 }; 3031 3032 qup_spi8_data_clk: qup-spi8-data-clk { 3033 pins = "gpio32", "gpio33", "gpio34"; 3034 function = "qup10"; 3035 }; 3036 3037 qup_spi8_cs: qup-spi8-cs { 3038 pins = "gpio35"; 3039 function = "qup10"; 3040 }; 3041 3042 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 3043 pins = "gpio35"; 3044 function = "gpio"; 3045 }; 3046 3047 qup_spi9_data_clk: qup-spi9-data-clk { 3048 pins = "gpio36", "gpio37", "gpio38"; 3049 function = "qup11"; 3050 }; 3051 3052 qup_spi9_cs: qup-spi9-cs { 3053 pins = "gpio39"; 3054 function = "qup11"; 3055 }; 3056 3057 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 3058 pins = "gpio39"; 3059 function = "gpio"; 3060 }; 3061 3062 qup_spi10_data_clk: qup-spi10-data-clk { 3063 pins = "gpio40", "gpio41", "gpio42"; 3064 function = "qup12"; 3065 }; 3066 3067 qup_spi10_cs: qup-spi10-cs { 3068 pins = "gpio43"; 3069 function = "qup12"; 3070 }; 3071 3072 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 3073 pins = "gpio43"; 3074 function = "gpio"; 3075 }; 3076 3077 qup_spi11_data_clk: qup-spi11-data-clk { 3078 pins = "gpio44", "gpio45", "gpio46"; 3079 function = "qup13"; 3080 }; 3081 3082 qup_spi11_cs: qup-spi11-cs { 3083 pins = "gpio47"; 3084 function = "qup13"; 3085 }; 3086 3087 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 3088 pins = "gpio47"; 3089 function = "gpio"; 3090 }; 3091 3092 qup_spi12_data_clk: qup-spi12-data-clk { 3093 pins = "gpio48", "gpio49", "gpio50"; 3094 function = "qup14"; 3095 }; 3096 3097 qup_spi12_cs: qup-spi12-cs { 3098 pins = "gpio51"; 3099 function = "qup14"; 3100 }; 3101 3102 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 3103 pins = "gpio51"; 3104 function = "gpio"; 3105 }; 3106 3107 qup_spi13_data_clk: qup-spi13-data-clk { 3108 pins = "gpio52", "gpio53", "gpio54"; 3109 function = "qup15"; 3110 }; 3111 3112 qup_spi13_cs: qup-spi13-cs { 3113 pins = "gpio55"; 3114 function = "qup15"; 3115 }; 3116 3117 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 3118 pins = "gpio55"; 3119 function = "gpio"; 3120 }; 3121 3122 qup_spi14_data_clk: qup-spi14-data-clk { 3123 pins = "gpio56", "gpio57", "gpio58"; 3124 function = "qup16"; 3125 }; 3126 3127 qup_spi14_cs: qup-spi14-cs { 3128 pins = "gpio59"; 3129 function = "qup16"; 3130 }; 3131 3132 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 3133 pins = "gpio59"; 3134 function = "gpio"; 3135 }; 3136 3137 qup_spi15_data_clk: qup-spi15-data-clk { 3138 pins = "gpio60", "gpio61", "gpio62"; 3139 function = "qup17"; 3140 }; 3141 3142 qup_spi15_cs: qup-spi15-cs { 3143 pins = "gpio63"; 3144 function = "qup17"; 3145 }; 3146 3147 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 3148 pins = "gpio63"; 3149 function = "gpio"; 3150 }; 3151 3152 qup_uart0_cts: qup-uart0-cts { 3153 pins = "gpio0"; 3154 function = "qup00"; 3155 }; 3156 3157 qup_uart0_rts: qup-uart0-rts { 3158 pins = "gpio1"; 3159 function = "qup00"; 3160 }; 3161 3162 qup_uart0_tx: qup-uart0-tx { 3163 pins = "gpio2"; 3164 function = "qup00"; 3165 }; 3166 3167 qup_uart0_rx: qup-uart0-rx { 3168 pins = "gpio3"; 3169 function = "qup00"; 3170 }; 3171 3172 qup_uart1_cts: qup-uart1-cts { 3173 pins = "gpio4"; 3174 function = "qup01"; 3175 }; 3176 3177 qup_uart1_rts: qup-uart1-rts { 3178 pins = "gpio5"; 3179 function = "qup01"; 3180 }; 3181 3182 qup_uart1_tx: qup-uart1-tx { 3183 pins = "gpio6"; 3184 function = "qup01"; 3185 }; 3186 3187 qup_uart1_rx: qup-uart1-rx { 3188 pins = "gpio7"; 3189 function = "qup01"; 3190 }; 3191 3192 qup_uart2_cts: qup-uart2-cts { 3193 pins = "gpio8"; 3194 function = "qup02"; 3195 }; 3196 3197 qup_uart2_rts: qup-uart2-rts { 3198 pins = "gpio9"; 3199 function = "qup02"; 3200 }; 3201 3202 qup_uart2_tx: qup-uart2-tx { 3203 pins = "gpio10"; 3204 function = "qup02"; 3205 }; 3206 3207 qup_uart2_rx: qup-uart2-rx { 3208 pins = "gpio11"; 3209 function = "qup02"; 3210 }; 3211 3212 qup_uart3_cts: qup-uart3-cts { 3213 pins = "gpio12"; 3214 function = "qup03"; 3215 }; 3216 3217 qup_uart3_rts: qup-uart3-rts { 3218 pins = "gpio13"; 3219 function = "qup03"; 3220 }; 3221 3222 qup_uart3_tx: qup-uart3-tx { 3223 pins = "gpio14"; 3224 function = "qup03"; 3225 }; 3226 3227 qup_uart3_rx: qup-uart3-rx { 3228 pins = "gpio15"; 3229 function = "qup03"; 3230 }; 3231 3232 qup_uart4_cts: qup-uart4-cts { 3233 pins = "gpio16"; 3234 function = "qup04"; 3235 }; 3236 3237 qup_uart4_rts: qup-uart4-rts { 3238 pins = "gpio17"; 3239 function = "qup04"; 3240 }; 3241 3242 qup_uart4_tx: qup-uart4-tx { 3243 pins = "gpio18"; 3244 function = "qup04"; 3245 }; 3246 3247 qup_uart4_rx: qup-uart4-rx { 3248 pins = "gpio19"; 3249 function = "qup04"; 3250 }; 3251 3252 qup_uart5_cts: qup-uart5-cts { 3253 pins = "gpio20"; 3254 function = "qup05"; 3255 }; 3256 3257 qup_uart5_rts: qup-uart5-rts { 3258 pins = "gpio21"; 3259 function = "qup05"; 3260 }; 3261 3262 qup_uart5_tx: qup-uart5-tx { 3263 pins = "gpio22"; 3264 function = "qup05"; 3265 }; 3266 3267 qup_uart5_rx: qup-uart5-rx { 3268 pins = "gpio23"; 3269 function = "qup05"; 3270 }; 3271 3272 qup_uart6_cts: qup-uart6-cts { 3273 pins = "gpio24"; 3274 function = "qup06"; 3275 }; 3276 3277 qup_uart6_rts: qup-uart6-rts { 3278 pins = "gpio25"; 3279 function = "qup06"; 3280 }; 3281 3282 qup_uart6_tx: qup-uart6-tx { 3283 pins = "gpio26"; 3284 function = "qup06"; 3285 }; 3286 3287 qup_uart6_rx: qup-uart6-rx { 3288 pins = "gpio27"; 3289 function = "qup06"; 3290 }; 3291 3292 qup_uart7_cts: qup-uart7-cts { 3293 pins = "gpio28"; 3294 function = "qup07"; 3295 }; 3296 3297 qup_uart7_rts: qup-uart7-rts { 3298 pins = "gpio29"; 3299 function = "qup07"; 3300 }; 3301 3302 qup_uart7_tx: qup-uart7-tx { 3303 pins = "gpio30"; 3304 function = "qup07"; 3305 }; 3306 3307 qup_uart7_rx: qup-uart7-rx { 3308 pins = "gpio31"; 3309 function = "qup07"; 3310 }; 3311 3312 sdc1_on: sdc1-on { 3313 clk { 3314 pins = "sdc1_clk"; 3315 }; 3316 3317 cmd { 3318 pins = "sdc1_cmd"; 3319 }; 3320 3321 data { 3322 pins = "sdc1_data"; 3323 }; 3324 3325 rclk { 3326 pins = "sdc1_rclk"; 3327 }; 3328 }; 3329 3330 sdc1_off: sdc1-off { 3331 clk { 3332 pins = "sdc1_clk"; 3333 drive-strength = <2>; 3334 bias-bus-hold; 3335 }; 3336 3337 cmd { 3338 pins = "sdc1_cmd"; 3339 drive-strength = <2>; 3340 bias-bus-hold; 3341 }; 3342 3343 data { 3344 pins = "sdc1_data"; 3345 drive-strength = <2>; 3346 bias-bus-hold; 3347 }; 3348 3349 rclk { 3350 pins = "sdc1_rclk"; 3351 bias-bus-hold; 3352 }; 3353 }; 3354 3355 sdc2_on: sdc2-on { 3356 clk { 3357 pins = "sdc2_clk"; 3358 }; 3359 3360 cmd { 3361 pins = "sdc2_cmd"; 3362 }; 3363 3364 data { 3365 pins = "sdc2_data"; 3366 }; 3367 }; 3368 3369 sdc2_off: sdc2-off { 3370 clk { 3371 pins = "sdc2_clk"; 3372 drive-strength = <2>; 3373 bias-bus-hold; 3374 }; 3375 3376 cmd { 3377 pins ="sdc2_cmd"; 3378 drive-strength = <2>; 3379 bias-bus-hold; 3380 }; 3381 3382 data { 3383 pins ="sdc2_data"; 3384 drive-strength = <2>; 3385 bias-bus-hold; 3386 }; 3387 }; 3388 3389 qup_uart8_cts: qup-uart8-cts { 3390 pins = "gpio32"; 3391 function = "qup10"; 3392 }; 3393 3394 qup_uart8_rts: qup-uart8-rts { 3395 pins = "gpio33"; 3396 function = "qup10"; 3397 }; 3398 3399 qup_uart8_tx: qup-uart8-tx { 3400 pins = "gpio34"; 3401 function = "qup10"; 3402 }; 3403 3404 qup_uart8_rx: qup-uart8-rx { 3405 pins = "gpio35"; 3406 function = "qup10"; 3407 }; 3408 3409 qup_uart9_cts: qup-uart9-cts { 3410 pins = "gpio36"; 3411 function = "qup11"; 3412 }; 3413 3414 qup_uart9_rts: qup-uart9-rts { 3415 pins = "gpio37"; 3416 function = "qup11"; 3417 }; 3418 3419 qup_uart9_tx: qup-uart9-tx { 3420 pins = "gpio38"; 3421 function = "qup11"; 3422 }; 3423 3424 qup_uart9_rx: qup-uart9-rx { 3425 pins = "gpio39"; 3426 function = "qup11"; 3427 }; 3428 3429 qup_uart10_cts: qup-uart10-cts { 3430 pins = "gpio40"; 3431 function = "qup12"; 3432 }; 3433 3434 qup_uart10_rts: qup-uart10-rts { 3435 pins = "gpio41"; 3436 function = "qup12"; 3437 }; 3438 3439 qup_uart10_tx: qup-uart10-tx { 3440 pins = "gpio42"; 3441 function = "qup12"; 3442 }; 3443 3444 qup_uart10_rx: qup-uart10-rx { 3445 pins = "gpio43"; 3446 function = "qup12"; 3447 }; 3448 3449 qup_uart11_cts: qup-uart11-cts { 3450 pins = "gpio44"; 3451 function = "qup13"; 3452 }; 3453 3454 qup_uart11_rts: qup-uart11-rts { 3455 pins = "gpio45"; 3456 function = "qup13"; 3457 }; 3458 3459 qup_uart11_tx: qup-uart11-tx { 3460 pins = "gpio46"; 3461 function = "qup13"; 3462 }; 3463 3464 qup_uart11_rx: qup-uart11-rx { 3465 pins = "gpio47"; 3466 function = "qup13"; 3467 }; 3468 3469 qup_uart12_cts: qup-uart12-cts { 3470 pins = "gpio48"; 3471 function = "qup14"; 3472 }; 3473 3474 qup_uart12_rts: qup-uart12-rts { 3475 pins = "gpio49"; 3476 function = "qup14"; 3477 }; 3478 3479 qup_uart12_tx: qup-uart12-tx { 3480 pins = "gpio50"; 3481 function = "qup14"; 3482 }; 3483 3484 qup_uart12_rx: qup-uart12-rx { 3485 pins = "gpio51"; 3486 function = "qup14"; 3487 }; 3488 3489 qup_uart13_cts: qup-uart13-cts { 3490 pins = "gpio52"; 3491 function = "qup15"; 3492 }; 3493 3494 qup_uart13_rts: qup-uart13-rts { 3495 pins = "gpio53"; 3496 function = "qup15"; 3497 }; 3498 3499 qup_uart13_tx: qup-uart13-tx { 3500 pins = "gpio54"; 3501 function = "qup15"; 3502 }; 3503 3504 qup_uart13_rx: qup-uart13-rx { 3505 pins = "gpio55"; 3506 function = "qup15"; 3507 }; 3508 3509 qup_uart14_cts: qup-uart14-cts { 3510 pins = "gpio56"; 3511 function = "qup16"; 3512 }; 3513 3514 qup_uart14_rts: qup-uart14-rts { 3515 pins = "gpio57"; 3516 function = "qup16"; 3517 }; 3518 3519 qup_uart14_tx: qup-uart14-tx { 3520 pins = "gpio58"; 3521 function = "qup16"; 3522 }; 3523 3524 qup_uart14_rx: qup-uart14-rx { 3525 pins = "gpio59"; 3526 function = "qup16"; 3527 }; 3528 3529 qup_uart15_cts: qup-uart15-cts { 3530 pins = "gpio60"; 3531 function = "qup17"; 3532 }; 3533 3534 qup_uart15_rts: qup-uart15-rts { 3535 pins = "gpio61"; 3536 function = "qup17"; 3537 }; 3538 3539 qup_uart15_tx: qup-uart15-tx { 3540 pins = "gpio62"; 3541 function = "qup17"; 3542 }; 3543 3544 qup_uart15_rx: qup-uart15-rx { 3545 pins = "gpio63"; 3546 function = "qup17"; 3547 }; 3548 }; 3549 3550 imem@146a5000 { 3551 compatible = "qcom,sc7280-imem", "syscon"; 3552 reg = <0 0x146a5000 0 0x6000>; 3553 3554 #address-cells = <1>; 3555 #size-cells = <1>; 3556 3557 ranges = <0 0 0x146a5000 0x6000>; 3558 3559 pil-reloc@594c { 3560 compatible = "qcom,pil-reloc-info"; 3561 reg = <0x594c 0xc8>; 3562 }; 3563 }; 3564 3565 apps_smmu: iommu@15000000 { 3566 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 3567 reg = <0 0x15000000 0 0x100000>; 3568 #iommu-cells = <2>; 3569 #global-interrupts = <1>; 3570 dma-coherent; 3571 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3572 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3573 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3574 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3575 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3576 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3577 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3578 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3579 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3580 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3581 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3582 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3583 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3584 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3585 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3586 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3587 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3588 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3589 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3590 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3591 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3592 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3593 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3594 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3595 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3596 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3597 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3598 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3599 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3600 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3601 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3602 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3603 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3604 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3605 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3606 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3607 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3608 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3609 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3610 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3611 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3612 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3613 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3614 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3615 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3616 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3617 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3618 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3619 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3620 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3621 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3622 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3623 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3624 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3625 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3626 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3627 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3628 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3629 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3630 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3631 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3632 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3633 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3634 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3635 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3636 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3637 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3638 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3639 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3640 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3641 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3642 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3643 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3644 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3645 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3646 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3647 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3648 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3649 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3650 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3651 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 3652 }; 3653 3654 intc: interrupt-controller@17a00000 { 3655 compatible = "arm,gic-v3"; 3656 #address-cells = <2>; 3657 #size-cells = <2>; 3658 ranges; 3659 #interrupt-cells = <3>; 3660 interrupt-controller; 3661 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3662 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3663 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 3664 3665 gic-its@17a40000 { 3666 compatible = "arm,gic-v3-its"; 3667 msi-controller; 3668 #msi-cells = <1>; 3669 reg = <0 0x17a40000 0 0x20000>; 3670 status = "disabled"; 3671 }; 3672 }; 3673 3674 watchdog@17c10000 { 3675 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 3676 reg = <0 0x17c10000 0 0x1000>; 3677 clocks = <&sleep_clk>; 3678 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3679 }; 3680 3681 timer@17c20000 { 3682 #address-cells = <2>; 3683 #size-cells = <2>; 3684 ranges; 3685 compatible = "arm,armv7-timer-mem"; 3686 reg = <0 0x17c20000 0 0x1000>; 3687 3688 frame@17c21000 { 3689 frame-number = <0>; 3690 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3691 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3692 reg = <0 0x17c21000 0 0x1000>, 3693 <0 0x17c22000 0 0x1000>; 3694 }; 3695 3696 frame@17c23000 { 3697 frame-number = <1>; 3698 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3699 reg = <0 0x17c23000 0 0x1000>; 3700 status = "disabled"; 3701 }; 3702 3703 frame@17c25000 { 3704 frame-number = <2>; 3705 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3706 reg = <0 0x17c25000 0 0x1000>; 3707 status = "disabled"; 3708 }; 3709 3710 frame@17c27000 { 3711 frame-number = <3>; 3712 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3713 reg = <0 0x17c27000 0 0x1000>; 3714 status = "disabled"; 3715 }; 3716 3717 frame@17c29000 { 3718 frame-number = <4>; 3719 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3720 reg = <0 0x17c29000 0 0x1000>; 3721 status = "disabled"; 3722 }; 3723 3724 frame@17c2b000 { 3725 frame-number = <5>; 3726 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3727 reg = <0 0x17c2b000 0 0x1000>; 3728 status = "disabled"; 3729 }; 3730 3731 frame@17c2d000 { 3732 frame-number = <6>; 3733 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3734 reg = <0 0x17c2d000 0 0x1000>; 3735 status = "disabled"; 3736 }; 3737 }; 3738 3739 apps_rsc: rsc@18200000 { 3740 compatible = "qcom,rpmh-rsc"; 3741 reg = <0 0x18200000 0 0x10000>, 3742 <0 0x18210000 0 0x10000>, 3743 <0 0x18220000 0 0x10000>; 3744 reg-names = "drv-0", "drv-1", "drv-2"; 3745 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3746 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3747 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3748 qcom,tcs-offset = <0xd00>; 3749 qcom,drv-id = <2>; 3750 qcom,tcs-config = <ACTIVE_TCS 2>, 3751 <SLEEP_TCS 3>, 3752 <WAKE_TCS 3>, 3753 <CONTROL_TCS 1>; 3754 3755 apps_bcm_voter: bcm-voter { 3756 compatible = "qcom,bcm-voter"; 3757 }; 3758 3759 rpmhpd: power-controller { 3760 compatible = "qcom,sc7280-rpmhpd"; 3761 #power-domain-cells = <1>; 3762 operating-points-v2 = <&rpmhpd_opp_table>; 3763 3764 rpmhpd_opp_table: opp-table { 3765 compatible = "operating-points-v2"; 3766 3767 rpmhpd_opp_ret: opp1 { 3768 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3769 }; 3770 3771 rpmhpd_opp_low_svs: opp2 { 3772 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3773 }; 3774 3775 rpmhpd_opp_svs: opp3 { 3776 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3777 }; 3778 3779 rpmhpd_opp_svs_l1: opp4 { 3780 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3781 }; 3782 3783 rpmhpd_opp_svs_l2: opp5 { 3784 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3785 }; 3786 3787 rpmhpd_opp_nom: opp6 { 3788 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3789 }; 3790 3791 rpmhpd_opp_nom_l1: opp7 { 3792 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3793 }; 3794 3795 rpmhpd_opp_turbo: opp8 { 3796 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3797 }; 3798 3799 rpmhpd_opp_turbo_l1: opp9 { 3800 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3801 }; 3802 }; 3803 }; 3804 3805 rpmhcc: clock-controller { 3806 compatible = "qcom,sc7280-rpmh-clk"; 3807 clocks = <&xo_board>; 3808 clock-names = "xo"; 3809 #clock-cells = <1>; 3810 }; 3811 }; 3812 3813 cpufreq_hw: cpufreq@18591000 { 3814 compatible = "qcom,cpufreq-epss"; 3815 reg = <0 0x18591000 0 0x1000>, 3816 <0 0x18592000 0 0x1000>, 3817 <0 0x18593000 0 0x1000>; 3818 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3819 clock-names = "xo", "alternate"; 3820 #freq-domain-cells = <1>; 3821 }; 3822 }; 3823 3824 thermal_zones: thermal-zones { 3825 cpu0-thermal { 3826 polling-delay-passive = <250>; 3827 polling-delay = <0>; 3828 3829 thermal-sensors = <&tsens0 1>; 3830 3831 trips { 3832 cpu0_alert0: trip-point0 { 3833 temperature = <90000>; 3834 hysteresis = <2000>; 3835 type = "passive"; 3836 }; 3837 3838 cpu0_alert1: trip-point1 { 3839 temperature = <95000>; 3840 hysteresis = <2000>; 3841 type = "passive"; 3842 }; 3843 3844 cpu0_crit: cpu-crit { 3845 temperature = <110000>; 3846 hysteresis = <0>; 3847 type = "critical"; 3848 }; 3849 }; 3850 3851 cooling-maps { 3852 map0 { 3853 trip = <&cpu0_alert0>; 3854 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3855 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3856 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3857 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3858 }; 3859 map1 { 3860 trip = <&cpu0_alert1>; 3861 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3862 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3863 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3864 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3865 }; 3866 }; 3867 }; 3868 3869 cpu1-thermal { 3870 polling-delay-passive = <250>; 3871 polling-delay = <0>; 3872 3873 thermal-sensors = <&tsens0 2>; 3874 3875 trips { 3876 cpu1_alert0: trip-point0 { 3877 temperature = <90000>; 3878 hysteresis = <2000>; 3879 type = "passive"; 3880 }; 3881 3882 cpu1_alert1: trip-point1 { 3883 temperature = <95000>; 3884 hysteresis = <2000>; 3885 type = "passive"; 3886 }; 3887 3888 cpu1_crit: cpu-crit { 3889 temperature = <110000>; 3890 hysteresis = <0>; 3891 type = "critical"; 3892 }; 3893 }; 3894 3895 cooling-maps { 3896 map0 { 3897 trip = <&cpu1_alert0>; 3898 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3899 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3900 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3901 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3902 }; 3903 map1 { 3904 trip = <&cpu1_alert1>; 3905 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3906 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3907 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3908 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3909 }; 3910 }; 3911 }; 3912 3913 cpu2-thermal { 3914 polling-delay-passive = <250>; 3915 polling-delay = <0>; 3916 3917 thermal-sensors = <&tsens0 3>; 3918 3919 trips { 3920 cpu2_alert0: trip-point0 { 3921 temperature = <90000>; 3922 hysteresis = <2000>; 3923 type = "passive"; 3924 }; 3925 3926 cpu2_alert1: trip-point1 { 3927 temperature = <95000>; 3928 hysteresis = <2000>; 3929 type = "passive"; 3930 }; 3931 3932 cpu2_crit: cpu-crit { 3933 temperature = <110000>; 3934 hysteresis = <0>; 3935 type = "critical"; 3936 }; 3937 }; 3938 3939 cooling-maps { 3940 map0 { 3941 trip = <&cpu2_alert0>; 3942 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3943 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3944 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3945 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3946 }; 3947 map1 { 3948 trip = <&cpu2_alert1>; 3949 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3950 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3951 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3952 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3953 }; 3954 }; 3955 }; 3956 3957 cpu3-thermal { 3958 polling-delay-passive = <250>; 3959 polling-delay = <0>; 3960 3961 thermal-sensors = <&tsens0 4>; 3962 3963 trips { 3964 cpu3_alert0: trip-point0 { 3965 temperature = <90000>; 3966 hysteresis = <2000>; 3967 type = "passive"; 3968 }; 3969 3970 cpu3_alert1: trip-point1 { 3971 temperature = <95000>; 3972 hysteresis = <2000>; 3973 type = "passive"; 3974 }; 3975 3976 cpu3_crit: cpu-crit { 3977 temperature = <110000>; 3978 hysteresis = <0>; 3979 type = "critical"; 3980 }; 3981 }; 3982 3983 cooling-maps { 3984 map0 { 3985 trip = <&cpu3_alert0>; 3986 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3987 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3988 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3989 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3990 }; 3991 map1 { 3992 trip = <&cpu3_alert1>; 3993 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3994 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3995 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3996 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3997 }; 3998 }; 3999 }; 4000 4001 cpu4-thermal { 4002 polling-delay-passive = <250>; 4003 polling-delay = <0>; 4004 4005 thermal-sensors = <&tsens0 7>; 4006 4007 trips { 4008 cpu4_alert0: trip-point0 { 4009 temperature = <90000>; 4010 hysteresis = <2000>; 4011 type = "passive"; 4012 }; 4013 4014 cpu4_alert1: trip-point1 { 4015 temperature = <95000>; 4016 hysteresis = <2000>; 4017 type = "passive"; 4018 }; 4019 4020 cpu4_crit: cpu-crit { 4021 temperature = <110000>; 4022 hysteresis = <0>; 4023 type = "critical"; 4024 }; 4025 }; 4026 4027 cooling-maps { 4028 map0 { 4029 trip = <&cpu4_alert0>; 4030 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4031 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4032 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4033 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4034 }; 4035 map1 { 4036 trip = <&cpu4_alert1>; 4037 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4038 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4039 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4040 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4041 }; 4042 }; 4043 }; 4044 4045 cpu5-thermal { 4046 polling-delay-passive = <250>; 4047 polling-delay = <0>; 4048 4049 thermal-sensors = <&tsens0 8>; 4050 4051 trips { 4052 cpu5_alert0: trip-point0 { 4053 temperature = <90000>; 4054 hysteresis = <2000>; 4055 type = "passive"; 4056 }; 4057 4058 cpu5_alert1: trip-point1 { 4059 temperature = <95000>; 4060 hysteresis = <2000>; 4061 type = "passive"; 4062 }; 4063 4064 cpu5_crit: cpu-crit { 4065 temperature = <110000>; 4066 hysteresis = <0>; 4067 type = "critical"; 4068 }; 4069 }; 4070 4071 cooling-maps { 4072 map0 { 4073 trip = <&cpu5_alert0>; 4074 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4075 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4076 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4077 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4078 }; 4079 map1 { 4080 trip = <&cpu5_alert1>; 4081 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4082 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4083 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4084 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4085 }; 4086 }; 4087 }; 4088 4089 cpu6-thermal { 4090 polling-delay-passive = <250>; 4091 polling-delay = <0>; 4092 4093 thermal-sensors = <&tsens0 9>; 4094 4095 trips { 4096 cpu6_alert0: trip-point0 { 4097 temperature = <90000>; 4098 hysteresis = <2000>; 4099 type = "passive"; 4100 }; 4101 4102 cpu6_alert1: trip-point1 { 4103 temperature = <95000>; 4104 hysteresis = <2000>; 4105 type = "passive"; 4106 }; 4107 4108 cpu6_crit: cpu-crit { 4109 temperature = <110000>; 4110 hysteresis = <0>; 4111 type = "critical"; 4112 }; 4113 }; 4114 4115 cooling-maps { 4116 map0 { 4117 trip = <&cpu6_alert0>; 4118 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4119 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4120 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4121 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4122 }; 4123 map1 { 4124 trip = <&cpu6_alert1>; 4125 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4126 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4127 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4128 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4129 }; 4130 }; 4131 }; 4132 4133 cpu7-thermal { 4134 polling-delay-passive = <250>; 4135 polling-delay = <0>; 4136 4137 thermal-sensors = <&tsens0 10>; 4138 4139 trips { 4140 cpu7_alert0: trip-point0 { 4141 temperature = <90000>; 4142 hysteresis = <2000>; 4143 type = "passive"; 4144 }; 4145 4146 cpu7_alert1: trip-point1 { 4147 temperature = <95000>; 4148 hysteresis = <2000>; 4149 type = "passive"; 4150 }; 4151 4152 cpu7_crit: cpu-crit { 4153 temperature = <110000>; 4154 hysteresis = <0>; 4155 type = "critical"; 4156 }; 4157 }; 4158 4159 cooling-maps { 4160 map0 { 4161 trip = <&cpu7_alert0>; 4162 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4163 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4164 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4165 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4166 }; 4167 map1 { 4168 trip = <&cpu7_alert1>; 4169 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4170 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4171 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4172 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4173 }; 4174 }; 4175 }; 4176 4177 cpu8-thermal { 4178 polling-delay-passive = <250>; 4179 polling-delay = <0>; 4180 4181 thermal-sensors = <&tsens0 11>; 4182 4183 trips { 4184 cpu8_alert0: trip-point0 { 4185 temperature = <90000>; 4186 hysteresis = <2000>; 4187 type = "passive"; 4188 }; 4189 4190 cpu8_alert1: trip-point1 { 4191 temperature = <95000>; 4192 hysteresis = <2000>; 4193 type = "passive"; 4194 }; 4195 4196 cpu8_crit: cpu-crit { 4197 temperature = <110000>; 4198 hysteresis = <0>; 4199 type = "critical"; 4200 }; 4201 }; 4202 4203 cooling-maps { 4204 map0 { 4205 trip = <&cpu8_alert0>; 4206 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4207 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4208 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4209 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4210 }; 4211 map1 { 4212 trip = <&cpu8_alert1>; 4213 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4214 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4215 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4216 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4217 }; 4218 }; 4219 }; 4220 4221 cpu9-thermal { 4222 polling-delay-passive = <250>; 4223 polling-delay = <0>; 4224 4225 thermal-sensors = <&tsens0 12>; 4226 4227 trips { 4228 cpu9_alert0: trip-point0 { 4229 temperature = <90000>; 4230 hysteresis = <2000>; 4231 type = "passive"; 4232 }; 4233 4234 cpu9_alert1: trip-point1 { 4235 temperature = <95000>; 4236 hysteresis = <2000>; 4237 type = "passive"; 4238 }; 4239 4240 cpu9_crit: cpu-crit { 4241 temperature = <110000>; 4242 hysteresis = <0>; 4243 type = "critical"; 4244 }; 4245 }; 4246 4247 cooling-maps { 4248 map0 { 4249 trip = <&cpu9_alert0>; 4250 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4251 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4252 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4253 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4254 }; 4255 map1 { 4256 trip = <&cpu9_alert1>; 4257 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4258 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4259 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4260 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4261 }; 4262 }; 4263 }; 4264 4265 cpu10-thermal { 4266 polling-delay-passive = <250>; 4267 polling-delay = <0>; 4268 4269 thermal-sensors = <&tsens0 13>; 4270 4271 trips { 4272 cpu10_alert0: trip-point0 { 4273 temperature = <90000>; 4274 hysteresis = <2000>; 4275 type = "passive"; 4276 }; 4277 4278 cpu10_alert1: trip-point1 { 4279 temperature = <95000>; 4280 hysteresis = <2000>; 4281 type = "passive"; 4282 }; 4283 4284 cpu10_crit: cpu-crit { 4285 temperature = <110000>; 4286 hysteresis = <0>; 4287 type = "critical"; 4288 }; 4289 }; 4290 4291 cooling-maps { 4292 map0 { 4293 trip = <&cpu10_alert0>; 4294 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4295 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4296 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4297 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4298 }; 4299 map1 { 4300 trip = <&cpu10_alert1>; 4301 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4302 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4303 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4304 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4305 }; 4306 }; 4307 }; 4308 4309 cpu11-thermal { 4310 polling-delay-passive = <250>; 4311 polling-delay = <0>; 4312 4313 thermal-sensors = <&tsens0 14>; 4314 4315 trips { 4316 cpu11_alert0: trip-point0 { 4317 temperature = <90000>; 4318 hysteresis = <2000>; 4319 type = "passive"; 4320 }; 4321 4322 cpu11_alert1: trip-point1 { 4323 temperature = <95000>; 4324 hysteresis = <2000>; 4325 type = "passive"; 4326 }; 4327 4328 cpu11_crit: cpu-crit { 4329 temperature = <110000>; 4330 hysteresis = <0>; 4331 type = "critical"; 4332 }; 4333 }; 4334 4335 cooling-maps { 4336 map0 { 4337 trip = <&cpu11_alert0>; 4338 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4339 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4340 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4341 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4342 }; 4343 map1 { 4344 trip = <&cpu11_alert1>; 4345 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4346 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4347 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4348 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4349 }; 4350 }; 4351 }; 4352 4353 aoss0-thermal { 4354 polling-delay-passive = <0>; 4355 polling-delay = <0>; 4356 4357 thermal-sensors = <&tsens0 0>; 4358 4359 trips { 4360 aoss0_alert0: trip-point0 { 4361 temperature = <90000>; 4362 hysteresis = <2000>; 4363 type = "hot"; 4364 }; 4365 4366 aoss0_crit: aoss0-crit { 4367 temperature = <110000>; 4368 hysteresis = <0>; 4369 type = "critical"; 4370 }; 4371 }; 4372 }; 4373 4374 aoss1-thermal { 4375 polling-delay-passive = <0>; 4376 polling-delay = <0>; 4377 4378 thermal-sensors = <&tsens1 0>; 4379 4380 trips { 4381 aoss1_alert0: trip-point0 { 4382 temperature = <90000>; 4383 hysteresis = <2000>; 4384 type = "hot"; 4385 }; 4386 4387 aoss1_crit: aoss1-crit { 4388 temperature = <110000>; 4389 hysteresis = <0>; 4390 type = "critical"; 4391 }; 4392 }; 4393 }; 4394 4395 cpuss0-thermal { 4396 polling-delay-passive = <0>; 4397 polling-delay = <0>; 4398 4399 thermal-sensors = <&tsens0 5>; 4400 4401 trips { 4402 cpuss0_alert0: trip-point0 { 4403 temperature = <90000>; 4404 hysteresis = <2000>; 4405 type = "hot"; 4406 }; 4407 cpuss0_crit: cluster0-crit { 4408 temperature = <110000>; 4409 hysteresis = <0>; 4410 type = "critical"; 4411 }; 4412 }; 4413 }; 4414 4415 cpuss1-thermal { 4416 polling-delay-passive = <0>; 4417 polling-delay = <0>; 4418 4419 thermal-sensors = <&tsens0 6>; 4420 4421 trips { 4422 cpuss1_alert0: trip-point0 { 4423 temperature = <90000>; 4424 hysteresis = <2000>; 4425 type = "hot"; 4426 }; 4427 cpuss1_crit: cluster0-crit { 4428 temperature = <110000>; 4429 hysteresis = <0>; 4430 type = "critical"; 4431 }; 4432 }; 4433 }; 4434 4435 gpuss0-thermal { 4436 polling-delay-passive = <100>; 4437 polling-delay = <0>; 4438 4439 thermal-sensors = <&tsens1 1>; 4440 4441 trips { 4442 gpuss0_alert0: trip-point0 { 4443 temperature = <95000>; 4444 hysteresis = <2000>; 4445 type = "passive"; 4446 }; 4447 4448 gpuss0_crit: gpuss0-crit { 4449 temperature = <110000>; 4450 hysteresis = <0>; 4451 type = "critical"; 4452 }; 4453 }; 4454 4455 cooling-maps { 4456 map0 { 4457 trip = <&gpuss0_alert0>; 4458 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4459 }; 4460 }; 4461 }; 4462 4463 gpuss1-thermal { 4464 polling-delay-passive = <100>; 4465 polling-delay = <0>; 4466 4467 thermal-sensors = <&tsens1 2>; 4468 4469 trips { 4470 gpuss1_alert0: trip-point0 { 4471 temperature = <95000>; 4472 hysteresis = <2000>; 4473 type = "passive"; 4474 }; 4475 4476 gpuss1_crit: gpuss1-crit { 4477 temperature = <110000>; 4478 hysteresis = <0>; 4479 type = "critical"; 4480 }; 4481 }; 4482 4483 cooling-maps { 4484 map0 { 4485 trip = <&gpuss1_alert0>; 4486 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4487 }; 4488 }; 4489 }; 4490 4491 nspss0-thermal { 4492 polling-delay-passive = <0>; 4493 polling-delay = <0>; 4494 4495 thermal-sensors = <&tsens1 3>; 4496 4497 trips { 4498 nspss0_alert0: trip-point0 { 4499 temperature = <90000>; 4500 hysteresis = <2000>; 4501 type = "hot"; 4502 }; 4503 4504 nspss0_crit: nspss0-crit { 4505 temperature = <110000>; 4506 hysteresis = <0>; 4507 type = "critical"; 4508 }; 4509 }; 4510 }; 4511 4512 nspss1-thermal { 4513 polling-delay-passive = <0>; 4514 polling-delay = <0>; 4515 4516 thermal-sensors = <&tsens1 4>; 4517 4518 trips { 4519 nspss1_alert0: trip-point0 { 4520 temperature = <90000>; 4521 hysteresis = <2000>; 4522 type = "hot"; 4523 }; 4524 4525 nspss1_crit: nspss1-crit { 4526 temperature = <110000>; 4527 hysteresis = <0>; 4528 type = "critical"; 4529 }; 4530 }; 4531 }; 4532 4533 video-thermal { 4534 polling-delay-passive = <0>; 4535 polling-delay = <0>; 4536 4537 thermal-sensors = <&tsens1 5>; 4538 4539 trips { 4540 video_alert0: trip-point0 { 4541 temperature = <90000>; 4542 hysteresis = <2000>; 4543 type = "hot"; 4544 }; 4545 4546 video_crit: video-crit { 4547 temperature = <110000>; 4548 hysteresis = <0>; 4549 type = "critical"; 4550 }; 4551 }; 4552 }; 4553 4554 ddr-thermal { 4555 polling-delay-passive = <0>; 4556 polling-delay = <0>; 4557 4558 thermal-sensors = <&tsens1 6>; 4559 4560 trips { 4561 ddr_alert0: trip-point0 { 4562 temperature = <90000>; 4563 hysteresis = <2000>; 4564 type = "hot"; 4565 }; 4566 4567 ddr_crit: ddr-crit { 4568 temperature = <110000>; 4569 hysteresis = <0>; 4570 type = "critical"; 4571 }; 4572 }; 4573 }; 4574 4575 mdmss0-thermal { 4576 polling-delay-passive = <0>; 4577 polling-delay = <0>; 4578 4579 thermal-sensors = <&tsens1 7>; 4580 4581 trips { 4582 mdmss0_alert0: trip-point0 { 4583 temperature = <90000>; 4584 hysteresis = <2000>; 4585 type = "hot"; 4586 }; 4587 4588 mdmss0_crit: mdmss0-crit { 4589 temperature = <110000>; 4590 hysteresis = <0>; 4591 type = "critical"; 4592 }; 4593 }; 4594 }; 4595 4596 mdmss1-thermal { 4597 polling-delay-passive = <0>; 4598 polling-delay = <0>; 4599 4600 thermal-sensors = <&tsens1 8>; 4601 4602 trips { 4603 mdmss1_alert0: trip-point0 { 4604 temperature = <90000>; 4605 hysteresis = <2000>; 4606 type = "hot"; 4607 }; 4608 4609 mdmss1_crit: mdmss1-crit { 4610 temperature = <110000>; 4611 hysteresis = <0>; 4612 type = "critical"; 4613 }; 4614 }; 4615 }; 4616 4617 mdmss2-thermal { 4618 polling-delay-passive = <0>; 4619 polling-delay = <0>; 4620 4621 thermal-sensors = <&tsens1 9>; 4622 4623 trips { 4624 mdmss2_alert0: trip-point0 { 4625 temperature = <90000>; 4626 hysteresis = <2000>; 4627 type = "hot"; 4628 }; 4629 4630 mdmss2_crit: mdmss2-crit { 4631 temperature = <110000>; 4632 hysteresis = <0>; 4633 type = "critical"; 4634 }; 4635 }; 4636 }; 4637 4638 mdmss3-thermal { 4639 polling-delay-passive = <0>; 4640 polling-delay = <0>; 4641 4642 thermal-sensors = <&tsens1 10>; 4643 4644 trips { 4645 mdmss3_alert0: trip-point0 { 4646 temperature = <90000>; 4647 hysteresis = <2000>; 4648 type = "hot"; 4649 }; 4650 4651 mdmss3_crit: mdmss3-crit { 4652 temperature = <110000>; 4653 hysteresis = <0>; 4654 type = "critical"; 4655 }; 4656 }; 4657 }; 4658 4659 camera0-thermal { 4660 polling-delay-passive = <0>; 4661 polling-delay = <0>; 4662 4663 thermal-sensors = <&tsens1 11>; 4664 4665 trips { 4666 camera0_alert0: trip-point0 { 4667 temperature = <90000>; 4668 hysteresis = <2000>; 4669 type = "hot"; 4670 }; 4671 4672 camera0_crit: camera0-crit { 4673 temperature = <110000>; 4674 hysteresis = <0>; 4675 type = "critical"; 4676 }; 4677 }; 4678 }; 4679 }; 4680 4681 timer { 4682 compatible = "arm,armv8-timer"; 4683 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 4684 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 4685 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 4686 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 4687 }; 4688}; 4689