1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/interconnect/qcom,osm-l3.h> 17#include <dt-bindings/interconnect/qcom,sc7280.h> 18#include <dt-bindings/interrupt-controller/arm-gic.h> 19#include <dt-bindings/mailbox/qcom-ipcc.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/reset/qcom,sdm845-aoss.h> 22#include <dt-bindings/reset/qcom,sdm845-pdc.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/thermal/thermal.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 chosen { }; 33 34 aliases { 35 i2c0 = &i2c0; 36 i2c1 = &i2c1; 37 i2c2 = &i2c2; 38 i2c3 = &i2c3; 39 i2c4 = &i2c4; 40 i2c5 = &i2c5; 41 i2c6 = &i2c6; 42 i2c7 = &i2c7; 43 i2c8 = &i2c8; 44 i2c9 = &i2c9; 45 i2c10 = &i2c10; 46 i2c11 = &i2c11; 47 i2c12 = &i2c12; 48 i2c13 = &i2c13; 49 i2c14 = &i2c14; 50 i2c15 = &i2c15; 51 mmc1 = &sdhc_1; 52 mmc2 = &sdhc_2; 53 spi0 = &spi0; 54 spi1 = &spi1; 55 spi2 = &spi2; 56 spi3 = &spi3; 57 spi4 = &spi4; 58 spi5 = &spi5; 59 spi6 = &spi6; 60 spi7 = &spi7; 61 spi8 = &spi8; 62 spi9 = &spi9; 63 spi10 = &spi10; 64 spi11 = &spi11; 65 spi12 = &spi12; 66 spi13 = &spi13; 67 spi14 = &spi14; 68 spi15 = &spi15; 69 }; 70 71 clocks { 72 xo_board: xo-board { 73 compatible = "fixed-clock"; 74 clock-frequency = <76800000>; 75 #clock-cells = <0>; 76 }; 77 78 sleep_clk: sleep-clk { 79 compatible = "fixed-clock"; 80 clock-frequency = <32000>; 81 #clock-cells = <0>; 82 }; 83 }; 84 85 reserved-memory { 86 #address-cells = <2>; 87 #size-cells = <2>; 88 ranges; 89 90 wlan_ce_mem: memory@4cd000 { 91 no-map; 92 reg = <0x0 0x004cd000 0x0 0x1000>; 93 }; 94 95 hyp_mem: memory@80000000 { 96 reg = <0x0 0x80000000 0x0 0x600000>; 97 no-map; 98 }; 99 100 xbl_mem: memory@80600000 { 101 reg = <0x0 0x80600000 0x0 0x200000>; 102 no-map; 103 }; 104 105 aop_mem: memory@80800000 { 106 reg = <0x0 0x80800000 0x0 0x60000>; 107 no-map; 108 }; 109 110 aop_cmd_db_mem: memory@80860000 { 111 reg = <0x0 0x80860000 0x0 0x20000>; 112 compatible = "qcom,cmd-db"; 113 no-map; 114 }; 115 116 reserved_xbl_uefi_log: memory@80880000 { 117 reg = <0x0 0x80884000 0x0 0x10000>; 118 no-map; 119 }; 120 121 sec_apps_mem: memory@808ff000 { 122 reg = <0x0 0x808ff000 0x0 0x1000>; 123 no-map; 124 }; 125 126 smem_mem: memory@80900000 { 127 reg = <0x0 0x80900000 0x0 0x200000>; 128 no-map; 129 }; 130 131 cpucp_mem: memory@80b00000 { 132 no-map; 133 reg = <0x0 0x80b00000 0x0 0x100000>; 134 }; 135 136 wlan_fw_mem: memory@80c00000 { 137 reg = <0x0 0x80c00000 0x0 0xc00000>; 138 no-map; 139 }; 140 141 video_mem: memory@8b200000 { 142 reg = <0x0 0x8b200000 0x0 0x500000>; 143 no-map; 144 }; 145 146 ipa_fw_mem: memory@8b700000 { 147 reg = <0 0x8b700000 0 0x10000>; 148 no-map; 149 }; 150 151 rmtfs_mem: memory@9c900000 { 152 compatible = "qcom,rmtfs-mem"; 153 reg = <0x0 0x9c900000 0x0 0x280000>; 154 no-map; 155 156 qcom,client-id = <1>; 157 qcom,vmid = <15>; 158 }; 159 }; 160 161 cpus { 162 #address-cells = <2>; 163 #size-cells = <0>; 164 165 CPU0: cpu@0 { 166 device_type = "cpu"; 167 compatible = "arm,kryo"; 168 reg = <0x0 0x0>; 169 enable-method = "psci"; 170 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 171 &LITTLE_CPU_SLEEP_1 172 &CLUSTER_SLEEP_0>; 173 next-level-cache = <&L2_0>; 174 operating-points-v2 = <&cpu0_opp_table>; 175 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 176 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 177 qcom,freq-domain = <&cpufreq_hw 0>; 178 #cooling-cells = <2>; 179 L2_0: l2-cache { 180 compatible = "cache"; 181 next-level-cache = <&L3_0>; 182 L3_0: l3-cache { 183 compatible = "cache"; 184 }; 185 }; 186 }; 187 188 CPU1: cpu@100 { 189 device_type = "cpu"; 190 compatible = "arm,kryo"; 191 reg = <0x0 0x100>; 192 enable-method = "psci"; 193 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 194 &LITTLE_CPU_SLEEP_1 195 &CLUSTER_SLEEP_0>; 196 next-level-cache = <&L2_100>; 197 operating-points-v2 = <&cpu0_opp_table>; 198 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 199 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 200 qcom,freq-domain = <&cpufreq_hw 0>; 201 #cooling-cells = <2>; 202 L2_100: l2-cache { 203 compatible = "cache"; 204 next-level-cache = <&L3_0>; 205 }; 206 }; 207 208 CPU2: cpu@200 { 209 device_type = "cpu"; 210 compatible = "arm,kryo"; 211 reg = <0x0 0x200>; 212 enable-method = "psci"; 213 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 214 &LITTLE_CPU_SLEEP_1 215 &CLUSTER_SLEEP_0>; 216 next-level-cache = <&L2_200>; 217 operating-points-v2 = <&cpu0_opp_table>; 218 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 219 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 220 qcom,freq-domain = <&cpufreq_hw 0>; 221 #cooling-cells = <2>; 222 L2_200: l2-cache { 223 compatible = "cache"; 224 next-level-cache = <&L3_0>; 225 }; 226 }; 227 228 CPU3: cpu@300 { 229 device_type = "cpu"; 230 compatible = "arm,kryo"; 231 reg = <0x0 0x300>; 232 enable-method = "psci"; 233 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 234 &LITTLE_CPU_SLEEP_1 235 &CLUSTER_SLEEP_0>; 236 next-level-cache = <&L2_300>; 237 operating-points-v2 = <&cpu0_opp_table>; 238 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 239 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 240 qcom,freq-domain = <&cpufreq_hw 0>; 241 #cooling-cells = <2>; 242 L2_300: l2-cache { 243 compatible = "cache"; 244 next-level-cache = <&L3_0>; 245 }; 246 }; 247 248 CPU4: cpu@400 { 249 device_type = "cpu"; 250 compatible = "arm,kryo"; 251 reg = <0x0 0x400>; 252 enable-method = "psci"; 253 cpu-idle-states = <&BIG_CPU_SLEEP_0 254 &BIG_CPU_SLEEP_1 255 &CLUSTER_SLEEP_0>; 256 next-level-cache = <&L2_400>; 257 operating-points-v2 = <&cpu4_opp_table>; 258 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 259 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 260 qcom,freq-domain = <&cpufreq_hw 1>; 261 #cooling-cells = <2>; 262 L2_400: l2-cache { 263 compatible = "cache"; 264 next-level-cache = <&L3_0>; 265 }; 266 }; 267 268 CPU5: cpu@500 { 269 device_type = "cpu"; 270 compatible = "arm,kryo"; 271 reg = <0x0 0x500>; 272 enable-method = "psci"; 273 cpu-idle-states = <&BIG_CPU_SLEEP_0 274 &BIG_CPU_SLEEP_1 275 &CLUSTER_SLEEP_0>; 276 next-level-cache = <&L2_500>; 277 operating-points-v2 = <&cpu4_opp_table>; 278 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 279 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 280 qcom,freq-domain = <&cpufreq_hw 1>; 281 #cooling-cells = <2>; 282 L2_500: l2-cache { 283 compatible = "cache"; 284 next-level-cache = <&L3_0>; 285 }; 286 }; 287 288 CPU6: cpu@600 { 289 device_type = "cpu"; 290 compatible = "arm,kryo"; 291 reg = <0x0 0x600>; 292 enable-method = "psci"; 293 cpu-idle-states = <&BIG_CPU_SLEEP_0 294 &BIG_CPU_SLEEP_1 295 &CLUSTER_SLEEP_0>; 296 next-level-cache = <&L2_600>; 297 operating-points-v2 = <&cpu4_opp_table>; 298 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 299 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 300 qcom,freq-domain = <&cpufreq_hw 1>; 301 #cooling-cells = <2>; 302 L2_600: l2-cache { 303 compatible = "cache"; 304 next-level-cache = <&L3_0>; 305 }; 306 }; 307 308 CPU7: cpu@700 { 309 device_type = "cpu"; 310 compatible = "arm,kryo"; 311 reg = <0x0 0x700>; 312 enable-method = "psci"; 313 cpu-idle-states = <&BIG_CPU_SLEEP_0 314 &BIG_CPU_SLEEP_1 315 &CLUSTER_SLEEP_0>; 316 next-level-cache = <&L2_700>; 317 operating-points-v2 = <&cpu7_opp_table>; 318 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 319 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 320 qcom,freq-domain = <&cpufreq_hw 2>; 321 #cooling-cells = <2>; 322 L2_700: l2-cache { 323 compatible = "cache"; 324 next-level-cache = <&L3_0>; 325 }; 326 }; 327 328 cpu-map { 329 cluster0 { 330 core0 { 331 cpu = <&CPU0>; 332 }; 333 334 core1 { 335 cpu = <&CPU1>; 336 }; 337 338 core2 { 339 cpu = <&CPU2>; 340 }; 341 342 core3 { 343 cpu = <&CPU3>; 344 }; 345 346 core4 { 347 cpu = <&CPU4>; 348 }; 349 350 core5 { 351 cpu = <&CPU5>; 352 }; 353 354 core6 { 355 cpu = <&CPU6>; 356 }; 357 358 core7 { 359 cpu = <&CPU7>; 360 }; 361 }; 362 }; 363 364 idle-states { 365 entry-method = "psci"; 366 367 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 368 compatible = "arm,idle-state"; 369 idle-state-name = "little-power-down"; 370 arm,psci-suspend-param = <0x40000003>; 371 entry-latency-us = <549>; 372 exit-latency-us = <901>; 373 min-residency-us = <1774>; 374 local-timer-stop; 375 }; 376 377 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 378 compatible = "arm,idle-state"; 379 idle-state-name = "little-rail-power-down"; 380 arm,psci-suspend-param = <0x40000004>; 381 entry-latency-us = <702>; 382 exit-latency-us = <915>; 383 min-residency-us = <4001>; 384 local-timer-stop; 385 }; 386 387 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 388 compatible = "arm,idle-state"; 389 idle-state-name = "big-power-down"; 390 arm,psci-suspend-param = <0x40000003>; 391 entry-latency-us = <523>; 392 exit-latency-us = <1244>; 393 min-residency-us = <2207>; 394 local-timer-stop; 395 }; 396 397 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 398 compatible = "arm,idle-state"; 399 idle-state-name = "big-rail-power-down"; 400 arm,psci-suspend-param = <0x40000004>; 401 entry-latency-us = <526>; 402 exit-latency-us = <1854>; 403 min-residency-us = <5555>; 404 local-timer-stop; 405 }; 406 407 CLUSTER_SLEEP_0: cluster-sleep-0 { 408 compatible = "arm,idle-state"; 409 idle-state-name = "cluster-power-down"; 410 arm,psci-suspend-param = <0x40003444>; 411 entry-latency-us = <3263>; 412 exit-latency-us = <6562>; 413 min-residency-us = <9926>; 414 local-timer-stop; 415 }; 416 }; 417 }; 418 419 cpu0_opp_table: cpu0-opp-table { 420 compatible = "operating-points-v2"; 421 opp-shared; 422 423 cpu0_opp_300mhz: opp-300000000 { 424 opp-hz = /bits/ 64 <300000000>; 425 opp-peak-kBps = <800000 9600000>; 426 }; 427 428 cpu0_opp_691mhz: opp-691200000 { 429 opp-hz = /bits/ 64 <691200000>; 430 opp-peak-kBps = <800000 17817600>; 431 }; 432 433 cpu0_opp_806mhz: opp-806400000 { 434 opp-hz = /bits/ 64 <806400000>; 435 opp-peak-kBps = <800000 20889600>; 436 }; 437 438 cpu0_opp_941mhz: opp-940800000 { 439 opp-hz = /bits/ 64 <940800000>; 440 opp-peak-kBps = <1804000 24576000>; 441 }; 442 443 cpu0_opp_1152mhz: opp-1152000000 { 444 opp-hz = /bits/ 64 <1152000000>; 445 opp-peak-kBps = <2188000 27033600>; 446 }; 447 448 cpu0_opp_1325mhz: opp-1324800000 { 449 opp-hz = /bits/ 64 <1324800000>; 450 opp-peak-kBps = <2188000 33792000>; 451 }; 452 453 cpu0_opp_1517mhz: opp-1516800000 { 454 opp-hz = /bits/ 64 <1516800000>; 455 opp-peak-kBps = <3072000 38092800>; 456 }; 457 458 cpu0_opp_1651mhz: opp-1651200000 { 459 opp-hz = /bits/ 64 <1651200000>; 460 opp-peak-kBps = <3072000 41779200>; 461 }; 462 463 cpu0_opp_1805mhz: opp-1804800000 { 464 opp-hz = /bits/ 64 <1804800000>; 465 opp-peak-kBps = <4068000 48537600>; 466 }; 467 468 cpu0_opp_1958mhz: opp-1958400000 { 469 opp-hz = /bits/ 64 <1958400000>; 470 opp-peak-kBps = <4068000 48537600>; 471 }; 472 473 cpu0_opp_2016mhz: opp-2016000000 { 474 opp-hz = /bits/ 64 <2016000000>; 475 opp-peak-kBps = <6220000 48537600>; 476 }; 477 }; 478 479 cpu4_opp_table: cpu4-opp-table { 480 compatible = "operating-points-v2"; 481 opp-shared; 482 483 cpu4_opp_691mhz: opp-691200000 { 484 opp-hz = /bits/ 64 <691200000>; 485 opp-peak-kBps = <1804000 9600000>; 486 }; 487 488 cpu4_opp_941mhz: opp-940800000 { 489 opp-hz = /bits/ 64 <940800000>; 490 opp-peak-kBps = <2188000 17817600>; 491 }; 492 493 cpu4_opp_1229mhz: opp-1228800000 { 494 opp-hz = /bits/ 64 <1228800000>; 495 opp-peak-kBps = <4068000 24576000>; 496 }; 497 498 cpu4_opp_1344mhz: opp-1344000000 { 499 opp-hz = /bits/ 64 <1344000000>; 500 opp-peak-kBps = <4068000 24576000>; 501 }; 502 503 cpu4_opp_1517mhz: opp-1516800000 { 504 opp-hz = /bits/ 64 <1516800000>; 505 opp-peak-kBps = <4068000 24576000>; 506 }; 507 508 cpu4_opp_1651mhz: opp-1651200000 { 509 opp-hz = /bits/ 64 <1651200000>; 510 opp-peak-kBps = <6220000 38092800>; 511 }; 512 513 cpu4_opp_1901mhz: opp-1900800000 { 514 opp-hz = /bits/ 64 <1900800000>; 515 opp-peak-kBps = <6220000 44851200>; 516 }; 517 518 cpu4_opp_2054mhz: opp-2054400000 { 519 opp-hz = /bits/ 64 <2054400000>; 520 opp-peak-kBps = <6220000 44851200>; 521 }; 522 523 cpu4_opp_2112mhz: opp-2112000000 { 524 opp-hz = /bits/ 64 <2112000000>; 525 opp-peak-kBps = <6220000 44851200>; 526 }; 527 528 cpu4_opp_2131mhz: opp-2131200000 { 529 opp-hz = /bits/ 64 <2131200000>; 530 opp-peak-kBps = <6220000 44851200>; 531 }; 532 533 cpu4_opp_2208mhz: opp-2208000000 { 534 opp-hz = /bits/ 64 <2208000000>; 535 opp-peak-kBps = <6220000 44851200>; 536 }; 537 538 cpu4_opp_2400mhz: opp-2400000000 { 539 opp-hz = /bits/ 64 <2400000000>; 540 opp-peak-kBps = <8532000 48537600>; 541 }; 542 543 cpu4_opp_2611mhz: opp-2611200000 { 544 opp-hz = /bits/ 64 <2611200000>; 545 opp-peak-kBps = <8532000 48537600>; 546 }; 547 }; 548 549 cpu7_opp_table: cpu7-opp-table { 550 compatible = "operating-points-v2"; 551 opp-shared; 552 553 cpu7_opp_806mhz: opp-806400000 { 554 opp-hz = /bits/ 64 <806400000>; 555 opp-peak-kBps = <1804000 9600000>; 556 }; 557 558 cpu7_opp_1056mhz: opp-1056000000 { 559 opp-hz = /bits/ 64 <1056000000>; 560 opp-peak-kBps = <2188000 17817600>; 561 }; 562 563 cpu7_opp_1325mhz: opp-1324800000 { 564 opp-hz = /bits/ 64 <1324800000>; 565 opp-peak-kBps = <4068000 24576000>; 566 }; 567 568 cpu7_opp_1517mhz: opp-1516800000 { 569 opp-hz = /bits/ 64 <1516800000>; 570 opp-peak-kBps = <4068000 24576000>; 571 }; 572 573 cpu7_opp_1766mhz: opp-1766400000 { 574 opp-hz = /bits/ 64 <1766400000>; 575 opp-peak-kBps = <6220000 38092800>; 576 }; 577 578 cpu7_opp_1862mhz: opp-1862400000 { 579 opp-hz = /bits/ 64 <1862400000>; 580 opp-peak-kBps = <6220000 38092800>; 581 }; 582 583 cpu7_opp_2035mhz: opp-2035200000 { 584 opp-hz = /bits/ 64 <2035200000>; 585 opp-peak-kBps = <6220000 38092800>; 586 }; 587 588 cpu7_opp_2112mhz: opp-2112000000 { 589 opp-hz = /bits/ 64 <2112000000>; 590 opp-peak-kBps = <6220000 44851200>; 591 }; 592 593 cpu7_opp_2208mhz: opp-2208000000 { 594 opp-hz = /bits/ 64 <2208000000>; 595 opp-peak-kBps = <6220000 44851200>; 596 }; 597 598 cpu7_opp_2381mhz: opp-2380800000 { 599 opp-hz = /bits/ 64 <2380800000>; 600 opp-peak-kBps = <6832000 44851200>; 601 }; 602 603 cpu7_opp_2400mhz: opp-2400000000 { 604 opp-hz = /bits/ 64 <2400000000>; 605 opp-peak-kBps = <8532000 48537600>; 606 }; 607 608 cpu7_opp_2515mhz: opp-2515200000 { 609 opp-hz = /bits/ 64 <2515200000>; 610 opp-peak-kBps = <8532000 48537600>; 611 }; 612 613 cpu7_opp_2707mhz: opp-2707200000 { 614 opp-hz = /bits/ 64 <2707200000>; 615 opp-peak-kBps = <8532000 48537600>; 616 }; 617 618 cpu7_opp_3014mhz: opp-3014400000 { 619 opp-hz = /bits/ 64 <3014400000>; 620 opp-peak-kBps = <8532000 48537600>; 621 }; 622 }; 623 624 memory@80000000 { 625 device_type = "memory"; 626 /* We expect the bootloader to fill in the size */ 627 reg = <0 0x80000000 0 0>; 628 }; 629 630 firmware { 631 scm { 632 compatible = "qcom,scm-sc7280", "qcom,scm"; 633 }; 634 }; 635 636 clk_virt: interconnect { 637 compatible = "qcom,sc7280-clk-virt"; 638 #interconnect-cells = <2>; 639 qcom,bcm-voters = <&apps_bcm_voter>; 640 }; 641 642 smem { 643 compatible = "qcom,smem"; 644 memory-region = <&smem_mem>; 645 hwlocks = <&tcsr_mutex 3>; 646 }; 647 648 smp2p-adsp { 649 compatible = "qcom,smp2p"; 650 qcom,smem = <443>, <429>; 651 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 652 IPCC_MPROC_SIGNAL_SMP2P 653 IRQ_TYPE_EDGE_RISING>; 654 mboxes = <&ipcc IPCC_CLIENT_LPASS 655 IPCC_MPROC_SIGNAL_SMP2P>; 656 657 qcom,local-pid = <0>; 658 qcom,remote-pid = <2>; 659 660 adsp_smp2p_out: master-kernel { 661 qcom,entry-name = "master-kernel"; 662 #qcom,smem-state-cells = <1>; 663 }; 664 665 adsp_smp2p_in: slave-kernel { 666 qcom,entry-name = "slave-kernel"; 667 interrupt-controller; 668 #interrupt-cells = <2>; 669 }; 670 }; 671 672 smp2p-cdsp { 673 compatible = "qcom,smp2p"; 674 qcom,smem = <94>, <432>; 675 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 676 IPCC_MPROC_SIGNAL_SMP2P 677 IRQ_TYPE_EDGE_RISING>; 678 mboxes = <&ipcc IPCC_CLIENT_CDSP 679 IPCC_MPROC_SIGNAL_SMP2P>; 680 681 qcom,local-pid = <0>; 682 qcom,remote-pid = <5>; 683 684 cdsp_smp2p_out: master-kernel { 685 qcom,entry-name = "master-kernel"; 686 #qcom,smem-state-cells = <1>; 687 }; 688 689 cdsp_smp2p_in: slave-kernel { 690 qcom,entry-name = "slave-kernel"; 691 interrupt-controller; 692 #interrupt-cells = <2>; 693 }; 694 }; 695 696 smp2p-mpss { 697 compatible = "qcom,smp2p"; 698 qcom,smem = <435>, <428>; 699 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 700 IPCC_MPROC_SIGNAL_SMP2P 701 IRQ_TYPE_EDGE_RISING>; 702 mboxes = <&ipcc IPCC_CLIENT_MPSS 703 IPCC_MPROC_SIGNAL_SMP2P>; 704 705 qcom,local-pid = <0>; 706 qcom,remote-pid = <1>; 707 708 modem_smp2p_out: master-kernel { 709 qcom,entry-name = "master-kernel"; 710 #qcom,smem-state-cells = <1>; 711 }; 712 713 modem_smp2p_in: slave-kernel { 714 qcom,entry-name = "slave-kernel"; 715 interrupt-controller; 716 #interrupt-cells = <2>; 717 }; 718 719 ipa_smp2p_out: ipa-ap-to-modem { 720 qcom,entry-name = "ipa"; 721 #qcom,smem-state-cells = <1>; 722 }; 723 724 ipa_smp2p_in: ipa-modem-to-ap { 725 qcom,entry-name = "ipa"; 726 interrupt-controller; 727 #interrupt-cells = <2>; 728 }; 729 }; 730 731 smp2p-wpss { 732 compatible = "qcom,smp2p"; 733 qcom,smem = <617>, <616>; 734 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 735 IPCC_MPROC_SIGNAL_SMP2P 736 IRQ_TYPE_EDGE_RISING>; 737 mboxes = <&ipcc IPCC_CLIENT_WPSS 738 IPCC_MPROC_SIGNAL_SMP2P>; 739 740 qcom,local-pid = <0>; 741 qcom,remote-pid = <13>; 742 743 wpss_smp2p_out: master-kernel { 744 qcom,entry-name = "master-kernel"; 745 #qcom,smem-state-cells = <1>; 746 }; 747 748 wpss_smp2p_in: slave-kernel { 749 qcom,entry-name = "slave-kernel"; 750 interrupt-controller; 751 #interrupt-cells = <2>; 752 }; 753 }; 754 755 pmu { 756 compatible = "arm,armv8-pmuv3"; 757 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 758 }; 759 760 psci { 761 compatible = "arm,psci-1.0"; 762 method = "smc"; 763 }; 764 765 qspi_opp_table: qspi-opp-table { 766 compatible = "operating-points-v2"; 767 768 opp-75000000 { 769 opp-hz = /bits/ 64 <75000000>; 770 required-opps = <&rpmhpd_opp_low_svs>; 771 }; 772 773 opp-150000000 { 774 opp-hz = /bits/ 64 <150000000>; 775 required-opps = <&rpmhpd_opp_svs>; 776 }; 777 778 opp-200000000 { 779 opp-hz = /bits/ 64 <200000000>; 780 required-opps = <&rpmhpd_opp_svs_l1>; 781 }; 782 783 opp-300000000 { 784 opp-hz = /bits/ 64 <300000000>; 785 required-opps = <&rpmhpd_opp_nom>; 786 }; 787 }; 788 789 qup_opp_table: qup-opp-table { 790 compatible = "operating-points-v2"; 791 792 opp-75000000 { 793 opp-hz = /bits/ 64 <75000000>; 794 required-opps = <&rpmhpd_opp_low_svs>; 795 }; 796 797 opp-100000000 { 798 opp-hz = /bits/ 64 <100000000>; 799 required-opps = <&rpmhpd_opp_svs>; 800 }; 801 802 opp-128000000 { 803 opp-hz = /bits/ 64 <128000000>; 804 required-opps = <&rpmhpd_opp_nom>; 805 }; 806 }; 807 808 soc: soc@0 { 809 #address-cells = <2>; 810 #size-cells = <2>; 811 ranges = <0 0 0 0 0x10 0>; 812 dma-ranges = <0 0 0 0 0x10 0>; 813 compatible = "simple-bus"; 814 815 gcc: clock-controller@100000 { 816 compatible = "qcom,gcc-sc7280"; 817 reg = <0 0x00100000 0 0x1f0000>; 818 clocks = <&rpmhcc RPMH_CXO_CLK>, 819 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 820 <0>, <&pcie1_lane 0>, 821 <0>, <0>, <0>, <0>; 822 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 823 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 824 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 825 "ufs_phy_tx_symbol_0_clk", 826 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 827 #clock-cells = <1>; 828 #reset-cells = <1>; 829 #power-domain-cells = <1>; 830 }; 831 832 ipcc: mailbox@408000 { 833 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 834 reg = <0 0x00408000 0 0x1000>; 835 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 836 interrupt-controller; 837 #interrupt-cells = <3>; 838 #mbox-cells = <2>; 839 }; 840 841 qfprom: efuse@784000 { 842 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 843 reg = <0 0x00784000 0 0xa20>, 844 <0 0x00780000 0 0xa20>, 845 <0 0x00782000 0 0x120>, 846 <0 0x00786000 0 0x1fff>; 847 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 848 clock-names = "core"; 849 power-domains = <&rpmhpd SC7280_MX>; 850 #address-cells = <1>; 851 #size-cells = <1>; 852 853 gpu_speed_bin: gpu_speed_bin@1e9 { 854 reg = <0x1e9 0x2>; 855 bits = <5 8>; 856 }; 857 }; 858 859 sdhc_1: sdhci@7c4000 { 860 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 861 pinctrl-names = "default", "sleep"; 862 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 863 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 864 status = "disabled"; 865 866 reg = <0 0x007c4000 0 0x1000>, 867 <0 0x007c5000 0 0x1000>; 868 reg-names = "hc", "cqhci"; 869 870 iommus = <&apps_smmu 0xc0 0x0>; 871 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 873 interrupt-names = "hc_irq", "pwr_irq"; 874 875 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 876 <&gcc GCC_SDCC1_AHB_CLK>, 877 <&rpmhcc RPMH_CXO_CLK>; 878 clock-names = "core", "iface", "xo"; 879 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 880 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 881 interconnect-names = "sdhc-ddr","cpu-sdhc"; 882 power-domains = <&rpmhpd SC7280_CX>; 883 operating-points-v2 = <&sdhc1_opp_table>; 884 885 bus-width = <8>; 886 supports-cqe; 887 888 qcom,dll-config = <0x0007642c>; 889 qcom,ddr-config = <0x80040868>; 890 891 mmc-ddr-1_8v; 892 mmc-hs200-1_8v; 893 mmc-hs400-1_8v; 894 mmc-hs400-enhanced-strobe; 895 896 resets = <&gcc GCC_SDCC1_BCR>; 897 898 sdhc1_opp_table: opp-table { 899 compatible = "operating-points-v2"; 900 901 opp-100000000 { 902 opp-hz = /bits/ 64 <100000000>; 903 required-opps = <&rpmhpd_opp_low_svs>; 904 opp-peak-kBps = <1800000 400000>; 905 opp-avg-kBps = <100000 0>; 906 }; 907 908 opp-384000000 { 909 opp-hz = /bits/ 64 <384000000>; 910 required-opps = <&rpmhpd_opp_nom>; 911 opp-peak-kBps = <5400000 1600000>; 912 opp-avg-kBps = <390000 0>; 913 }; 914 }; 915 916 }; 917 918 qupv3_id_0: geniqup@9c0000 { 919 compatible = "qcom,geni-se-qup"; 920 reg = <0 0x009c0000 0 0x2000>; 921 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 922 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 923 clock-names = "m-ahb", "s-ahb"; 924 #address-cells = <2>; 925 #size-cells = <2>; 926 ranges; 927 iommus = <&apps_smmu 0x123 0x0>; 928 status = "disabled"; 929 930 i2c0: i2c@980000 { 931 compatible = "qcom,geni-i2c"; 932 reg = <0 0x00980000 0 0x4000>; 933 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 934 clock-names = "se"; 935 pinctrl-names = "default"; 936 pinctrl-0 = <&qup_i2c0_data_clk>; 937 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 938 #address-cells = <1>; 939 #size-cells = <0>; 940 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 941 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 942 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 943 interconnect-names = "qup-core", "qup-config", 944 "qup-memory"; 945 status = "disabled"; 946 }; 947 948 spi0: spi@980000 { 949 compatible = "qcom,geni-spi"; 950 reg = <0 0x00980000 0 0x4000>; 951 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 952 clock-names = "se"; 953 pinctrl-names = "default"; 954 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 955 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 956 #address-cells = <1>; 957 #size-cells = <0>; 958 power-domains = <&rpmhpd SC7280_CX>; 959 operating-points-v2 = <&qup_opp_table>; 960 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 961 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 962 interconnect-names = "qup-core", "qup-config"; 963 status = "disabled"; 964 }; 965 966 uart0: serial@980000 { 967 compatible = "qcom,geni-uart"; 968 reg = <0 0x00980000 0 0x4000>; 969 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 970 clock-names = "se"; 971 pinctrl-names = "default"; 972 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 973 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 974 power-domains = <&rpmhpd SC7280_CX>; 975 operating-points-v2 = <&qup_opp_table>; 976 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 977 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 978 interconnect-names = "qup-core", "qup-config"; 979 status = "disabled"; 980 }; 981 982 i2c1: i2c@984000 { 983 compatible = "qcom,geni-i2c"; 984 reg = <0 0x00984000 0 0x4000>; 985 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 986 clock-names = "se"; 987 pinctrl-names = "default"; 988 pinctrl-0 = <&qup_i2c1_data_clk>; 989 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 990 #address-cells = <1>; 991 #size-cells = <0>; 992 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 993 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 994 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 995 interconnect-names = "qup-core", "qup-config", 996 "qup-memory"; 997 status = "disabled"; 998 }; 999 1000 spi1: spi@984000 { 1001 compatible = "qcom,geni-spi"; 1002 reg = <0 0x00984000 0 0x4000>; 1003 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1004 clock-names = "se"; 1005 pinctrl-names = "default"; 1006 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1007 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 power-domains = <&rpmhpd SC7280_CX>; 1011 operating-points-v2 = <&qup_opp_table>; 1012 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1013 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1014 interconnect-names = "qup-core", "qup-config"; 1015 status = "disabled"; 1016 }; 1017 1018 uart1: serial@984000 { 1019 compatible = "qcom,geni-uart"; 1020 reg = <0 0x00984000 0 0x4000>; 1021 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1022 clock-names = "se"; 1023 pinctrl-names = "default"; 1024 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1025 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1026 power-domains = <&rpmhpd SC7280_CX>; 1027 operating-points-v2 = <&qup_opp_table>; 1028 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1029 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1030 interconnect-names = "qup-core", "qup-config"; 1031 status = "disabled"; 1032 }; 1033 1034 i2c2: i2c@988000 { 1035 compatible = "qcom,geni-i2c"; 1036 reg = <0 0x00988000 0 0x4000>; 1037 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1038 clock-names = "se"; 1039 pinctrl-names = "default"; 1040 pinctrl-0 = <&qup_i2c2_data_clk>; 1041 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1045 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1046 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1047 interconnect-names = "qup-core", "qup-config", 1048 "qup-memory"; 1049 status = "disabled"; 1050 }; 1051 1052 spi2: spi@988000 { 1053 compatible = "qcom,geni-spi"; 1054 reg = <0 0x00988000 0 0x4000>; 1055 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1056 clock-names = "se"; 1057 pinctrl-names = "default"; 1058 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1059 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1060 #address-cells = <1>; 1061 #size-cells = <0>; 1062 power-domains = <&rpmhpd SC7280_CX>; 1063 operating-points-v2 = <&qup_opp_table>; 1064 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1065 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1066 interconnect-names = "qup-core", "qup-config"; 1067 status = "disabled"; 1068 }; 1069 1070 uart2: serial@988000 { 1071 compatible = "qcom,geni-uart"; 1072 reg = <0 0x00988000 0 0x4000>; 1073 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1074 clock-names = "se"; 1075 pinctrl-names = "default"; 1076 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1077 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1078 power-domains = <&rpmhpd SC7280_CX>; 1079 operating-points-v2 = <&qup_opp_table>; 1080 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1081 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1082 interconnect-names = "qup-core", "qup-config"; 1083 status = "disabled"; 1084 }; 1085 1086 i2c3: i2c@98c000 { 1087 compatible = "qcom,geni-i2c"; 1088 reg = <0 0x0098c000 0 0x4000>; 1089 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1090 clock-names = "se"; 1091 pinctrl-names = "default"; 1092 pinctrl-0 = <&qup_i2c3_data_clk>; 1093 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1097 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1098 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1099 interconnect-names = "qup-core", "qup-config", 1100 "qup-memory"; 1101 status = "disabled"; 1102 }; 1103 1104 spi3: spi@98c000 { 1105 compatible = "qcom,geni-spi"; 1106 reg = <0 0x0098c000 0 0x4000>; 1107 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1108 clock-names = "se"; 1109 pinctrl-names = "default"; 1110 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1111 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1112 #address-cells = <1>; 1113 #size-cells = <0>; 1114 power-domains = <&rpmhpd SC7280_CX>; 1115 operating-points-v2 = <&qup_opp_table>; 1116 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1117 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1118 interconnect-names = "qup-core", "qup-config"; 1119 status = "disabled"; 1120 }; 1121 1122 uart3: serial@98c000 { 1123 compatible = "qcom,geni-uart"; 1124 reg = <0 0x0098c000 0 0x4000>; 1125 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1126 clock-names = "se"; 1127 pinctrl-names = "default"; 1128 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1129 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1130 power-domains = <&rpmhpd SC7280_CX>; 1131 operating-points-v2 = <&qup_opp_table>; 1132 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1133 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1134 interconnect-names = "qup-core", "qup-config"; 1135 status = "disabled"; 1136 }; 1137 1138 i2c4: i2c@990000 { 1139 compatible = "qcom,geni-i2c"; 1140 reg = <0 0x00990000 0 0x4000>; 1141 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1142 clock-names = "se"; 1143 pinctrl-names = "default"; 1144 pinctrl-0 = <&qup_i2c4_data_clk>; 1145 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1149 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1150 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1151 interconnect-names = "qup-core", "qup-config", 1152 "qup-memory"; 1153 status = "disabled"; 1154 }; 1155 1156 spi4: spi@990000 { 1157 compatible = "qcom,geni-spi"; 1158 reg = <0 0x00990000 0 0x4000>; 1159 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1160 clock-names = "se"; 1161 pinctrl-names = "default"; 1162 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1163 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1164 #address-cells = <1>; 1165 #size-cells = <0>; 1166 power-domains = <&rpmhpd SC7280_CX>; 1167 operating-points-v2 = <&qup_opp_table>; 1168 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1169 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1170 interconnect-names = "qup-core", "qup-config"; 1171 status = "disabled"; 1172 }; 1173 1174 uart4: serial@990000 { 1175 compatible = "qcom,geni-uart"; 1176 reg = <0 0x00990000 0 0x4000>; 1177 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1178 clock-names = "se"; 1179 pinctrl-names = "default"; 1180 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1181 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1182 power-domains = <&rpmhpd SC7280_CX>; 1183 operating-points-v2 = <&qup_opp_table>; 1184 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1185 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1186 interconnect-names = "qup-core", "qup-config"; 1187 status = "disabled"; 1188 }; 1189 1190 i2c5: i2c@994000 { 1191 compatible = "qcom,geni-i2c"; 1192 reg = <0 0x00994000 0 0x4000>; 1193 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1194 clock-names = "se"; 1195 pinctrl-names = "default"; 1196 pinctrl-0 = <&qup_i2c5_data_clk>; 1197 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1201 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1202 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1203 interconnect-names = "qup-core", "qup-config", 1204 "qup-memory"; 1205 status = "disabled"; 1206 }; 1207 1208 spi5: spi@994000 { 1209 compatible = "qcom,geni-spi"; 1210 reg = <0 0x00994000 0 0x4000>; 1211 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1212 clock-names = "se"; 1213 pinctrl-names = "default"; 1214 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1215 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1216 #address-cells = <1>; 1217 #size-cells = <0>; 1218 power-domains = <&rpmhpd SC7280_CX>; 1219 operating-points-v2 = <&qup_opp_table>; 1220 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1221 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1222 interconnect-names = "qup-core", "qup-config"; 1223 status = "disabled"; 1224 }; 1225 1226 uart5: serial@994000 { 1227 compatible = "qcom,geni-uart"; 1228 reg = <0 0x00994000 0 0x4000>; 1229 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1230 clock-names = "se"; 1231 pinctrl-names = "default"; 1232 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1233 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1234 power-domains = <&rpmhpd SC7280_CX>; 1235 operating-points-v2 = <&qup_opp_table>; 1236 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1237 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1238 interconnect-names = "qup-core", "qup-config"; 1239 status = "disabled"; 1240 }; 1241 1242 i2c6: i2c@998000 { 1243 compatible = "qcom,geni-i2c"; 1244 reg = <0 0x00998000 0 0x4000>; 1245 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1246 clock-names = "se"; 1247 pinctrl-names = "default"; 1248 pinctrl-0 = <&qup_i2c6_data_clk>; 1249 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1253 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1254 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1255 interconnect-names = "qup-core", "qup-config", 1256 "qup-memory"; 1257 status = "disabled"; 1258 }; 1259 1260 spi6: spi@998000 { 1261 compatible = "qcom,geni-spi"; 1262 reg = <0 0x00998000 0 0x4000>; 1263 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1264 clock-names = "se"; 1265 pinctrl-names = "default"; 1266 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1267 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1268 #address-cells = <1>; 1269 #size-cells = <0>; 1270 power-domains = <&rpmhpd SC7280_CX>; 1271 operating-points-v2 = <&qup_opp_table>; 1272 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1273 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1274 interconnect-names = "qup-core", "qup-config"; 1275 status = "disabled"; 1276 }; 1277 1278 uart6: serial@998000 { 1279 compatible = "qcom,geni-uart"; 1280 reg = <0 0x00998000 0 0x4000>; 1281 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1282 clock-names = "se"; 1283 pinctrl-names = "default"; 1284 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1285 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1286 power-domains = <&rpmhpd SC7280_CX>; 1287 operating-points-v2 = <&qup_opp_table>; 1288 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1289 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1290 interconnect-names = "qup-core", "qup-config"; 1291 status = "disabled"; 1292 }; 1293 1294 i2c7: i2c@99c000 { 1295 compatible = "qcom,geni-i2c"; 1296 reg = <0 0x0099c000 0 0x4000>; 1297 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1298 clock-names = "se"; 1299 pinctrl-names = "default"; 1300 pinctrl-0 = <&qup_i2c7_data_clk>; 1301 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1302 #address-cells = <1>; 1303 #size-cells = <0>; 1304 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1305 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1306 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1307 interconnect-names = "qup-core", "qup-config", 1308 "qup-memory"; 1309 status = "disabled"; 1310 }; 1311 1312 spi7: spi@99c000 { 1313 compatible = "qcom,geni-spi"; 1314 reg = <0 0x0099c000 0 0x4000>; 1315 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1316 clock-names = "se"; 1317 pinctrl-names = "default"; 1318 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1319 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1320 #address-cells = <1>; 1321 #size-cells = <0>; 1322 power-domains = <&rpmhpd SC7280_CX>; 1323 operating-points-v2 = <&qup_opp_table>; 1324 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1325 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1326 interconnect-names = "qup-core", "qup-config"; 1327 status = "disabled"; 1328 }; 1329 1330 uart7: serial@99c000 { 1331 compatible = "qcom,geni-uart"; 1332 reg = <0 0x0099c000 0 0x4000>; 1333 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1334 clock-names = "se"; 1335 pinctrl-names = "default"; 1336 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1337 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1338 power-domains = <&rpmhpd SC7280_CX>; 1339 operating-points-v2 = <&qup_opp_table>; 1340 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1341 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1342 interconnect-names = "qup-core", "qup-config"; 1343 status = "disabled"; 1344 }; 1345 }; 1346 1347 qupv3_id_1: geniqup@ac0000 { 1348 compatible = "qcom,geni-se-qup"; 1349 reg = <0 0x00ac0000 0 0x2000>; 1350 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1351 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1352 clock-names = "m-ahb", "s-ahb"; 1353 #address-cells = <2>; 1354 #size-cells = <2>; 1355 ranges; 1356 iommus = <&apps_smmu 0x43 0x0>; 1357 status = "disabled"; 1358 1359 i2c8: i2c@a80000 { 1360 compatible = "qcom,geni-i2c"; 1361 reg = <0 0x00a80000 0 0x4000>; 1362 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1363 clock-names = "se"; 1364 pinctrl-names = "default"; 1365 pinctrl-0 = <&qup_i2c8_data_clk>; 1366 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1367 #address-cells = <1>; 1368 #size-cells = <0>; 1369 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1370 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1371 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1372 interconnect-names = "qup-core", "qup-config", 1373 "qup-memory"; 1374 status = "disabled"; 1375 }; 1376 1377 spi8: spi@a80000 { 1378 compatible = "qcom,geni-spi"; 1379 reg = <0 0x00a80000 0 0x4000>; 1380 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1381 clock-names = "se"; 1382 pinctrl-names = "default"; 1383 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1384 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1385 #address-cells = <1>; 1386 #size-cells = <0>; 1387 power-domains = <&rpmhpd SC7280_CX>; 1388 operating-points-v2 = <&qup_opp_table>; 1389 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1390 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1391 interconnect-names = "qup-core", "qup-config"; 1392 status = "disabled"; 1393 }; 1394 1395 uart8: serial@a80000 { 1396 compatible = "qcom,geni-uart"; 1397 reg = <0 0x00a80000 0 0x4000>; 1398 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1399 clock-names = "se"; 1400 pinctrl-names = "default"; 1401 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1402 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1403 power-domains = <&rpmhpd SC7280_CX>; 1404 operating-points-v2 = <&qup_opp_table>; 1405 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1406 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1407 interconnect-names = "qup-core", "qup-config"; 1408 status = "disabled"; 1409 }; 1410 1411 i2c9: i2c@a84000 { 1412 compatible = "qcom,geni-i2c"; 1413 reg = <0 0x00a84000 0 0x4000>; 1414 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1415 clock-names = "se"; 1416 pinctrl-names = "default"; 1417 pinctrl-0 = <&qup_i2c9_data_clk>; 1418 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1419 #address-cells = <1>; 1420 #size-cells = <0>; 1421 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1422 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1423 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1424 interconnect-names = "qup-core", "qup-config", 1425 "qup-memory"; 1426 status = "disabled"; 1427 }; 1428 1429 spi9: spi@a84000 { 1430 compatible = "qcom,geni-spi"; 1431 reg = <0 0x00a84000 0 0x4000>; 1432 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1433 clock-names = "se"; 1434 pinctrl-names = "default"; 1435 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1436 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1437 #address-cells = <1>; 1438 #size-cells = <0>; 1439 power-domains = <&rpmhpd SC7280_CX>; 1440 operating-points-v2 = <&qup_opp_table>; 1441 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1442 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1443 interconnect-names = "qup-core", "qup-config"; 1444 status = "disabled"; 1445 }; 1446 1447 uart9: serial@a84000 { 1448 compatible = "qcom,geni-uart"; 1449 reg = <0 0x00a84000 0 0x4000>; 1450 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1451 clock-names = "se"; 1452 pinctrl-names = "default"; 1453 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1454 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1455 power-domains = <&rpmhpd SC7280_CX>; 1456 operating-points-v2 = <&qup_opp_table>; 1457 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1458 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1459 interconnect-names = "qup-core", "qup-config"; 1460 status = "disabled"; 1461 }; 1462 1463 i2c10: i2c@a88000 { 1464 compatible = "qcom,geni-i2c"; 1465 reg = <0 0x00a88000 0 0x4000>; 1466 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1467 clock-names = "se"; 1468 pinctrl-names = "default"; 1469 pinctrl-0 = <&qup_i2c10_data_clk>; 1470 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1471 #address-cells = <1>; 1472 #size-cells = <0>; 1473 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1474 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1475 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1476 interconnect-names = "qup-core", "qup-config", 1477 "qup-memory"; 1478 status = "disabled"; 1479 }; 1480 1481 spi10: spi@a88000 { 1482 compatible = "qcom,geni-spi"; 1483 reg = <0 0x00a88000 0 0x4000>; 1484 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1485 clock-names = "se"; 1486 pinctrl-names = "default"; 1487 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1488 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1489 #address-cells = <1>; 1490 #size-cells = <0>; 1491 power-domains = <&rpmhpd SC7280_CX>; 1492 operating-points-v2 = <&qup_opp_table>; 1493 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1494 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1495 interconnect-names = "qup-core", "qup-config"; 1496 status = "disabled"; 1497 }; 1498 1499 uart10: serial@a88000 { 1500 compatible = "qcom,geni-uart"; 1501 reg = <0 0x00a88000 0 0x4000>; 1502 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1503 clock-names = "se"; 1504 pinctrl-names = "default"; 1505 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1506 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1507 power-domains = <&rpmhpd SC7280_CX>; 1508 operating-points-v2 = <&qup_opp_table>; 1509 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1510 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1511 interconnect-names = "qup-core", "qup-config"; 1512 status = "disabled"; 1513 }; 1514 1515 i2c11: i2c@a8c000 { 1516 compatible = "qcom,geni-i2c"; 1517 reg = <0 0x00a8c000 0 0x4000>; 1518 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1519 clock-names = "se"; 1520 pinctrl-names = "default"; 1521 pinctrl-0 = <&qup_i2c11_data_clk>; 1522 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1523 #address-cells = <1>; 1524 #size-cells = <0>; 1525 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1526 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1527 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1528 interconnect-names = "qup-core", "qup-config", 1529 "qup-memory"; 1530 status = "disabled"; 1531 }; 1532 1533 spi11: spi@a8c000 { 1534 compatible = "qcom,geni-spi"; 1535 reg = <0 0x00a8c000 0 0x4000>; 1536 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1537 clock-names = "se"; 1538 pinctrl-names = "default"; 1539 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1540 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1541 #address-cells = <1>; 1542 #size-cells = <0>; 1543 power-domains = <&rpmhpd SC7280_CX>; 1544 operating-points-v2 = <&qup_opp_table>; 1545 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1546 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1547 interconnect-names = "qup-core", "qup-config"; 1548 status = "disabled"; 1549 }; 1550 1551 uart11: serial@a8c000 { 1552 compatible = "qcom,geni-uart"; 1553 reg = <0 0x00a8c000 0 0x4000>; 1554 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1555 clock-names = "se"; 1556 pinctrl-names = "default"; 1557 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1558 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1559 power-domains = <&rpmhpd SC7280_CX>; 1560 operating-points-v2 = <&qup_opp_table>; 1561 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1562 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1563 interconnect-names = "qup-core", "qup-config"; 1564 status = "disabled"; 1565 }; 1566 1567 i2c12: i2c@a90000 { 1568 compatible = "qcom,geni-i2c"; 1569 reg = <0 0x00a90000 0 0x4000>; 1570 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1571 clock-names = "se"; 1572 pinctrl-names = "default"; 1573 pinctrl-0 = <&qup_i2c12_data_clk>; 1574 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1575 #address-cells = <1>; 1576 #size-cells = <0>; 1577 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1578 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1579 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1580 interconnect-names = "qup-core", "qup-config", 1581 "qup-memory"; 1582 status = "disabled"; 1583 }; 1584 1585 spi12: spi@a90000 { 1586 compatible = "qcom,geni-spi"; 1587 reg = <0 0x00a90000 0 0x4000>; 1588 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1589 clock-names = "se"; 1590 pinctrl-names = "default"; 1591 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1592 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1593 #address-cells = <1>; 1594 #size-cells = <0>; 1595 power-domains = <&rpmhpd SC7280_CX>; 1596 operating-points-v2 = <&qup_opp_table>; 1597 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1598 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1599 interconnect-names = "qup-core", "qup-config"; 1600 status = "disabled"; 1601 }; 1602 1603 uart12: serial@a90000 { 1604 compatible = "qcom,geni-uart"; 1605 reg = <0 0x00a90000 0 0x4000>; 1606 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1607 clock-names = "se"; 1608 pinctrl-names = "default"; 1609 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1610 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1611 power-domains = <&rpmhpd SC7280_CX>; 1612 operating-points-v2 = <&qup_opp_table>; 1613 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1614 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1615 interconnect-names = "qup-core", "qup-config"; 1616 status = "disabled"; 1617 }; 1618 1619 i2c13: i2c@a94000 { 1620 compatible = "qcom,geni-i2c"; 1621 reg = <0 0x00a94000 0 0x4000>; 1622 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1623 clock-names = "se"; 1624 pinctrl-names = "default"; 1625 pinctrl-0 = <&qup_i2c13_data_clk>; 1626 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1630 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1631 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1632 interconnect-names = "qup-core", "qup-config", 1633 "qup-memory"; 1634 status = "disabled"; 1635 }; 1636 1637 spi13: spi@a94000 { 1638 compatible = "qcom,geni-spi"; 1639 reg = <0 0x00a94000 0 0x4000>; 1640 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1641 clock-names = "se"; 1642 pinctrl-names = "default"; 1643 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1644 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1645 #address-cells = <1>; 1646 #size-cells = <0>; 1647 power-domains = <&rpmhpd SC7280_CX>; 1648 operating-points-v2 = <&qup_opp_table>; 1649 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1650 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1651 interconnect-names = "qup-core", "qup-config"; 1652 status = "disabled"; 1653 }; 1654 1655 uart13: serial@a94000 { 1656 compatible = "qcom,geni-uart"; 1657 reg = <0 0x00a94000 0 0x4000>; 1658 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1659 clock-names = "se"; 1660 pinctrl-names = "default"; 1661 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1662 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1663 power-domains = <&rpmhpd SC7280_CX>; 1664 operating-points-v2 = <&qup_opp_table>; 1665 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1666 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1667 interconnect-names = "qup-core", "qup-config"; 1668 status = "disabled"; 1669 }; 1670 1671 i2c14: i2c@a98000 { 1672 compatible = "qcom,geni-i2c"; 1673 reg = <0 0x00a98000 0 0x4000>; 1674 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1675 clock-names = "se"; 1676 pinctrl-names = "default"; 1677 pinctrl-0 = <&qup_i2c14_data_clk>; 1678 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1679 #address-cells = <1>; 1680 #size-cells = <0>; 1681 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1682 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1683 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1684 interconnect-names = "qup-core", "qup-config", 1685 "qup-memory"; 1686 status = "disabled"; 1687 }; 1688 1689 spi14: spi@a98000 { 1690 compatible = "qcom,geni-spi"; 1691 reg = <0 0x00a98000 0 0x4000>; 1692 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1693 clock-names = "se"; 1694 pinctrl-names = "default"; 1695 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1696 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1697 #address-cells = <1>; 1698 #size-cells = <0>; 1699 power-domains = <&rpmhpd SC7280_CX>; 1700 operating-points-v2 = <&qup_opp_table>; 1701 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1702 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1703 interconnect-names = "qup-core", "qup-config"; 1704 status = "disabled"; 1705 }; 1706 1707 uart14: serial@a98000 { 1708 compatible = "qcom,geni-uart"; 1709 reg = <0 0x00a98000 0 0x4000>; 1710 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1711 clock-names = "se"; 1712 pinctrl-names = "default"; 1713 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1714 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1715 power-domains = <&rpmhpd SC7280_CX>; 1716 operating-points-v2 = <&qup_opp_table>; 1717 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1718 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1719 interconnect-names = "qup-core", "qup-config"; 1720 status = "disabled"; 1721 }; 1722 1723 i2c15: i2c@a9c000 { 1724 compatible = "qcom,geni-i2c"; 1725 reg = <0 0x00a9c000 0 0x4000>; 1726 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1727 clock-names = "se"; 1728 pinctrl-names = "default"; 1729 pinctrl-0 = <&qup_i2c15_data_clk>; 1730 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1731 #address-cells = <1>; 1732 #size-cells = <0>; 1733 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1734 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1735 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1736 interconnect-names = "qup-core", "qup-config", 1737 "qup-memory"; 1738 status = "disabled"; 1739 }; 1740 1741 spi15: spi@a9c000 { 1742 compatible = "qcom,geni-spi"; 1743 reg = <0 0x00a9c000 0 0x4000>; 1744 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1745 clock-names = "se"; 1746 pinctrl-names = "default"; 1747 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1748 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1749 #address-cells = <1>; 1750 #size-cells = <0>; 1751 power-domains = <&rpmhpd SC7280_CX>; 1752 operating-points-v2 = <&qup_opp_table>; 1753 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1754 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1755 interconnect-names = "qup-core", "qup-config"; 1756 status = "disabled"; 1757 }; 1758 1759 uart15: serial@a9c000 { 1760 compatible = "qcom,geni-uart"; 1761 reg = <0 0x00a9c000 0 0x4000>; 1762 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1763 clock-names = "se"; 1764 pinctrl-names = "default"; 1765 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1766 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1767 power-domains = <&rpmhpd SC7280_CX>; 1768 operating-points-v2 = <&qup_opp_table>; 1769 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1770 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1771 interconnect-names = "qup-core", "qup-config"; 1772 status = "disabled"; 1773 }; 1774 }; 1775 1776 cnoc2: interconnect@1500000 { 1777 reg = <0 0x01500000 0 0x1000>; 1778 compatible = "qcom,sc7280-cnoc2"; 1779 #interconnect-cells = <2>; 1780 qcom,bcm-voters = <&apps_bcm_voter>; 1781 }; 1782 1783 cnoc3: interconnect@1502000 { 1784 reg = <0 0x01502000 0 0x1000>; 1785 compatible = "qcom,sc7280-cnoc3"; 1786 #interconnect-cells = <2>; 1787 qcom,bcm-voters = <&apps_bcm_voter>; 1788 }; 1789 1790 mc_virt: interconnect@1580000 { 1791 reg = <0 0x01580000 0 0x4>; 1792 compatible = "qcom,sc7280-mc-virt"; 1793 #interconnect-cells = <2>; 1794 qcom,bcm-voters = <&apps_bcm_voter>; 1795 }; 1796 1797 system_noc: interconnect@1680000 { 1798 reg = <0 0x01680000 0 0x15480>; 1799 compatible = "qcom,sc7280-system-noc"; 1800 #interconnect-cells = <2>; 1801 qcom,bcm-voters = <&apps_bcm_voter>; 1802 }; 1803 1804 aggre1_noc: interconnect@16e0000 { 1805 compatible = "qcom,sc7280-aggre1-noc"; 1806 reg = <0 0x016e0000 0 0x1c080>; 1807 #interconnect-cells = <2>; 1808 qcom,bcm-voters = <&apps_bcm_voter>; 1809 }; 1810 1811 aggre2_noc: interconnect@1700000 { 1812 reg = <0 0x01700000 0 0x2b080>; 1813 compatible = "qcom,sc7280-aggre2-noc"; 1814 #interconnect-cells = <2>; 1815 qcom,bcm-voters = <&apps_bcm_voter>; 1816 }; 1817 1818 mmss_noc: interconnect@1740000 { 1819 reg = <0 0x01740000 0 0x1e080>; 1820 compatible = "qcom,sc7280-mmss-noc"; 1821 #interconnect-cells = <2>; 1822 qcom,bcm-voters = <&apps_bcm_voter>; 1823 }; 1824 1825 wifi: wifi@17a10040 { 1826 compatible = "qcom,wcn6750-wifi"; 1827 reg = <0 0x17a10040 0 0x0>; 1828 iommus = <&apps_smmu 0x1c00 0x1>; 1829 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 1830 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 1831 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 1832 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 1833 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 1834 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 1835 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 1836 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 1837 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 1838 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 1839 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 1840 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 1841 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 1842 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 1843 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 1844 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 1845 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 1846 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 1847 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 1848 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 1849 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 1850 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 1851 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 1852 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 1853 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 1854 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 1855 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 1856 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 1857 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 1858 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 1859 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 1860 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 1861 qcom,rproc = <&remoteproc_wpss>; 1862 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 1863 status = "disabled"; 1864 }; 1865 1866 pcie1: pci@1c08000 { 1867 compatible = "qcom,pcie-sc7280"; 1868 reg = <0 0x01c08000 0 0x3000>, 1869 <0 0x40000000 0 0xf1d>, 1870 <0 0x40000f20 0 0xa8>, 1871 <0 0x40001000 0 0x1000>, 1872 <0 0x40100000 0 0x100000>; 1873 1874 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1875 device_type = "pci"; 1876 linux,pci-domain = <1>; 1877 bus-range = <0x00 0xff>; 1878 num-lanes = <2>; 1879 1880 #address-cells = <3>; 1881 #size-cells = <2>; 1882 1883 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1884 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1885 1886 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1887 interrupt-names = "msi"; 1888 #interrupt-cells = <1>; 1889 interrupt-map-mask = <0 0 0 0x7>; 1890 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 1891 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 1892 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 1893 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 1894 1895 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1896 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1897 <&pcie1_lane 0>, 1898 <&rpmhcc RPMH_CXO_CLK>, 1899 <&gcc GCC_PCIE_1_AUX_CLK>, 1900 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1901 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1902 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1903 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1904 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1905 <&gcc GCC_DDRSS_PCIE_SF_CLK>; 1906 1907 clock-names = "pipe", 1908 "pipe_mux", 1909 "phy_pipe", 1910 "ref", 1911 "aux", 1912 "cfg", 1913 "bus_master", 1914 "bus_slave", 1915 "slave_q2a", 1916 "tbu", 1917 "ddrss_sf_tbu"; 1918 1919 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1920 assigned-clock-rates = <19200000>; 1921 1922 resets = <&gcc GCC_PCIE_1_BCR>; 1923 reset-names = "pci"; 1924 1925 power-domains = <&gcc GCC_PCIE_1_GDSC>; 1926 1927 phys = <&pcie1_lane>; 1928 phy-names = "pciephy"; 1929 1930 pinctrl-names = "default"; 1931 pinctrl-0 = <&pcie1_clkreq_n>; 1932 1933 iommus = <&apps_smmu 0x1c80 0x1>; 1934 1935 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1936 <0x100 &apps_smmu 0x1c81 0x1>; 1937 1938 status = "disabled"; 1939 }; 1940 1941 pcie1_phy: phy@1c0e000 { 1942 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1943 reg = <0 0x01c0e000 0 0x1c0>; 1944 #address-cells = <2>; 1945 #size-cells = <2>; 1946 ranges; 1947 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1948 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1949 <&gcc GCC_PCIE_CLKREF_EN>, 1950 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1951 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1952 1953 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1954 reset-names = "phy"; 1955 1956 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1957 assigned-clock-rates = <100000000>; 1958 1959 status = "disabled"; 1960 1961 pcie1_lane: phy@1c0e200 { 1962 reg = <0 0x01c0e200 0 0x170>, 1963 <0 0x01c0e400 0 0x200>, 1964 <0 0x01c0ea00 0 0x1f0>, 1965 <0 0x01c0e600 0 0x170>, 1966 <0 0x01c0e800 0 0x200>, 1967 <0 0x01c0ee00 0 0xf4>; 1968 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1969 clock-names = "pipe0"; 1970 1971 #phy-cells = <0>; 1972 #clock-cells = <1>; 1973 clock-output-names = "pcie_1_pipe_clk"; 1974 }; 1975 }; 1976 1977 ipa: ipa@1e40000 { 1978 compatible = "qcom,sc7280-ipa"; 1979 1980 iommus = <&apps_smmu 0x480 0x0>, 1981 <&apps_smmu 0x482 0x0>; 1982 reg = <0 0x1e40000 0 0x8000>, 1983 <0 0x1e50000 0 0x4ad0>, 1984 <0 0x1e04000 0 0x23000>; 1985 reg-names = "ipa-reg", 1986 "ipa-shared", 1987 "gsi"; 1988 1989 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 1990 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1991 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1992 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1993 interrupt-names = "ipa", 1994 "gsi", 1995 "ipa-clock-query", 1996 "ipa-setup-ready"; 1997 1998 clocks = <&rpmhcc RPMH_IPA_CLK>; 1999 clock-names = "core"; 2000 2001 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2002 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2003 interconnect-names = "memory", 2004 "config"; 2005 2006 qcom,qmp = <&aoss_qmp>; 2007 2008 qcom,smem-states = <&ipa_smp2p_out 0>, 2009 <&ipa_smp2p_out 1>; 2010 qcom,smem-state-names = "ipa-clock-enabled-valid", 2011 "ipa-clock-enabled"; 2012 2013 status = "disabled"; 2014 }; 2015 2016 tcsr_mutex: hwlock@1f40000 { 2017 compatible = "qcom,tcsr-mutex", "syscon"; 2018 reg = <0 0x01f40000 0 0x40000>; 2019 #hwlock-cells = <1>; 2020 }; 2021 2022 tcsr: syscon@1fc0000 { 2023 compatible = "qcom,sc7280-tcsr", "syscon"; 2024 reg = <0 0x01fc0000 0 0x30000>; 2025 }; 2026 2027 lpasscc: lpasscc@3000000 { 2028 compatible = "qcom,sc7280-lpasscc"; 2029 reg = <0 0x03000000 0 0x40>, 2030 <0 0x03c04000 0 0x4>, 2031 <0 0x03389000 0 0x24>; 2032 reg-names = "qdsp6ss", "top_cc", "cc"; 2033 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2034 clock-names = "iface"; 2035 #clock-cells = <1>; 2036 }; 2037 2038 lpass_audiocc: clock-controller@3300000 { 2039 compatible = "qcom,sc7280-lpassaudiocc"; 2040 reg = <0 0x03300000 0 0x30000>; 2041 clocks = <&rpmhcc RPMH_CXO_CLK>, 2042 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2043 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2044 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2045 #clock-cells = <1>; 2046 #power-domain-cells = <1>; 2047 }; 2048 2049 lpass_aon: clock-controller@3380000 { 2050 compatible = "qcom,sc7280-lpassaoncc"; 2051 reg = <0 0x03380000 0 0x30000>; 2052 clocks = <&rpmhcc RPMH_CXO_CLK>, 2053 <&rpmhcc RPMH_CXO_CLK_A>, 2054 <&lpasscore LPASS_CORE_CC_CORE_CLK>; 2055 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2056 #clock-cells = <1>; 2057 #power-domain-cells = <1>; 2058 }; 2059 2060 lpasscore: clock-controller@3900000 { 2061 compatible = "qcom,sc7280-lpasscorecc"; 2062 reg = <0 0x03900000 0 0x50000>; 2063 clocks = <&rpmhcc RPMH_CXO_CLK>; 2064 clock-names = "bi_tcxo"; 2065 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2066 #clock-cells = <1>; 2067 #power-domain-cells = <1>; 2068 }; 2069 2070 lpass_hm: clock-controller@3c00000 { 2071 compatible = "qcom,sc7280-lpasshm"; 2072 reg = <0 0x3c00000 0 0x28>; 2073 clocks = <&rpmhcc RPMH_CXO_CLK>; 2074 clock-names = "bi_tcxo"; 2075 #clock-cells = <1>; 2076 #power-domain-cells = <1>; 2077 }; 2078 2079 lpass_ag_noc: interconnect@3c40000 { 2080 reg = <0 0x03c40000 0 0xf080>; 2081 compatible = "qcom,sc7280-lpass-ag-noc"; 2082 #interconnect-cells = <2>; 2083 qcom,bcm-voters = <&apps_bcm_voter>; 2084 }; 2085 2086 gpu: gpu@3d00000 { 2087 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2088 reg = <0 0x03d00000 0 0x40000>, 2089 <0 0x03d9e000 0 0x1000>, 2090 <0 0x03d61000 0 0x800>; 2091 reg-names = "kgsl_3d0_reg_memory", 2092 "cx_mem", 2093 "cx_dbgc"; 2094 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2095 iommus = <&adreno_smmu 0 0x401>; 2096 operating-points-v2 = <&gpu_opp_table>; 2097 qcom,gmu = <&gmu>; 2098 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2099 interconnect-names = "gfx-mem"; 2100 #cooling-cells = <2>; 2101 2102 nvmem-cells = <&gpu_speed_bin>; 2103 nvmem-cell-names = "speed_bin"; 2104 2105 gpu_opp_table: opp-table { 2106 compatible = "operating-points-v2"; 2107 2108 opp-315000000 { 2109 opp-hz = /bits/ 64 <315000000>; 2110 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2111 opp-peak-kBps = <1804000>; 2112 opp-supported-hw = <0x03>; 2113 }; 2114 2115 opp-450000000 { 2116 opp-hz = /bits/ 64 <450000000>; 2117 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2118 opp-peak-kBps = <4068000>; 2119 opp-supported-hw = <0x03>; 2120 }; 2121 2122 opp-550000000 { 2123 opp-hz = /bits/ 64 <550000000>; 2124 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2125 opp-peak-kBps = <6832000>; 2126 opp-supported-hw = <0x03>; 2127 }; 2128 2129 opp-608000000 { 2130 opp-hz = /bits/ 64 <608000000>; 2131 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2132 opp-peak-kBps = <8368000>; 2133 opp-supported-hw = <0x02>; 2134 }; 2135 2136 opp-700000000 { 2137 opp-hz = /bits/ 64 <700000000>; 2138 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2139 opp-peak-kBps = <8532000>; 2140 opp-supported-hw = <0x02>; 2141 }; 2142 2143 opp-812000000 { 2144 opp-hz = /bits/ 64 <812000000>; 2145 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2146 opp-peak-kBps = <8532000>; 2147 opp-supported-hw = <0x02>; 2148 }; 2149 2150 opp-840000000 { 2151 opp-hz = /bits/ 64 <840000000>; 2152 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2153 opp-peak-kBps = <8532000>; 2154 opp-supported-hw = <0x02>; 2155 }; 2156 2157 opp-900000000 { 2158 opp-hz = /bits/ 64 <900000000>; 2159 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2160 opp-peak-kBps = <8532000>; 2161 opp-supported-hw = <0x02>; 2162 }; 2163 }; 2164 }; 2165 2166 gmu: gmu@3d6a000 { 2167 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2168 reg = <0 0x03d6a000 0 0x34000>, 2169 <0 0x3de0000 0 0x10000>, 2170 <0 0x0b290000 0 0x10000>; 2171 reg-names = "gmu", "rscc", "gmu_pdc"; 2172 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2173 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2174 interrupt-names = "hfi", "gmu"; 2175 clocks = <&gpucc 5>, 2176 <&gpucc 8>, 2177 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2178 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2179 <&gpucc 2>, 2180 <&gpucc 15>, 2181 <&gpucc 11>; 2182 clock-names = "gmu", 2183 "cxo", 2184 "axi", 2185 "memnoc", 2186 "ahb", 2187 "hub", 2188 "smmu_vote"; 2189 power-domains = <&gpucc 0>, 2190 <&gpucc 1>; 2191 power-domain-names = "cx", 2192 "gx"; 2193 iommus = <&adreno_smmu 5 0x400>; 2194 operating-points-v2 = <&gmu_opp_table>; 2195 2196 gmu_opp_table: opp-table { 2197 compatible = "operating-points-v2"; 2198 2199 opp-200000000 { 2200 opp-hz = /bits/ 64 <200000000>; 2201 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2202 }; 2203 }; 2204 }; 2205 2206 gpucc: clock-controller@3d90000 { 2207 compatible = "qcom,sc7280-gpucc"; 2208 reg = <0 0x03d90000 0 0x9000>; 2209 clocks = <&rpmhcc RPMH_CXO_CLK>, 2210 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2211 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2212 clock-names = "bi_tcxo", 2213 "gcc_gpu_gpll0_clk_src", 2214 "gcc_gpu_gpll0_div_clk_src"; 2215 #clock-cells = <1>; 2216 #reset-cells = <1>; 2217 #power-domain-cells = <1>; 2218 }; 2219 2220 adreno_smmu: iommu@3da0000 { 2221 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2222 reg = <0 0x03da0000 0 0x20000>; 2223 #iommu-cells = <2>; 2224 #global-interrupts = <2>; 2225 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2226 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2227 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2228 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2229 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2230 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2231 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2232 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2233 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2234 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2235 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2236 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2237 2238 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2239 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2240 <&gpucc 2>, 2241 <&gpucc 11>, 2242 <&gpucc 5>, 2243 <&gpucc 15>, 2244 <&gpucc 13>; 2245 clock-names = "gcc_gpu_memnoc_gfx_clk", 2246 "gcc_gpu_snoc_dvm_gfx_clk", 2247 "gpu_cc_ahb_clk", 2248 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2249 "gpu_cc_cx_gmu_clk", 2250 "gpu_cc_hub_cx_int_clk", 2251 "gpu_cc_hub_aon_clk"; 2252 2253 power-domains = <&gpucc 0>; 2254 }; 2255 2256 remoteproc_mpss: remoteproc@4080000 { 2257 compatible = "qcom,sc7280-mpss-pas"; 2258 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2259 reg-names = "qdsp6", "rmb"; 2260 2261 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2262 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2263 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2264 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2265 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2266 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2267 interrupt-names = "wdog", "fatal", "ready", "handover", 2268 "stop-ack", "shutdown-ack"; 2269 2270 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2271 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 2272 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2273 <&rpmhcc RPMH_PKA_CLK>, 2274 <&rpmhcc RPMH_CXO_CLK>; 2275 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 2276 2277 power-domains = <&rpmhpd SC7280_CX>, 2278 <&rpmhpd SC7280_MSS>; 2279 power-domain-names = "cx", "mss"; 2280 2281 memory-region = <&mpss_mem>; 2282 2283 qcom,qmp = <&aoss_qmp>; 2284 2285 qcom,smem-states = <&modem_smp2p_out 0>; 2286 qcom,smem-state-names = "stop"; 2287 2288 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2289 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2290 reset-names = "mss_restart", "pdc_reset"; 2291 2292 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; 2293 qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>; 2294 qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>; 2295 2296 status = "disabled"; 2297 2298 glink-edge { 2299 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2300 IPCC_MPROC_SIGNAL_GLINK_QMP 2301 IRQ_TYPE_EDGE_RISING>; 2302 mboxes = <&ipcc IPCC_CLIENT_MPSS 2303 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2304 label = "modem"; 2305 qcom,remote-pid = <1>; 2306 }; 2307 }; 2308 2309 stm@6002000 { 2310 compatible = "arm,coresight-stm", "arm,primecell"; 2311 reg = <0 0x06002000 0 0x1000>, 2312 <0 0x16280000 0 0x180000>; 2313 reg-names = "stm-base", "stm-stimulus-base"; 2314 2315 clocks = <&aoss_qmp>; 2316 clock-names = "apb_pclk"; 2317 2318 out-ports { 2319 port { 2320 stm_out: endpoint { 2321 remote-endpoint = <&funnel0_in7>; 2322 }; 2323 }; 2324 }; 2325 }; 2326 2327 funnel@6041000 { 2328 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2329 reg = <0 0x06041000 0 0x1000>; 2330 2331 clocks = <&aoss_qmp>; 2332 clock-names = "apb_pclk"; 2333 2334 out-ports { 2335 port { 2336 funnel0_out: endpoint { 2337 remote-endpoint = <&merge_funnel_in0>; 2338 }; 2339 }; 2340 }; 2341 2342 in-ports { 2343 #address-cells = <1>; 2344 #size-cells = <0>; 2345 2346 port@7 { 2347 reg = <7>; 2348 funnel0_in7: endpoint { 2349 remote-endpoint = <&stm_out>; 2350 }; 2351 }; 2352 }; 2353 }; 2354 2355 funnel@6042000 { 2356 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2357 reg = <0 0x06042000 0 0x1000>; 2358 2359 clocks = <&aoss_qmp>; 2360 clock-names = "apb_pclk"; 2361 2362 out-ports { 2363 port { 2364 funnel1_out: endpoint { 2365 remote-endpoint = <&merge_funnel_in1>; 2366 }; 2367 }; 2368 }; 2369 2370 in-ports { 2371 #address-cells = <1>; 2372 #size-cells = <0>; 2373 2374 port@4 { 2375 reg = <4>; 2376 funnel1_in4: endpoint { 2377 remote-endpoint = <&apss_merge_funnel_out>; 2378 }; 2379 }; 2380 }; 2381 }; 2382 2383 funnel@6045000 { 2384 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2385 reg = <0 0x06045000 0 0x1000>; 2386 2387 clocks = <&aoss_qmp>; 2388 clock-names = "apb_pclk"; 2389 2390 out-ports { 2391 port { 2392 merge_funnel_out: endpoint { 2393 remote-endpoint = <&swao_funnel_in>; 2394 }; 2395 }; 2396 }; 2397 2398 in-ports { 2399 #address-cells = <1>; 2400 #size-cells = <0>; 2401 2402 port@0 { 2403 reg = <0>; 2404 merge_funnel_in0: endpoint { 2405 remote-endpoint = <&funnel0_out>; 2406 }; 2407 }; 2408 2409 port@1 { 2410 reg = <1>; 2411 merge_funnel_in1: endpoint { 2412 remote-endpoint = <&funnel1_out>; 2413 }; 2414 }; 2415 }; 2416 }; 2417 2418 replicator@6046000 { 2419 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2420 reg = <0 0x06046000 0 0x1000>; 2421 2422 clocks = <&aoss_qmp>; 2423 clock-names = "apb_pclk"; 2424 2425 out-ports { 2426 port { 2427 replicator_out: endpoint { 2428 remote-endpoint = <&etr_in>; 2429 }; 2430 }; 2431 }; 2432 2433 in-ports { 2434 port { 2435 replicator_in: endpoint { 2436 remote-endpoint = <&swao_replicator_out>; 2437 }; 2438 }; 2439 }; 2440 }; 2441 2442 etr@6048000 { 2443 compatible = "arm,coresight-tmc", "arm,primecell"; 2444 reg = <0 0x06048000 0 0x1000>; 2445 iommus = <&apps_smmu 0x04c0 0>; 2446 2447 clocks = <&aoss_qmp>; 2448 clock-names = "apb_pclk"; 2449 arm,scatter-gather; 2450 2451 in-ports { 2452 port { 2453 etr_in: endpoint { 2454 remote-endpoint = <&replicator_out>; 2455 }; 2456 }; 2457 }; 2458 }; 2459 2460 funnel@6b04000 { 2461 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2462 reg = <0 0x06b04000 0 0x1000>; 2463 2464 clocks = <&aoss_qmp>; 2465 clock-names = "apb_pclk"; 2466 2467 out-ports { 2468 port { 2469 swao_funnel_out: endpoint { 2470 remote-endpoint = <&etf_in>; 2471 }; 2472 }; 2473 }; 2474 2475 in-ports { 2476 #address-cells = <1>; 2477 #size-cells = <0>; 2478 2479 port@7 { 2480 reg = <7>; 2481 swao_funnel_in: endpoint { 2482 remote-endpoint = <&merge_funnel_out>; 2483 }; 2484 }; 2485 }; 2486 }; 2487 2488 etf@6b05000 { 2489 compatible = "arm,coresight-tmc", "arm,primecell"; 2490 reg = <0 0x06b05000 0 0x1000>; 2491 2492 clocks = <&aoss_qmp>; 2493 clock-names = "apb_pclk"; 2494 2495 out-ports { 2496 port { 2497 etf_out: endpoint { 2498 remote-endpoint = <&swao_replicator_in>; 2499 }; 2500 }; 2501 }; 2502 2503 in-ports { 2504 port { 2505 etf_in: endpoint { 2506 remote-endpoint = <&swao_funnel_out>; 2507 }; 2508 }; 2509 }; 2510 }; 2511 2512 replicator@6b06000 { 2513 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2514 reg = <0 0x06b06000 0 0x1000>; 2515 2516 clocks = <&aoss_qmp>; 2517 clock-names = "apb_pclk"; 2518 qcom,replicator-loses-context; 2519 2520 out-ports { 2521 port { 2522 swao_replicator_out: endpoint { 2523 remote-endpoint = <&replicator_in>; 2524 }; 2525 }; 2526 }; 2527 2528 in-ports { 2529 port { 2530 swao_replicator_in: endpoint { 2531 remote-endpoint = <&etf_out>; 2532 }; 2533 }; 2534 }; 2535 }; 2536 2537 etm@7040000 { 2538 compatible = "arm,coresight-etm4x", "arm,primecell"; 2539 reg = <0 0x07040000 0 0x1000>; 2540 2541 cpu = <&CPU0>; 2542 2543 clocks = <&aoss_qmp>; 2544 clock-names = "apb_pclk"; 2545 arm,coresight-loses-context-with-cpu; 2546 qcom,skip-power-up; 2547 2548 out-ports { 2549 port { 2550 etm0_out: endpoint { 2551 remote-endpoint = <&apss_funnel_in0>; 2552 }; 2553 }; 2554 }; 2555 }; 2556 2557 etm@7140000 { 2558 compatible = "arm,coresight-etm4x", "arm,primecell"; 2559 reg = <0 0x07140000 0 0x1000>; 2560 2561 cpu = <&CPU1>; 2562 2563 clocks = <&aoss_qmp>; 2564 clock-names = "apb_pclk"; 2565 arm,coresight-loses-context-with-cpu; 2566 qcom,skip-power-up; 2567 2568 out-ports { 2569 port { 2570 etm1_out: endpoint { 2571 remote-endpoint = <&apss_funnel_in1>; 2572 }; 2573 }; 2574 }; 2575 }; 2576 2577 etm@7240000 { 2578 compatible = "arm,coresight-etm4x", "arm,primecell"; 2579 reg = <0 0x07240000 0 0x1000>; 2580 2581 cpu = <&CPU2>; 2582 2583 clocks = <&aoss_qmp>; 2584 clock-names = "apb_pclk"; 2585 arm,coresight-loses-context-with-cpu; 2586 qcom,skip-power-up; 2587 2588 out-ports { 2589 port { 2590 etm2_out: endpoint { 2591 remote-endpoint = <&apss_funnel_in2>; 2592 }; 2593 }; 2594 }; 2595 }; 2596 2597 etm@7340000 { 2598 compatible = "arm,coresight-etm4x", "arm,primecell"; 2599 reg = <0 0x07340000 0 0x1000>; 2600 2601 cpu = <&CPU3>; 2602 2603 clocks = <&aoss_qmp>; 2604 clock-names = "apb_pclk"; 2605 arm,coresight-loses-context-with-cpu; 2606 qcom,skip-power-up; 2607 2608 out-ports { 2609 port { 2610 etm3_out: endpoint { 2611 remote-endpoint = <&apss_funnel_in3>; 2612 }; 2613 }; 2614 }; 2615 }; 2616 2617 etm@7440000 { 2618 compatible = "arm,coresight-etm4x", "arm,primecell"; 2619 reg = <0 0x07440000 0 0x1000>; 2620 2621 cpu = <&CPU4>; 2622 2623 clocks = <&aoss_qmp>; 2624 clock-names = "apb_pclk"; 2625 arm,coresight-loses-context-with-cpu; 2626 qcom,skip-power-up; 2627 2628 out-ports { 2629 port { 2630 etm4_out: endpoint { 2631 remote-endpoint = <&apss_funnel_in4>; 2632 }; 2633 }; 2634 }; 2635 }; 2636 2637 etm@7540000 { 2638 compatible = "arm,coresight-etm4x", "arm,primecell"; 2639 reg = <0 0x07540000 0 0x1000>; 2640 2641 cpu = <&CPU5>; 2642 2643 clocks = <&aoss_qmp>; 2644 clock-names = "apb_pclk"; 2645 arm,coresight-loses-context-with-cpu; 2646 qcom,skip-power-up; 2647 2648 out-ports { 2649 port { 2650 etm5_out: endpoint { 2651 remote-endpoint = <&apss_funnel_in5>; 2652 }; 2653 }; 2654 }; 2655 }; 2656 2657 etm@7640000 { 2658 compatible = "arm,coresight-etm4x", "arm,primecell"; 2659 reg = <0 0x07640000 0 0x1000>; 2660 2661 cpu = <&CPU6>; 2662 2663 clocks = <&aoss_qmp>; 2664 clock-names = "apb_pclk"; 2665 arm,coresight-loses-context-with-cpu; 2666 qcom,skip-power-up; 2667 2668 out-ports { 2669 port { 2670 etm6_out: endpoint { 2671 remote-endpoint = <&apss_funnel_in6>; 2672 }; 2673 }; 2674 }; 2675 }; 2676 2677 etm@7740000 { 2678 compatible = "arm,coresight-etm4x", "arm,primecell"; 2679 reg = <0 0x07740000 0 0x1000>; 2680 2681 cpu = <&CPU7>; 2682 2683 clocks = <&aoss_qmp>; 2684 clock-names = "apb_pclk"; 2685 arm,coresight-loses-context-with-cpu; 2686 qcom,skip-power-up; 2687 2688 out-ports { 2689 port { 2690 etm7_out: endpoint { 2691 remote-endpoint = <&apss_funnel_in7>; 2692 }; 2693 }; 2694 }; 2695 }; 2696 2697 funnel@7800000 { /* APSS Funnel */ 2698 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2699 reg = <0 0x07800000 0 0x1000>; 2700 2701 clocks = <&aoss_qmp>; 2702 clock-names = "apb_pclk"; 2703 2704 out-ports { 2705 port { 2706 apss_funnel_out: endpoint { 2707 remote-endpoint = <&apss_merge_funnel_in>; 2708 }; 2709 }; 2710 }; 2711 2712 in-ports { 2713 #address-cells = <1>; 2714 #size-cells = <0>; 2715 2716 port@0 { 2717 reg = <0>; 2718 apss_funnel_in0: endpoint { 2719 remote-endpoint = <&etm0_out>; 2720 }; 2721 }; 2722 2723 port@1 { 2724 reg = <1>; 2725 apss_funnel_in1: endpoint { 2726 remote-endpoint = <&etm1_out>; 2727 }; 2728 }; 2729 2730 port@2 { 2731 reg = <2>; 2732 apss_funnel_in2: endpoint { 2733 remote-endpoint = <&etm2_out>; 2734 }; 2735 }; 2736 2737 port@3 { 2738 reg = <3>; 2739 apss_funnel_in3: endpoint { 2740 remote-endpoint = <&etm3_out>; 2741 }; 2742 }; 2743 2744 port@4 { 2745 reg = <4>; 2746 apss_funnel_in4: endpoint { 2747 remote-endpoint = <&etm4_out>; 2748 }; 2749 }; 2750 2751 port@5 { 2752 reg = <5>; 2753 apss_funnel_in5: endpoint { 2754 remote-endpoint = <&etm5_out>; 2755 }; 2756 }; 2757 2758 port@6 { 2759 reg = <6>; 2760 apss_funnel_in6: endpoint { 2761 remote-endpoint = <&etm6_out>; 2762 }; 2763 }; 2764 2765 port@7 { 2766 reg = <7>; 2767 apss_funnel_in7: endpoint { 2768 remote-endpoint = <&etm7_out>; 2769 }; 2770 }; 2771 }; 2772 }; 2773 2774 funnel@7810000 { 2775 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2776 reg = <0 0x07810000 0 0x1000>; 2777 2778 clocks = <&aoss_qmp>; 2779 clock-names = "apb_pclk"; 2780 2781 out-ports { 2782 port { 2783 apss_merge_funnel_out: endpoint { 2784 remote-endpoint = <&funnel1_in4>; 2785 }; 2786 }; 2787 }; 2788 2789 in-ports { 2790 port { 2791 apss_merge_funnel_in: endpoint { 2792 remote-endpoint = <&apss_funnel_out>; 2793 }; 2794 }; 2795 }; 2796 }; 2797 2798 sdhc_2: sdhci@8804000 { 2799 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 2800 pinctrl-names = "default", "sleep"; 2801 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 2802 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 2803 status = "disabled"; 2804 2805 reg = <0 0x08804000 0 0x1000>; 2806 2807 iommus = <&apps_smmu 0x100 0x0>; 2808 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2809 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2810 interrupt-names = "hc_irq", "pwr_irq"; 2811 2812 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2813 <&gcc GCC_SDCC2_AHB_CLK>, 2814 <&rpmhcc RPMH_CXO_CLK>; 2815 clock-names = "core", "iface", "xo"; 2816 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2817 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 2818 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2819 power-domains = <&rpmhpd SC7280_CX>; 2820 operating-points-v2 = <&sdhc2_opp_table>; 2821 2822 bus-width = <4>; 2823 2824 qcom,dll-config = <0x0007642c>; 2825 2826 resets = <&gcc GCC_SDCC2_BCR>; 2827 2828 sdhc2_opp_table: opp-table { 2829 compatible = "operating-points-v2"; 2830 2831 opp-100000000 { 2832 opp-hz = /bits/ 64 <100000000>; 2833 required-opps = <&rpmhpd_opp_low_svs>; 2834 opp-peak-kBps = <1800000 400000>; 2835 opp-avg-kBps = <100000 0>; 2836 }; 2837 2838 opp-202000000 { 2839 opp-hz = /bits/ 64 <202000000>; 2840 required-opps = <&rpmhpd_opp_nom>; 2841 opp-peak-kBps = <5400000 1600000>; 2842 opp-avg-kBps = <200000 0>; 2843 }; 2844 }; 2845 2846 }; 2847 2848 usb_1_hsphy: phy@88e3000 { 2849 compatible = "qcom,sc7280-usb-hs-phy", 2850 "qcom,usb-snps-hs-7nm-phy"; 2851 reg = <0 0x088e3000 0 0x400>; 2852 status = "disabled"; 2853 #phy-cells = <0>; 2854 2855 clocks = <&rpmhcc RPMH_CXO_CLK>; 2856 clock-names = "ref"; 2857 2858 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2859 }; 2860 2861 usb_2_hsphy: phy@88e4000 { 2862 compatible = "qcom,sc7280-usb-hs-phy", 2863 "qcom,usb-snps-hs-7nm-phy"; 2864 reg = <0 0x088e4000 0 0x400>; 2865 status = "disabled"; 2866 #phy-cells = <0>; 2867 2868 clocks = <&rpmhcc RPMH_CXO_CLK>; 2869 clock-names = "ref"; 2870 2871 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2872 }; 2873 2874 usb_1_qmpphy: phy-wrapper@88e9000 { 2875 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 2876 "qcom,sm8250-qmp-usb3-dp-phy"; 2877 reg = <0 0x088e9000 0 0x200>, 2878 <0 0x088e8000 0 0x40>, 2879 <0 0x088ea000 0 0x200>; 2880 status = "disabled"; 2881 #address-cells = <2>; 2882 #size-cells = <2>; 2883 ranges; 2884 2885 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2886 <&rpmhcc RPMH_CXO_CLK>, 2887 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2888 clock-names = "aux", "ref_clk_src", "com_aux"; 2889 2890 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2891 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2892 reset-names = "phy", "common"; 2893 2894 usb_1_ssphy: usb3-phy@88e9200 { 2895 reg = <0 0x088e9200 0 0x200>, 2896 <0 0x088e9400 0 0x200>, 2897 <0 0x088e9c00 0 0x400>, 2898 <0 0x088e9600 0 0x200>, 2899 <0 0x088e9800 0 0x200>, 2900 <0 0x088e9a00 0 0x100>; 2901 #clock-cells = <0>; 2902 #phy-cells = <0>; 2903 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2904 clock-names = "pipe0"; 2905 clock-output-names = "usb3_phy_pipe_clk_src"; 2906 }; 2907 2908 dp_phy: dp-phy@88ea200 { 2909 reg = <0 0x088ea200 0 0x200>, 2910 <0 0x088ea400 0 0x200>, 2911 <0 0x088eaa00 0 0x200>, 2912 <0 0x088ea600 0 0x200>, 2913 <0 0x088ea800 0 0x200>; 2914 #phy-cells = <0>; 2915 #clock-cells = <1>; 2916 }; 2917 }; 2918 2919 usb_2: usb@8cf8800 { 2920 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2921 reg = <0 0x08cf8800 0 0x400>; 2922 status = "disabled"; 2923 #address-cells = <2>; 2924 #size-cells = <2>; 2925 ranges; 2926 dma-ranges; 2927 2928 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2929 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2930 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2931 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2932 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 2933 clock-names = "cfg_noc", "core", "iface","mock_utmi", 2934 "sleep"; 2935 2936 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2937 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2938 assigned-clock-rates = <19200000>, <200000000>; 2939 2940 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2941 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 2942 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 2943 interrupt-names = "hs_phy_irq", 2944 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2945 2946 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 2947 2948 resets = <&gcc GCC_USB30_SEC_BCR>; 2949 2950 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 2951 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 2952 interconnect-names = "usb-ddr", "apps-usb"; 2953 2954 usb_2_dwc3: usb@8c00000 { 2955 compatible = "snps,dwc3"; 2956 reg = <0 0x08c00000 0 0xe000>; 2957 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2958 iommus = <&apps_smmu 0xa0 0x0>; 2959 snps,dis_u2_susphy_quirk; 2960 snps,dis_enblslpm_quirk; 2961 phys = <&usb_2_hsphy>; 2962 phy-names = "usb2-phy"; 2963 maximum-speed = "high-speed"; 2964 }; 2965 }; 2966 2967 qspi: spi@88dc000 { 2968 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 2969 reg = <0 0x088dc000 0 0x1000>; 2970 #address-cells = <1>; 2971 #size-cells = <0>; 2972 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2973 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2974 <&gcc GCC_QSPI_CORE_CLK>; 2975 clock-names = "iface", "core"; 2976 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2977 &cnoc2 SLAVE_QSPI_0 0>; 2978 interconnect-names = "qspi-config"; 2979 power-domains = <&rpmhpd SC7280_CX>; 2980 operating-points-v2 = <&qspi_opp_table>; 2981 status = "disabled"; 2982 }; 2983 2984 remoteproc_wpss: remoteproc@8a00000 { 2985 compatible = "qcom,sc7280-wpss-pil"; 2986 reg = <0 0x08a00000 0 0x10000>; 2987 2988 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 2989 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2990 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2991 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2992 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2993 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2994 interrupt-names = "wdog", "fatal", "ready", "handover", 2995 "stop-ack", "shutdown-ack"; 2996 2997 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 2998 <&gcc GCC_WPSS_AHB_CLK>, 2999 <&gcc GCC_WPSS_RSCP_CLK>, 3000 <&rpmhcc RPMH_CXO_CLK>; 3001 clock-names = "ahb_bdg", "ahb", 3002 "rscp", "xo"; 3003 3004 power-domains = <&rpmhpd SC7280_CX>, 3005 <&rpmhpd SC7280_MX>; 3006 power-domain-names = "cx", "mx"; 3007 3008 memory-region = <&wpss_mem>; 3009 3010 qcom,qmp = <&aoss_qmp>; 3011 3012 qcom,smem-states = <&wpss_smp2p_out 0>; 3013 qcom,smem-state-names = "stop"; 3014 3015 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3016 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3017 reset-names = "restart", "pdc_sync"; 3018 3019 qcom,halt-regs = <&tcsr_mutex 0x37000>; 3020 3021 status = "disabled"; 3022 3023 glink-edge { 3024 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3025 IPCC_MPROC_SIGNAL_GLINK_QMP 3026 IRQ_TYPE_EDGE_RISING>; 3027 mboxes = <&ipcc IPCC_CLIENT_WPSS 3028 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3029 3030 label = "wpss"; 3031 qcom,remote-pid = <13>; 3032 }; 3033 }; 3034 3035 dc_noc: interconnect@90e0000 { 3036 reg = <0 0x090e0000 0 0x5080>; 3037 compatible = "qcom,sc7280-dc-noc"; 3038 #interconnect-cells = <2>; 3039 qcom,bcm-voters = <&apps_bcm_voter>; 3040 }; 3041 3042 gem_noc: interconnect@9100000 { 3043 reg = <0 0x9100000 0 0xe2200>; 3044 compatible = "qcom,sc7280-gem-noc"; 3045 #interconnect-cells = <2>; 3046 qcom,bcm-voters = <&apps_bcm_voter>; 3047 }; 3048 3049 system-cache-controller@9200000 { 3050 compatible = "qcom,sc7280-llcc"; 3051 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 3052 reg-names = "llcc_base", "llcc_broadcast_base"; 3053 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3054 }; 3055 3056 nsp_noc: interconnect@a0c0000 { 3057 reg = <0 0x0a0c0000 0 0x10000>; 3058 compatible = "qcom,sc7280-nsp-noc"; 3059 #interconnect-cells = <2>; 3060 qcom,bcm-voters = <&apps_bcm_voter>; 3061 }; 3062 3063 usb_1: usb@a6f8800 { 3064 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3065 reg = <0 0x0a6f8800 0 0x400>; 3066 status = "disabled"; 3067 #address-cells = <2>; 3068 #size-cells = <2>; 3069 ranges; 3070 dma-ranges; 3071 3072 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3073 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3074 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3075 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3076 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 3077 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3078 "sleep"; 3079 3080 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3081 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3082 assigned-clock-rates = <19200000>, <200000000>; 3083 3084 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3085 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3086 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3087 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3088 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 3089 "dm_hs_phy_irq", "ss_phy_irq"; 3090 3091 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3092 3093 resets = <&gcc GCC_USB30_PRIM_BCR>; 3094 3095 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3096 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3097 interconnect-names = "usb-ddr", "apps-usb"; 3098 3099 usb_1_dwc3: usb@a600000 { 3100 compatible = "snps,dwc3"; 3101 reg = <0 0x0a600000 0 0xe000>; 3102 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3103 iommus = <&apps_smmu 0xe0 0x0>; 3104 snps,dis_u2_susphy_quirk; 3105 snps,dis_enblslpm_quirk; 3106 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3107 phy-names = "usb2-phy", "usb3-phy"; 3108 maximum-speed = "super-speed"; 3109 }; 3110 }; 3111 3112 venus: video-codec@aa00000 { 3113 compatible = "qcom,sc7280-venus"; 3114 reg = <0 0x0aa00000 0 0xd0600>; 3115 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3116 3117 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3118 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3119 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3120 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3121 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3122 clock-names = "core", "bus", "iface", 3123 "vcodec_core", "vcodec_bus"; 3124 3125 power-domains = <&videocc MVSC_GDSC>, 3126 <&videocc MVS0_GDSC>, 3127 <&rpmhpd SC7280_CX>; 3128 power-domain-names = "venus", "vcodec0", "cx"; 3129 operating-points-v2 = <&venus_opp_table>; 3130 3131 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3132 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3133 interconnect-names = "cpu-cfg", "video-mem"; 3134 3135 iommus = <&apps_smmu 0x2180 0x20>, 3136 <&apps_smmu 0x2184 0x20>; 3137 memory-region = <&video_mem>; 3138 3139 video-decoder { 3140 compatible = "venus-decoder"; 3141 }; 3142 3143 video-encoder { 3144 compatible = "venus-encoder"; 3145 }; 3146 3147 video-firmware { 3148 iommus = <&apps_smmu 0x21a2 0x0>; 3149 }; 3150 3151 venus_opp_table: venus-opp-table { 3152 compatible = "operating-points-v2"; 3153 3154 opp-133330000 { 3155 opp-hz = /bits/ 64 <133330000>; 3156 required-opps = <&rpmhpd_opp_low_svs>; 3157 }; 3158 3159 opp-240000000 { 3160 opp-hz = /bits/ 64 <240000000>; 3161 required-opps = <&rpmhpd_opp_svs>; 3162 }; 3163 3164 opp-335000000 { 3165 opp-hz = /bits/ 64 <335000000>; 3166 required-opps = <&rpmhpd_opp_svs_l1>; 3167 }; 3168 3169 opp-424000000 { 3170 opp-hz = /bits/ 64 <424000000>; 3171 required-opps = <&rpmhpd_opp_nom>; 3172 }; 3173 3174 opp-460000048 { 3175 opp-hz = /bits/ 64 <460000048>; 3176 required-opps = <&rpmhpd_opp_turbo>; 3177 }; 3178 }; 3179 3180 }; 3181 3182 videocc: clock-controller@aaf0000 { 3183 compatible = "qcom,sc7280-videocc"; 3184 reg = <0 0xaaf0000 0 0x10000>; 3185 clocks = <&rpmhcc RPMH_CXO_CLK>, 3186 <&rpmhcc RPMH_CXO_CLK_A>; 3187 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3188 #clock-cells = <1>; 3189 #reset-cells = <1>; 3190 #power-domain-cells = <1>; 3191 }; 3192 3193 camcc: clock-controller@ad00000 { 3194 compatible = "qcom,sc7280-camcc"; 3195 reg = <0 0x0ad00000 0 0x10000>; 3196 clocks = <&rpmhcc RPMH_CXO_CLK>, 3197 <&rpmhcc RPMH_CXO_CLK_A>, 3198 <&sleep_clk>; 3199 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3200 #clock-cells = <1>; 3201 #reset-cells = <1>; 3202 #power-domain-cells = <1>; 3203 }; 3204 3205 dispcc: clock-controller@af00000 { 3206 compatible = "qcom,sc7280-dispcc"; 3207 reg = <0 0xaf00000 0 0x20000>; 3208 clocks = <&rpmhcc RPMH_CXO_CLK>, 3209 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3210 <&mdss_dsi_phy 0>, 3211 <&mdss_dsi_phy 1>, 3212 <&dp_phy 0>, 3213 <&dp_phy 1>, 3214 <&mdss_edp_phy 0>, 3215 <&mdss_edp_phy 1>; 3216 clock-names = "bi_tcxo", 3217 "gcc_disp_gpll0_clk", 3218 "dsi0_phy_pll_out_byteclk", 3219 "dsi0_phy_pll_out_dsiclk", 3220 "dp_phy_pll_link_clk", 3221 "dp_phy_pll_vco_div_clk", 3222 "edp_phy_pll_link_clk", 3223 "edp_phy_pll_vco_div_clk"; 3224 #clock-cells = <1>; 3225 #reset-cells = <1>; 3226 #power-domain-cells = <1>; 3227 }; 3228 3229 mdss: display-subsystem@ae00000 { 3230 compatible = "qcom,sc7280-mdss"; 3231 reg = <0 0x0ae00000 0 0x1000>; 3232 reg-names = "mdss"; 3233 3234 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3235 3236 clocks = <&gcc GCC_DISP_AHB_CLK>, 3237 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3238 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3239 clock-names = "iface", 3240 "ahb", 3241 "core"; 3242 3243 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 3244 assigned-clock-rates = <300000000>; 3245 3246 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3247 interrupt-controller; 3248 #interrupt-cells = <1>; 3249 3250 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3251 interconnect-names = "mdp0-mem"; 3252 3253 iommus = <&apps_smmu 0x900 0x402>; 3254 3255 #address-cells = <2>; 3256 #size-cells = <2>; 3257 ranges; 3258 3259 status = "disabled"; 3260 3261 mdss_mdp: display-controller@ae01000 { 3262 compatible = "qcom,sc7280-dpu"; 3263 reg = <0 0x0ae01000 0 0x8f030>, 3264 <0 0x0aeb0000 0 0x2008>; 3265 reg-names = "mdp", "vbif"; 3266 3267 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3268 <&gcc GCC_DISP_SF_AXI_CLK>, 3269 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3270 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3271 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3272 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3273 clock-names = "bus", 3274 "nrt_bus", 3275 "iface", 3276 "lut", 3277 "core", 3278 "vsync"; 3279 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 3280 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3281 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3282 assigned-clock-rates = <300000000>, 3283 <19200000>, 3284 <19200000>; 3285 operating-points-v2 = <&mdp_opp_table>; 3286 power-domains = <&rpmhpd SC7280_CX>; 3287 3288 interrupt-parent = <&mdss>; 3289 interrupts = <0>; 3290 3291 status = "disabled"; 3292 3293 ports { 3294 #address-cells = <1>; 3295 #size-cells = <0>; 3296 3297 port@0 { 3298 reg = <0>; 3299 dpu_intf1_out: endpoint { 3300 remote-endpoint = <&dsi0_in>; 3301 }; 3302 }; 3303 3304 port@1 { 3305 reg = <1>; 3306 dpu_intf5_out: endpoint { 3307 remote-endpoint = <&edp_in>; 3308 }; 3309 }; 3310 3311 port@2 { 3312 reg = <2>; 3313 dpu_intf0_out: endpoint { 3314 remote-endpoint = <&dp_in>; 3315 }; 3316 }; 3317 }; 3318 3319 mdp_opp_table: opp-table { 3320 compatible = "operating-points-v2"; 3321 3322 opp-200000000 { 3323 opp-hz = /bits/ 64 <200000000>; 3324 required-opps = <&rpmhpd_opp_low_svs>; 3325 }; 3326 3327 opp-300000000 { 3328 opp-hz = /bits/ 64 <300000000>; 3329 required-opps = <&rpmhpd_opp_svs>; 3330 }; 3331 3332 opp-380000000 { 3333 opp-hz = /bits/ 64 <380000000>; 3334 required-opps = <&rpmhpd_opp_svs_l1>; 3335 }; 3336 3337 opp-506666667 { 3338 opp-hz = /bits/ 64 <506666667>; 3339 required-opps = <&rpmhpd_opp_nom>; 3340 }; 3341 }; 3342 }; 3343 3344 mdss_dsi: dsi@ae94000 { 3345 compatible = "qcom,mdss-dsi-ctrl"; 3346 reg = <0 0x0ae94000 0 0x400>; 3347 reg-names = "dsi_ctrl"; 3348 3349 interrupt-parent = <&mdss>; 3350 interrupts = <4>; 3351 3352 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3353 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3354 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3355 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3356 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3357 <&gcc GCC_DISP_HF_AXI_CLK>; 3358 clock-names = "byte", 3359 "byte_intf", 3360 "pixel", 3361 "core", 3362 "iface", 3363 "bus"; 3364 3365 operating-points-v2 = <&dsi_opp_table>; 3366 power-domains = <&rpmhpd SC7280_CX>; 3367 3368 phys = <&mdss_dsi_phy>; 3369 phy-names = "dsi"; 3370 3371 #address-cells = <1>; 3372 #size-cells = <0>; 3373 3374 status = "disabled"; 3375 3376 ports { 3377 #address-cells = <1>; 3378 #size-cells = <0>; 3379 3380 port@0 { 3381 reg = <0>; 3382 dsi0_in: endpoint { 3383 remote-endpoint = <&dpu_intf1_out>; 3384 }; 3385 }; 3386 3387 port@1 { 3388 reg = <1>; 3389 dsi0_out: endpoint { 3390 }; 3391 }; 3392 }; 3393 3394 dsi_opp_table: opp-table { 3395 compatible = "operating-points-v2"; 3396 3397 opp-187500000 { 3398 opp-hz = /bits/ 64 <187500000>; 3399 required-opps = <&rpmhpd_opp_low_svs>; 3400 }; 3401 3402 opp-300000000 { 3403 opp-hz = /bits/ 64 <300000000>; 3404 required-opps = <&rpmhpd_opp_svs>; 3405 }; 3406 3407 opp-358000000 { 3408 opp-hz = /bits/ 64 <358000000>; 3409 required-opps = <&rpmhpd_opp_svs_l1>; 3410 }; 3411 }; 3412 }; 3413 3414 mdss_dsi_phy: phy@ae94400 { 3415 compatible = "qcom,sc7280-dsi-phy-7nm"; 3416 reg = <0 0x0ae94400 0 0x200>, 3417 <0 0x0ae94600 0 0x280>, 3418 <0 0x0ae94900 0 0x280>; 3419 reg-names = "dsi_phy", 3420 "dsi_phy_lane", 3421 "dsi_pll"; 3422 3423 #clock-cells = <1>; 3424 #phy-cells = <0>; 3425 3426 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3427 <&rpmhcc RPMH_CXO_CLK>; 3428 clock-names = "iface", "ref"; 3429 3430 status = "disabled"; 3431 }; 3432 3433 mdss_edp: edp@aea0000 { 3434 compatible = "qcom,sc7280-edp"; 3435 pinctrl-names = "default"; 3436 pinctrl-0 = <&edp_hot_plug_det>; 3437 3438 reg = <0 0xaea0000 0 0x200>, 3439 <0 0xaea0200 0 0x200>, 3440 <0 0xaea0400 0 0xc00>, 3441 <0 0xaea1000 0 0x400>; 3442 3443 interrupt-parent = <&mdss>; 3444 interrupts = <14>; 3445 3446 clocks = <&rpmhcc RPMH_CXO_CLK>, 3447 <&gcc GCC_EDP_CLKREF_EN>, 3448 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3449 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3450 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 3451 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 3452 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 3453 clock-names = "core_xo", 3454 "core_ref", 3455 "core_iface", 3456 "core_aux", 3457 "ctrl_link", 3458 "ctrl_link_iface", 3459 "stream_pixel"; 3460 #clock-cells = <1>; 3461 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 3462 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 3463 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 3464 3465 phys = <&mdss_edp_phy>; 3466 phy-names = "dp"; 3467 3468 operating-points-v2 = <&edp_opp_table>; 3469 power-domains = <&rpmhpd SC7280_CX>; 3470 3471 #address-cells = <1>; 3472 #size-cells = <0>; 3473 3474 status = "disabled"; 3475 3476 ports { 3477 #address-cells = <1>; 3478 #size-cells = <0>; 3479 3480 port@0 { 3481 reg = <0>; 3482 edp_in: endpoint { 3483 remote-endpoint = <&dpu_intf5_out>; 3484 }; 3485 }; 3486 3487 port@1 { 3488 reg = <1>; 3489 mdss_edp_out: endpoint { }; 3490 }; 3491 }; 3492 3493 edp_opp_table: opp-table { 3494 compatible = "operating-points-v2"; 3495 3496 opp-160000000 { 3497 opp-hz = /bits/ 64 <160000000>; 3498 required-opps = <&rpmhpd_opp_low_svs>; 3499 }; 3500 3501 opp-270000000 { 3502 opp-hz = /bits/ 64 <270000000>; 3503 required-opps = <&rpmhpd_opp_svs>; 3504 }; 3505 3506 opp-540000000 { 3507 opp-hz = /bits/ 64 <540000000>; 3508 required-opps = <&rpmhpd_opp_nom>; 3509 }; 3510 3511 opp-810000000 { 3512 opp-hz = /bits/ 64 <810000000>; 3513 required-opps = <&rpmhpd_opp_nom>; 3514 }; 3515 }; 3516 }; 3517 3518 mdss_edp_phy: phy@aec2a00 { 3519 compatible = "qcom,sc7280-edp-phy"; 3520 3521 reg = <0 0xaec2a00 0 0x19c>, 3522 <0 0xaec2200 0 0xa0>, 3523 <0 0xaec2600 0 0xa0>, 3524 <0 0xaec2000 0 0x1c0>; 3525 3526 clocks = <&rpmhcc RPMH_CXO_CLK>, 3527 <&gcc GCC_EDP_CLKREF_EN>; 3528 clock-names = "aux", 3529 "cfg_ahb"; 3530 3531 #clock-cells = <1>; 3532 #phy-cells = <0>; 3533 3534 status = "disabled"; 3535 }; 3536 3537 mdss_dp: displayport-controller@ae90000 { 3538 compatible = "qcom,sc7280-dp"; 3539 3540 reg = <0 0x0ae90000 0 0x1400>; 3541 3542 interrupt-parent = <&mdss>; 3543 interrupts = <12>; 3544 3545 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3546 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3547 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3548 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3549 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3550 clock-names = "core_iface", 3551 "core_aux", 3552 "ctrl_link", 3553 "ctrl_link_iface", 3554 "stream_pixel"; 3555 #clock-cells = <1>; 3556 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3557 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3558 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 3559 phys = <&dp_phy>; 3560 phy-names = "dp"; 3561 3562 operating-points-v2 = <&dp_opp_table>; 3563 power-domains = <&rpmhpd SC7280_CX>; 3564 3565 #sound-dai-cells = <0>; 3566 3567 status = "disabled"; 3568 3569 ports { 3570 #address-cells = <1>; 3571 #size-cells = <0>; 3572 3573 port@0 { 3574 reg = <0>; 3575 dp_in: endpoint { 3576 remote-endpoint = <&dpu_intf0_out>; 3577 }; 3578 }; 3579 3580 port@1 { 3581 reg = <1>; 3582 dp_out: endpoint { }; 3583 }; 3584 }; 3585 3586 dp_opp_table: opp-table { 3587 compatible = "operating-points-v2"; 3588 3589 opp-160000000 { 3590 opp-hz = /bits/ 64 <160000000>; 3591 required-opps = <&rpmhpd_opp_low_svs>; 3592 }; 3593 3594 opp-270000000 { 3595 opp-hz = /bits/ 64 <270000000>; 3596 required-opps = <&rpmhpd_opp_svs>; 3597 }; 3598 3599 opp-540000000 { 3600 opp-hz = /bits/ 64 <540000000>; 3601 required-opps = <&rpmhpd_opp_svs_l1>; 3602 }; 3603 3604 opp-810000000 { 3605 opp-hz = /bits/ 64 <810000000>; 3606 required-opps = <&rpmhpd_opp_nom>; 3607 }; 3608 }; 3609 }; 3610 }; 3611 3612 pdc: interrupt-controller@b220000 { 3613 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 3614 reg = <0 0x0b220000 0 0x30000>; 3615 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 3616 <55 306 4>, <59 312 3>, <62 374 2>, 3617 <64 434 2>, <66 438 3>, <69 86 1>, 3618 <70 520 54>, <124 609 31>, <155 63 1>, 3619 <156 716 12>; 3620 #interrupt-cells = <2>; 3621 interrupt-parent = <&intc>; 3622 interrupt-controller; 3623 }; 3624 3625 pdc_reset: reset-controller@b5e0000 { 3626 compatible = "qcom,sc7280-pdc-global"; 3627 reg = <0 0x0b5e0000 0 0x20000>; 3628 #reset-cells = <1>; 3629 }; 3630 3631 tsens0: thermal-sensor@c263000 { 3632 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3633 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3634 <0 0x0c222000 0 0x1ff>; /* SROT */ 3635 #qcom,sensors = <15>; 3636 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3637 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3638 interrupt-names = "uplow","critical"; 3639 #thermal-sensor-cells = <1>; 3640 }; 3641 3642 tsens1: thermal-sensor@c265000 { 3643 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3644 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3645 <0 0x0c223000 0 0x1ff>; /* SROT */ 3646 #qcom,sensors = <12>; 3647 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3648 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3649 interrupt-names = "uplow","critical"; 3650 #thermal-sensor-cells = <1>; 3651 }; 3652 3653 aoss_reset: reset-controller@c2a0000 { 3654 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 3655 reg = <0 0x0c2a0000 0 0x31000>; 3656 #reset-cells = <1>; 3657 }; 3658 3659 aoss_qmp: power-controller@c300000 { 3660 compatible = "qcom,sc7280-aoss-qmp"; 3661 reg = <0 0x0c300000 0 0x400>; 3662 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3663 IPCC_MPROC_SIGNAL_GLINK_QMP 3664 IRQ_TYPE_EDGE_RISING>; 3665 mboxes = <&ipcc IPCC_CLIENT_AOP 3666 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3667 3668 #clock-cells = <0>; 3669 }; 3670 3671 sram@c3f0000 { 3672 compatible = "qcom,rpmh-stats"; 3673 reg = <0 0x0c3f0000 0 0x400>; 3674 }; 3675 3676 spmi_bus: spmi@c440000 { 3677 compatible = "qcom,spmi-pmic-arb"; 3678 reg = <0 0x0c440000 0 0x1100>, 3679 <0 0x0c600000 0 0x2000000>, 3680 <0 0x0e600000 0 0x100000>, 3681 <0 0x0e700000 0 0xa0000>, 3682 <0 0x0c40a000 0 0x26000>; 3683 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3684 interrupt-names = "periph_irq"; 3685 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3686 qcom,ee = <0>; 3687 qcom,channel = <0>; 3688 #address-cells = <1>; 3689 #size-cells = <1>; 3690 interrupt-controller; 3691 #interrupt-cells = <4>; 3692 }; 3693 3694 tlmm: pinctrl@f100000 { 3695 compatible = "qcom,sc7280-pinctrl"; 3696 reg = <0 0x0f100000 0 0x300000>; 3697 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3698 gpio-controller; 3699 #gpio-cells = <2>; 3700 interrupt-controller; 3701 #interrupt-cells = <2>; 3702 gpio-ranges = <&tlmm 0 0 175>; 3703 wakeup-parent = <&pdc>; 3704 3705 dp_hot_plug_det: dp-hot-plug-det { 3706 pins = "gpio47"; 3707 function = "dp_hot"; 3708 }; 3709 3710 edp_hot_plug_det: edp-hot-plug-det { 3711 pins = "gpio60"; 3712 function = "edp_hot"; 3713 }; 3714 3715 pcie1_clkreq_n: pcie1-clkreq-n { 3716 pins = "gpio79"; 3717 function = "pcie1_clkreqn"; 3718 }; 3719 3720 qspi_clk: qspi-clk { 3721 pins = "gpio14"; 3722 function = "qspi_clk"; 3723 }; 3724 3725 qspi_cs0: qspi-cs0 { 3726 pins = "gpio15"; 3727 function = "qspi_cs"; 3728 }; 3729 3730 qspi_cs1: qspi-cs1 { 3731 pins = "gpio19"; 3732 function = "qspi_cs"; 3733 }; 3734 3735 qspi_data01: qspi-data01 { 3736 pins = "gpio12", "gpio13"; 3737 function = "qspi_data"; 3738 }; 3739 3740 qspi_data12: qspi-data12 { 3741 pins = "gpio16", "gpio17"; 3742 function = "qspi_data"; 3743 }; 3744 3745 qup_i2c0_data_clk: qup-i2c0-data-clk { 3746 pins = "gpio0", "gpio1"; 3747 function = "qup00"; 3748 }; 3749 3750 qup_i2c1_data_clk: qup-i2c1-data-clk { 3751 pins = "gpio4", "gpio5"; 3752 function = "qup01"; 3753 }; 3754 3755 qup_i2c2_data_clk: qup-i2c2-data-clk { 3756 pins = "gpio8", "gpio9"; 3757 function = "qup02"; 3758 }; 3759 3760 qup_i2c3_data_clk: qup-i2c3-data-clk { 3761 pins = "gpio12", "gpio13"; 3762 function = "qup03"; 3763 }; 3764 3765 qup_i2c4_data_clk: qup-i2c4-data-clk { 3766 pins = "gpio16", "gpio17"; 3767 function = "qup04"; 3768 }; 3769 3770 qup_i2c5_data_clk: qup-i2c5-data-clk { 3771 pins = "gpio20", "gpio21"; 3772 function = "qup05"; 3773 }; 3774 3775 qup_i2c6_data_clk: qup-i2c6-data-clk { 3776 pins = "gpio24", "gpio25"; 3777 function = "qup06"; 3778 }; 3779 3780 qup_i2c7_data_clk: qup-i2c7-data-clk { 3781 pins = "gpio28", "gpio29"; 3782 function = "qup07"; 3783 }; 3784 3785 qup_i2c8_data_clk: qup-i2c8-data-clk { 3786 pins = "gpio32", "gpio33"; 3787 function = "qup10"; 3788 }; 3789 3790 qup_i2c9_data_clk: qup-i2c9-data-clk { 3791 pins = "gpio36", "gpio37"; 3792 function = "qup11"; 3793 }; 3794 3795 qup_i2c10_data_clk: qup-i2c10-data-clk { 3796 pins = "gpio40", "gpio41"; 3797 function = "qup12"; 3798 }; 3799 3800 qup_i2c11_data_clk: qup-i2c11-data-clk { 3801 pins = "gpio44", "gpio45"; 3802 function = "qup13"; 3803 }; 3804 3805 qup_i2c12_data_clk: qup-i2c12-data-clk { 3806 pins = "gpio48", "gpio49"; 3807 function = "qup14"; 3808 }; 3809 3810 qup_i2c13_data_clk: qup-i2c13-data-clk { 3811 pins = "gpio52", "gpio53"; 3812 function = "qup15"; 3813 }; 3814 3815 qup_i2c14_data_clk: qup-i2c14-data-clk { 3816 pins = "gpio56", "gpio57"; 3817 function = "qup16"; 3818 }; 3819 3820 qup_i2c15_data_clk: qup-i2c15-data-clk { 3821 pins = "gpio60", "gpio61"; 3822 function = "qup17"; 3823 }; 3824 3825 qup_spi0_data_clk: qup-spi0-data-clk { 3826 pins = "gpio0", "gpio1", "gpio2"; 3827 function = "qup00"; 3828 }; 3829 3830 qup_spi0_cs: qup-spi0-cs { 3831 pins = "gpio3"; 3832 function = "qup00"; 3833 }; 3834 3835 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 3836 pins = "gpio3"; 3837 function = "gpio"; 3838 }; 3839 3840 qup_spi1_data_clk: qup-spi1-data-clk { 3841 pins = "gpio4", "gpio5", "gpio6"; 3842 function = "qup01"; 3843 }; 3844 3845 qup_spi1_cs: qup-spi1-cs { 3846 pins = "gpio7"; 3847 function = "qup01"; 3848 }; 3849 3850 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 3851 pins = "gpio7"; 3852 function = "gpio"; 3853 }; 3854 3855 qup_spi2_data_clk: qup-spi2-data-clk { 3856 pins = "gpio8", "gpio9", "gpio10"; 3857 function = "qup02"; 3858 }; 3859 3860 qup_spi2_cs: qup-spi2-cs { 3861 pins = "gpio11"; 3862 function = "qup02"; 3863 }; 3864 3865 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 3866 pins = "gpio11"; 3867 function = "gpio"; 3868 }; 3869 3870 qup_spi3_data_clk: qup-spi3-data-clk { 3871 pins = "gpio12", "gpio13", "gpio14"; 3872 function = "qup03"; 3873 }; 3874 3875 qup_spi3_cs: qup-spi3-cs { 3876 pins = "gpio15"; 3877 function = "qup03"; 3878 }; 3879 3880 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 3881 pins = "gpio15"; 3882 function = "gpio"; 3883 }; 3884 3885 qup_spi4_data_clk: qup-spi4-data-clk { 3886 pins = "gpio16", "gpio17", "gpio18"; 3887 function = "qup04"; 3888 }; 3889 3890 qup_spi4_cs: qup-spi4-cs { 3891 pins = "gpio19"; 3892 function = "qup04"; 3893 }; 3894 3895 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 3896 pins = "gpio19"; 3897 function = "gpio"; 3898 }; 3899 3900 qup_spi5_data_clk: qup-spi5-data-clk { 3901 pins = "gpio20", "gpio21", "gpio22"; 3902 function = "qup05"; 3903 }; 3904 3905 qup_spi5_cs: qup-spi5-cs { 3906 pins = "gpio23"; 3907 function = "qup05"; 3908 }; 3909 3910 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 3911 pins = "gpio23"; 3912 function = "gpio"; 3913 }; 3914 3915 qup_spi6_data_clk: qup-spi6-data-clk { 3916 pins = "gpio24", "gpio25", "gpio26"; 3917 function = "qup06"; 3918 }; 3919 3920 qup_spi6_cs: qup-spi6-cs { 3921 pins = "gpio27"; 3922 function = "qup06"; 3923 }; 3924 3925 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3926 pins = "gpio27"; 3927 function = "gpio"; 3928 }; 3929 3930 qup_spi7_data_clk: qup-spi7-data-clk { 3931 pins = "gpio28", "gpio29", "gpio30"; 3932 function = "qup07"; 3933 }; 3934 3935 qup_spi7_cs: qup-spi7-cs { 3936 pins = "gpio31"; 3937 function = "qup07"; 3938 }; 3939 3940 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3941 pins = "gpio31"; 3942 function = "gpio"; 3943 }; 3944 3945 qup_spi8_data_clk: qup-spi8-data-clk { 3946 pins = "gpio32", "gpio33", "gpio34"; 3947 function = "qup10"; 3948 }; 3949 3950 qup_spi8_cs: qup-spi8-cs { 3951 pins = "gpio35"; 3952 function = "qup10"; 3953 }; 3954 3955 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 3956 pins = "gpio35"; 3957 function = "gpio"; 3958 }; 3959 3960 qup_spi9_data_clk: qup-spi9-data-clk { 3961 pins = "gpio36", "gpio37", "gpio38"; 3962 function = "qup11"; 3963 }; 3964 3965 qup_spi9_cs: qup-spi9-cs { 3966 pins = "gpio39"; 3967 function = "qup11"; 3968 }; 3969 3970 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 3971 pins = "gpio39"; 3972 function = "gpio"; 3973 }; 3974 3975 qup_spi10_data_clk: qup-spi10-data-clk { 3976 pins = "gpio40", "gpio41", "gpio42"; 3977 function = "qup12"; 3978 }; 3979 3980 qup_spi10_cs: qup-spi10-cs { 3981 pins = "gpio43"; 3982 function = "qup12"; 3983 }; 3984 3985 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 3986 pins = "gpio43"; 3987 function = "gpio"; 3988 }; 3989 3990 qup_spi11_data_clk: qup-spi11-data-clk { 3991 pins = "gpio44", "gpio45", "gpio46"; 3992 function = "qup13"; 3993 }; 3994 3995 qup_spi11_cs: qup-spi11-cs { 3996 pins = "gpio47"; 3997 function = "qup13"; 3998 }; 3999 4000 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 4001 pins = "gpio47"; 4002 function = "gpio"; 4003 }; 4004 4005 qup_spi12_data_clk: qup-spi12-data-clk { 4006 pins = "gpio48", "gpio49", "gpio50"; 4007 function = "qup14"; 4008 }; 4009 4010 qup_spi12_cs: qup-spi12-cs { 4011 pins = "gpio51"; 4012 function = "qup14"; 4013 }; 4014 4015 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 4016 pins = "gpio51"; 4017 function = "gpio"; 4018 }; 4019 4020 qup_spi13_data_clk: qup-spi13-data-clk { 4021 pins = "gpio52", "gpio53", "gpio54"; 4022 function = "qup15"; 4023 }; 4024 4025 qup_spi13_cs: qup-spi13-cs { 4026 pins = "gpio55"; 4027 function = "qup15"; 4028 }; 4029 4030 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 4031 pins = "gpio55"; 4032 function = "gpio"; 4033 }; 4034 4035 qup_spi14_data_clk: qup-spi14-data-clk { 4036 pins = "gpio56", "gpio57", "gpio58"; 4037 function = "qup16"; 4038 }; 4039 4040 qup_spi14_cs: qup-spi14-cs { 4041 pins = "gpio59"; 4042 function = "qup16"; 4043 }; 4044 4045 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 4046 pins = "gpio59"; 4047 function = "gpio"; 4048 }; 4049 4050 qup_spi15_data_clk: qup-spi15-data-clk { 4051 pins = "gpio60", "gpio61", "gpio62"; 4052 function = "qup17"; 4053 }; 4054 4055 qup_spi15_cs: qup-spi15-cs { 4056 pins = "gpio63"; 4057 function = "qup17"; 4058 }; 4059 4060 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 4061 pins = "gpio63"; 4062 function = "gpio"; 4063 }; 4064 4065 qup_uart0_cts: qup-uart0-cts { 4066 pins = "gpio0"; 4067 function = "qup00"; 4068 }; 4069 4070 qup_uart0_rts: qup-uart0-rts { 4071 pins = "gpio1"; 4072 function = "qup00"; 4073 }; 4074 4075 qup_uart0_tx: qup-uart0-tx { 4076 pins = "gpio2"; 4077 function = "qup00"; 4078 }; 4079 4080 qup_uart0_rx: qup-uart0-rx { 4081 pins = "gpio3"; 4082 function = "qup00"; 4083 }; 4084 4085 qup_uart1_cts: qup-uart1-cts { 4086 pins = "gpio4"; 4087 function = "qup01"; 4088 }; 4089 4090 qup_uart1_rts: qup-uart1-rts { 4091 pins = "gpio5"; 4092 function = "qup01"; 4093 }; 4094 4095 qup_uart1_tx: qup-uart1-tx { 4096 pins = "gpio6"; 4097 function = "qup01"; 4098 }; 4099 4100 qup_uart1_rx: qup-uart1-rx { 4101 pins = "gpio7"; 4102 function = "qup01"; 4103 }; 4104 4105 qup_uart2_cts: qup-uart2-cts { 4106 pins = "gpio8"; 4107 function = "qup02"; 4108 }; 4109 4110 qup_uart2_rts: qup-uart2-rts { 4111 pins = "gpio9"; 4112 function = "qup02"; 4113 }; 4114 4115 qup_uart2_tx: qup-uart2-tx { 4116 pins = "gpio10"; 4117 function = "qup02"; 4118 }; 4119 4120 qup_uart2_rx: qup-uart2-rx { 4121 pins = "gpio11"; 4122 function = "qup02"; 4123 }; 4124 4125 qup_uart3_cts: qup-uart3-cts { 4126 pins = "gpio12"; 4127 function = "qup03"; 4128 }; 4129 4130 qup_uart3_rts: qup-uart3-rts { 4131 pins = "gpio13"; 4132 function = "qup03"; 4133 }; 4134 4135 qup_uart3_tx: qup-uart3-tx { 4136 pins = "gpio14"; 4137 function = "qup03"; 4138 }; 4139 4140 qup_uart3_rx: qup-uart3-rx { 4141 pins = "gpio15"; 4142 function = "qup03"; 4143 }; 4144 4145 qup_uart4_cts: qup-uart4-cts { 4146 pins = "gpio16"; 4147 function = "qup04"; 4148 }; 4149 4150 qup_uart4_rts: qup-uart4-rts { 4151 pins = "gpio17"; 4152 function = "qup04"; 4153 }; 4154 4155 qup_uart4_tx: qup-uart4-tx { 4156 pins = "gpio18"; 4157 function = "qup04"; 4158 }; 4159 4160 qup_uart4_rx: qup-uart4-rx { 4161 pins = "gpio19"; 4162 function = "qup04"; 4163 }; 4164 4165 qup_uart5_cts: qup-uart5-cts { 4166 pins = "gpio20"; 4167 function = "qup05"; 4168 }; 4169 4170 qup_uart5_rts: qup-uart5-rts { 4171 pins = "gpio21"; 4172 function = "qup05"; 4173 }; 4174 4175 qup_uart5_tx: qup-uart5-tx { 4176 pins = "gpio22"; 4177 function = "qup05"; 4178 }; 4179 4180 qup_uart5_rx: qup-uart5-rx { 4181 pins = "gpio23"; 4182 function = "qup05"; 4183 }; 4184 4185 qup_uart6_cts: qup-uart6-cts { 4186 pins = "gpio24"; 4187 function = "qup06"; 4188 }; 4189 4190 qup_uart6_rts: qup-uart6-rts { 4191 pins = "gpio25"; 4192 function = "qup06"; 4193 }; 4194 4195 qup_uart6_tx: qup-uart6-tx { 4196 pins = "gpio26"; 4197 function = "qup06"; 4198 }; 4199 4200 qup_uart6_rx: qup-uart6-rx { 4201 pins = "gpio27"; 4202 function = "qup06"; 4203 }; 4204 4205 qup_uart7_cts: qup-uart7-cts { 4206 pins = "gpio28"; 4207 function = "qup07"; 4208 }; 4209 4210 qup_uart7_rts: qup-uart7-rts { 4211 pins = "gpio29"; 4212 function = "qup07"; 4213 }; 4214 4215 qup_uart7_tx: qup-uart7-tx { 4216 pins = "gpio30"; 4217 function = "qup07"; 4218 }; 4219 4220 qup_uart7_rx: qup-uart7-rx { 4221 pins = "gpio31"; 4222 function = "qup07"; 4223 }; 4224 4225 qup_uart8_cts: qup-uart8-cts { 4226 pins = "gpio32"; 4227 function = "qup10"; 4228 }; 4229 4230 qup_uart8_rts: qup-uart8-rts { 4231 pins = "gpio33"; 4232 function = "qup10"; 4233 }; 4234 4235 qup_uart8_tx: qup-uart8-tx { 4236 pins = "gpio34"; 4237 function = "qup10"; 4238 }; 4239 4240 qup_uart8_rx: qup-uart8-rx { 4241 pins = "gpio35"; 4242 function = "qup10"; 4243 }; 4244 4245 qup_uart9_cts: qup-uart9-cts { 4246 pins = "gpio36"; 4247 function = "qup11"; 4248 }; 4249 4250 qup_uart9_rts: qup-uart9-rts { 4251 pins = "gpio37"; 4252 function = "qup11"; 4253 }; 4254 4255 qup_uart9_tx: qup-uart9-tx { 4256 pins = "gpio38"; 4257 function = "qup11"; 4258 }; 4259 4260 qup_uart9_rx: qup-uart9-rx { 4261 pins = "gpio39"; 4262 function = "qup11"; 4263 }; 4264 4265 qup_uart10_cts: qup-uart10-cts { 4266 pins = "gpio40"; 4267 function = "qup12"; 4268 }; 4269 4270 qup_uart10_rts: qup-uart10-rts { 4271 pins = "gpio41"; 4272 function = "qup12"; 4273 }; 4274 4275 qup_uart10_tx: qup-uart10-tx { 4276 pins = "gpio42"; 4277 function = "qup12"; 4278 }; 4279 4280 qup_uart10_rx: qup-uart10-rx { 4281 pins = "gpio43"; 4282 function = "qup12"; 4283 }; 4284 4285 qup_uart11_cts: qup-uart11-cts { 4286 pins = "gpio44"; 4287 function = "qup13"; 4288 }; 4289 4290 qup_uart11_rts: qup-uart11-rts { 4291 pins = "gpio45"; 4292 function = "qup13"; 4293 }; 4294 4295 qup_uart11_tx: qup-uart11-tx { 4296 pins = "gpio46"; 4297 function = "qup13"; 4298 }; 4299 4300 qup_uart11_rx: qup-uart11-rx { 4301 pins = "gpio47"; 4302 function = "qup13"; 4303 }; 4304 4305 qup_uart12_cts: qup-uart12-cts { 4306 pins = "gpio48"; 4307 function = "qup14"; 4308 }; 4309 4310 qup_uart12_rts: qup-uart12-rts { 4311 pins = "gpio49"; 4312 function = "qup14"; 4313 }; 4314 4315 qup_uart12_tx: qup-uart12-tx { 4316 pins = "gpio50"; 4317 function = "qup14"; 4318 }; 4319 4320 qup_uart12_rx: qup-uart12-rx { 4321 pins = "gpio51"; 4322 function = "qup14"; 4323 }; 4324 4325 qup_uart13_cts: qup-uart13-cts { 4326 pins = "gpio52"; 4327 function = "qup15"; 4328 }; 4329 4330 qup_uart13_rts: qup-uart13-rts { 4331 pins = "gpio53"; 4332 function = "qup15"; 4333 }; 4334 4335 qup_uart13_tx: qup-uart13-tx { 4336 pins = "gpio54"; 4337 function = "qup15"; 4338 }; 4339 4340 qup_uart13_rx: qup-uart13-rx { 4341 pins = "gpio55"; 4342 function = "qup15"; 4343 }; 4344 4345 qup_uart14_cts: qup-uart14-cts { 4346 pins = "gpio56"; 4347 function = "qup16"; 4348 }; 4349 4350 qup_uart14_rts: qup-uart14-rts { 4351 pins = "gpio57"; 4352 function = "qup16"; 4353 }; 4354 4355 qup_uart14_tx: qup-uart14-tx { 4356 pins = "gpio58"; 4357 function = "qup16"; 4358 }; 4359 4360 qup_uart14_rx: qup-uart14-rx { 4361 pins = "gpio59"; 4362 function = "qup16"; 4363 }; 4364 4365 qup_uart15_cts: qup-uart15-cts { 4366 pins = "gpio60"; 4367 function = "qup17"; 4368 }; 4369 4370 qup_uart15_rts: qup-uart15-rts { 4371 pins = "gpio61"; 4372 function = "qup17"; 4373 }; 4374 4375 qup_uart15_tx: qup-uart15-tx { 4376 pins = "gpio62"; 4377 function = "qup17"; 4378 }; 4379 4380 qup_uart15_rx: qup-uart15-rx { 4381 pins = "gpio63"; 4382 function = "qup17"; 4383 }; 4384 4385 sdc1_clk: sdc1-clk { 4386 pins = "sdc1_clk"; 4387 }; 4388 4389 sdc1_cmd: sdc1-cmd { 4390 pins = "sdc1_cmd"; 4391 }; 4392 4393 sdc1_data: sdc1-data { 4394 pins = "sdc1_data"; 4395 }; 4396 4397 sdc1_rclk: sdc1-rclk { 4398 pins = "sdc1_rclk"; 4399 }; 4400 4401 sdc1_clk_sleep: sdc1-clk-sleep { 4402 pins = "sdc1_clk"; 4403 drive-strength = <2>; 4404 bias-bus-hold; 4405 }; 4406 4407 sdc1_cmd_sleep: sdc1-cmd-sleep { 4408 pins = "sdc1_cmd"; 4409 drive-strength = <2>; 4410 bias-bus-hold; 4411 }; 4412 4413 sdc1_data_sleep: sdc1-data-sleep { 4414 pins = "sdc1_data"; 4415 drive-strength = <2>; 4416 bias-bus-hold; 4417 }; 4418 4419 sdc1_rclk_sleep: sdc1-rclk-sleep { 4420 pins = "sdc1_rclk"; 4421 drive-strength = <2>; 4422 bias-bus-hold; 4423 }; 4424 4425 sdc2_clk: sdc2-clk { 4426 pins = "sdc2_clk"; 4427 }; 4428 4429 sdc2_cmd: sdc2-cmd { 4430 pins = "sdc2_cmd"; 4431 }; 4432 4433 sdc2_data: sdc2-data { 4434 pins = "sdc2_data"; 4435 }; 4436 4437 sdc2_clk_sleep: sdc2-clk-sleep { 4438 pins = "sdc2_clk"; 4439 drive-strength = <2>; 4440 bias-bus-hold; 4441 }; 4442 4443 sdc2_cmd_sleep: sdc2-cmd-sleep { 4444 pins = "sdc2_cmd"; 4445 drive-strength = <2>; 4446 bias-bus-hold; 4447 }; 4448 4449 sdc2_data_sleep: sdc2-data-sleep { 4450 pins = "sdc2_data"; 4451 drive-strength = <2>; 4452 bias-bus-hold; 4453 }; 4454 }; 4455 4456 imem@146a5000 { 4457 compatible = "qcom,sc7280-imem", "syscon"; 4458 reg = <0 0x146a5000 0 0x6000>; 4459 4460 #address-cells = <1>; 4461 #size-cells = <1>; 4462 4463 ranges = <0 0 0x146a5000 0x6000>; 4464 4465 pil-reloc@594c { 4466 compatible = "qcom,pil-reloc-info"; 4467 reg = <0x594c 0xc8>; 4468 }; 4469 }; 4470 4471 apps_smmu: iommu@15000000 { 4472 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 4473 reg = <0 0x15000000 0 0x100000>; 4474 #iommu-cells = <2>; 4475 #global-interrupts = <1>; 4476 dma-coherent; 4477 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4478 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 4479 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4480 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4481 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4482 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4483 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4484 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4485 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4486 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4487 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4488 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4489 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4490 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4491 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4492 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4493 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4494 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4495 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4496 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4497 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4498 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4499 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4500 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4501 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4502 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4503 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4504 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4505 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4506 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4507 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4508 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4509 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4510 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4511 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4512 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4513 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4514 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4515 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4516 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4517 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4518 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4519 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4520 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4521 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4522 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4523 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4524 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4525 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4526 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4527 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4528 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4529 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4530 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4531 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4532 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4533 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4534 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4535 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4536 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4537 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4538 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4539 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4540 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4541 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4542 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4543 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4544 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4545 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4546 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4547 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4548 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4549 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4550 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4551 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4552 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4553 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4554 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4555 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4556 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4557 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 4558 }; 4559 4560 intc: interrupt-controller@17a00000 { 4561 compatible = "arm,gic-v3"; 4562 #address-cells = <2>; 4563 #size-cells = <2>; 4564 ranges; 4565 #interrupt-cells = <3>; 4566 interrupt-controller; 4567 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 4568 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 4569 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 4570 4571 gic-its@17a40000 { 4572 compatible = "arm,gic-v3-its"; 4573 msi-controller; 4574 #msi-cells = <1>; 4575 reg = <0 0x17a40000 0 0x20000>; 4576 status = "disabled"; 4577 }; 4578 }; 4579 4580 watchdog@17c10000 { 4581 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 4582 reg = <0 0x17c10000 0 0x1000>; 4583 clocks = <&sleep_clk>; 4584 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4585 }; 4586 4587 timer@17c20000 { 4588 #address-cells = <2>; 4589 #size-cells = <2>; 4590 ranges; 4591 compatible = "arm,armv7-timer-mem"; 4592 reg = <0 0x17c20000 0 0x1000>; 4593 4594 frame@17c21000 { 4595 frame-number = <0>; 4596 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4597 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4598 reg = <0 0x17c21000 0 0x1000>, 4599 <0 0x17c22000 0 0x1000>; 4600 }; 4601 4602 frame@17c23000 { 4603 frame-number = <1>; 4604 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4605 reg = <0 0x17c23000 0 0x1000>; 4606 status = "disabled"; 4607 }; 4608 4609 frame@17c25000 { 4610 frame-number = <2>; 4611 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4612 reg = <0 0x17c25000 0 0x1000>; 4613 status = "disabled"; 4614 }; 4615 4616 frame@17c27000 { 4617 frame-number = <3>; 4618 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4619 reg = <0 0x17c27000 0 0x1000>; 4620 status = "disabled"; 4621 }; 4622 4623 frame@17c29000 { 4624 frame-number = <4>; 4625 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4626 reg = <0 0x17c29000 0 0x1000>; 4627 status = "disabled"; 4628 }; 4629 4630 frame@17c2b000 { 4631 frame-number = <5>; 4632 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4633 reg = <0 0x17c2b000 0 0x1000>; 4634 status = "disabled"; 4635 }; 4636 4637 frame@17c2d000 { 4638 frame-number = <6>; 4639 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4640 reg = <0 0x17c2d000 0 0x1000>; 4641 status = "disabled"; 4642 }; 4643 }; 4644 4645 apps_rsc: rsc@18200000 { 4646 compatible = "qcom,rpmh-rsc"; 4647 reg = <0 0x18200000 0 0x10000>, 4648 <0 0x18210000 0 0x10000>, 4649 <0 0x18220000 0 0x10000>; 4650 reg-names = "drv-0", "drv-1", "drv-2"; 4651 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4652 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4653 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4654 qcom,tcs-offset = <0xd00>; 4655 qcom,drv-id = <2>; 4656 qcom,tcs-config = <ACTIVE_TCS 2>, 4657 <SLEEP_TCS 3>, 4658 <WAKE_TCS 3>, 4659 <CONTROL_TCS 1>; 4660 4661 apps_bcm_voter: bcm-voter { 4662 compatible = "qcom,bcm-voter"; 4663 }; 4664 4665 rpmhpd: power-controller { 4666 compatible = "qcom,sc7280-rpmhpd"; 4667 #power-domain-cells = <1>; 4668 operating-points-v2 = <&rpmhpd_opp_table>; 4669 4670 rpmhpd_opp_table: opp-table { 4671 compatible = "operating-points-v2"; 4672 4673 rpmhpd_opp_ret: opp1 { 4674 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4675 }; 4676 4677 rpmhpd_opp_low_svs: opp2 { 4678 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4679 }; 4680 4681 rpmhpd_opp_svs: opp3 { 4682 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4683 }; 4684 4685 rpmhpd_opp_svs_l1: opp4 { 4686 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4687 }; 4688 4689 rpmhpd_opp_svs_l2: opp5 { 4690 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4691 }; 4692 4693 rpmhpd_opp_nom: opp6 { 4694 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4695 }; 4696 4697 rpmhpd_opp_nom_l1: opp7 { 4698 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4699 }; 4700 4701 rpmhpd_opp_turbo: opp8 { 4702 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4703 }; 4704 4705 rpmhpd_opp_turbo_l1: opp9 { 4706 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4707 }; 4708 }; 4709 }; 4710 4711 rpmhcc: clock-controller { 4712 compatible = "qcom,sc7280-rpmh-clk"; 4713 clocks = <&xo_board>; 4714 clock-names = "xo"; 4715 #clock-cells = <1>; 4716 }; 4717 }; 4718 4719 epss_l3: interconnect@18590000 { 4720 compatible = "qcom,sc7280-epss-l3"; 4721 reg = <0 0x18590000 0 0x1000>; 4722 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4723 clock-names = "xo", "alternate"; 4724 #interconnect-cells = <1>; 4725 }; 4726 4727 cpufreq_hw: cpufreq@18591000 { 4728 compatible = "qcom,cpufreq-epss"; 4729 reg = <0 0x18591000 0 0x1000>, 4730 <0 0x18592000 0 0x1000>, 4731 <0 0x18593000 0 0x1000>; 4732 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4733 clock-names = "xo", "alternate"; 4734 #freq-domain-cells = <1>; 4735 }; 4736 }; 4737 4738 thermal_zones: thermal-zones { 4739 cpu0-thermal { 4740 polling-delay-passive = <250>; 4741 polling-delay = <0>; 4742 4743 thermal-sensors = <&tsens0 1>; 4744 4745 trips { 4746 cpu0_alert0: trip-point0 { 4747 temperature = <90000>; 4748 hysteresis = <2000>; 4749 type = "passive"; 4750 }; 4751 4752 cpu0_alert1: trip-point1 { 4753 temperature = <95000>; 4754 hysteresis = <2000>; 4755 type = "passive"; 4756 }; 4757 4758 cpu0_crit: cpu-crit { 4759 temperature = <110000>; 4760 hysteresis = <0>; 4761 type = "critical"; 4762 }; 4763 }; 4764 4765 cooling-maps { 4766 map0 { 4767 trip = <&cpu0_alert0>; 4768 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4769 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4770 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4771 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4772 }; 4773 map1 { 4774 trip = <&cpu0_alert1>; 4775 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4776 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4777 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4778 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4779 }; 4780 }; 4781 }; 4782 4783 cpu1-thermal { 4784 polling-delay-passive = <250>; 4785 polling-delay = <0>; 4786 4787 thermal-sensors = <&tsens0 2>; 4788 4789 trips { 4790 cpu1_alert0: trip-point0 { 4791 temperature = <90000>; 4792 hysteresis = <2000>; 4793 type = "passive"; 4794 }; 4795 4796 cpu1_alert1: trip-point1 { 4797 temperature = <95000>; 4798 hysteresis = <2000>; 4799 type = "passive"; 4800 }; 4801 4802 cpu1_crit: cpu-crit { 4803 temperature = <110000>; 4804 hysteresis = <0>; 4805 type = "critical"; 4806 }; 4807 }; 4808 4809 cooling-maps { 4810 map0 { 4811 trip = <&cpu1_alert0>; 4812 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4813 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4814 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4815 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4816 }; 4817 map1 { 4818 trip = <&cpu1_alert1>; 4819 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4820 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4821 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4822 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4823 }; 4824 }; 4825 }; 4826 4827 cpu2-thermal { 4828 polling-delay-passive = <250>; 4829 polling-delay = <0>; 4830 4831 thermal-sensors = <&tsens0 3>; 4832 4833 trips { 4834 cpu2_alert0: trip-point0 { 4835 temperature = <90000>; 4836 hysteresis = <2000>; 4837 type = "passive"; 4838 }; 4839 4840 cpu2_alert1: trip-point1 { 4841 temperature = <95000>; 4842 hysteresis = <2000>; 4843 type = "passive"; 4844 }; 4845 4846 cpu2_crit: cpu-crit { 4847 temperature = <110000>; 4848 hysteresis = <0>; 4849 type = "critical"; 4850 }; 4851 }; 4852 4853 cooling-maps { 4854 map0 { 4855 trip = <&cpu2_alert0>; 4856 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4857 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4858 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4859 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4860 }; 4861 map1 { 4862 trip = <&cpu2_alert1>; 4863 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4864 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4865 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4866 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4867 }; 4868 }; 4869 }; 4870 4871 cpu3-thermal { 4872 polling-delay-passive = <250>; 4873 polling-delay = <0>; 4874 4875 thermal-sensors = <&tsens0 4>; 4876 4877 trips { 4878 cpu3_alert0: trip-point0 { 4879 temperature = <90000>; 4880 hysteresis = <2000>; 4881 type = "passive"; 4882 }; 4883 4884 cpu3_alert1: trip-point1 { 4885 temperature = <95000>; 4886 hysteresis = <2000>; 4887 type = "passive"; 4888 }; 4889 4890 cpu3_crit: cpu-crit { 4891 temperature = <110000>; 4892 hysteresis = <0>; 4893 type = "critical"; 4894 }; 4895 }; 4896 4897 cooling-maps { 4898 map0 { 4899 trip = <&cpu3_alert0>; 4900 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4901 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4902 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4903 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4904 }; 4905 map1 { 4906 trip = <&cpu3_alert1>; 4907 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4908 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4909 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4910 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4911 }; 4912 }; 4913 }; 4914 4915 cpu4-thermal { 4916 polling-delay-passive = <250>; 4917 polling-delay = <0>; 4918 4919 thermal-sensors = <&tsens0 7>; 4920 4921 trips { 4922 cpu4_alert0: trip-point0 { 4923 temperature = <90000>; 4924 hysteresis = <2000>; 4925 type = "passive"; 4926 }; 4927 4928 cpu4_alert1: trip-point1 { 4929 temperature = <95000>; 4930 hysteresis = <2000>; 4931 type = "passive"; 4932 }; 4933 4934 cpu4_crit: cpu-crit { 4935 temperature = <110000>; 4936 hysteresis = <0>; 4937 type = "critical"; 4938 }; 4939 }; 4940 4941 cooling-maps { 4942 map0 { 4943 trip = <&cpu4_alert0>; 4944 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4945 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4946 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4947 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4948 }; 4949 map1 { 4950 trip = <&cpu4_alert1>; 4951 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4952 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4953 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4954 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4955 }; 4956 }; 4957 }; 4958 4959 cpu5-thermal { 4960 polling-delay-passive = <250>; 4961 polling-delay = <0>; 4962 4963 thermal-sensors = <&tsens0 8>; 4964 4965 trips { 4966 cpu5_alert0: trip-point0 { 4967 temperature = <90000>; 4968 hysteresis = <2000>; 4969 type = "passive"; 4970 }; 4971 4972 cpu5_alert1: trip-point1 { 4973 temperature = <95000>; 4974 hysteresis = <2000>; 4975 type = "passive"; 4976 }; 4977 4978 cpu5_crit: cpu-crit { 4979 temperature = <110000>; 4980 hysteresis = <0>; 4981 type = "critical"; 4982 }; 4983 }; 4984 4985 cooling-maps { 4986 map0 { 4987 trip = <&cpu5_alert0>; 4988 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4989 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4990 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4991 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4992 }; 4993 map1 { 4994 trip = <&cpu5_alert1>; 4995 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4996 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4997 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4998 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4999 }; 5000 }; 5001 }; 5002 5003 cpu6-thermal { 5004 polling-delay-passive = <250>; 5005 polling-delay = <0>; 5006 5007 thermal-sensors = <&tsens0 9>; 5008 5009 trips { 5010 cpu6_alert0: trip-point0 { 5011 temperature = <90000>; 5012 hysteresis = <2000>; 5013 type = "passive"; 5014 }; 5015 5016 cpu6_alert1: trip-point1 { 5017 temperature = <95000>; 5018 hysteresis = <2000>; 5019 type = "passive"; 5020 }; 5021 5022 cpu6_crit: cpu-crit { 5023 temperature = <110000>; 5024 hysteresis = <0>; 5025 type = "critical"; 5026 }; 5027 }; 5028 5029 cooling-maps { 5030 map0 { 5031 trip = <&cpu6_alert0>; 5032 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5033 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5034 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5035 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5036 }; 5037 map1 { 5038 trip = <&cpu6_alert1>; 5039 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5040 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5041 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5042 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5043 }; 5044 }; 5045 }; 5046 5047 cpu7-thermal { 5048 polling-delay-passive = <250>; 5049 polling-delay = <0>; 5050 5051 thermal-sensors = <&tsens0 10>; 5052 5053 trips { 5054 cpu7_alert0: trip-point0 { 5055 temperature = <90000>; 5056 hysteresis = <2000>; 5057 type = "passive"; 5058 }; 5059 5060 cpu7_alert1: trip-point1 { 5061 temperature = <95000>; 5062 hysteresis = <2000>; 5063 type = "passive"; 5064 }; 5065 5066 cpu7_crit: cpu-crit { 5067 temperature = <110000>; 5068 hysteresis = <0>; 5069 type = "critical"; 5070 }; 5071 }; 5072 5073 cooling-maps { 5074 map0 { 5075 trip = <&cpu7_alert0>; 5076 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5077 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5078 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5079 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5080 }; 5081 map1 { 5082 trip = <&cpu7_alert1>; 5083 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5084 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5085 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5086 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5087 }; 5088 }; 5089 }; 5090 5091 cpu8-thermal { 5092 polling-delay-passive = <250>; 5093 polling-delay = <0>; 5094 5095 thermal-sensors = <&tsens0 11>; 5096 5097 trips { 5098 cpu8_alert0: trip-point0 { 5099 temperature = <90000>; 5100 hysteresis = <2000>; 5101 type = "passive"; 5102 }; 5103 5104 cpu8_alert1: trip-point1 { 5105 temperature = <95000>; 5106 hysteresis = <2000>; 5107 type = "passive"; 5108 }; 5109 5110 cpu8_crit: cpu-crit { 5111 temperature = <110000>; 5112 hysteresis = <0>; 5113 type = "critical"; 5114 }; 5115 }; 5116 5117 cooling-maps { 5118 map0 { 5119 trip = <&cpu8_alert0>; 5120 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5121 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5122 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5123 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5124 }; 5125 map1 { 5126 trip = <&cpu8_alert1>; 5127 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5128 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5129 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5130 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5131 }; 5132 }; 5133 }; 5134 5135 cpu9-thermal { 5136 polling-delay-passive = <250>; 5137 polling-delay = <0>; 5138 5139 thermal-sensors = <&tsens0 12>; 5140 5141 trips { 5142 cpu9_alert0: trip-point0 { 5143 temperature = <90000>; 5144 hysteresis = <2000>; 5145 type = "passive"; 5146 }; 5147 5148 cpu9_alert1: trip-point1 { 5149 temperature = <95000>; 5150 hysteresis = <2000>; 5151 type = "passive"; 5152 }; 5153 5154 cpu9_crit: cpu-crit { 5155 temperature = <110000>; 5156 hysteresis = <0>; 5157 type = "critical"; 5158 }; 5159 }; 5160 5161 cooling-maps { 5162 map0 { 5163 trip = <&cpu9_alert0>; 5164 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5165 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5166 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5167 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5168 }; 5169 map1 { 5170 trip = <&cpu9_alert1>; 5171 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5172 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5173 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5174 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5175 }; 5176 }; 5177 }; 5178 5179 cpu10-thermal { 5180 polling-delay-passive = <250>; 5181 polling-delay = <0>; 5182 5183 thermal-sensors = <&tsens0 13>; 5184 5185 trips { 5186 cpu10_alert0: trip-point0 { 5187 temperature = <90000>; 5188 hysteresis = <2000>; 5189 type = "passive"; 5190 }; 5191 5192 cpu10_alert1: trip-point1 { 5193 temperature = <95000>; 5194 hysteresis = <2000>; 5195 type = "passive"; 5196 }; 5197 5198 cpu10_crit: cpu-crit { 5199 temperature = <110000>; 5200 hysteresis = <0>; 5201 type = "critical"; 5202 }; 5203 }; 5204 5205 cooling-maps { 5206 map0 { 5207 trip = <&cpu10_alert0>; 5208 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5209 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5210 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5211 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5212 }; 5213 map1 { 5214 trip = <&cpu10_alert1>; 5215 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5216 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5217 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5218 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5219 }; 5220 }; 5221 }; 5222 5223 cpu11-thermal { 5224 polling-delay-passive = <250>; 5225 polling-delay = <0>; 5226 5227 thermal-sensors = <&tsens0 14>; 5228 5229 trips { 5230 cpu11_alert0: trip-point0 { 5231 temperature = <90000>; 5232 hysteresis = <2000>; 5233 type = "passive"; 5234 }; 5235 5236 cpu11_alert1: trip-point1 { 5237 temperature = <95000>; 5238 hysteresis = <2000>; 5239 type = "passive"; 5240 }; 5241 5242 cpu11_crit: cpu-crit { 5243 temperature = <110000>; 5244 hysteresis = <0>; 5245 type = "critical"; 5246 }; 5247 }; 5248 5249 cooling-maps { 5250 map0 { 5251 trip = <&cpu11_alert0>; 5252 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5253 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5254 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5255 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5256 }; 5257 map1 { 5258 trip = <&cpu11_alert1>; 5259 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5260 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5261 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5262 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5263 }; 5264 }; 5265 }; 5266 5267 aoss0-thermal { 5268 polling-delay-passive = <0>; 5269 polling-delay = <0>; 5270 5271 thermal-sensors = <&tsens0 0>; 5272 5273 trips { 5274 aoss0_alert0: trip-point0 { 5275 temperature = <90000>; 5276 hysteresis = <2000>; 5277 type = "hot"; 5278 }; 5279 5280 aoss0_crit: aoss0-crit { 5281 temperature = <110000>; 5282 hysteresis = <0>; 5283 type = "critical"; 5284 }; 5285 }; 5286 }; 5287 5288 aoss1-thermal { 5289 polling-delay-passive = <0>; 5290 polling-delay = <0>; 5291 5292 thermal-sensors = <&tsens1 0>; 5293 5294 trips { 5295 aoss1_alert0: trip-point0 { 5296 temperature = <90000>; 5297 hysteresis = <2000>; 5298 type = "hot"; 5299 }; 5300 5301 aoss1_crit: aoss1-crit { 5302 temperature = <110000>; 5303 hysteresis = <0>; 5304 type = "critical"; 5305 }; 5306 }; 5307 }; 5308 5309 cpuss0-thermal { 5310 polling-delay-passive = <0>; 5311 polling-delay = <0>; 5312 5313 thermal-sensors = <&tsens0 5>; 5314 5315 trips { 5316 cpuss0_alert0: trip-point0 { 5317 temperature = <90000>; 5318 hysteresis = <2000>; 5319 type = "hot"; 5320 }; 5321 cpuss0_crit: cluster0-crit { 5322 temperature = <110000>; 5323 hysteresis = <0>; 5324 type = "critical"; 5325 }; 5326 }; 5327 }; 5328 5329 cpuss1-thermal { 5330 polling-delay-passive = <0>; 5331 polling-delay = <0>; 5332 5333 thermal-sensors = <&tsens0 6>; 5334 5335 trips { 5336 cpuss1_alert0: trip-point0 { 5337 temperature = <90000>; 5338 hysteresis = <2000>; 5339 type = "hot"; 5340 }; 5341 cpuss1_crit: cluster0-crit { 5342 temperature = <110000>; 5343 hysteresis = <0>; 5344 type = "critical"; 5345 }; 5346 }; 5347 }; 5348 5349 gpuss0-thermal { 5350 polling-delay-passive = <100>; 5351 polling-delay = <0>; 5352 5353 thermal-sensors = <&tsens1 1>; 5354 5355 trips { 5356 gpuss0_alert0: trip-point0 { 5357 temperature = <95000>; 5358 hysteresis = <2000>; 5359 type = "passive"; 5360 }; 5361 5362 gpuss0_crit: gpuss0-crit { 5363 temperature = <110000>; 5364 hysteresis = <0>; 5365 type = "critical"; 5366 }; 5367 }; 5368 5369 cooling-maps { 5370 map0 { 5371 trip = <&gpuss0_alert0>; 5372 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5373 }; 5374 }; 5375 }; 5376 5377 gpuss1-thermal { 5378 polling-delay-passive = <100>; 5379 polling-delay = <0>; 5380 5381 thermal-sensors = <&tsens1 2>; 5382 5383 trips { 5384 gpuss1_alert0: trip-point0 { 5385 temperature = <95000>; 5386 hysteresis = <2000>; 5387 type = "passive"; 5388 }; 5389 5390 gpuss1_crit: gpuss1-crit { 5391 temperature = <110000>; 5392 hysteresis = <0>; 5393 type = "critical"; 5394 }; 5395 }; 5396 5397 cooling-maps { 5398 map0 { 5399 trip = <&gpuss1_alert0>; 5400 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5401 }; 5402 }; 5403 }; 5404 5405 nspss0-thermal { 5406 polling-delay-passive = <0>; 5407 polling-delay = <0>; 5408 5409 thermal-sensors = <&tsens1 3>; 5410 5411 trips { 5412 nspss0_alert0: trip-point0 { 5413 temperature = <90000>; 5414 hysteresis = <2000>; 5415 type = "hot"; 5416 }; 5417 5418 nspss0_crit: nspss0-crit { 5419 temperature = <110000>; 5420 hysteresis = <0>; 5421 type = "critical"; 5422 }; 5423 }; 5424 }; 5425 5426 nspss1-thermal { 5427 polling-delay-passive = <0>; 5428 polling-delay = <0>; 5429 5430 thermal-sensors = <&tsens1 4>; 5431 5432 trips { 5433 nspss1_alert0: trip-point0 { 5434 temperature = <90000>; 5435 hysteresis = <2000>; 5436 type = "hot"; 5437 }; 5438 5439 nspss1_crit: nspss1-crit { 5440 temperature = <110000>; 5441 hysteresis = <0>; 5442 type = "critical"; 5443 }; 5444 }; 5445 }; 5446 5447 video-thermal { 5448 polling-delay-passive = <0>; 5449 polling-delay = <0>; 5450 5451 thermal-sensors = <&tsens1 5>; 5452 5453 trips { 5454 video_alert0: trip-point0 { 5455 temperature = <90000>; 5456 hysteresis = <2000>; 5457 type = "hot"; 5458 }; 5459 5460 video_crit: video-crit { 5461 temperature = <110000>; 5462 hysteresis = <0>; 5463 type = "critical"; 5464 }; 5465 }; 5466 }; 5467 5468 ddr-thermal { 5469 polling-delay-passive = <0>; 5470 polling-delay = <0>; 5471 5472 thermal-sensors = <&tsens1 6>; 5473 5474 trips { 5475 ddr_alert0: trip-point0 { 5476 temperature = <90000>; 5477 hysteresis = <2000>; 5478 type = "hot"; 5479 }; 5480 5481 ddr_crit: ddr-crit { 5482 temperature = <110000>; 5483 hysteresis = <0>; 5484 type = "critical"; 5485 }; 5486 }; 5487 }; 5488 5489 mdmss0-thermal { 5490 polling-delay-passive = <0>; 5491 polling-delay = <0>; 5492 5493 thermal-sensors = <&tsens1 7>; 5494 5495 trips { 5496 mdmss0_alert0: trip-point0 { 5497 temperature = <90000>; 5498 hysteresis = <2000>; 5499 type = "hot"; 5500 }; 5501 5502 mdmss0_crit: mdmss0-crit { 5503 temperature = <110000>; 5504 hysteresis = <0>; 5505 type = "critical"; 5506 }; 5507 }; 5508 }; 5509 5510 mdmss1-thermal { 5511 polling-delay-passive = <0>; 5512 polling-delay = <0>; 5513 5514 thermal-sensors = <&tsens1 8>; 5515 5516 trips { 5517 mdmss1_alert0: trip-point0 { 5518 temperature = <90000>; 5519 hysteresis = <2000>; 5520 type = "hot"; 5521 }; 5522 5523 mdmss1_crit: mdmss1-crit { 5524 temperature = <110000>; 5525 hysteresis = <0>; 5526 type = "critical"; 5527 }; 5528 }; 5529 }; 5530 5531 mdmss2-thermal { 5532 polling-delay-passive = <0>; 5533 polling-delay = <0>; 5534 5535 thermal-sensors = <&tsens1 9>; 5536 5537 trips { 5538 mdmss2_alert0: trip-point0 { 5539 temperature = <90000>; 5540 hysteresis = <2000>; 5541 type = "hot"; 5542 }; 5543 5544 mdmss2_crit: mdmss2-crit { 5545 temperature = <110000>; 5546 hysteresis = <0>; 5547 type = "critical"; 5548 }; 5549 }; 5550 }; 5551 5552 mdmss3-thermal { 5553 polling-delay-passive = <0>; 5554 polling-delay = <0>; 5555 5556 thermal-sensors = <&tsens1 10>; 5557 5558 trips { 5559 mdmss3_alert0: trip-point0 { 5560 temperature = <90000>; 5561 hysteresis = <2000>; 5562 type = "hot"; 5563 }; 5564 5565 mdmss3_crit: mdmss3-crit { 5566 temperature = <110000>; 5567 hysteresis = <0>; 5568 type = "critical"; 5569 }; 5570 }; 5571 }; 5572 5573 camera0-thermal { 5574 polling-delay-passive = <0>; 5575 polling-delay = <0>; 5576 5577 thermal-sensors = <&tsens1 11>; 5578 5579 trips { 5580 camera0_alert0: trip-point0 { 5581 temperature = <90000>; 5582 hysteresis = <2000>; 5583 type = "hot"; 5584 }; 5585 5586 camera0_crit: camera0-crit { 5587 temperature = <110000>; 5588 hysteresis = <0>; 5589 type = "critical"; 5590 }; 5591 }; 5592 }; 5593 }; 5594 5595 timer { 5596 compatible = "arm,armv8-timer"; 5597 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 5598 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 5599 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 5600 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 5601 }; 5602}; 5603