1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7280.h> 13#include <dt-bindings/interconnect/qcom,sc7280.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-aoss-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/reset/qcom,sdm845-aoss.h> 19#include <dt-bindings/reset/qcom,sdm845-pdc.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 chosen { }; 30 31 aliases { 32 mmc1 = &sdhc_1; 33 mmc2 = &sdhc_2; 34 }; 35 36 clocks { 37 xo_board: xo-board { 38 compatible = "fixed-clock"; 39 clock-frequency = <76800000>; 40 #clock-cells = <0>; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 clock-frequency = <32000>; 46 #clock-cells = <0>; 47 }; 48 }; 49 50 reserved-memory { 51 #address-cells = <2>; 52 #size-cells = <2>; 53 ranges; 54 55 aop_mem: memory@80800000 { 56 reg = <0x0 0x80800000 0x0 0x60000>; 57 no-map; 58 }; 59 60 aop_cmd_db_mem: memory@80860000 { 61 reg = <0x0 0x80860000 0x0 0x20000>; 62 compatible = "qcom,cmd-db"; 63 no-map; 64 }; 65 66 smem_mem: memory@80900000 { 67 reg = <0x0 0x80900000 0x0 0x200000>; 68 no-map; 69 }; 70 71 cpucp_mem: memory@80b00000 { 72 no-map; 73 reg = <0x0 0x80b00000 0x0 0x100000>; 74 }; 75 76 ipa_fw_mem: memory@8b700000 { 77 reg = <0 0x8b700000 0 0x10000>; 78 no-map; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <2>; 84 #size-cells = <0>; 85 86 CPU0: cpu@0 { 87 device_type = "cpu"; 88 compatible = "arm,kryo"; 89 reg = <0x0 0x0>; 90 enable-method = "psci"; 91 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 92 &LITTLE_CPU_SLEEP_1 93 &CLUSTER_SLEEP_0>; 94 next-level-cache = <&L2_0>; 95 qcom,freq-domain = <&cpufreq_hw 0>; 96 #cooling-cells = <2>; 97 L2_0: l2-cache { 98 compatible = "cache"; 99 next-level-cache = <&L3_0>; 100 L3_0: l3-cache { 101 compatible = "cache"; 102 }; 103 }; 104 }; 105 106 CPU1: cpu@100 { 107 device_type = "cpu"; 108 compatible = "arm,kryo"; 109 reg = <0x0 0x100>; 110 enable-method = "psci"; 111 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 112 &LITTLE_CPU_SLEEP_1 113 &CLUSTER_SLEEP_0>; 114 next-level-cache = <&L2_100>; 115 qcom,freq-domain = <&cpufreq_hw 0>; 116 #cooling-cells = <2>; 117 L2_100: l2-cache { 118 compatible = "cache"; 119 next-level-cache = <&L3_0>; 120 }; 121 }; 122 123 CPU2: cpu@200 { 124 device_type = "cpu"; 125 compatible = "arm,kryo"; 126 reg = <0x0 0x200>; 127 enable-method = "psci"; 128 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 129 &LITTLE_CPU_SLEEP_1 130 &CLUSTER_SLEEP_0>; 131 next-level-cache = <&L2_200>; 132 qcom,freq-domain = <&cpufreq_hw 0>; 133 #cooling-cells = <2>; 134 L2_200: l2-cache { 135 compatible = "cache"; 136 next-level-cache = <&L3_0>; 137 }; 138 }; 139 140 CPU3: cpu@300 { 141 device_type = "cpu"; 142 compatible = "arm,kryo"; 143 reg = <0x0 0x300>; 144 enable-method = "psci"; 145 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 146 &LITTLE_CPU_SLEEP_1 147 &CLUSTER_SLEEP_0>; 148 next-level-cache = <&L2_300>; 149 qcom,freq-domain = <&cpufreq_hw 0>; 150 #cooling-cells = <2>; 151 L2_300: l2-cache { 152 compatible = "cache"; 153 next-level-cache = <&L3_0>; 154 }; 155 }; 156 157 CPU4: cpu@400 { 158 device_type = "cpu"; 159 compatible = "arm,kryo"; 160 reg = <0x0 0x400>; 161 enable-method = "psci"; 162 cpu-idle-states = <&BIG_CPU_SLEEP_0 163 &BIG_CPU_SLEEP_1 164 &CLUSTER_SLEEP_0>; 165 next-level-cache = <&L2_400>; 166 qcom,freq-domain = <&cpufreq_hw 1>; 167 #cooling-cells = <2>; 168 L2_400: l2-cache { 169 compatible = "cache"; 170 next-level-cache = <&L3_0>; 171 }; 172 }; 173 174 CPU5: cpu@500 { 175 device_type = "cpu"; 176 compatible = "arm,kryo"; 177 reg = <0x0 0x500>; 178 enable-method = "psci"; 179 cpu-idle-states = <&BIG_CPU_SLEEP_0 180 &BIG_CPU_SLEEP_1 181 &CLUSTER_SLEEP_0>; 182 next-level-cache = <&L2_500>; 183 qcom,freq-domain = <&cpufreq_hw 1>; 184 #cooling-cells = <2>; 185 L2_500: l2-cache { 186 compatible = "cache"; 187 next-level-cache = <&L3_0>; 188 }; 189 }; 190 191 CPU6: cpu@600 { 192 device_type = "cpu"; 193 compatible = "arm,kryo"; 194 reg = <0x0 0x600>; 195 enable-method = "psci"; 196 cpu-idle-states = <&BIG_CPU_SLEEP_0 197 &BIG_CPU_SLEEP_1 198 &CLUSTER_SLEEP_0>; 199 next-level-cache = <&L2_600>; 200 qcom,freq-domain = <&cpufreq_hw 1>; 201 #cooling-cells = <2>; 202 L2_600: l2-cache { 203 compatible = "cache"; 204 next-level-cache = <&L3_0>; 205 }; 206 }; 207 208 CPU7: cpu@700 { 209 device_type = "cpu"; 210 compatible = "arm,kryo"; 211 reg = <0x0 0x700>; 212 enable-method = "psci"; 213 cpu-idle-states = <&BIG_CPU_SLEEP_0 214 &BIG_CPU_SLEEP_1 215 &CLUSTER_SLEEP_0>; 216 next-level-cache = <&L2_700>; 217 qcom,freq-domain = <&cpufreq_hw 2>; 218 #cooling-cells = <2>; 219 L2_700: l2-cache { 220 compatible = "cache"; 221 next-level-cache = <&L3_0>; 222 }; 223 }; 224 225 cpu-map { 226 cluster0 { 227 core0 { 228 cpu = <&CPU0>; 229 }; 230 231 core1 { 232 cpu = <&CPU1>; 233 }; 234 235 core2 { 236 cpu = <&CPU2>; 237 }; 238 239 core3 { 240 cpu = <&CPU3>; 241 }; 242 243 core4 { 244 cpu = <&CPU4>; 245 }; 246 247 core5 { 248 cpu = <&CPU5>; 249 }; 250 251 core6 { 252 cpu = <&CPU6>; 253 }; 254 255 core7 { 256 cpu = <&CPU7>; 257 }; 258 }; 259 }; 260 261 idle-states { 262 entry-method = "psci"; 263 264 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 265 compatible = "arm,idle-state"; 266 idle-state-name = "little-power-down"; 267 arm,psci-suspend-param = <0x40000003>; 268 entry-latency-us = <549>; 269 exit-latency-us = <901>; 270 min-residency-us = <1774>; 271 local-timer-stop; 272 }; 273 274 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 275 compatible = "arm,idle-state"; 276 idle-state-name = "little-rail-power-down"; 277 arm,psci-suspend-param = <0x40000004>; 278 entry-latency-us = <702>; 279 exit-latency-us = <915>; 280 min-residency-us = <4001>; 281 local-timer-stop; 282 }; 283 284 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 285 compatible = "arm,idle-state"; 286 idle-state-name = "big-power-down"; 287 arm,psci-suspend-param = <0x40000003>; 288 entry-latency-us = <523>; 289 exit-latency-us = <1244>; 290 min-residency-us = <2207>; 291 local-timer-stop; 292 }; 293 294 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 295 compatible = "arm,idle-state"; 296 idle-state-name = "big-rail-power-down"; 297 arm,psci-suspend-param = <0x40000004>; 298 entry-latency-us = <526>; 299 exit-latency-us = <1854>; 300 min-residency-us = <5555>; 301 local-timer-stop; 302 }; 303 304 CLUSTER_SLEEP_0: cluster-sleep-0 { 305 compatible = "arm,idle-state"; 306 idle-state-name = "cluster-power-down"; 307 arm,psci-suspend-param = <0x40003444>; 308 entry-latency-us = <3263>; 309 exit-latency-us = <6562>; 310 min-residency-us = <9926>; 311 local-timer-stop; 312 }; 313 }; 314 }; 315 316 memory@80000000 { 317 device_type = "memory"; 318 /* We expect the bootloader to fill in the size */ 319 reg = <0 0x80000000 0 0>; 320 }; 321 322 firmware { 323 scm { 324 compatible = "qcom,scm-sc7280", "qcom,scm"; 325 }; 326 }; 327 328 clk_virt: interconnect { 329 compatible = "qcom,sc7280-clk-virt"; 330 #interconnect-cells = <2>; 331 qcom,bcm-voters = <&apps_bcm_voter>; 332 }; 333 334 smem { 335 compatible = "qcom,smem"; 336 memory-region = <&smem_mem>; 337 hwlocks = <&tcsr_mutex 3>; 338 }; 339 340 smp2p-adsp { 341 compatible = "qcom,smp2p"; 342 qcom,smem = <443>, <429>; 343 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 344 IPCC_MPROC_SIGNAL_SMP2P 345 IRQ_TYPE_EDGE_RISING>; 346 mboxes = <&ipcc IPCC_CLIENT_LPASS 347 IPCC_MPROC_SIGNAL_SMP2P>; 348 349 qcom,local-pid = <0>; 350 qcom,remote-pid = <2>; 351 352 adsp_smp2p_out: master-kernel { 353 qcom,entry-name = "master-kernel"; 354 #qcom,smem-state-cells = <1>; 355 }; 356 357 adsp_smp2p_in: slave-kernel { 358 qcom,entry-name = "slave-kernel"; 359 interrupt-controller; 360 #interrupt-cells = <2>; 361 }; 362 }; 363 364 smp2p-cdsp { 365 compatible = "qcom,smp2p"; 366 qcom,smem = <94>, <432>; 367 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 368 IPCC_MPROC_SIGNAL_SMP2P 369 IRQ_TYPE_EDGE_RISING>; 370 mboxes = <&ipcc IPCC_CLIENT_CDSP 371 IPCC_MPROC_SIGNAL_SMP2P>; 372 373 qcom,local-pid = <0>; 374 qcom,remote-pid = <5>; 375 376 cdsp_smp2p_out: master-kernel { 377 qcom,entry-name = "master-kernel"; 378 #qcom,smem-state-cells = <1>; 379 }; 380 381 cdsp_smp2p_in: slave-kernel { 382 qcom,entry-name = "slave-kernel"; 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 }; 386 }; 387 388 smp2p-mpss { 389 compatible = "qcom,smp2p"; 390 qcom,smem = <435>, <428>; 391 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 392 IPCC_MPROC_SIGNAL_SMP2P 393 IRQ_TYPE_EDGE_RISING>; 394 mboxes = <&ipcc IPCC_CLIENT_MPSS 395 IPCC_MPROC_SIGNAL_SMP2P>; 396 397 qcom,local-pid = <0>; 398 qcom,remote-pid = <1>; 399 400 modem_smp2p_out: master-kernel { 401 qcom,entry-name = "master-kernel"; 402 #qcom,smem-state-cells = <1>; 403 }; 404 405 modem_smp2p_in: slave-kernel { 406 qcom,entry-name = "slave-kernel"; 407 interrupt-controller; 408 #interrupt-cells = <2>; 409 }; 410 411 ipa_smp2p_out: ipa-ap-to-modem { 412 qcom,entry-name = "ipa"; 413 #qcom,smem-state-cells = <1>; 414 }; 415 416 ipa_smp2p_in: ipa-modem-to-ap { 417 qcom,entry-name = "ipa"; 418 interrupt-controller; 419 #interrupt-cells = <2>; 420 }; 421 }; 422 423 smp2p-wpss { 424 compatible = "qcom,smp2p"; 425 qcom,smem = <617>, <616>; 426 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 427 IPCC_MPROC_SIGNAL_SMP2P 428 IRQ_TYPE_EDGE_RISING>; 429 mboxes = <&ipcc IPCC_CLIENT_WPSS 430 IPCC_MPROC_SIGNAL_SMP2P>; 431 432 qcom,local-pid = <0>; 433 qcom,remote-pid = <13>; 434 435 wpss_smp2p_out: master-kernel { 436 qcom,entry-name = "master-kernel"; 437 #qcom,smem-state-cells = <1>; 438 }; 439 440 wpss_smp2p_in: slave-kernel { 441 qcom,entry-name = "slave-kernel"; 442 interrupt-controller; 443 #interrupt-cells = <2>; 444 }; 445 }; 446 447 pmu { 448 compatible = "arm,armv8-pmuv3"; 449 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 450 }; 451 452 psci { 453 compatible = "arm,psci-1.0"; 454 method = "smc"; 455 }; 456 457 qspi_opp_table: qspi-opp-table { 458 compatible = "operating-points-v2"; 459 460 opp-75000000 { 461 opp-hz = /bits/ 64 <75000000>; 462 required-opps = <&rpmhpd_opp_low_svs>; 463 }; 464 465 opp-150000000 { 466 opp-hz = /bits/ 64 <150000000>; 467 required-opps = <&rpmhpd_opp_svs>; 468 }; 469 470 opp-300000000 { 471 opp-hz = /bits/ 64 <300000000>; 472 required-opps = <&rpmhpd_opp_nom>; 473 }; 474 }; 475 476 qup_opp_table: qup-opp-table { 477 compatible = "operating-points-v2"; 478 479 opp-75000000 { 480 opp-hz = /bits/ 64 <75000000>; 481 required-opps = <&rpmhpd_opp_low_svs>; 482 }; 483 484 opp-100000000 { 485 opp-hz = /bits/ 64 <100000000>; 486 required-opps = <&rpmhpd_opp_svs>; 487 }; 488 489 opp-128000000 { 490 opp-hz = /bits/ 64 <128000000>; 491 required-opps = <&rpmhpd_opp_nom>; 492 }; 493 }; 494 495 soc: soc@0 { 496 #address-cells = <2>; 497 #size-cells = <2>; 498 ranges = <0 0 0 0 0x10 0>; 499 dma-ranges = <0 0 0 0 0x10 0>; 500 compatible = "simple-bus"; 501 502 gcc: clock-controller@100000 { 503 compatible = "qcom,gcc-sc7280"; 504 reg = <0 0x00100000 0 0x1f0000>; 505 clocks = <&rpmhcc RPMH_CXO_CLK>, 506 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 507 <0>, <0>, <0>, <0>, <0>, <0>; 508 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 509 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 510 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 511 "ufs_phy_tx_symbol_0_clk", 512 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 513 #clock-cells = <1>; 514 #reset-cells = <1>; 515 #power-domain-cells = <1>; 516 }; 517 518 ipcc: mailbox@408000 { 519 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 520 reg = <0 0x00408000 0 0x1000>; 521 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 522 interrupt-controller; 523 #interrupt-cells = <3>; 524 #mbox-cells = <2>; 525 }; 526 527 qfprom: efuse@784000 { 528 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 529 reg = <0 0x00784000 0 0xa20>, 530 <0 0x00780000 0 0xa20>, 531 <0 0x00782000 0 0x120>, 532 <0 0x00786000 0 0x1fff>; 533 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 534 clock-names = "core"; 535 power-domains = <&rpmhpd SC7280_MX>; 536 #address-cells = <1>; 537 #size-cells = <1>; 538 }; 539 540 sdhc_1: sdhci@7c4000 { 541 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 542 status = "disabled"; 543 544 reg = <0 0x007c4000 0 0x1000>, 545 <0 0x007c5000 0 0x1000>; 546 reg-names = "hc", "cqhci"; 547 548 iommus = <&apps_smmu 0xc0 0x0>; 549 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 551 interrupt-names = "hc_irq", "pwr_irq"; 552 553 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 554 <&gcc GCC_SDCC1_AHB_CLK>, 555 <&rpmhcc RPMH_CXO_CLK>; 556 clock-names = "core", "iface", "xo"; 557 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 558 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 559 interconnect-names = "sdhc-ddr","cpu-sdhc"; 560 power-domains = <&rpmhpd SC7280_CX>; 561 operating-points-v2 = <&sdhc1_opp_table>; 562 563 bus-width = <8>; 564 supports-cqe; 565 566 qcom,dll-config = <0x0007642c>; 567 qcom,ddr-config = <0x80040868>; 568 569 mmc-ddr-1_8v; 570 mmc-hs200-1_8v; 571 mmc-hs400-1_8v; 572 mmc-hs400-enhanced-strobe; 573 574 sdhc1_opp_table: opp-table { 575 compatible = "operating-points-v2"; 576 577 opp-100000000 { 578 opp-hz = /bits/ 64 <100000000>; 579 required-opps = <&rpmhpd_opp_low_svs>; 580 opp-peak-kBps = <1800000 400000>; 581 opp-avg-kBps = <100000 0>; 582 }; 583 584 opp-384000000 { 585 opp-hz = /bits/ 64 <384000000>; 586 required-opps = <&rpmhpd_opp_nom>; 587 opp-peak-kBps = <5400000 1600000>; 588 opp-avg-kBps = <390000 0>; 589 }; 590 }; 591 592 }; 593 594 qupv3_id_0: geniqup@9c0000 { 595 compatible = "qcom,geni-se-qup"; 596 reg = <0 0x009c0000 0 0x2000>; 597 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 598 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 599 clock-names = "m-ahb", "s-ahb"; 600 #address-cells = <2>; 601 #size-cells = <2>; 602 ranges; 603 iommus = <&apps_smmu 0x123 0x0>; 604 status = "disabled"; 605 606 i2c0: i2c@980000 { 607 compatible = "qcom,geni-i2c"; 608 reg = <0 0x00980000 0 0x4000>; 609 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 610 clock-names = "se"; 611 pinctrl-names = "default"; 612 pinctrl-0 = <&qup_i2c0_data_clk>; 613 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 614 #address-cells = <1>; 615 #size-cells = <0>; 616 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 617 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 618 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 619 interconnect-names = "qup-core", "qup-config", 620 "qup-memory"; 621 status = "disabled"; 622 }; 623 624 spi0: spi@980000 { 625 compatible = "qcom,geni-spi"; 626 reg = <0 0x00980000 0 0x4000>; 627 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 628 clock-names = "se"; 629 pinctrl-names = "default"; 630 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 631 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 power-domains = <&rpmhpd SC7280_CX>; 635 operating-points-v2 = <&qup_opp_table>; 636 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 637 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 638 interconnect-names = "qup-core", "qup-config"; 639 status = "disabled"; 640 }; 641 642 uart0: serial@980000 { 643 compatible = "qcom,geni-uart"; 644 reg = <0 0x00980000 0 0x4000>; 645 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 646 clock-names = "se"; 647 pinctrl-names = "default"; 648 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 649 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 650 power-domains = <&rpmhpd SC7280_CX>; 651 operating-points-v2 = <&qup_opp_table>; 652 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 653 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 654 interconnect-names = "qup-core", "qup-config"; 655 status = "disabled"; 656 }; 657 658 i2c1: i2c@984000 { 659 compatible = "qcom,geni-i2c"; 660 reg = <0 0x00984000 0 0x4000>; 661 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 662 clock-names = "se"; 663 pinctrl-names = "default"; 664 pinctrl-0 = <&qup_i2c1_data_clk>; 665 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 666 #address-cells = <1>; 667 #size-cells = <0>; 668 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 669 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 670 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 671 interconnect-names = "qup-core", "qup-config", 672 "qup-memory"; 673 status = "disabled"; 674 }; 675 676 spi1: spi@984000 { 677 compatible = "qcom,geni-spi"; 678 reg = <0 0x00984000 0 0x4000>; 679 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 680 clock-names = "se"; 681 pinctrl-names = "default"; 682 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 683 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 power-domains = <&rpmhpd SC7280_CX>; 687 operating-points-v2 = <&qup_opp_table>; 688 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 689 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 690 interconnect-names = "qup-core", "qup-config"; 691 status = "disabled"; 692 }; 693 694 uart1: serial@984000 { 695 compatible = "qcom,geni-uart"; 696 reg = <0 0x00984000 0 0x4000>; 697 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 698 clock-names = "se"; 699 pinctrl-names = "default"; 700 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 701 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 702 power-domains = <&rpmhpd SC7280_CX>; 703 operating-points-v2 = <&qup_opp_table>; 704 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 705 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 706 interconnect-names = "qup-core", "qup-config"; 707 status = "disabled"; 708 }; 709 710 i2c2: i2c@988000 { 711 compatible = "qcom,geni-i2c"; 712 reg = <0 0x00988000 0 0x4000>; 713 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 714 clock-names = "se"; 715 pinctrl-names = "default"; 716 pinctrl-0 = <&qup_i2c2_data_clk>; 717 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 721 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 722 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 723 interconnect-names = "qup-core", "qup-config", 724 "qup-memory"; 725 status = "disabled"; 726 }; 727 728 spi2: spi@988000 { 729 compatible = "qcom,geni-spi"; 730 reg = <0 0x00988000 0 0x4000>; 731 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 732 clock-names = "se"; 733 pinctrl-names = "default"; 734 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 735 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 736 #address-cells = <1>; 737 #size-cells = <0>; 738 power-domains = <&rpmhpd SC7280_CX>; 739 operating-points-v2 = <&qup_opp_table>; 740 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 741 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 742 interconnect-names = "qup-core", "qup-config"; 743 status = "disabled"; 744 }; 745 746 uart2: serial@988000 { 747 compatible = "qcom,geni-uart"; 748 reg = <0 0x00988000 0 0x4000>; 749 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 750 clock-names = "se"; 751 pinctrl-names = "default"; 752 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 753 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 754 power-domains = <&rpmhpd SC7280_CX>; 755 operating-points-v2 = <&qup_opp_table>; 756 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 757 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 758 interconnect-names = "qup-core", "qup-config"; 759 status = "disabled"; 760 }; 761 762 i2c3: i2c@98c000 { 763 compatible = "qcom,geni-i2c"; 764 reg = <0 0x0098c000 0 0x4000>; 765 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 766 clock-names = "se"; 767 pinctrl-names = "default"; 768 pinctrl-0 = <&qup_i2c3_data_clk>; 769 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 770 #address-cells = <1>; 771 #size-cells = <0>; 772 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 773 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 774 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 775 interconnect-names = "qup-core", "qup-config", 776 "qup-memory"; 777 status = "disabled"; 778 }; 779 780 spi3: spi@98c000 { 781 compatible = "qcom,geni-spi"; 782 reg = <0 0x0098c000 0 0x4000>; 783 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 784 clock-names = "se"; 785 pinctrl-names = "default"; 786 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 787 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 power-domains = <&rpmhpd SC7280_CX>; 791 operating-points-v2 = <&qup_opp_table>; 792 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 793 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 794 interconnect-names = "qup-core", "qup-config"; 795 status = "disabled"; 796 }; 797 798 uart3: serial@98c000 { 799 compatible = "qcom,geni-uart"; 800 reg = <0 0x0098c000 0 0x4000>; 801 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 802 clock-names = "se"; 803 pinctrl-names = "default"; 804 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 805 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 806 power-domains = <&rpmhpd SC7280_CX>; 807 operating-points-v2 = <&qup_opp_table>; 808 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 809 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 810 interconnect-names = "qup-core", "qup-config"; 811 status = "disabled"; 812 }; 813 814 i2c4: i2c@990000 { 815 compatible = "qcom,geni-i2c"; 816 reg = <0 0x00990000 0 0x4000>; 817 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 818 clock-names = "se"; 819 pinctrl-names = "default"; 820 pinctrl-0 = <&qup_i2c4_data_clk>; 821 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 825 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 826 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 827 interconnect-names = "qup-core", "qup-config", 828 "qup-memory"; 829 status = "disabled"; 830 }; 831 832 spi4: spi@990000 { 833 compatible = "qcom,geni-spi"; 834 reg = <0 0x00990000 0 0x4000>; 835 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 836 clock-names = "se"; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 839 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 power-domains = <&rpmhpd SC7280_CX>; 843 operating-points-v2 = <&qup_opp_table>; 844 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 845 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 846 interconnect-names = "qup-core", "qup-config"; 847 status = "disabled"; 848 }; 849 850 uart4: serial@990000 { 851 compatible = "qcom,geni-uart"; 852 reg = <0 0x00990000 0 0x4000>; 853 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 854 clock-names = "se"; 855 pinctrl-names = "default"; 856 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 857 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 858 power-domains = <&rpmhpd SC7280_CX>; 859 operating-points-v2 = <&qup_opp_table>; 860 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 861 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 862 interconnect-names = "qup-core", "qup-config"; 863 status = "disabled"; 864 }; 865 866 i2c5: i2c@994000 { 867 compatible = "qcom,geni-i2c"; 868 reg = <0 0x00994000 0 0x4000>; 869 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 870 clock-names = "se"; 871 pinctrl-names = "default"; 872 pinctrl-0 = <&qup_i2c5_data_clk>; 873 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 874 #address-cells = <1>; 875 #size-cells = <0>; 876 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 877 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 878 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 879 interconnect-names = "qup-core", "qup-config", 880 "qup-memory"; 881 status = "disabled"; 882 }; 883 884 spi5: spi@994000 { 885 compatible = "qcom,geni-spi"; 886 reg = <0 0x00994000 0 0x4000>; 887 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 888 clock-names = "se"; 889 pinctrl-names = "default"; 890 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 891 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 892 #address-cells = <1>; 893 #size-cells = <0>; 894 power-domains = <&rpmhpd SC7280_CX>; 895 operating-points-v2 = <&qup_opp_table>; 896 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 897 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 898 interconnect-names = "qup-core", "qup-config"; 899 status = "disabled"; 900 }; 901 902 uart5: serial@994000 { 903 compatible = "qcom,geni-uart"; 904 reg = <0 0x00994000 0 0x4000>; 905 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 906 clock-names = "se"; 907 pinctrl-names = "default"; 908 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 909 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 910 power-domains = <&rpmhpd SC7280_CX>; 911 operating-points-v2 = <&qup_opp_table>; 912 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 913 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 914 interconnect-names = "qup-core", "qup-config"; 915 status = "disabled"; 916 }; 917 918 i2c6: i2c@998000 { 919 compatible = "qcom,geni-i2c"; 920 reg = <0 0x00998000 0 0x4000>; 921 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 922 clock-names = "se"; 923 pinctrl-names = "default"; 924 pinctrl-0 = <&qup_i2c6_data_clk>; 925 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 926 #address-cells = <1>; 927 #size-cells = <0>; 928 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 929 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 930 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 931 interconnect-names = "qup-core", "qup-config", 932 "qup-memory"; 933 status = "disabled"; 934 }; 935 936 spi6: spi@998000 { 937 compatible = "qcom,geni-spi"; 938 reg = <0 0x00998000 0 0x4000>; 939 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 940 clock-names = "se"; 941 pinctrl-names = "default"; 942 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 943 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 944 #address-cells = <1>; 945 #size-cells = <0>; 946 power-domains = <&rpmhpd SC7280_CX>; 947 operating-points-v2 = <&qup_opp_table>; 948 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 949 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 950 interconnect-names = "qup-core", "qup-config"; 951 status = "disabled"; 952 }; 953 954 uart6: serial@998000 { 955 compatible = "qcom,geni-uart"; 956 reg = <0 0x00998000 0 0x4000>; 957 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 958 clock-names = "se"; 959 pinctrl-names = "default"; 960 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 961 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 962 power-domains = <&rpmhpd SC7280_CX>; 963 operating-points-v2 = <&qup_opp_table>; 964 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 965 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 966 interconnect-names = "qup-core", "qup-config"; 967 status = "disabled"; 968 }; 969 970 i2c7: i2c@99c000 { 971 compatible = "qcom,geni-i2c"; 972 reg = <0 0x0099c000 0 0x4000>; 973 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 974 clock-names = "se"; 975 pinctrl-names = "default"; 976 pinctrl-0 = <&qup_i2c7_data_clk>; 977 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 978 #address-cells = <1>; 979 #size-cells = <0>; 980 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 981 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 982 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 983 interconnect-names = "qup-core", "qup-config", 984 "qup-memory"; 985 status = "disabled"; 986 }; 987 988 spi7: spi@99c000 { 989 compatible = "qcom,geni-spi"; 990 reg = <0 0x0099c000 0 0x4000>; 991 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 992 clock-names = "se"; 993 pinctrl-names = "default"; 994 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 995 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 996 #address-cells = <1>; 997 #size-cells = <0>; 998 power-domains = <&rpmhpd SC7280_CX>; 999 operating-points-v2 = <&qup_opp_table>; 1000 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1001 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1002 interconnect-names = "qup-core", "qup-config"; 1003 status = "disabled"; 1004 }; 1005 1006 uart7: serial@99c000 { 1007 compatible = "qcom,geni-uart"; 1008 reg = <0 0x0099c000 0 0x4000>; 1009 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1010 clock-names = "se"; 1011 pinctrl-names = "default"; 1012 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1013 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1014 power-domains = <&rpmhpd SC7280_CX>; 1015 operating-points-v2 = <&qup_opp_table>; 1016 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1017 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1018 interconnect-names = "qup-core", "qup-config"; 1019 status = "disabled"; 1020 }; 1021 }; 1022 1023 cnoc2: interconnect@1500000 { 1024 reg = <0 0x01500000 0 0x1000>; 1025 compatible = "qcom,sc7280-cnoc2"; 1026 #interconnect-cells = <2>; 1027 qcom,bcm-voters = <&apps_bcm_voter>; 1028 }; 1029 1030 cnoc3: interconnect@1502000 { 1031 reg = <0 0x01502000 0 0x1000>; 1032 compatible = "qcom,sc7280-cnoc3"; 1033 #interconnect-cells = <2>; 1034 qcom,bcm-voters = <&apps_bcm_voter>; 1035 }; 1036 1037 mc_virt: interconnect@1580000 { 1038 reg = <0 0x01580000 0 0x4>; 1039 compatible = "qcom,sc7280-mc-virt"; 1040 #interconnect-cells = <2>; 1041 qcom,bcm-voters = <&apps_bcm_voter>; 1042 }; 1043 1044 system_noc: interconnect@1680000 { 1045 reg = <0 0x01680000 0 0x15480>; 1046 compatible = "qcom,sc7280-system-noc"; 1047 #interconnect-cells = <2>; 1048 qcom,bcm-voters = <&apps_bcm_voter>; 1049 }; 1050 1051 aggre1_noc: interconnect@16e0000 { 1052 compatible = "qcom,sc7280-aggre1-noc"; 1053 reg = <0 0x016e0000 0 0x1c080>; 1054 #interconnect-cells = <2>; 1055 qcom,bcm-voters = <&apps_bcm_voter>; 1056 }; 1057 1058 aggre2_noc: interconnect@1700000 { 1059 reg = <0 0x01700000 0 0x2b080>; 1060 compatible = "qcom,sc7280-aggre2-noc"; 1061 #interconnect-cells = <2>; 1062 qcom,bcm-voters = <&apps_bcm_voter>; 1063 }; 1064 1065 mmss_noc: interconnect@1740000 { 1066 reg = <0 0x01740000 0 0x1e080>; 1067 compatible = "qcom,sc7280-mmss-noc"; 1068 #interconnect-cells = <2>; 1069 qcom,bcm-voters = <&apps_bcm_voter>; 1070 }; 1071 1072 ipa: ipa@1e40000 { 1073 compatible = "qcom,sc7280-ipa"; 1074 1075 iommus = <&apps_smmu 0x480 0x0>, 1076 <&apps_smmu 0x482 0x0>; 1077 reg = <0 0x1e40000 0 0x8000>, 1078 <0 0x1e50000 0 0x4ad0>, 1079 <0 0x1e04000 0 0x23000>; 1080 reg-names = "ipa-reg", 1081 "ipa-shared", 1082 "gsi"; 1083 1084 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 1085 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1086 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1087 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1088 interrupt-names = "ipa", 1089 "gsi", 1090 "ipa-clock-query", 1091 "ipa-setup-ready"; 1092 1093 clocks = <&rpmhcc RPMH_IPA_CLK>; 1094 clock-names = "core"; 1095 1096 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1097 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 1098 interconnect-names = "memory", 1099 "config"; 1100 1101 qcom,smem-states = <&ipa_smp2p_out 0>, 1102 <&ipa_smp2p_out 1>; 1103 qcom,smem-state-names = "ipa-clock-enabled-valid", 1104 "ipa-clock-enabled"; 1105 1106 status = "disabled"; 1107 }; 1108 1109 tcsr_mutex: hwlock@1f40000 { 1110 compatible = "qcom,tcsr-mutex", "syscon"; 1111 reg = <0 0x01f40000 0 0x40000>; 1112 #hwlock-cells = <1>; 1113 }; 1114 1115 lpasscc: lpasscc@3000000 { 1116 compatible = "qcom,sc7280-lpasscc"; 1117 reg = <0 0x03000000 0 0x40>, 1118 <0 0x03c04000 0 0x4>, 1119 <0 0x03389000 0 0x24>; 1120 reg-names = "qdsp6ss", "top_cc", "cc"; 1121 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 1122 clock-names = "iface"; 1123 #clock-cells = <1>; 1124 }; 1125 1126 lpass_ag_noc: interconnect@3c40000 { 1127 reg = <0 0x03c40000 0 0xf080>; 1128 compatible = "qcom,sc7280-lpass-ag-noc"; 1129 #interconnect-cells = <2>; 1130 qcom,bcm-voters = <&apps_bcm_voter>; 1131 }; 1132 1133 gpu: gpu@3d00000 { 1134 compatible = "qcom,adreno-635.0", "qcom,adreno"; 1135 #stream-id-cells = <16>; 1136 reg = <0 0x03d00000 0 0x40000>, 1137 <0 0x03d9e000 0 0x1000>, 1138 <0 0x03d61000 0 0x800>; 1139 reg-names = "kgsl_3d0_reg_memory", 1140 "cx_mem", 1141 "cx_dbgc"; 1142 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1143 iommus = <&adreno_smmu 0 0x401>; 1144 operating-points-v2 = <&gpu_opp_table>; 1145 qcom,gmu = <&gmu>; 1146 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 1147 interconnect-names = "gfx-mem"; 1148 #cooling-cells = <2>; 1149 1150 gpu_opp_table: opp-table { 1151 compatible = "operating-points-v2"; 1152 1153 opp-315000000 { 1154 opp-hz = /bits/ 64 <315000000>; 1155 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1156 opp-peak-kBps = <1804000>; 1157 }; 1158 1159 opp-450000000 { 1160 opp-hz = /bits/ 64 <450000000>; 1161 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1162 opp-peak-kBps = <4068000>; 1163 }; 1164 1165 opp-550000000 { 1166 opp-hz = /bits/ 64 <550000000>; 1167 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1168 opp-peak-kBps = <6832000>; 1169 }; 1170 }; 1171 }; 1172 1173 gmu: gmu@3d69000 { 1174 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 1175 reg = <0 0x03d6a000 0 0x34000>, 1176 <0 0x3de0000 0 0x10000>, 1177 <0 0x0b290000 0 0x10000>; 1178 reg-names = "gmu", "rscc", "gmu_pdc"; 1179 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1181 interrupt-names = "hfi", "gmu"; 1182 clocks = <&gpucc 5>, 1183 <&gpucc 8>, 1184 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1185 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1186 <&gpucc 2>, 1187 <&gpucc 15>, 1188 <&gpucc 11>; 1189 clock-names = "gmu", 1190 "cxo", 1191 "axi", 1192 "memnoc", 1193 "ahb", 1194 "hub", 1195 "smmu_vote"; 1196 power-domains = <&gpucc 0>, 1197 <&gpucc 1>; 1198 power-domain-names = "cx", 1199 "gx"; 1200 iommus = <&adreno_smmu 5 0x400>; 1201 operating-points-v2 = <&gmu_opp_table>; 1202 1203 gmu_opp_table: opp-table { 1204 compatible = "operating-points-v2"; 1205 1206 opp-200000000 { 1207 opp-hz = /bits/ 64 <200000000>; 1208 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1209 }; 1210 }; 1211 }; 1212 1213 gpucc: clock-controller@3d90000 { 1214 compatible = "qcom,sc7280-gpucc"; 1215 reg = <0 0x03d90000 0 0x9000>; 1216 clocks = <&rpmhcc RPMH_CXO_CLK>, 1217 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1218 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1219 clock-names = "bi_tcxo", 1220 "gcc_gpu_gpll0_clk_src", 1221 "gcc_gpu_gpll0_div_clk_src"; 1222 #clock-cells = <1>; 1223 #reset-cells = <1>; 1224 #power-domain-cells = <1>; 1225 }; 1226 1227 adreno_smmu: iommu@3da0000 { 1228 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 1229 reg = <0 0x03da0000 0 0x20000>; 1230 #iommu-cells = <2>; 1231 #global-interrupts = <2>; 1232 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1244 1245 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1246 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1247 <&gpucc 2>, 1248 <&gpucc 11>, 1249 <&gpucc 5>, 1250 <&gpucc 15>, 1251 <&gpucc 13>; 1252 clock-names = "gcc_gpu_memnoc_gfx_clk", 1253 "gcc_gpu_snoc_dvm_gfx_clk", 1254 "gpu_cc_ahb_clk", 1255 "gpu_cc_hlos1_vote_gpu_smmu_clk", 1256 "gpu_cc_cx_gmu_clk", 1257 "gpu_cc_hub_cx_int_clk", 1258 "gpu_cc_hub_aon_clk"; 1259 1260 power-domains = <&gpucc 0>; 1261 }; 1262 1263 stm@6002000 { 1264 compatible = "arm,coresight-stm", "arm,primecell"; 1265 reg = <0 0x06002000 0 0x1000>, 1266 <0 0x16280000 0 0x180000>; 1267 reg-names = "stm-base", "stm-stimulus-base"; 1268 1269 clocks = <&aoss_qmp>; 1270 clock-names = "apb_pclk"; 1271 1272 out-ports { 1273 port { 1274 stm_out: endpoint { 1275 remote-endpoint = <&funnel0_in7>; 1276 }; 1277 }; 1278 }; 1279 }; 1280 1281 funnel@6041000 { 1282 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1283 reg = <0 0x06041000 0 0x1000>; 1284 1285 clocks = <&aoss_qmp>; 1286 clock-names = "apb_pclk"; 1287 1288 out-ports { 1289 port { 1290 funnel0_out: endpoint { 1291 remote-endpoint = <&merge_funnel_in0>; 1292 }; 1293 }; 1294 }; 1295 1296 in-ports { 1297 #address-cells = <1>; 1298 #size-cells = <0>; 1299 1300 port@7 { 1301 reg = <7>; 1302 funnel0_in7: endpoint { 1303 remote-endpoint = <&stm_out>; 1304 }; 1305 }; 1306 }; 1307 }; 1308 1309 funnel@6042000 { 1310 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1311 reg = <0 0x06042000 0 0x1000>; 1312 1313 clocks = <&aoss_qmp>; 1314 clock-names = "apb_pclk"; 1315 1316 out-ports { 1317 port { 1318 funnel1_out: endpoint { 1319 remote-endpoint = <&merge_funnel_in1>; 1320 }; 1321 }; 1322 }; 1323 1324 in-ports { 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 1328 port@4 { 1329 reg = <4>; 1330 funnel1_in4: endpoint { 1331 remote-endpoint = <&apss_merge_funnel_out>; 1332 }; 1333 }; 1334 }; 1335 }; 1336 1337 funnel@6045000 { 1338 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1339 reg = <0 0x06045000 0 0x1000>; 1340 1341 clocks = <&aoss_qmp>; 1342 clock-names = "apb_pclk"; 1343 1344 out-ports { 1345 port { 1346 merge_funnel_out: endpoint { 1347 remote-endpoint = <&swao_funnel_in>; 1348 }; 1349 }; 1350 }; 1351 1352 in-ports { 1353 #address-cells = <1>; 1354 #size-cells = <0>; 1355 1356 port@0 { 1357 reg = <0>; 1358 merge_funnel_in0: endpoint { 1359 remote-endpoint = <&funnel0_out>; 1360 }; 1361 }; 1362 1363 port@1 { 1364 reg = <1>; 1365 merge_funnel_in1: endpoint { 1366 remote-endpoint = <&funnel1_out>; 1367 }; 1368 }; 1369 }; 1370 }; 1371 1372 replicator@6046000 { 1373 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1374 reg = <0 0x06046000 0 0x1000>; 1375 1376 clocks = <&aoss_qmp>; 1377 clock-names = "apb_pclk"; 1378 1379 out-ports { 1380 port { 1381 replicator_out: endpoint { 1382 remote-endpoint = <&etr_in>; 1383 }; 1384 }; 1385 }; 1386 1387 in-ports { 1388 port { 1389 replicator_in: endpoint { 1390 remote-endpoint = <&swao_replicator_out>; 1391 }; 1392 }; 1393 }; 1394 }; 1395 1396 etr@6048000 { 1397 compatible = "arm,coresight-tmc", "arm,primecell"; 1398 reg = <0 0x06048000 0 0x1000>; 1399 iommus = <&apps_smmu 0x04c0 0>; 1400 1401 clocks = <&aoss_qmp>; 1402 clock-names = "apb_pclk"; 1403 arm,scatter-gather; 1404 1405 in-ports { 1406 port { 1407 etr_in: endpoint { 1408 remote-endpoint = <&replicator_out>; 1409 }; 1410 }; 1411 }; 1412 }; 1413 1414 funnel@6b04000 { 1415 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1416 reg = <0 0x06b04000 0 0x1000>; 1417 1418 clocks = <&aoss_qmp>; 1419 clock-names = "apb_pclk"; 1420 1421 out-ports { 1422 port { 1423 swao_funnel_out: endpoint { 1424 remote-endpoint = <&etf_in>; 1425 }; 1426 }; 1427 }; 1428 1429 in-ports { 1430 #address-cells = <1>; 1431 #size-cells = <0>; 1432 1433 port@7 { 1434 reg = <7>; 1435 swao_funnel_in: endpoint { 1436 remote-endpoint = <&merge_funnel_out>; 1437 }; 1438 }; 1439 }; 1440 }; 1441 1442 etf@6b05000 { 1443 compatible = "arm,coresight-tmc", "arm,primecell"; 1444 reg = <0 0x06b05000 0 0x1000>; 1445 1446 clocks = <&aoss_qmp>; 1447 clock-names = "apb_pclk"; 1448 1449 out-ports { 1450 port { 1451 etf_out: endpoint { 1452 remote-endpoint = <&swao_replicator_in>; 1453 }; 1454 }; 1455 }; 1456 1457 in-ports { 1458 port { 1459 etf_in: endpoint { 1460 remote-endpoint = <&swao_funnel_out>; 1461 }; 1462 }; 1463 }; 1464 }; 1465 1466 replicator@6b06000 { 1467 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1468 reg = <0 0x06b06000 0 0x1000>; 1469 1470 clocks = <&aoss_qmp>; 1471 clock-names = "apb_pclk"; 1472 qcom,replicator-loses-context; 1473 1474 out-ports { 1475 port { 1476 swao_replicator_out: endpoint { 1477 remote-endpoint = <&replicator_in>; 1478 }; 1479 }; 1480 }; 1481 1482 in-ports { 1483 port { 1484 swao_replicator_in: endpoint { 1485 remote-endpoint = <&etf_out>; 1486 }; 1487 }; 1488 }; 1489 }; 1490 1491 etm@7040000 { 1492 compatible = "arm,coresight-etm4x", "arm,primecell"; 1493 reg = <0 0x07040000 0 0x1000>; 1494 1495 cpu = <&CPU0>; 1496 1497 clocks = <&aoss_qmp>; 1498 clock-names = "apb_pclk"; 1499 arm,coresight-loses-context-with-cpu; 1500 qcom,skip-power-up; 1501 1502 out-ports { 1503 port { 1504 etm0_out: endpoint { 1505 remote-endpoint = <&apss_funnel_in0>; 1506 }; 1507 }; 1508 }; 1509 }; 1510 1511 etm@7140000 { 1512 compatible = "arm,coresight-etm4x", "arm,primecell"; 1513 reg = <0 0x07140000 0 0x1000>; 1514 1515 cpu = <&CPU1>; 1516 1517 clocks = <&aoss_qmp>; 1518 clock-names = "apb_pclk"; 1519 arm,coresight-loses-context-with-cpu; 1520 qcom,skip-power-up; 1521 1522 out-ports { 1523 port { 1524 etm1_out: endpoint { 1525 remote-endpoint = <&apss_funnel_in1>; 1526 }; 1527 }; 1528 }; 1529 }; 1530 1531 etm@7240000 { 1532 compatible = "arm,coresight-etm4x", "arm,primecell"; 1533 reg = <0 0x07240000 0 0x1000>; 1534 1535 cpu = <&CPU2>; 1536 1537 clocks = <&aoss_qmp>; 1538 clock-names = "apb_pclk"; 1539 arm,coresight-loses-context-with-cpu; 1540 qcom,skip-power-up; 1541 1542 out-ports { 1543 port { 1544 etm2_out: endpoint { 1545 remote-endpoint = <&apss_funnel_in2>; 1546 }; 1547 }; 1548 }; 1549 }; 1550 1551 etm@7340000 { 1552 compatible = "arm,coresight-etm4x", "arm,primecell"; 1553 reg = <0 0x07340000 0 0x1000>; 1554 1555 cpu = <&CPU3>; 1556 1557 clocks = <&aoss_qmp>; 1558 clock-names = "apb_pclk"; 1559 arm,coresight-loses-context-with-cpu; 1560 qcom,skip-power-up; 1561 1562 out-ports { 1563 port { 1564 etm3_out: endpoint { 1565 remote-endpoint = <&apss_funnel_in3>; 1566 }; 1567 }; 1568 }; 1569 }; 1570 1571 etm@7440000 { 1572 compatible = "arm,coresight-etm4x", "arm,primecell"; 1573 reg = <0 0x07440000 0 0x1000>; 1574 1575 cpu = <&CPU4>; 1576 1577 clocks = <&aoss_qmp>; 1578 clock-names = "apb_pclk"; 1579 arm,coresight-loses-context-with-cpu; 1580 qcom,skip-power-up; 1581 1582 out-ports { 1583 port { 1584 etm4_out: endpoint { 1585 remote-endpoint = <&apss_funnel_in4>; 1586 }; 1587 }; 1588 }; 1589 }; 1590 1591 etm@7540000 { 1592 compatible = "arm,coresight-etm4x", "arm,primecell"; 1593 reg = <0 0x07540000 0 0x1000>; 1594 1595 cpu = <&CPU5>; 1596 1597 clocks = <&aoss_qmp>; 1598 clock-names = "apb_pclk"; 1599 arm,coresight-loses-context-with-cpu; 1600 qcom,skip-power-up; 1601 1602 out-ports { 1603 port { 1604 etm5_out: endpoint { 1605 remote-endpoint = <&apss_funnel_in5>; 1606 }; 1607 }; 1608 }; 1609 }; 1610 1611 etm@7640000 { 1612 compatible = "arm,coresight-etm4x", "arm,primecell"; 1613 reg = <0 0x07640000 0 0x1000>; 1614 1615 cpu = <&CPU6>; 1616 1617 clocks = <&aoss_qmp>; 1618 clock-names = "apb_pclk"; 1619 arm,coresight-loses-context-with-cpu; 1620 qcom,skip-power-up; 1621 1622 out-ports { 1623 port { 1624 etm6_out: endpoint { 1625 remote-endpoint = <&apss_funnel_in6>; 1626 }; 1627 }; 1628 }; 1629 }; 1630 1631 etm@7740000 { 1632 compatible = "arm,coresight-etm4x", "arm,primecell"; 1633 reg = <0 0x07740000 0 0x1000>; 1634 1635 cpu = <&CPU7>; 1636 1637 clocks = <&aoss_qmp>; 1638 clock-names = "apb_pclk"; 1639 arm,coresight-loses-context-with-cpu; 1640 qcom,skip-power-up; 1641 1642 out-ports { 1643 port { 1644 etm7_out: endpoint { 1645 remote-endpoint = <&apss_funnel_in7>; 1646 }; 1647 }; 1648 }; 1649 }; 1650 1651 funnel@7800000 { /* APSS Funnel */ 1652 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1653 reg = <0 0x07800000 0 0x1000>; 1654 1655 clocks = <&aoss_qmp>; 1656 clock-names = "apb_pclk"; 1657 1658 out-ports { 1659 port { 1660 apss_funnel_out: endpoint { 1661 remote-endpoint = <&apss_merge_funnel_in>; 1662 }; 1663 }; 1664 }; 1665 1666 in-ports { 1667 #address-cells = <1>; 1668 #size-cells = <0>; 1669 1670 port@0 { 1671 reg = <0>; 1672 apss_funnel_in0: endpoint { 1673 remote-endpoint = <&etm0_out>; 1674 }; 1675 }; 1676 1677 port@1 { 1678 reg = <1>; 1679 apss_funnel_in1: endpoint { 1680 remote-endpoint = <&etm1_out>; 1681 }; 1682 }; 1683 1684 port@2 { 1685 reg = <2>; 1686 apss_funnel_in2: endpoint { 1687 remote-endpoint = <&etm2_out>; 1688 }; 1689 }; 1690 1691 port@3 { 1692 reg = <3>; 1693 apss_funnel_in3: endpoint { 1694 remote-endpoint = <&etm3_out>; 1695 }; 1696 }; 1697 1698 port@4 { 1699 reg = <4>; 1700 apss_funnel_in4: endpoint { 1701 remote-endpoint = <&etm4_out>; 1702 }; 1703 }; 1704 1705 port@5 { 1706 reg = <5>; 1707 apss_funnel_in5: endpoint { 1708 remote-endpoint = <&etm5_out>; 1709 }; 1710 }; 1711 1712 port@6 { 1713 reg = <6>; 1714 apss_funnel_in6: endpoint { 1715 remote-endpoint = <&etm6_out>; 1716 }; 1717 }; 1718 1719 port@7 { 1720 reg = <7>; 1721 apss_funnel_in7: endpoint { 1722 remote-endpoint = <&etm7_out>; 1723 }; 1724 }; 1725 }; 1726 }; 1727 1728 funnel@7810000 { 1729 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1730 reg = <0 0x07810000 0 0x1000>; 1731 1732 clocks = <&aoss_qmp>; 1733 clock-names = "apb_pclk"; 1734 1735 out-ports { 1736 port { 1737 apss_merge_funnel_out: endpoint { 1738 remote-endpoint = <&funnel1_in4>; 1739 }; 1740 }; 1741 }; 1742 1743 in-ports { 1744 port { 1745 apss_merge_funnel_in: endpoint { 1746 remote-endpoint = <&apss_funnel_out>; 1747 }; 1748 }; 1749 }; 1750 }; 1751 1752 sdhc_2: sdhci@8804000 { 1753 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 1754 status = "disabled"; 1755 1756 reg = <0 0x08804000 0 0x1000>; 1757 1758 iommus = <&apps_smmu 0x100 0x0>; 1759 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1761 interrupt-names = "hc_irq", "pwr_irq"; 1762 1763 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 1764 <&gcc GCC_SDCC2_AHB_CLK>, 1765 <&rpmhcc RPMH_CXO_CLK>; 1766 clock-names = "core", "iface", "xo"; 1767 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 1768 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 1769 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1770 power-domains = <&rpmhpd SC7280_CX>; 1771 operating-points-v2 = <&sdhc2_opp_table>; 1772 1773 bus-width = <4>; 1774 1775 qcom,dll-config = <0x0007642c>; 1776 1777 sdhc2_opp_table: opp-table { 1778 compatible = "operating-points-v2"; 1779 1780 opp-100000000 { 1781 opp-hz = /bits/ 64 <100000000>; 1782 required-opps = <&rpmhpd_opp_low_svs>; 1783 opp-peak-kBps = <1800000 400000>; 1784 opp-avg-kBps = <100000 0>; 1785 }; 1786 1787 opp-202000000 { 1788 opp-hz = /bits/ 64 <202000000>; 1789 required-opps = <&rpmhpd_opp_nom>; 1790 opp-peak-kBps = <5400000 1600000>; 1791 opp-avg-kBps = <200000 0>; 1792 }; 1793 }; 1794 1795 }; 1796 1797 usb_1_hsphy: phy@88e3000 { 1798 compatible = "qcom,sc7280-usb-hs-phy", 1799 "qcom,usb-snps-hs-7nm-phy"; 1800 reg = <0 0x088e3000 0 0x400>; 1801 status = "disabled"; 1802 #phy-cells = <0>; 1803 1804 clocks = <&rpmhcc RPMH_CXO_CLK>; 1805 clock-names = "ref"; 1806 1807 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1808 }; 1809 1810 usb_2_hsphy: phy@88e4000 { 1811 compatible = "qcom,sc7280-usb-hs-phy", 1812 "qcom,usb-snps-hs-7nm-phy"; 1813 reg = <0 0x088e4000 0 0x400>; 1814 status = "disabled"; 1815 #phy-cells = <0>; 1816 1817 clocks = <&rpmhcc RPMH_CXO_CLK>; 1818 clock-names = "ref"; 1819 1820 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1821 }; 1822 1823 usb_1_qmpphy: phy-wrapper@88e9000 { 1824 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 1825 "qcom,sm8250-qmp-usb3-dp-phy"; 1826 reg = <0 0x088e9000 0 0x200>, 1827 <0 0x088e8000 0 0x40>, 1828 <0 0x088ea000 0 0x200>; 1829 status = "disabled"; 1830 #address-cells = <2>; 1831 #size-cells = <2>; 1832 ranges; 1833 1834 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1835 <&rpmhcc RPMH_CXO_CLK>, 1836 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1837 clock-names = "aux", "ref_clk_src", "com_aux"; 1838 1839 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 1840 <&gcc GCC_USB3_PHY_PRIM_BCR>; 1841 reset-names = "phy", "common"; 1842 1843 usb_1_ssphy: usb3-phy@88e9200 { 1844 reg = <0 0x088e9200 0 0x200>, 1845 <0 0x088e9400 0 0x200>, 1846 <0 0x088e9c00 0 0x400>, 1847 <0 0x088e9600 0 0x200>, 1848 <0 0x088e9800 0 0x200>, 1849 <0 0x088e9a00 0 0x100>; 1850 #clock-cells = <0>; 1851 #phy-cells = <0>; 1852 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1853 clock-names = "pipe0"; 1854 clock-output-names = "usb3_phy_pipe_clk_src"; 1855 }; 1856 1857 dp_phy: dp-phy@88ea200 { 1858 reg = <0 0x088ea200 0 0x200>, 1859 <0 0x088ea400 0 0x200>, 1860 <0 0x088eaa00 0 0x200>, 1861 <0 0x088ea600 0 0x200>, 1862 <0 0x088ea800 0 0x200>; 1863 #phy-cells = <0>; 1864 #clock-cells = <1>; 1865 }; 1866 }; 1867 1868 usb_2: usb@8cf8800 { 1869 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 1870 reg = <0 0x08cf8800 0 0x400>; 1871 status = "disabled"; 1872 #address-cells = <2>; 1873 #size-cells = <2>; 1874 ranges; 1875 dma-ranges; 1876 1877 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 1878 <&gcc GCC_USB30_SEC_MASTER_CLK>, 1879 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 1880 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1881 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 1882 clock-names = "cfg_noc", "core", "iface","mock_utmi", 1883 "sleep"; 1884 1885 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1886 <&gcc GCC_USB30_SEC_MASTER_CLK>; 1887 assigned-clock-rates = <19200000>, <200000000>; 1888 1889 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1890 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 1891 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 1892 interrupt-names = "hs_phy_irq", 1893 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1894 1895 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 1896 1897 resets = <&gcc GCC_USB30_SEC_BCR>; 1898 1899 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 1900 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 1901 interconnect-names = "usb-ddr", "apps-usb"; 1902 1903 usb_2_dwc3: usb@8c00000 { 1904 compatible = "snps,dwc3"; 1905 reg = <0 0x08c00000 0 0xe000>; 1906 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1907 iommus = <&apps_smmu 0xa0 0x0>; 1908 snps,dis_u2_susphy_quirk; 1909 snps,dis_enblslpm_quirk; 1910 phys = <&usb_2_hsphy>; 1911 phy-names = "usb2-phy"; 1912 maximum-speed = "high-speed"; 1913 }; 1914 }; 1915 1916 qspi: spi@88dc000 { 1917 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 1918 reg = <0 0x088dc000 0 0x1000>; 1919 #address-cells = <1>; 1920 #size-cells = <0>; 1921 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1922 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 1923 <&gcc GCC_QSPI_CORE_CLK>; 1924 clock-names = "iface", "core"; 1925 interconnects = <&gem_noc MASTER_APPSS_PROC 0 1926 &cnoc2 SLAVE_QSPI_0 0>; 1927 interconnect-names = "qspi-config"; 1928 power-domains = <&rpmhpd SC7280_CX>; 1929 operating-points-v2 = <&qspi_opp_table>; 1930 status = "disabled"; 1931 }; 1932 1933 dc_noc: interconnect@90e0000 { 1934 reg = <0 0x090e0000 0 0x5080>; 1935 compatible = "qcom,sc7280-dc-noc"; 1936 #interconnect-cells = <2>; 1937 qcom,bcm-voters = <&apps_bcm_voter>; 1938 }; 1939 1940 gem_noc: interconnect@9100000 { 1941 reg = <0 0x9100000 0 0xe2200>; 1942 compatible = "qcom,sc7280-gem-noc"; 1943 #interconnect-cells = <2>; 1944 qcom,bcm-voters = <&apps_bcm_voter>; 1945 }; 1946 1947 system-cache-controller@9200000 { 1948 compatible = "qcom,sc7280-llcc"; 1949 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 1950 reg-names = "llcc_base", "llcc_broadcast_base"; 1951 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1952 }; 1953 1954 nsp_noc: interconnect@a0c0000 { 1955 reg = <0 0x0a0c0000 0 0x10000>; 1956 compatible = "qcom,sc7280-nsp-noc"; 1957 #interconnect-cells = <2>; 1958 qcom,bcm-voters = <&apps_bcm_voter>; 1959 }; 1960 1961 usb_1: usb@a6f8800 { 1962 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 1963 reg = <0 0x0a6f8800 0 0x400>; 1964 status = "disabled"; 1965 #address-cells = <2>; 1966 #size-cells = <2>; 1967 ranges; 1968 dma-ranges; 1969 1970 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1971 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1972 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1973 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1974 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 1975 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1976 "sleep"; 1977 1978 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1979 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1980 assigned-clock-rates = <19200000>, <200000000>; 1981 1982 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1983 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1984 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1985 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 1986 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 1987 "dm_hs_phy_irq", "ss_phy_irq"; 1988 1989 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1990 1991 resets = <&gcc GCC_USB30_PRIM_BCR>; 1992 1993 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 1994 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 1995 interconnect-names = "usb-ddr", "apps-usb"; 1996 1997 usb_1_dwc3: usb@a600000 { 1998 compatible = "snps,dwc3"; 1999 reg = <0 0x0a600000 0 0xe000>; 2000 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2001 iommus = <&apps_smmu 0xe0 0x0>; 2002 snps,dis_u2_susphy_quirk; 2003 snps,dis_enblslpm_quirk; 2004 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2005 phy-names = "usb2-phy", "usb3-phy"; 2006 maximum-speed = "super-speed"; 2007 }; 2008 }; 2009 2010 videocc: clock-controller@aaf0000 { 2011 compatible = "qcom,sc7280-videocc"; 2012 reg = <0 0xaaf0000 0 0x10000>; 2013 clocks = <&rpmhcc RPMH_CXO_CLK>, 2014 <&rpmhcc RPMH_CXO_CLK_A>; 2015 clock-names = "bi_tcxo", "bi_tcxo_ao"; 2016 #clock-cells = <1>; 2017 #reset-cells = <1>; 2018 #power-domain-cells = <1>; 2019 }; 2020 2021 dispcc: clock-controller@af00000 { 2022 compatible = "qcom,sc7280-dispcc"; 2023 reg = <0 0xaf00000 0 0x20000>; 2024 clocks = <&rpmhcc RPMH_CXO_CLK>, 2025 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2026 <0>, <0>, <0>, <0>, <0>, <0>; 2027 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 2028 "dsi0_phy_pll_out_byteclk", 2029 "dsi0_phy_pll_out_dsiclk", 2030 "dp_phy_pll_link_clk", 2031 "dp_phy_pll_vco_div_clk", 2032 "edp_phy_pll_link_clk", 2033 "edp_phy_pll_vco_div_clk"; 2034 #clock-cells = <1>; 2035 #reset-cells = <1>; 2036 #power-domain-cells = <1>; 2037 }; 2038 2039 pdc: interrupt-controller@b220000 { 2040 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 2041 reg = <0 0x0b220000 0 0x30000>; 2042 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 2043 <55 306 4>, <59 312 3>, <62 374 2>, 2044 <64 434 2>, <66 438 3>, <69 86 1>, 2045 <70 520 54>, <124 609 31>, <155 63 1>, 2046 <156 716 12>; 2047 #interrupt-cells = <2>; 2048 interrupt-parent = <&intc>; 2049 interrupt-controller; 2050 }; 2051 2052 pdc_reset: reset-controller@b5e0000 { 2053 compatible = "qcom,sc7280-pdc-global"; 2054 reg = <0 0x0b5e0000 0 0x20000>; 2055 #reset-cells = <1>; 2056 }; 2057 2058 tsens0: thermal-sensor@c263000 { 2059 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 2060 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2061 <0 0x0c222000 0 0x1ff>; /* SROT */ 2062 #qcom,sensors = <15>; 2063 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2064 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2065 interrupt-names = "uplow","critical"; 2066 #thermal-sensor-cells = <1>; 2067 }; 2068 2069 tsens1: thermal-sensor@c265000 { 2070 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 2071 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2072 <0 0x0c223000 0 0x1ff>; /* SROT */ 2073 #qcom,sensors = <12>; 2074 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2075 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2076 interrupt-names = "uplow","critical"; 2077 #thermal-sensor-cells = <1>; 2078 }; 2079 2080 aoss_reset: reset-controller@c2a0000 { 2081 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 2082 reg = <0 0x0c2a0000 0 0x31000>; 2083 #reset-cells = <1>; 2084 }; 2085 2086 aoss_qmp: power-controller@c300000 { 2087 compatible = "qcom,sc7280-aoss-qmp"; 2088 reg = <0 0x0c300000 0 0x100000>; 2089 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 2090 IPCC_MPROC_SIGNAL_GLINK_QMP 2091 IRQ_TYPE_EDGE_RISING>; 2092 mboxes = <&ipcc IPCC_CLIENT_AOP 2093 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2094 2095 #clock-cells = <0>; 2096 #power-domain-cells = <1>; 2097 }; 2098 2099 spmi_bus: spmi@c440000 { 2100 compatible = "qcom,spmi-pmic-arb"; 2101 reg = <0 0x0c440000 0 0x1100>, 2102 <0 0x0c600000 0 0x2000000>, 2103 <0 0x0e600000 0 0x100000>, 2104 <0 0x0e700000 0 0xa0000>, 2105 <0 0x0c40a000 0 0x26000>; 2106 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2107 interrupt-names = "periph_irq"; 2108 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2109 qcom,ee = <0>; 2110 qcom,channel = <0>; 2111 #address-cells = <1>; 2112 #size-cells = <1>; 2113 interrupt-controller; 2114 #interrupt-cells = <4>; 2115 }; 2116 2117 tlmm: pinctrl@f100000 { 2118 compatible = "qcom,sc7280-pinctrl"; 2119 reg = <0 0x0f100000 0 0x300000>; 2120 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2121 gpio-controller; 2122 #gpio-cells = <2>; 2123 interrupt-controller; 2124 #interrupt-cells = <2>; 2125 gpio-ranges = <&tlmm 0 0 175>; 2126 wakeup-parent = <&pdc>; 2127 2128 qspi_clk: qspi-clk { 2129 pins = "gpio14"; 2130 function = "qspi_clk"; 2131 }; 2132 2133 qspi_cs0: qspi-cs0 { 2134 pins = "gpio15"; 2135 function = "qspi_cs"; 2136 }; 2137 2138 qspi_cs1: qspi-cs1 { 2139 pins = "gpio19"; 2140 function = "qspi_cs"; 2141 }; 2142 2143 qspi_data01: qspi-data01 { 2144 pins = "gpio12", "gpio13"; 2145 function = "qspi_data"; 2146 }; 2147 2148 qspi_data12: qspi-data12 { 2149 pins = "gpio16", "gpio17"; 2150 function = "qspi_data"; 2151 }; 2152 2153 qup_i2c0_data_clk: qup-i2c0-data-clk { 2154 pins = "gpio0", "gpio1"; 2155 function = "qup00"; 2156 }; 2157 2158 qup_i2c1_data_clk: qup-i2c1-data-clk { 2159 pins = "gpio4", "gpio5"; 2160 function = "qup01"; 2161 }; 2162 2163 qup_i2c2_data_clk: qup-i2c2-data-clk { 2164 pins = "gpio8", "gpio9"; 2165 function = "qup02"; 2166 }; 2167 2168 qup_i2c3_data_clk: qup-i2c3-data-clk { 2169 pins = "gpio12", "gpio13"; 2170 function = "qup03"; 2171 }; 2172 2173 qup_i2c4_data_clk: qup-i2c4-data-clk { 2174 pins = "gpio16", "gpio17"; 2175 function = "qup04"; 2176 }; 2177 2178 qup_i2c5_data_clk: qup-i2c5-data-clk { 2179 pins = "gpio20", "gpio21"; 2180 function = "qup05"; 2181 }; 2182 2183 qup_i2c6_data_clk: qup-i2c6-data-clk { 2184 pins = "gpio24", "gpio25"; 2185 function = "qup06"; 2186 }; 2187 2188 qup_i2c7_data_clk: qup-i2c7-data-clk { 2189 pins = "gpio28", "gpio29"; 2190 function = "qup07"; 2191 }; 2192 2193 qup_spi0_data_clk: qup-spi0-data-clk { 2194 pins = "gpio0", "gpio1", "gpio2"; 2195 function = "qup00"; 2196 }; 2197 2198 qup_spi0_cs: qup-spi0-cs { 2199 pins = "gpio3"; 2200 function = "qup00"; 2201 }; 2202 2203 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 2204 pins = "gpio3"; 2205 function = "gpio"; 2206 }; 2207 2208 qup_spi1_data_clk: qup-spi1-data-clk { 2209 pins = "gpio4", "gpio5", "gpio6"; 2210 function = "qup01"; 2211 }; 2212 2213 qup_spi1_cs: qup-spi1-cs { 2214 pins = "gpio7"; 2215 function = "qup01"; 2216 }; 2217 2218 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 2219 pins = "gpio7"; 2220 function = "gpio"; 2221 }; 2222 2223 qup_spi2_data_clk: qup-spi2-data-clk { 2224 pins = "gpio8", "gpio9", "gpio10"; 2225 function = "qup02"; 2226 }; 2227 2228 qup_spi2_cs: qup-spi2-cs { 2229 pins = "gpio11"; 2230 function = "qup02"; 2231 }; 2232 2233 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 2234 pins = "gpio11"; 2235 function = "gpio"; 2236 }; 2237 2238 qup_spi3_data_clk: qup-spi3-data-clk { 2239 pins = "gpio12", "gpio13", "gpio14"; 2240 function = "qup03"; 2241 }; 2242 2243 qup_spi3_cs: qup-spi3-cs { 2244 pins = "gpio15"; 2245 function = "qup03"; 2246 }; 2247 2248 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 2249 pins = "gpio15"; 2250 function = "gpio"; 2251 }; 2252 2253 qup_spi4_data_clk: qup-spi4-data-clk { 2254 pins = "gpio16", "gpio17", "gpio18"; 2255 function = "qup04"; 2256 }; 2257 2258 qup_spi4_cs: qup-spi4-cs { 2259 pins = "gpio19"; 2260 function = "qup04"; 2261 }; 2262 2263 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 2264 pins = "gpio19"; 2265 function = "gpio"; 2266 }; 2267 2268 qup_spi5_data_clk: qup-spi5-data-clk { 2269 pins = "gpio20", "gpio21", "gpio22"; 2270 function = "qup05"; 2271 }; 2272 2273 qup_spi5_cs: qup-spi5-cs { 2274 pins = "gpio23"; 2275 function = "qup05"; 2276 }; 2277 2278 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 2279 pins = "gpio23"; 2280 function = "gpio"; 2281 }; 2282 2283 qup_spi6_data_clk: qup-spi6-data-clk { 2284 pins = "gpio24", "gpio25", "gpio26"; 2285 function = "qup06"; 2286 }; 2287 2288 qup_spi6_cs: qup-spi6-cs { 2289 pins = "gpio27"; 2290 function = "qup06"; 2291 }; 2292 2293 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 2294 pins = "gpio27"; 2295 function = "gpio"; 2296 }; 2297 2298 qup_spi7_data_clk: qup-spi7-data-clk { 2299 pins = "gpio28", "gpio29", "gpio30"; 2300 function = "qup07"; 2301 }; 2302 2303 qup_spi7_cs: qup-spi7-cs { 2304 pins = "gpio31"; 2305 function = "qup07"; 2306 }; 2307 2308 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 2309 pins = "gpio31"; 2310 function = "gpio"; 2311 }; 2312 2313 qup_uart0_cts: qup-uart0-cts { 2314 pins = "gpio0"; 2315 function = "qup00"; 2316 }; 2317 2318 qup_uart0_rts: qup-uart0-rts { 2319 pins = "gpio1"; 2320 function = "qup00"; 2321 }; 2322 2323 qup_uart0_tx: qup-uart0-tx { 2324 pins = "gpio2"; 2325 function = "qup00"; 2326 }; 2327 2328 qup_uart0_rx: qup-uart0-rx { 2329 pins = "gpio3"; 2330 function = "qup00"; 2331 }; 2332 2333 qup_uart1_cts: qup-uart1-cts { 2334 pins = "gpio4"; 2335 function = "qup01"; 2336 }; 2337 2338 qup_uart1_rts: qup-uart1-rts { 2339 pins = "gpio5"; 2340 function = "qup01"; 2341 }; 2342 2343 qup_uart1_tx: qup-uart1-tx { 2344 pins = "gpio6"; 2345 function = "qup01"; 2346 }; 2347 2348 qup_uart1_rx: qup-uart1-rx { 2349 pins = "gpio7"; 2350 function = "qup01"; 2351 }; 2352 2353 qup_uart2_cts: qup-uart2-cts { 2354 pins = "gpio8"; 2355 function = "qup02"; 2356 }; 2357 2358 qup_uart2_rts: qup-uart2-rts { 2359 pins = "gpio9"; 2360 function = "qup02"; 2361 }; 2362 2363 qup_uart2_tx: qup-uart2-tx { 2364 pins = "gpio10"; 2365 function = "qup02"; 2366 }; 2367 2368 qup_uart2_rx: qup-uart2-rx { 2369 pins = "gpio11"; 2370 function = "qup02"; 2371 }; 2372 2373 qup_uart3_cts: qup-uart3-cts { 2374 pins = "gpio12"; 2375 function = "qup03"; 2376 }; 2377 2378 qup_uart3_rts: qup-uart3-rts { 2379 pins = "gpio13"; 2380 function = "qup03"; 2381 }; 2382 2383 qup_uart3_tx: qup-uart3-tx { 2384 pins = "gpio14"; 2385 function = "qup03"; 2386 }; 2387 2388 qup_uart3_rx: qup-uart3-rx { 2389 pins = "gpio15"; 2390 function = "qup03"; 2391 }; 2392 2393 qup_uart4_cts: qup-uart4-cts { 2394 pins = "gpio16"; 2395 function = "qup04"; 2396 }; 2397 2398 qup_uart4_rts: qup-uart4-rts { 2399 pins = "gpio17"; 2400 function = "qup04"; 2401 }; 2402 2403 qup_uart4_tx: qup-uart4-tx { 2404 pins = "gpio18"; 2405 function = "qup04"; 2406 }; 2407 2408 qup_uart4_rx: qup-uart4-rx { 2409 pins = "gpio19"; 2410 function = "qup04"; 2411 }; 2412 2413 qup_uart5_cts: qup-uart5-cts { 2414 pins = "gpio20"; 2415 function = "qup05"; 2416 }; 2417 2418 qup_uart5_rts: qup-uart5-rts { 2419 pins = "gpio21"; 2420 function = "qup05"; 2421 }; 2422 2423 qup_uart5_tx: qup-uart5-tx { 2424 pins = "gpio22"; 2425 function = "qup05"; 2426 }; 2427 2428 qup_uart5_rx: qup-uart5-rx { 2429 pins = "gpio23"; 2430 function = "qup05"; 2431 }; 2432 2433 qup_uart6_cts: qup-uart6-cts { 2434 pins = "gpio24"; 2435 function = "qup06"; 2436 }; 2437 2438 qup_uart6_rts: qup-uart6-rts { 2439 pins = "gpio25"; 2440 function = "qup06"; 2441 }; 2442 2443 qup_uart6_tx: qup-uart6-tx { 2444 pins = "gpio26"; 2445 function = "qup06"; 2446 }; 2447 2448 qup_uart6_rx: qup-uart6-rx { 2449 pins = "gpio27"; 2450 function = "qup06"; 2451 }; 2452 2453 qup_uart7_cts: qup-uart7-cts { 2454 pins = "gpio28"; 2455 function = "qup07"; 2456 }; 2457 2458 qup_uart7_rts: qup-uart7-rts { 2459 pins = "gpio29"; 2460 function = "qup07"; 2461 }; 2462 2463 qup_uart7_tx: qup-uart7-tx { 2464 pins = "gpio30"; 2465 function = "qup07"; 2466 }; 2467 2468 qup_uart7_rx: qup-uart7-rx { 2469 pins = "gpio31"; 2470 function = "qup07"; 2471 }; 2472 2473 sdc1_on: sdc1-on { 2474 clk { 2475 pins = "sdc1_clk"; 2476 }; 2477 2478 cmd { 2479 pins = "sdc1_cmd"; 2480 }; 2481 2482 data { 2483 pins = "sdc1_data"; 2484 }; 2485 2486 rclk { 2487 pins = "sdc1_rclk"; 2488 }; 2489 }; 2490 2491 sdc1_off: sdc1-off { 2492 clk { 2493 pins = "sdc1_clk"; 2494 drive-strength = <2>; 2495 bias-bus-hold; 2496 }; 2497 2498 cmd { 2499 pins = "sdc1_cmd"; 2500 drive-strength = <2>; 2501 bias-bus-hold; 2502 }; 2503 2504 data { 2505 pins = "sdc1_data"; 2506 drive-strength = <2>; 2507 bias-bus-hold; 2508 }; 2509 2510 rclk { 2511 pins = "sdc1_rclk"; 2512 bias-bus-hold; 2513 }; 2514 }; 2515 2516 sdc2_on: sdc2-on { 2517 clk { 2518 pins = "sdc2_clk"; 2519 }; 2520 2521 cmd { 2522 pins = "sdc2_cmd"; 2523 }; 2524 2525 data { 2526 pins = "sdc2_data"; 2527 }; 2528 }; 2529 2530 sdc2_off: sdc2-off { 2531 clk { 2532 pins = "sdc2_clk"; 2533 drive-strength = <2>; 2534 bias-bus-hold; 2535 }; 2536 2537 cmd { 2538 pins ="sdc2_cmd"; 2539 drive-strength = <2>; 2540 bias-bus-hold; 2541 }; 2542 2543 data { 2544 pins ="sdc2_data"; 2545 drive-strength = <2>; 2546 bias-bus-hold; 2547 }; 2548 }; 2549 }; 2550 2551 apps_smmu: iommu@15000000 { 2552 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 2553 reg = <0 0x15000000 0 0x100000>; 2554 #iommu-cells = <2>; 2555 #global-interrupts = <1>; 2556 dma-coherent; 2557 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2558 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2559 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2560 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2561 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2562 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2563 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2564 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2565 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2566 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2567 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2568 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2569 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2570 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2571 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2572 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2573 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2574 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2575 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2576 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2577 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2578 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2579 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2580 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2581 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2582 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2583 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2584 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2585 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2586 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2587 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2588 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2589 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2590 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2591 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2592 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2593 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2594 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2595 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2596 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2597 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2598 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2599 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2600 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2601 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2602 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2603 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2604 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2605 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2606 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2607 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2608 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2609 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2610 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2611 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2612 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2613 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2614 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2615 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2616 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2617 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2618 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2619 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2620 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2621 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2622 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2623 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2624 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2625 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2626 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2627 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2628 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2629 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2630 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2631 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2632 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2633 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2634 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2635 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2636 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2637 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 2638 }; 2639 2640 intc: interrupt-controller@17a00000 { 2641 compatible = "arm,gic-v3"; 2642 #address-cells = <2>; 2643 #size-cells = <2>; 2644 ranges; 2645 #interrupt-cells = <3>; 2646 interrupt-controller; 2647 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 2648 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 2649 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 2650 2651 gic-its@17a40000 { 2652 compatible = "arm,gic-v3-its"; 2653 msi-controller; 2654 #msi-cells = <1>; 2655 reg = <0 0x17a40000 0 0x20000>; 2656 status = "disabled"; 2657 }; 2658 }; 2659 2660 watchdog@17c10000 { 2661 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 2662 reg = <0 0x17c10000 0 0x1000>; 2663 clocks = <&sleep_clk>; 2664 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 2665 }; 2666 2667 timer@17c20000 { 2668 #address-cells = <2>; 2669 #size-cells = <2>; 2670 ranges; 2671 compatible = "arm,armv7-timer-mem"; 2672 reg = <0 0x17c20000 0 0x1000>; 2673 2674 frame@17c21000 { 2675 frame-number = <0>; 2676 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2677 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2678 reg = <0 0x17c21000 0 0x1000>, 2679 <0 0x17c22000 0 0x1000>; 2680 }; 2681 2682 frame@17c23000 { 2683 frame-number = <1>; 2684 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2685 reg = <0 0x17c23000 0 0x1000>; 2686 status = "disabled"; 2687 }; 2688 2689 frame@17c25000 { 2690 frame-number = <2>; 2691 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2692 reg = <0 0x17c25000 0 0x1000>; 2693 status = "disabled"; 2694 }; 2695 2696 frame@17c27000 { 2697 frame-number = <3>; 2698 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2699 reg = <0 0x17c27000 0 0x1000>; 2700 status = "disabled"; 2701 }; 2702 2703 frame@17c29000 { 2704 frame-number = <4>; 2705 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2706 reg = <0 0x17c29000 0 0x1000>; 2707 status = "disabled"; 2708 }; 2709 2710 frame@17c2b000 { 2711 frame-number = <5>; 2712 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2713 reg = <0 0x17c2b000 0 0x1000>; 2714 status = "disabled"; 2715 }; 2716 2717 frame@17c2d000 { 2718 frame-number = <6>; 2719 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2720 reg = <0 0x17c2d000 0 0x1000>; 2721 status = "disabled"; 2722 }; 2723 }; 2724 2725 apps_rsc: rsc@18200000 { 2726 compatible = "qcom,rpmh-rsc"; 2727 reg = <0 0x18200000 0 0x10000>, 2728 <0 0x18210000 0 0x10000>, 2729 <0 0x18220000 0 0x10000>; 2730 reg-names = "drv-0", "drv-1", "drv-2"; 2731 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2732 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2733 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2734 qcom,tcs-offset = <0xd00>; 2735 qcom,drv-id = <2>; 2736 qcom,tcs-config = <ACTIVE_TCS 2>, 2737 <SLEEP_TCS 3>, 2738 <WAKE_TCS 3>, 2739 <CONTROL_TCS 1>; 2740 2741 apps_bcm_voter: bcm-voter { 2742 compatible = "qcom,bcm-voter"; 2743 }; 2744 2745 rpmhpd: power-controller { 2746 compatible = "qcom,sc7280-rpmhpd"; 2747 #power-domain-cells = <1>; 2748 operating-points-v2 = <&rpmhpd_opp_table>; 2749 2750 rpmhpd_opp_table: opp-table { 2751 compatible = "operating-points-v2"; 2752 2753 rpmhpd_opp_ret: opp1 { 2754 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2755 }; 2756 2757 rpmhpd_opp_low_svs: opp2 { 2758 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2759 }; 2760 2761 rpmhpd_opp_svs: opp3 { 2762 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2763 }; 2764 2765 rpmhpd_opp_svs_l1: opp4 { 2766 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2767 }; 2768 2769 rpmhpd_opp_svs_l2: opp5 { 2770 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2771 }; 2772 2773 rpmhpd_opp_nom: opp6 { 2774 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2775 }; 2776 2777 rpmhpd_opp_nom_l1: opp7 { 2778 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2779 }; 2780 2781 rpmhpd_opp_turbo: opp8 { 2782 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2783 }; 2784 2785 rpmhpd_opp_turbo_l1: opp9 { 2786 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2787 }; 2788 }; 2789 }; 2790 2791 rpmhcc: clock-controller { 2792 compatible = "qcom,sc7280-rpmh-clk"; 2793 clocks = <&xo_board>; 2794 clock-names = "xo"; 2795 #clock-cells = <1>; 2796 }; 2797 }; 2798 2799 cpufreq_hw: cpufreq@18591000 { 2800 compatible = "qcom,cpufreq-epss"; 2801 reg = <0 0x18591100 0 0x900>, 2802 <0 0x18592100 0 0x900>, 2803 <0 0x18593100 0 0x900>; 2804 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 2805 clock-names = "xo", "alternate"; 2806 #freq-domain-cells = <1>; 2807 }; 2808 }; 2809 2810 thermal_zones: thermal-zones { 2811 cpu0-thermal { 2812 polling-delay-passive = <250>; 2813 polling-delay = <0>; 2814 2815 thermal-sensors = <&tsens0 1>; 2816 2817 trips { 2818 cpu0_alert0: trip-point0 { 2819 temperature = <90000>; 2820 hysteresis = <2000>; 2821 type = "passive"; 2822 }; 2823 2824 cpu0_alert1: trip-point1 { 2825 temperature = <95000>; 2826 hysteresis = <2000>; 2827 type = "passive"; 2828 }; 2829 2830 cpu0_crit: cpu-crit { 2831 temperature = <110000>; 2832 hysteresis = <0>; 2833 type = "critical"; 2834 }; 2835 }; 2836 2837 cooling-maps { 2838 map0 { 2839 trip = <&cpu0_alert0>; 2840 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2841 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2842 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2843 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2844 }; 2845 map1 { 2846 trip = <&cpu0_alert1>; 2847 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2848 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2849 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2850 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2851 }; 2852 }; 2853 }; 2854 2855 cpu1-thermal { 2856 polling-delay-passive = <250>; 2857 polling-delay = <0>; 2858 2859 thermal-sensors = <&tsens0 2>; 2860 2861 trips { 2862 cpu1_alert0: trip-point0 { 2863 temperature = <90000>; 2864 hysteresis = <2000>; 2865 type = "passive"; 2866 }; 2867 2868 cpu1_alert1: trip-point1 { 2869 temperature = <95000>; 2870 hysteresis = <2000>; 2871 type = "passive"; 2872 }; 2873 2874 cpu1_crit: cpu-crit { 2875 temperature = <110000>; 2876 hysteresis = <0>; 2877 type = "critical"; 2878 }; 2879 }; 2880 2881 cooling-maps { 2882 map0 { 2883 trip = <&cpu1_alert0>; 2884 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2885 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2886 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2887 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2888 }; 2889 map1 { 2890 trip = <&cpu1_alert1>; 2891 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2892 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2893 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2894 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2895 }; 2896 }; 2897 }; 2898 2899 cpu2-thermal { 2900 polling-delay-passive = <250>; 2901 polling-delay = <0>; 2902 2903 thermal-sensors = <&tsens0 3>; 2904 2905 trips { 2906 cpu2_alert0: trip-point0 { 2907 temperature = <90000>; 2908 hysteresis = <2000>; 2909 type = "passive"; 2910 }; 2911 2912 cpu2_alert1: trip-point1 { 2913 temperature = <95000>; 2914 hysteresis = <2000>; 2915 type = "passive"; 2916 }; 2917 2918 cpu2_crit: cpu-crit { 2919 temperature = <110000>; 2920 hysteresis = <0>; 2921 type = "critical"; 2922 }; 2923 }; 2924 2925 cooling-maps { 2926 map0 { 2927 trip = <&cpu2_alert0>; 2928 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2929 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2930 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2931 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2932 }; 2933 map1 { 2934 trip = <&cpu2_alert1>; 2935 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2936 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2937 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2938 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2939 }; 2940 }; 2941 }; 2942 2943 cpu3-thermal { 2944 polling-delay-passive = <250>; 2945 polling-delay = <0>; 2946 2947 thermal-sensors = <&tsens0 4>; 2948 2949 trips { 2950 cpu3_alert0: trip-point0 { 2951 temperature = <90000>; 2952 hysteresis = <2000>; 2953 type = "passive"; 2954 }; 2955 2956 cpu3_alert1: trip-point1 { 2957 temperature = <95000>; 2958 hysteresis = <2000>; 2959 type = "passive"; 2960 }; 2961 2962 cpu3_crit: cpu-crit { 2963 temperature = <110000>; 2964 hysteresis = <0>; 2965 type = "critical"; 2966 }; 2967 }; 2968 2969 cooling-maps { 2970 map0 { 2971 trip = <&cpu3_alert0>; 2972 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2973 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2974 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2975 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2976 }; 2977 map1 { 2978 trip = <&cpu3_alert1>; 2979 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2980 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2981 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2982 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2983 }; 2984 }; 2985 }; 2986 2987 cpu4-thermal { 2988 polling-delay-passive = <250>; 2989 polling-delay = <0>; 2990 2991 thermal-sensors = <&tsens0 7>; 2992 2993 trips { 2994 cpu4_alert0: trip-point0 { 2995 temperature = <90000>; 2996 hysteresis = <2000>; 2997 type = "passive"; 2998 }; 2999 3000 cpu4_alert1: trip-point1 { 3001 temperature = <95000>; 3002 hysteresis = <2000>; 3003 type = "passive"; 3004 }; 3005 3006 cpu4_crit: cpu-crit { 3007 temperature = <110000>; 3008 hysteresis = <0>; 3009 type = "critical"; 3010 }; 3011 }; 3012 3013 cooling-maps { 3014 map0 { 3015 trip = <&cpu4_alert0>; 3016 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3017 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3018 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3019 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3020 }; 3021 map1 { 3022 trip = <&cpu4_alert1>; 3023 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3024 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3025 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3026 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3027 }; 3028 }; 3029 }; 3030 3031 cpu5-thermal { 3032 polling-delay-passive = <250>; 3033 polling-delay = <0>; 3034 3035 thermal-sensors = <&tsens0 8>; 3036 3037 trips { 3038 cpu5_alert0: trip-point0 { 3039 temperature = <90000>; 3040 hysteresis = <2000>; 3041 type = "passive"; 3042 }; 3043 3044 cpu5_alert1: trip-point1 { 3045 temperature = <95000>; 3046 hysteresis = <2000>; 3047 type = "passive"; 3048 }; 3049 3050 cpu5_crit: cpu-crit { 3051 temperature = <110000>; 3052 hysteresis = <0>; 3053 type = "critical"; 3054 }; 3055 }; 3056 3057 cooling-maps { 3058 map0 { 3059 trip = <&cpu5_alert0>; 3060 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3061 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3062 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3063 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3064 }; 3065 map1 { 3066 trip = <&cpu5_alert1>; 3067 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3068 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3069 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3070 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3071 }; 3072 }; 3073 }; 3074 3075 cpu6-thermal { 3076 polling-delay-passive = <250>; 3077 polling-delay = <0>; 3078 3079 thermal-sensors = <&tsens0 9>; 3080 3081 trips { 3082 cpu6_alert0: trip-point0 { 3083 temperature = <90000>; 3084 hysteresis = <2000>; 3085 type = "passive"; 3086 }; 3087 3088 cpu6_alert1: trip-point1 { 3089 temperature = <95000>; 3090 hysteresis = <2000>; 3091 type = "passive"; 3092 }; 3093 3094 cpu6_crit: cpu-crit { 3095 temperature = <110000>; 3096 hysteresis = <0>; 3097 type = "critical"; 3098 }; 3099 }; 3100 3101 cooling-maps { 3102 map0 { 3103 trip = <&cpu6_alert0>; 3104 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3105 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3106 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3107 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3108 }; 3109 map1 { 3110 trip = <&cpu6_alert1>; 3111 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3112 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3113 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3114 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3115 }; 3116 }; 3117 }; 3118 3119 cpu7-thermal { 3120 polling-delay-passive = <250>; 3121 polling-delay = <0>; 3122 3123 thermal-sensors = <&tsens0 10>; 3124 3125 trips { 3126 cpu7_alert0: trip-point0 { 3127 temperature = <90000>; 3128 hysteresis = <2000>; 3129 type = "passive"; 3130 }; 3131 3132 cpu7_alert1: trip-point1 { 3133 temperature = <95000>; 3134 hysteresis = <2000>; 3135 type = "passive"; 3136 }; 3137 3138 cpu7_crit: cpu-crit { 3139 temperature = <110000>; 3140 hysteresis = <0>; 3141 type = "critical"; 3142 }; 3143 }; 3144 3145 cooling-maps { 3146 map0 { 3147 trip = <&cpu7_alert0>; 3148 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3149 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3150 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3151 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3152 }; 3153 map1 { 3154 trip = <&cpu7_alert1>; 3155 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3156 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3157 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3158 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3159 }; 3160 }; 3161 }; 3162 3163 cpu8-thermal { 3164 polling-delay-passive = <250>; 3165 polling-delay = <0>; 3166 3167 thermal-sensors = <&tsens0 11>; 3168 3169 trips { 3170 cpu8_alert0: trip-point0 { 3171 temperature = <90000>; 3172 hysteresis = <2000>; 3173 type = "passive"; 3174 }; 3175 3176 cpu8_alert1: trip-point1 { 3177 temperature = <95000>; 3178 hysteresis = <2000>; 3179 type = "passive"; 3180 }; 3181 3182 cpu8_crit: cpu-crit { 3183 temperature = <110000>; 3184 hysteresis = <0>; 3185 type = "critical"; 3186 }; 3187 }; 3188 3189 cooling-maps { 3190 map0 { 3191 trip = <&cpu8_alert0>; 3192 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3193 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3194 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3195 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3196 }; 3197 map1 { 3198 trip = <&cpu8_alert1>; 3199 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3200 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3201 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3202 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3203 }; 3204 }; 3205 }; 3206 3207 cpu9-thermal { 3208 polling-delay-passive = <250>; 3209 polling-delay = <0>; 3210 3211 thermal-sensors = <&tsens0 12>; 3212 3213 trips { 3214 cpu9_alert0: trip-point0 { 3215 temperature = <90000>; 3216 hysteresis = <2000>; 3217 type = "passive"; 3218 }; 3219 3220 cpu9_alert1: trip-point1 { 3221 temperature = <95000>; 3222 hysteresis = <2000>; 3223 type = "passive"; 3224 }; 3225 3226 cpu9_crit: cpu-crit { 3227 temperature = <110000>; 3228 hysteresis = <0>; 3229 type = "critical"; 3230 }; 3231 }; 3232 3233 cooling-maps { 3234 map0 { 3235 trip = <&cpu9_alert0>; 3236 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3237 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3238 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3239 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3240 }; 3241 map1 { 3242 trip = <&cpu9_alert1>; 3243 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3244 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3245 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3246 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3247 }; 3248 }; 3249 }; 3250 3251 cpu10-thermal { 3252 polling-delay-passive = <250>; 3253 polling-delay = <0>; 3254 3255 thermal-sensors = <&tsens0 13>; 3256 3257 trips { 3258 cpu10_alert0: trip-point0 { 3259 temperature = <90000>; 3260 hysteresis = <2000>; 3261 type = "passive"; 3262 }; 3263 3264 cpu10_alert1: trip-point1 { 3265 temperature = <95000>; 3266 hysteresis = <2000>; 3267 type = "passive"; 3268 }; 3269 3270 cpu10_crit: cpu-crit { 3271 temperature = <110000>; 3272 hysteresis = <0>; 3273 type = "critical"; 3274 }; 3275 }; 3276 3277 cooling-maps { 3278 map0 { 3279 trip = <&cpu10_alert0>; 3280 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3281 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3282 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3283 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3284 }; 3285 map1 { 3286 trip = <&cpu10_alert1>; 3287 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3288 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3289 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3290 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3291 }; 3292 }; 3293 }; 3294 3295 cpu11-thermal { 3296 polling-delay-passive = <250>; 3297 polling-delay = <0>; 3298 3299 thermal-sensors = <&tsens0 14>; 3300 3301 trips { 3302 cpu11_alert0: trip-point0 { 3303 temperature = <90000>; 3304 hysteresis = <2000>; 3305 type = "passive"; 3306 }; 3307 3308 cpu11_alert1: trip-point1 { 3309 temperature = <95000>; 3310 hysteresis = <2000>; 3311 type = "passive"; 3312 }; 3313 3314 cpu11_crit: cpu-crit { 3315 temperature = <110000>; 3316 hysteresis = <0>; 3317 type = "critical"; 3318 }; 3319 }; 3320 3321 cooling-maps { 3322 map0 { 3323 trip = <&cpu11_alert0>; 3324 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3325 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3326 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3327 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3328 }; 3329 map1 { 3330 trip = <&cpu11_alert1>; 3331 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3332 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3333 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3334 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3335 }; 3336 }; 3337 }; 3338 3339 aoss0-thermal { 3340 polling-delay-passive = <0>; 3341 polling-delay = <0>; 3342 3343 thermal-sensors = <&tsens0 0>; 3344 3345 trips { 3346 aoss0_alert0: trip-point0 { 3347 temperature = <90000>; 3348 hysteresis = <2000>; 3349 type = "hot"; 3350 }; 3351 3352 aoss0_crit: aoss0-crit { 3353 temperature = <110000>; 3354 hysteresis = <0>; 3355 type = "critical"; 3356 }; 3357 }; 3358 }; 3359 3360 aoss1-thermal { 3361 polling-delay-passive = <0>; 3362 polling-delay = <0>; 3363 3364 thermal-sensors = <&tsens1 0>; 3365 3366 trips { 3367 aoss1_alert0: trip-point0 { 3368 temperature = <90000>; 3369 hysteresis = <2000>; 3370 type = "hot"; 3371 }; 3372 3373 aoss1_crit: aoss1-crit { 3374 temperature = <110000>; 3375 hysteresis = <0>; 3376 type = "critical"; 3377 }; 3378 }; 3379 }; 3380 3381 cpuss0-thermal { 3382 polling-delay-passive = <0>; 3383 polling-delay = <0>; 3384 3385 thermal-sensors = <&tsens0 5>; 3386 3387 trips { 3388 cpuss0_alert0: trip-point0 { 3389 temperature = <90000>; 3390 hysteresis = <2000>; 3391 type = "hot"; 3392 }; 3393 cpuss0_crit: cluster0-crit { 3394 temperature = <110000>; 3395 hysteresis = <0>; 3396 type = "critical"; 3397 }; 3398 }; 3399 }; 3400 3401 cpuss1-thermal { 3402 polling-delay-passive = <0>; 3403 polling-delay = <0>; 3404 3405 thermal-sensors = <&tsens0 6>; 3406 3407 trips { 3408 cpuss1_alert0: trip-point0 { 3409 temperature = <90000>; 3410 hysteresis = <2000>; 3411 type = "hot"; 3412 }; 3413 cpuss1_crit: cluster0-crit { 3414 temperature = <110000>; 3415 hysteresis = <0>; 3416 type = "critical"; 3417 }; 3418 }; 3419 }; 3420 3421 gpuss0-thermal { 3422 polling-delay-passive = <100>; 3423 polling-delay = <0>; 3424 3425 thermal-sensors = <&tsens1 1>; 3426 3427 trips { 3428 gpuss0_alert0: trip-point0 { 3429 temperature = <95000>; 3430 hysteresis = <2000>; 3431 type = "passive"; 3432 }; 3433 3434 gpuss0_crit: gpuss0-crit { 3435 temperature = <110000>; 3436 hysteresis = <0>; 3437 type = "critical"; 3438 }; 3439 }; 3440 3441 cooling-maps { 3442 map0 { 3443 trip = <&gpuss0_alert0>; 3444 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3445 }; 3446 }; 3447 }; 3448 3449 gpuss1-thermal { 3450 polling-delay-passive = <100>; 3451 polling-delay = <0>; 3452 3453 thermal-sensors = <&tsens1 2>; 3454 3455 trips { 3456 gpuss1_alert0: trip-point0 { 3457 temperature = <95000>; 3458 hysteresis = <2000>; 3459 type = "passive"; 3460 }; 3461 3462 gpuss1_crit: gpuss1-crit { 3463 temperature = <110000>; 3464 hysteresis = <0>; 3465 type = "critical"; 3466 }; 3467 }; 3468 3469 cooling-maps { 3470 map0 { 3471 trip = <&gpuss1_alert0>; 3472 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3473 }; 3474 }; 3475 }; 3476 3477 nspss0-thermal { 3478 polling-delay-passive = <0>; 3479 polling-delay = <0>; 3480 3481 thermal-sensors = <&tsens1 3>; 3482 3483 trips { 3484 nspss0_alert0: trip-point0 { 3485 temperature = <90000>; 3486 hysteresis = <2000>; 3487 type = "hot"; 3488 }; 3489 3490 nspss0_crit: nspss0-crit { 3491 temperature = <110000>; 3492 hysteresis = <0>; 3493 type = "critical"; 3494 }; 3495 }; 3496 }; 3497 3498 nspss1-thermal { 3499 polling-delay-passive = <0>; 3500 polling-delay = <0>; 3501 3502 thermal-sensors = <&tsens1 4>; 3503 3504 trips { 3505 nspss1_alert0: trip-point0 { 3506 temperature = <90000>; 3507 hysteresis = <2000>; 3508 type = "hot"; 3509 }; 3510 3511 nspss1_crit: nspss1-crit { 3512 temperature = <110000>; 3513 hysteresis = <0>; 3514 type = "critical"; 3515 }; 3516 }; 3517 }; 3518 3519 video-thermal { 3520 polling-delay-passive = <0>; 3521 polling-delay = <0>; 3522 3523 thermal-sensors = <&tsens1 5>; 3524 3525 trips { 3526 video_alert0: trip-point0 { 3527 temperature = <90000>; 3528 hysteresis = <2000>; 3529 type = "hot"; 3530 }; 3531 3532 video_crit: video-crit { 3533 temperature = <110000>; 3534 hysteresis = <0>; 3535 type = "critical"; 3536 }; 3537 }; 3538 }; 3539 3540 ddr-thermal { 3541 polling-delay-passive = <0>; 3542 polling-delay = <0>; 3543 3544 thermal-sensors = <&tsens1 6>; 3545 3546 trips { 3547 ddr_alert0: trip-point0 { 3548 temperature = <90000>; 3549 hysteresis = <2000>; 3550 type = "hot"; 3551 }; 3552 3553 ddr_crit: ddr-crit { 3554 temperature = <110000>; 3555 hysteresis = <0>; 3556 type = "critical"; 3557 }; 3558 }; 3559 }; 3560 3561 mdmss0-thermal { 3562 polling-delay-passive = <0>; 3563 polling-delay = <0>; 3564 3565 thermal-sensors = <&tsens1 7>; 3566 3567 trips { 3568 mdmss0_alert0: trip-point0 { 3569 temperature = <90000>; 3570 hysteresis = <2000>; 3571 type = "hot"; 3572 }; 3573 3574 mdmss0_crit: mdmss0-crit { 3575 temperature = <110000>; 3576 hysteresis = <0>; 3577 type = "critical"; 3578 }; 3579 }; 3580 }; 3581 3582 mdmss1-thermal { 3583 polling-delay-passive = <0>; 3584 polling-delay = <0>; 3585 3586 thermal-sensors = <&tsens1 8>; 3587 3588 trips { 3589 mdmss1_alert0: trip-point0 { 3590 temperature = <90000>; 3591 hysteresis = <2000>; 3592 type = "hot"; 3593 }; 3594 3595 mdmss1_crit: mdmss1-crit { 3596 temperature = <110000>; 3597 hysteresis = <0>; 3598 type = "critical"; 3599 }; 3600 }; 3601 }; 3602 3603 mdmss2-thermal { 3604 polling-delay-passive = <0>; 3605 polling-delay = <0>; 3606 3607 thermal-sensors = <&tsens1 9>; 3608 3609 trips { 3610 mdmss2_alert0: trip-point0 { 3611 temperature = <90000>; 3612 hysteresis = <2000>; 3613 type = "hot"; 3614 }; 3615 3616 mdmss2_crit: mdmss2-crit { 3617 temperature = <110000>; 3618 hysteresis = <0>; 3619 type = "critical"; 3620 }; 3621 }; 3622 }; 3623 3624 mdmss3-thermal { 3625 polling-delay-passive = <0>; 3626 polling-delay = <0>; 3627 3628 thermal-sensors = <&tsens1 10>; 3629 3630 trips { 3631 mdmss3_alert0: trip-point0 { 3632 temperature = <90000>; 3633 hysteresis = <2000>; 3634 type = "hot"; 3635 }; 3636 3637 mdmss3_crit: mdmss3-crit { 3638 temperature = <110000>; 3639 hysteresis = <0>; 3640 type = "critical"; 3641 }; 3642 }; 3643 }; 3644 3645 camera0-thermal { 3646 polling-delay-passive = <0>; 3647 polling-delay = <0>; 3648 3649 thermal-sensors = <&tsens1 11>; 3650 3651 trips { 3652 camera0_alert0: trip-point0 { 3653 temperature = <90000>; 3654 hysteresis = <2000>; 3655 type = "hot"; 3656 }; 3657 3658 camera0_crit: camera0-crit { 3659 temperature = <110000>; 3660 hysteresis = <0>; 3661 type = "critical"; 3662 }; 3663 }; 3664 }; 3665 }; 3666 3667 timer { 3668 compatible = "arm,armv8-timer"; 3669 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 3670 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 3671 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 3672 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 3673 }; 3674}; 3675