1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-sc7280.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11 12/ { 13 interrupt-parent = <&intc>; 14 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 chosen { }; 19 20 clocks { 21 xo_board: xo-board { 22 compatible = "fixed-clock"; 23 clock-frequency = <76800000>; 24 #clock-cells = <0>; 25 }; 26 27 sleep_clk: sleep-clk { 28 compatible = "fixed-clock"; 29 clock-frequency = <32000>; 30 #clock-cells = <0>; 31 }; 32 }; 33 34 reserved-memory { 35 #address-cells = <2>; 36 #size-cells = <2>; 37 ranges; 38 39 aop_cmd_db_mem: memory@80860000 { 40 reg = <0x0 0x80860000 0x0 0x20000>; 41 compatible = "qcom,cmd-db"; 42 no-map; 43 }; 44 }; 45 46 cpus { 47 #address-cells = <2>; 48 #size-cells = <0>; 49 50 CPU0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,kryo"; 53 reg = <0x0 0x0>; 54 enable-method = "psci"; 55 next-level-cache = <&L2_0>; 56 L2_0: l2-cache { 57 compatible = "cache"; 58 next-level-cache = <&L3_0>; 59 L3_0: l3-cache { 60 compatible = "cache"; 61 }; 62 }; 63 }; 64 65 CPU1: cpu@100 { 66 device_type = "cpu"; 67 compatible = "arm,kryo"; 68 reg = <0x0 0x100>; 69 enable-method = "psci"; 70 next-level-cache = <&L2_100>; 71 L2_100: l2-cache { 72 compatible = "cache"; 73 next-level-cache = <&L3_0>; 74 }; 75 }; 76 77 CPU2: cpu@200 { 78 device_type = "cpu"; 79 compatible = "arm,kryo"; 80 reg = <0x0 0x200>; 81 enable-method = "psci"; 82 next-level-cache = <&L2_200>; 83 L2_200: l2-cache { 84 compatible = "cache"; 85 next-level-cache = <&L3_0>; 86 }; 87 }; 88 89 CPU3: cpu@300 { 90 device_type = "cpu"; 91 compatible = "arm,kryo"; 92 reg = <0x0 0x300>; 93 enable-method = "psci"; 94 next-level-cache = <&L2_300>; 95 L2_300: l2-cache { 96 compatible = "cache"; 97 next-level-cache = <&L3_0>; 98 }; 99 }; 100 101 CPU4: cpu@400 { 102 device_type = "cpu"; 103 compatible = "arm,kryo"; 104 reg = <0x0 0x400>; 105 enable-method = "psci"; 106 next-level-cache = <&L2_400>; 107 L2_400: l2-cache { 108 compatible = "cache"; 109 next-level-cache = <&L3_0>; 110 }; 111 }; 112 113 CPU5: cpu@500 { 114 device_type = "cpu"; 115 compatible = "arm,kryo"; 116 reg = <0x0 0x500>; 117 enable-method = "psci"; 118 next-level-cache = <&L2_500>; 119 L2_500: l2-cache { 120 compatible = "cache"; 121 next-level-cache = <&L3_0>; 122 }; 123 }; 124 125 CPU6: cpu@600 { 126 device_type = "cpu"; 127 compatible = "arm,kryo"; 128 reg = <0x0 0x600>; 129 enable-method = "psci"; 130 next-level-cache = <&L2_600>; 131 L2_600: l2-cache { 132 compatible = "cache"; 133 next-level-cache = <&L3_0>; 134 }; 135 }; 136 137 CPU7: cpu@700 { 138 device_type = "cpu"; 139 compatible = "arm,kryo"; 140 reg = <0x0 0x700>; 141 enable-method = "psci"; 142 next-level-cache = <&L2_700>; 143 L2_700: l2-cache { 144 compatible = "cache"; 145 next-level-cache = <&L3_0>; 146 }; 147 }; 148 }; 149 150 memory@80000000 { 151 device_type = "memory"; 152 /* We expect the bootloader to fill in the size */ 153 reg = <0 0x80000000 0 0>; 154 }; 155 156 firmware { 157 scm { 158 compatible = "qcom,scm-sc7280", "qcom,scm"; 159 }; 160 }; 161 162 pmu { 163 compatible = "arm,armv8-pmuv3"; 164 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 165 }; 166 167 psci { 168 compatible = "arm,psci-1.0"; 169 method = "smc"; 170 }; 171 172 soc: soc@0 { 173 #address-cells = <2>; 174 #size-cells = <2>; 175 ranges = <0 0 0 0 0x10 0>; 176 dma-ranges = <0 0 0 0 0x10 0>; 177 compatible = "simple-bus"; 178 179 gcc: clock-controller@100000 { 180 compatible = "qcom,gcc-sc7280"; 181 reg = <0 0x00100000 0 0x1f0000>; 182 #clock-cells = <1>; 183 #reset-cells = <1>; 184 #power-domain-cells = <1>; 185 }; 186 187 qupv3_id_0: geniqup@9c0000 { 188 compatible = "qcom,geni-se-qup"; 189 reg = <0 0x009c0000 0 0x2000>; 190 clock-names = "m-ahb", "s-ahb"; 191 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 192 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 193 #address-cells = <2>; 194 #size-cells = <2>; 195 ranges; 196 status = "disabled"; 197 198 uart5: serial@994000 { 199 compatible = "qcom,geni-debug-uart"; 200 reg = <0 0x00994000 0 0x4000>; 201 clock-names = "se"; 202 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 203 pinctrl-names = "default"; 204 pinctrl-0 = <&qup_uart5_default>; 205 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 206 status = "disabled"; 207 }; 208 }; 209 210 pdc: interrupt-controller@b220000 { 211 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 212 reg = <0 0x0b220000 0 0x30000>; 213 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 214 <55 306 4>, <59 312 3>, <62 374 2>, 215 <64 434 2>, <66 438 3>, <69 86 1>, 216 <70 520 54>, <124 609 31>, <155 63 1>, 217 <156 716 12>; 218 #interrupt-cells = <2>; 219 interrupt-parent = <&intc>; 220 interrupt-controller; 221 }; 222 223 tlmm: pinctrl@f100000 { 224 compatible = "qcom,sc7280-pinctrl"; 225 reg = <0 0x0f100000 0 0x300000>; 226 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 227 gpio-controller; 228 #gpio-cells = <2>; 229 interrupt-controller; 230 #interrupt-cells = <2>; 231 gpio-ranges = <&tlmm 0 0 175>; 232 wakeup-parent = <&pdc>; 233 234 qup_uart5_default: qup-uart5-default { 235 pins = "gpio46", "gpio47"; 236 function = "qup13"; 237 }; 238 }; 239 240 intc: interrupt-controller@17a00000 { 241 compatible = "arm,gic-v3"; 242 #address-cells = <2>; 243 #size-cells = <2>; 244 ranges; 245 #interrupt-cells = <3>; 246 interrupt-controller; 247 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 248 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 249 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 250 251 gic-its@17a40000 { 252 compatible = "arm,gic-v3-its"; 253 msi-controller; 254 #msi-cells = <1>; 255 reg = <0 0x17a40000 0 0x20000>; 256 status = "disabled"; 257 }; 258 }; 259 260 timer@17c20000 { 261 #address-cells = <2>; 262 #size-cells = <2>; 263 ranges; 264 compatible = "arm,armv7-timer-mem"; 265 reg = <0 0x17c20000 0 0x1000>; 266 267 frame@17c21000 { 268 frame-number = <0>; 269 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 271 reg = <0 0x17c21000 0 0x1000>, 272 <0 0x17c22000 0 0x1000>; 273 }; 274 275 frame@17c23000 { 276 frame-number = <1>; 277 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 278 reg = <0 0x17c23000 0 0x1000>; 279 status = "disabled"; 280 }; 281 282 frame@17c25000 { 283 frame-number = <2>; 284 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 285 reg = <0 0x17c25000 0 0x1000>; 286 status = "disabled"; 287 }; 288 289 frame@17c27000 { 290 frame-number = <3>; 291 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 292 reg = <0 0x17c27000 0 0x1000>; 293 status = "disabled"; 294 }; 295 296 frame@17c29000 { 297 frame-number = <4>; 298 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 299 reg = <0 0x17c29000 0 0x1000>; 300 status = "disabled"; 301 }; 302 303 frame@17c2b000 { 304 frame-number = <5>; 305 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 306 reg = <0 0x17c2b000 0 0x1000>; 307 status = "disabled"; 308 }; 309 310 frame@17c2d000 { 311 frame-number = <6>; 312 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 313 reg = <0 0x17c2d000 0 0x1000>; 314 status = "disabled"; 315 }; 316 }; 317 318 apps_rsc: rsc@18200000 { 319 compatible = "qcom,rpmh-rsc"; 320 reg = <0 0x18200000 0 0x10000>, 321 <0 0x18210000 0 0x10000>, 322 <0 0x18220000 0 0x10000>; 323 reg-names = "drv-0", "drv-1", "drv-2"; 324 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 327 qcom,tcs-offset = <0xd00>; 328 qcom,drv-id = <2>; 329 qcom,tcs-config = <ACTIVE_TCS 2>, 330 <SLEEP_TCS 3>, 331 <WAKE_TCS 3>, 332 <CONTROL_TCS 1>; 333 }; 334 }; 335 336 timer { 337 compatible = "arm,armv8-timer"; 338 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 339 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 340 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 341 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 342 }; 343}; 344