1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,lpass.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 mmc1 = &sdhc_1; 54 mmc2 = &sdhc_2; 55 spi0 = &spi0; 56 spi1 = &spi1; 57 spi2 = &spi2; 58 spi3 = &spi3; 59 spi4 = &spi4; 60 spi5 = &spi5; 61 spi6 = &spi6; 62 spi7 = &spi7; 63 spi8 = &spi8; 64 spi9 = &spi9; 65 spi10 = &spi10; 66 spi11 = &spi11; 67 spi12 = &spi12; 68 spi13 = &spi13; 69 spi14 = &spi14; 70 spi15 = &spi15; 71 }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 clock-frequency = <76800000>; 77 #clock-cells = <0>; 78 }; 79 80 sleep_clk: sleep-clk { 81 compatible = "fixed-clock"; 82 clock-frequency = <32000>; 83 #clock-cells = <0>; 84 }; 85 }; 86 87 reserved-memory { 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges; 91 92 wlan_ce_mem: memory@4cd000 { 93 no-map; 94 reg = <0x0 0x004cd000 0x0 0x1000>; 95 }; 96 97 hyp_mem: memory@80000000 { 98 reg = <0x0 0x80000000 0x0 0x600000>; 99 no-map; 100 }; 101 102 xbl_mem: memory@80600000 { 103 reg = <0x0 0x80600000 0x0 0x200000>; 104 no-map; 105 }; 106 107 aop_mem: memory@80800000 { 108 reg = <0x0 0x80800000 0x0 0x60000>; 109 no-map; 110 }; 111 112 aop_cmd_db_mem: memory@80860000 { 113 reg = <0x0 0x80860000 0x0 0x20000>; 114 compatible = "qcom,cmd-db"; 115 no-map; 116 }; 117 118 reserved_xbl_uefi_log: memory@80880000 { 119 reg = <0x0 0x80884000 0x0 0x10000>; 120 no-map; 121 }; 122 123 sec_apps_mem: memory@808ff000 { 124 reg = <0x0 0x808ff000 0x0 0x1000>; 125 no-map; 126 }; 127 128 smem_mem: memory@80900000 { 129 reg = <0x0 0x80900000 0x0 0x200000>; 130 no-map; 131 }; 132 133 cpucp_mem: memory@80b00000 { 134 no-map; 135 reg = <0x0 0x80b00000 0x0 0x100000>; 136 }; 137 138 wlan_fw_mem: memory@80c00000 { 139 reg = <0x0 0x80c00000 0x0 0xc00000>; 140 no-map; 141 }; 142 143 video_mem: memory@8b200000 { 144 reg = <0x0 0x8b200000 0x0 0x500000>; 145 no-map; 146 }; 147 148 ipa_fw_mem: memory@8b700000 { 149 reg = <0 0x8b700000 0 0x10000>; 150 no-map; 151 }; 152 153 rmtfs_mem: memory@9c900000 { 154 compatible = "qcom,rmtfs-mem"; 155 reg = <0x0 0x9c900000 0x0 0x280000>; 156 no-map; 157 158 qcom,client-id = <1>; 159 qcom,vmid = <15>; 160 }; 161 }; 162 163 cpus { 164 #address-cells = <2>; 165 #size-cells = <0>; 166 167 CPU0: cpu@0 { 168 device_type = "cpu"; 169 compatible = "qcom,kryo"; 170 reg = <0x0 0x0>; 171 clocks = <&cpufreq_hw 0>; 172 enable-method = "psci"; 173 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 174 &LITTLE_CPU_SLEEP_1 175 &CLUSTER_SLEEP_0>; 176 next-level-cache = <&L2_0>; 177 operating-points-v2 = <&cpu0_opp_table>; 178 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 179 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 180 qcom,freq-domain = <&cpufreq_hw 0>; 181 #cooling-cells = <2>; 182 L2_0: l2-cache { 183 compatible = "cache"; 184 cache-level = <2>; 185 cache-unified; 186 next-level-cache = <&L3_0>; 187 L3_0: l3-cache { 188 compatible = "cache"; 189 cache-level = <3>; 190 cache-unified; 191 }; 192 }; 193 }; 194 195 CPU1: cpu@100 { 196 device_type = "cpu"; 197 compatible = "qcom,kryo"; 198 reg = <0x0 0x100>; 199 clocks = <&cpufreq_hw 0>; 200 enable-method = "psci"; 201 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 202 &LITTLE_CPU_SLEEP_1 203 &CLUSTER_SLEEP_0>; 204 next-level-cache = <&L2_100>; 205 operating-points-v2 = <&cpu0_opp_table>; 206 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 207 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 208 qcom,freq-domain = <&cpufreq_hw 0>; 209 #cooling-cells = <2>; 210 L2_100: l2-cache { 211 compatible = "cache"; 212 cache-level = <2>; 213 cache-unified; 214 next-level-cache = <&L3_0>; 215 }; 216 }; 217 218 CPU2: cpu@200 { 219 device_type = "cpu"; 220 compatible = "qcom,kryo"; 221 reg = <0x0 0x200>; 222 clocks = <&cpufreq_hw 0>; 223 enable-method = "psci"; 224 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 225 &LITTLE_CPU_SLEEP_1 226 &CLUSTER_SLEEP_0>; 227 next-level-cache = <&L2_200>; 228 operating-points-v2 = <&cpu0_opp_table>; 229 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 230 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 231 qcom,freq-domain = <&cpufreq_hw 0>; 232 #cooling-cells = <2>; 233 L2_200: l2-cache { 234 compatible = "cache"; 235 cache-level = <2>; 236 cache-unified; 237 next-level-cache = <&L3_0>; 238 }; 239 }; 240 241 CPU3: cpu@300 { 242 device_type = "cpu"; 243 compatible = "qcom,kryo"; 244 reg = <0x0 0x300>; 245 clocks = <&cpufreq_hw 0>; 246 enable-method = "psci"; 247 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 248 &LITTLE_CPU_SLEEP_1 249 &CLUSTER_SLEEP_0>; 250 next-level-cache = <&L2_300>; 251 operating-points-v2 = <&cpu0_opp_table>; 252 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 253 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 254 qcom,freq-domain = <&cpufreq_hw 0>; 255 #cooling-cells = <2>; 256 L2_300: l2-cache { 257 compatible = "cache"; 258 cache-level = <2>; 259 cache-unified; 260 next-level-cache = <&L3_0>; 261 }; 262 }; 263 264 CPU4: cpu@400 { 265 device_type = "cpu"; 266 compatible = "qcom,kryo"; 267 reg = <0x0 0x400>; 268 clocks = <&cpufreq_hw 1>; 269 enable-method = "psci"; 270 cpu-idle-states = <&BIG_CPU_SLEEP_0 271 &BIG_CPU_SLEEP_1 272 &CLUSTER_SLEEP_0>; 273 next-level-cache = <&L2_400>; 274 operating-points-v2 = <&cpu4_opp_table>; 275 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 276 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 277 qcom,freq-domain = <&cpufreq_hw 1>; 278 #cooling-cells = <2>; 279 L2_400: l2-cache { 280 compatible = "cache"; 281 cache-level = <2>; 282 cache-unified; 283 next-level-cache = <&L3_0>; 284 }; 285 }; 286 287 CPU5: cpu@500 { 288 device_type = "cpu"; 289 compatible = "qcom,kryo"; 290 reg = <0x0 0x500>; 291 clocks = <&cpufreq_hw 1>; 292 enable-method = "psci"; 293 cpu-idle-states = <&BIG_CPU_SLEEP_0 294 &BIG_CPU_SLEEP_1 295 &CLUSTER_SLEEP_0>; 296 next-level-cache = <&L2_500>; 297 operating-points-v2 = <&cpu4_opp_table>; 298 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 299 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 300 qcom,freq-domain = <&cpufreq_hw 1>; 301 #cooling-cells = <2>; 302 L2_500: l2-cache { 303 compatible = "cache"; 304 cache-level = <2>; 305 cache-unified; 306 next-level-cache = <&L3_0>; 307 }; 308 }; 309 310 CPU6: cpu@600 { 311 device_type = "cpu"; 312 compatible = "qcom,kryo"; 313 reg = <0x0 0x600>; 314 clocks = <&cpufreq_hw 1>; 315 enable-method = "psci"; 316 cpu-idle-states = <&BIG_CPU_SLEEP_0 317 &BIG_CPU_SLEEP_1 318 &CLUSTER_SLEEP_0>; 319 next-level-cache = <&L2_600>; 320 operating-points-v2 = <&cpu4_opp_table>; 321 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 322 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 323 qcom,freq-domain = <&cpufreq_hw 1>; 324 #cooling-cells = <2>; 325 L2_600: l2-cache { 326 compatible = "cache"; 327 cache-level = <2>; 328 cache-unified; 329 next-level-cache = <&L3_0>; 330 }; 331 }; 332 333 CPU7: cpu@700 { 334 device_type = "cpu"; 335 compatible = "qcom,kryo"; 336 reg = <0x0 0x700>; 337 clocks = <&cpufreq_hw 2>; 338 enable-method = "psci"; 339 cpu-idle-states = <&BIG_CPU_SLEEP_0 340 &BIG_CPU_SLEEP_1 341 &CLUSTER_SLEEP_0>; 342 next-level-cache = <&L2_700>; 343 operating-points-v2 = <&cpu7_opp_table>; 344 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 345 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 346 qcom,freq-domain = <&cpufreq_hw 2>; 347 #cooling-cells = <2>; 348 L2_700: l2-cache { 349 compatible = "cache"; 350 cache-level = <2>; 351 cache-unified; 352 next-level-cache = <&L3_0>; 353 }; 354 }; 355 356 cpu-map { 357 cluster0 { 358 core0 { 359 cpu = <&CPU0>; 360 }; 361 362 core1 { 363 cpu = <&CPU1>; 364 }; 365 366 core2 { 367 cpu = <&CPU2>; 368 }; 369 370 core3 { 371 cpu = <&CPU3>; 372 }; 373 374 core4 { 375 cpu = <&CPU4>; 376 }; 377 378 core5 { 379 cpu = <&CPU5>; 380 }; 381 382 core6 { 383 cpu = <&CPU6>; 384 }; 385 386 core7 { 387 cpu = <&CPU7>; 388 }; 389 }; 390 }; 391 392 idle-states { 393 entry-method = "psci"; 394 395 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 396 compatible = "arm,idle-state"; 397 idle-state-name = "little-power-down"; 398 arm,psci-suspend-param = <0x40000003>; 399 entry-latency-us = <549>; 400 exit-latency-us = <901>; 401 min-residency-us = <1774>; 402 local-timer-stop; 403 }; 404 405 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 406 compatible = "arm,idle-state"; 407 idle-state-name = "little-rail-power-down"; 408 arm,psci-suspend-param = <0x40000004>; 409 entry-latency-us = <702>; 410 exit-latency-us = <915>; 411 min-residency-us = <4001>; 412 local-timer-stop; 413 }; 414 415 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 416 compatible = "arm,idle-state"; 417 idle-state-name = "big-power-down"; 418 arm,psci-suspend-param = <0x40000003>; 419 entry-latency-us = <523>; 420 exit-latency-us = <1244>; 421 min-residency-us = <2207>; 422 local-timer-stop; 423 }; 424 425 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 426 compatible = "arm,idle-state"; 427 idle-state-name = "big-rail-power-down"; 428 arm,psci-suspend-param = <0x40000004>; 429 entry-latency-us = <526>; 430 exit-latency-us = <1854>; 431 min-residency-us = <5555>; 432 local-timer-stop; 433 }; 434 435 CLUSTER_SLEEP_0: cluster-sleep-0 { 436 compatible = "arm,idle-state"; 437 idle-state-name = "cluster-power-down"; 438 arm,psci-suspend-param = <0x40003444>; 439 entry-latency-us = <3263>; 440 exit-latency-us = <6562>; 441 min-residency-us = <9926>; 442 local-timer-stop; 443 }; 444 }; 445 }; 446 447 cpu0_opp_table: opp-table-cpu0 { 448 compatible = "operating-points-v2"; 449 opp-shared; 450 451 cpu0_opp_300mhz: opp-300000000 { 452 opp-hz = /bits/ 64 <300000000>; 453 opp-peak-kBps = <800000 9600000>; 454 }; 455 456 cpu0_opp_691mhz: opp-691200000 { 457 opp-hz = /bits/ 64 <691200000>; 458 opp-peak-kBps = <800000 17817600>; 459 }; 460 461 cpu0_opp_806mhz: opp-806400000 { 462 opp-hz = /bits/ 64 <806400000>; 463 opp-peak-kBps = <800000 20889600>; 464 }; 465 466 cpu0_opp_941mhz: opp-940800000 { 467 opp-hz = /bits/ 64 <940800000>; 468 opp-peak-kBps = <1804000 24576000>; 469 }; 470 471 cpu0_opp_1152mhz: opp-1152000000 { 472 opp-hz = /bits/ 64 <1152000000>; 473 opp-peak-kBps = <2188000 27033600>; 474 }; 475 476 cpu0_opp_1325mhz: opp-1324800000 { 477 opp-hz = /bits/ 64 <1324800000>; 478 opp-peak-kBps = <2188000 33792000>; 479 }; 480 481 cpu0_opp_1517mhz: opp-1516800000 { 482 opp-hz = /bits/ 64 <1516800000>; 483 opp-peak-kBps = <3072000 38092800>; 484 }; 485 486 cpu0_opp_1651mhz: opp-1651200000 { 487 opp-hz = /bits/ 64 <1651200000>; 488 opp-peak-kBps = <3072000 41779200>; 489 }; 490 491 cpu0_opp_1805mhz: opp-1804800000 { 492 opp-hz = /bits/ 64 <1804800000>; 493 opp-peak-kBps = <4068000 48537600>; 494 }; 495 496 cpu0_opp_1958mhz: opp-1958400000 { 497 opp-hz = /bits/ 64 <1958400000>; 498 opp-peak-kBps = <4068000 48537600>; 499 }; 500 501 cpu0_opp_2016mhz: opp-2016000000 { 502 opp-hz = /bits/ 64 <2016000000>; 503 opp-peak-kBps = <6220000 48537600>; 504 }; 505 }; 506 507 cpu4_opp_table: opp-table-cpu4 { 508 compatible = "operating-points-v2"; 509 opp-shared; 510 511 cpu4_opp_691mhz: opp-691200000 { 512 opp-hz = /bits/ 64 <691200000>; 513 opp-peak-kBps = <1804000 9600000>; 514 }; 515 516 cpu4_opp_941mhz: opp-940800000 { 517 opp-hz = /bits/ 64 <940800000>; 518 opp-peak-kBps = <2188000 17817600>; 519 }; 520 521 cpu4_opp_1229mhz: opp-1228800000 { 522 opp-hz = /bits/ 64 <1228800000>; 523 opp-peak-kBps = <4068000 24576000>; 524 }; 525 526 cpu4_opp_1344mhz: opp-1344000000 { 527 opp-hz = /bits/ 64 <1344000000>; 528 opp-peak-kBps = <4068000 24576000>; 529 }; 530 531 cpu4_opp_1517mhz: opp-1516800000 { 532 opp-hz = /bits/ 64 <1516800000>; 533 opp-peak-kBps = <4068000 24576000>; 534 }; 535 536 cpu4_opp_1651mhz: opp-1651200000 { 537 opp-hz = /bits/ 64 <1651200000>; 538 opp-peak-kBps = <6220000 38092800>; 539 }; 540 541 cpu4_opp_1901mhz: opp-1900800000 { 542 opp-hz = /bits/ 64 <1900800000>; 543 opp-peak-kBps = <6220000 44851200>; 544 }; 545 546 cpu4_opp_2054mhz: opp-2054400000 { 547 opp-hz = /bits/ 64 <2054400000>; 548 opp-peak-kBps = <6220000 44851200>; 549 }; 550 551 cpu4_opp_2112mhz: opp-2112000000 { 552 opp-hz = /bits/ 64 <2112000000>; 553 opp-peak-kBps = <6220000 44851200>; 554 }; 555 556 cpu4_opp_2131mhz: opp-2131200000 { 557 opp-hz = /bits/ 64 <2131200000>; 558 opp-peak-kBps = <6220000 44851200>; 559 }; 560 561 cpu4_opp_2208mhz: opp-2208000000 { 562 opp-hz = /bits/ 64 <2208000000>; 563 opp-peak-kBps = <6220000 44851200>; 564 }; 565 566 cpu4_opp_2400mhz: opp-2400000000 { 567 opp-hz = /bits/ 64 <2400000000>; 568 opp-peak-kBps = <8532000 48537600>; 569 }; 570 571 cpu4_opp_2611mhz: opp-2611200000 { 572 opp-hz = /bits/ 64 <2611200000>; 573 opp-peak-kBps = <8532000 48537600>; 574 }; 575 }; 576 577 cpu7_opp_table: opp-table-cpu7 { 578 compatible = "operating-points-v2"; 579 opp-shared; 580 581 cpu7_opp_806mhz: opp-806400000 { 582 opp-hz = /bits/ 64 <806400000>; 583 opp-peak-kBps = <1804000 9600000>; 584 }; 585 586 cpu7_opp_1056mhz: opp-1056000000 { 587 opp-hz = /bits/ 64 <1056000000>; 588 opp-peak-kBps = <2188000 17817600>; 589 }; 590 591 cpu7_opp_1325mhz: opp-1324800000 { 592 opp-hz = /bits/ 64 <1324800000>; 593 opp-peak-kBps = <4068000 24576000>; 594 }; 595 596 cpu7_opp_1517mhz: opp-1516800000 { 597 opp-hz = /bits/ 64 <1516800000>; 598 opp-peak-kBps = <4068000 24576000>; 599 }; 600 601 cpu7_opp_1766mhz: opp-1766400000 { 602 opp-hz = /bits/ 64 <1766400000>; 603 opp-peak-kBps = <6220000 38092800>; 604 }; 605 606 cpu7_opp_1862mhz: opp-1862400000 { 607 opp-hz = /bits/ 64 <1862400000>; 608 opp-peak-kBps = <6220000 38092800>; 609 }; 610 611 cpu7_opp_2035mhz: opp-2035200000 { 612 opp-hz = /bits/ 64 <2035200000>; 613 opp-peak-kBps = <6220000 38092800>; 614 }; 615 616 cpu7_opp_2112mhz: opp-2112000000 { 617 opp-hz = /bits/ 64 <2112000000>; 618 opp-peak-kBps = <6220000 44851200>; 619 }; 620 621 cpu7_opp_2208mhz: opp-2208000000 { 622 opp-hz = /bits/ 64 <2208000000>; 623 opp-peak-kBps = <6220000 44851200>; 624 }; 625 626 cpu7_opp_2381mhz: opp-2380800000 { 627 opp-hz = /bits/ 64 <2380800000>; 628 opp-peak-kBps = <6832000 44851200>; 629 }; 630 631 cpu7_opp_2400mhz: opp-2400000000 { 632 opp-hz = /bits/ 64 <2400000000>; 633 opp-peak-kBps = <8532000 48537600>; 634 }; 635 636 cpu7_opp_2515mhz: opp-2515200000 { 637 opp-hz = /bits/ 64 <2515200000>; 638 opp-peak-kBps = <8532000 48537600>; 639 }; 640 641 cpu7_opp_2707mhz: opp-2707200000 { 642 opp-hz = /bits/ 64 <2707200000>; 643 opp-peak-kBps = <8532000 48537600>; 644 }; 645 646 cpu7_opp_3014mhz: opp-3014400000 { 647 opp-hz = /bits/ 64 <3014400000>; 648 opp-peak-kBps = <8532000 48537600>; 649 }; 650 }; 651 652 eud_typec: connector { 653 compatible = "usb-c-connector"; 654 655 ports { 656 port@0 { 657 con_eud: endpoint { 658 remote-endpoint = <&eud_con>; 659 }; 660 }; 661 }; 662 }; 663 664 memory@80000000 { 665 device_type = "memory"; 666 /* We expect the bootloader to fill in the size */ 667 reg = <0 0x80000000 0 0>; 668 }; 669 670 firmware { 671 scm: scm { 672 compatible = "qcom,scm-sc7280", "qcom,scm"; 673 }; 674 }; 675 676 clk_virt: interconnect { 677 compatible = "qcom,sc7280-clk-virt"; 678 #interconnect-cells = <2>; 679 qcom,bcm-voters = <&apps_bcm_voter>; 680 }; 681 682 smem { 683 compatible = "qcom,smem"; 684 memory-region = <&smem_mem>; 685 hwlocks = <&tcsr_mutex 3>; 686 }; 687 688 smp2p-adsp { 689 compatible = "qcom,smp2p"; 690 qcom,smem = <443>, <429>; 691 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 692 IPCC_MPROC_SIGNAL_SMP2P 693 IRQ_TYPE_EDGE_RISING>; 694 mboxes = <&ipcc IPCC_CLIENT_LPASS 695 IPCC_MPROC_SIGNAL_SMP2P>; 696 697 qcom,local-pid = <0>; 698 qcom,remote-pid = <2>; 699 700 adsp_smp2p_out: master-kernel { 701 qcom,entry-name = "master-kernel"; 702 #qcom,smem-state-cells = <1>; 703 }; 704 705 adsp_smp2p_in: slave-kernel { 706 qcom,entry-name = "slave-kernel"; 707 interrupt-controller; 708 #interrupt-cells = <2>; 709 }; 710 }; 711 712 smp2p-cdsp { 713 compatible = "qcom,smp2p"; 714 qcom,smem = <94>, <432>; 715 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 716 IPCC_MPROC_SIGNAL_SMP2P 717 IRQ_TYPE_EDGE_RISING>; 718 mboxes = <&ipcc IPCC_CLIENT_CDSP 719 IPCC_MPROC_SIGNAL_SMP2P>; 720 721 qcom,local-pid = <0>; 722 qcom,remote-pid = <5>; 723 724 cdsp_smp2p_out: master-kernel { 725 qcom,entry-name = "master-kernel"; 726 #qcom,smem-state-cells = <1>; 727 }; 728 729 cdsp_smp2p_in: slave-kernel { 730 qcom,entry-name = "slave-kernel"; 731 interrupt-controller; 732 #interrupt-cells = <2>; 733 }; 734 }; 735 736 smp2p-mpss { 737 compatible = "qcom,smp2p"; 738 qcom,smem = <435>, <428>; 739 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 740 IPCC_MPROC_SIGNAL_SMP2P 741 IRQ_TYPE_EDGE_RISING>; 742 mboxes = <&ipcc IPCC_CLIENT_MPSS 743 IPCC_MPROC_SIGNAL_SMP2P>; 744 745 qcom,local-pid = <0>; 746 qcom,remote-pid = <1>; 747 748 modem_smp2p_out: master-kernel { 749 qcom,entry-name = "master-kernel"; 750 #qcom,smem-state-cells = <1>; 751 }; 752 753 modem_smp2p_in: slave-kernel { 754 qcom,entry-name = "slave-kernel"; 755 interrupt-controller; 756 #interrupt-cells = <2>; 757 }; 758 759 ipa_smp2p_out: ipa-ap-to-modem { 760 qcom,entry-name = "ipa"; 761 #qcom,smem-state-cells = <1>; 762 }; 763 764 ipa_smp2p_in: ipa-modem-to-ap { 765 qcom,entry-name = "ipa"; 766 interrupt-controller; 767 #interrupt-cells = <2>; 768 }; 769 }; 770 771 smp2p-wpss { 772 compatible = "qcom,smp2p"; 773 qcom,smem = <617>, <616>; 774 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 775 IPCC_MPROC_SIGNAL_SMP2P 776 IRQ_TYPE_EDGE_RISING>; 777 mboxes = <&ipcc IPCC_CLIENT_WPSS 778 IPCC_MPROC_SIGNAL_SMP2P>; 779 780 qcom,local-pid = <0>; 781 qcom,remote-pid = <13>; 782 783 wpss_smp2p_out: master-kernel { 784 qcom,entry-name = "master-kernel"; 785 #qcom,smem-state-cells = <1>; 786 }; 787 788 wpss_smp2p_in: slave-kernel { 789 qcom,entry-name = "slave-kernel"; 790 interrupt-controller; 791 #interrupt-cells = <2>; 792 }; 793 794 wlan_smp2p_out: wlan-ap-to-wpss { 795 qcom,entry-name = "wlan"; 796 #qcom,smem-state-cells = <1>; 797 }; 798 799 wlan_smp2p_in: wlan-wpss-to-ap { 800 qcom,entry-name = "wlan"; 801 interrupt-controller; 802 #interrupt-cells = <2>; 803 }; 804 }; 805 806 pmu { 807 compatible = "arm,armv8-pmuv3"; 808 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 809 }; 810 811 psci { 812 compatible = "arm,psci-1.0"; 813 method = "smc"; 814 }; 815 816 qspi_opp_table: opp-table-qspi { 817 compatible = "operating-points-v2"; 818 819 opp-75000000 { 820 opp-hz = /bits/ 64 <75000000>; 821 required-opps = <&rpmhpd_opp_low_svs>; 822 }; 823 824 opp-150000000 { 825 opp-hz = /bits/ 64 <150000000>; 826 required-opps = <&rpmhpd_opp_svs>; 827 }; 828 829 opp-200000000 { 830 opp-hz = /bits/ 64 <200000000>; 831 required-opps = <&rpmhpd_opp_svs_l1>; 832 }; 833 834 opp-300000000 { 835 opp-hz = /bits/ 64 <300000000>; 836 required-opps = <&rpmhpd_opp_nom>; 837 }; 838 }; 839 840 qup_opp_table: opp-table-qup { 841 compatible = "operating-points-v2"; 842 843 opp-75000000 { 844 opp-hz = /bits/ 64 <75000000>; 845 required-opps = <&rpmhpd_opp_low_svs>; 846 }; 847 848 opp-100000000 { 849 opp-hz = /bits/ 64 <100000000>; 850 required-opps = <&rpmhpd_opp_svs>; 851 }; 852 853 opp-128000000 { 854 opp-hz = /bits/ 64 <128000000>; 855 required-opps = <&rpmhpd_opp_nom>; 856 }; 857 }; 858 859 soc: soc@0 { 860 #address-cells = <2>; 861 #size-cells = <2>; 862 ranges = <0 0 0 0 0x10 0>; 863 dma-ranges = <0 0 0 0 0x10 0>; 864 compatible = "simple-bus"; 865 866 gcc: clock-controller@100000 { 867 compatible = "qcom,gcc-sc7280"; 868 reg = <0 0x00100000 0 0x1f0000>; 869 clocks = <&rpmhcc RPMH_CXO_CLK>, 870 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 871 <0>, <&pcie1_lane>, 872 <0>, <0>, <0>, <0>; 873 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 874 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 875 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 876 "ufs_phy_tx_symbol_0_clk", 877 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 878 #clock-cells = <1>; 879 #reset-cells = <1>; 880 #power-domain-cells = <1>; 881 power-domains = <&rpmhpd SC7280_CX>; 882 }; 883 884 ipcc: mailbox@408000 { 885 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 886 reg = <0 0x00408000 0 0x1000>; 887 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 888 interrupt-controller; 889 #interrupt-cells = <3>; 890 #mbox-cells = <2>; 891 }; 892 893 qfprom: efuse@784000 { 894 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 895 reg = <0 0x00784000 0 0xa20>, 896 <0 0x00780000 0 0xa20>, 897 <0 0x00782000 0 0x120>, 898 <0 0x00786000 0 0x1fff>; 899 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 900 clock-names = "core"; 901 power-domains = <&rpmhpd SC7280_MX>; 902 #address-cells = <1>; 903 #size-cells = <1>; 904 905 gpu_speed_bin: gpu_speed_bin@1e9 { 906 reg = <0x1e9 0x2>; 907 bits = <5 8>; 908 }; 909 }; 910 911 sdhc_1: mmc@7c4000 { 912 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 913 pinctrl-names = "default", "sleep"; 914 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 915 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 916 status = "disabled"; 917 918 reg = <0 0x007c4000 0 0x1000>, 919 <0 0x007c5000 0 0x1000>; 920 reg-names = "hc", "cqhci"; 921 922 iommus = <&apps_smmu 0xc0 0x0>; 923 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 925 interrupt-names = "hc_irq", "pwr_irq"; 926 927 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 928 <&gcc GCC_SDCC1_APPS_CLK>, 929 <&rpmhcc RPMH_CXO_CLK>; 930 clock-names = "iface", "core", "xo"; 931 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 932 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 933 interconnect-names = "sdhc-ddr","cpu-sdhc"; 934 power-domains = <&rpmhpd SC7280_CX>; 935 operating-points-v2 = <&sdhc1_opp_table>; 936 937 bus-width = <8>; 938 supports-cqe; 939 940 qcom,dll-config = <0x0007642c>; 941 qcom,ddr-config = <0x80040868>; 942 943 mmc-ddr-1_8v; 944 mmc-hs200-1_8v; 945 mmc-hs400-1_8v; 946 mmc-hs400-enhanced-strobe; 947 948 resets = <&gcc GCC_SDCC1_BCR>; 949 950 sdhc1_opp_table: opp-table { 951 compatible = "operating-points-v2"; 952 953 opp-100000000 { 954 opp-hz = /bits/ 64 <100000000>; 955 required-opps = <&rpmhpd_opp_low_svs>; 956 opp-peak-kBps = <1800000 400000>; 957 opp-avg-kBps = <100000 0>; 958 }; 959 960 opp-384000000 { 961 opp-hz = /bits/ 64 <384000000>; 962 required-opps = <&rpmhpd_opp_nom>; 963 opp-peak-kBps = <5400000 1600000>; 964 opp-avg-kBps = <390000 0>; 965 }; 966 }; 967 }; 968 969 gpi_dma0: dma-controller@900000 { 970 #dma-cells = <3>; 971 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 972 reg = <0 0x00900000 0 0x60000>; 973 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 978 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 979 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 982 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 985 dma-channels = <12>; 986 dma-channel-mask = <0x7f>; 987 iommus = <&apps_smmu 0x0136 0x0>; 988 status = "disabled"; 989 }; 990 991 qupv3_id_0: geniqup@9c0000 { 992 compatible = "qcom,geni-se-qup"; 993 reg = <0 0x009c0000 0 0x2000>; 994 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 995 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 996 clock-names = "m-ahb", "s-ahb"; 997 #address-cells = <2>; 998 #size-cells = <2>; 999 ranges; 1000 iommus = <&apps_smmu 0x123 0x0>; 1001 status = "disabled"; 1002 1003 i2c0: i2c@980000 { 1004 compatible = "qcom,geni-i2c"; 1005 reg = <0 0x00980000 0 0x4000>; 1006 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1007 clock-names = "se"; 1008 pinctrl-names = "default"; 1009 pinctrl-0 = <&qup_i2c0_data_clk>; 1010 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1014 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1015 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1016 interconnect-names = "qup-core", "qup-config", 1017 "qup-memory"; 1018 power-domains = <&rpmhpd SC7280_CX>; 1019 required-opps = <&rpmhpd_opp_low_svs>; 1020 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1021 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1022 dma-names = "tx", "rx"; 1023 status = "disabled"; 1024 }; 1025 1026 spi0: spi@980000 { 1027 compatible = "qcom,geni-spi"; 1028 reg = <0 0x00980000 0 0x4000>; 1029 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1030 clock-names = "se"; 1031 pinctrl-names = "default"; 1032 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1033 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 power-domains = <&rpmhpd SC7280_CX>; 1037 operating-points-v2 = <&qup_opp_table>; 1038 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1039 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1040 interconnect-names = "qup-core", "qup-config"; 1041 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1042 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1043 dma-names = "tx", "rx"; 1044 status = "disabled"; 1045 }; 1046 1047 uart0: serial@980000 { 1048 compatible = "qcom,geni-uart"; 1049 reg = <0 0x00980000 0 0x4000>; 1050 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1051 clock-names = "se"; 1052 pinctrl-names = "default"; 1053 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1054 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1055 power-domains = <&rpmhpd SC7280_CX>; 1056 operating-points-v2 = <&qup_opp_table>; 1057 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1058 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1059 interconnect-names = "qup-core", "qup-config"; 1060 status = "disabled"; 1061 }; 1062 1063 i2c1: i2c@984000 { 1064 compatible = "qcom,geni-i2c"; 1065 reg = <0 0x00984000 0 0x4000>; 1066 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1067 clock-names = "se"; 1068 pinctrl-names = "default"; 1069 pinctrl-0 = <&qup_i2c1_data_clk>; 1070 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1074 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1075 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1076 interconnect-names = "qup-core", "qup-config", 1077 "qup-memory"; 1078 power-domains = <&rpmhpd SC7280_CX>; 1079 required-opps = <&rpmhpd_opp_low_svs>; 1080 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1081 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1082 dma-names = "tx", "rx"; 1083 status = "disabled"; 1084 }; 1085 1086 spi1: spi@984000 { 1087 compatible = "qcom,geni-spi"; 1088 reg = <0 0x00984000 0 0x4000>; 1089 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1090 clock-names = "se"; 1091 pinctrl-names = "default"; 1092 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1093 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 power-domains = <&rpmhpd SC7280_CX>; 1097 operating-points-v2 = <&qup_opp_table>; 1098 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1099 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1100 interconnect-names = "qup-core", "qup-config"; 1101 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1102 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1103 dma-names = "tx", "rx"; 1104 status = "disabled"; 1105 }; 1106 1107 uart1: serial@984000 { 1108 compatible = "qcom,geni-uart"; 1109 reg = <0 0x00984000 0 0x4000>; 1110 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1111 clock-names = "se"; 1112 pinctrl-names = "default"; 1113 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1114 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1115 power-domains = <&rpmhpd SC7280_CX>; 1116 operating-points-v2 = <&qup_opp_table>; 1117 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1118 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1119 interconnect-names = "qup-core", "qup-config"; 1120 status = "disabled"; 1121 }; 1122 1123 i2c2: i2c@988000 { 1124 compatible = "qcom,geni-i2c"; 1125 reg = <0 0x00988000 0 0x4000>; 1126 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1127 clock-names = "se"; 1128 pinctrl-names = "default"; 1129 pinctrl-0 = <&qup_i2c2_data_clk>; 1130 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1134 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1135 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1136 interconnect-names = "qup-core", "qup-config", 1137 "qup-memory"; 1138 power-domains = <&rpmhpd SC7280_CX>; 1139 required-opps = <&rpmhpd_opp_low_svs>; 1140 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1141 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1142 dma-names = "tx", "rx"; 1143 status = "disabled"; 1144 }; 1145 1146 spi2: spi@988000 { 1147 compatible = "qcom,geni-spi"; 1148 reg = <0 0x00988000 0 0x4000>; 1149 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1150 clock-names = "se"; 1151 pinctrl-names = "default"; 1152 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1153 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 power-domains = <&rpmhpd SC7280_CX>; 1157 operating-points-v2 = <&qup_opp_table>; 1158 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1159 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1160 interconnect-names = "qup-core", "qup-config"; 1161 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1162 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1163 dma-names = "tx", "rx"; 1164 status = "disabled"; 1165 }; 1166 1167 uart2: serial@988000 { 1168 compatible = "qcom,geni-uart"; 1169 reg = <0 0x00988000 0 0x4000>; 1170 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1171 clock-names = "se"; 1172 pinctrl-names = "default"; 1173 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1174 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1175 power-domains = <&rpmhpd SC7280_CX>; 1176 operating-points-v2 = <&qup_opp_table>; 1177 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1178 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1179 interconnect-names = "qup-core", "qup-config"; 1180 status = "disabled"; 1181 }; 1182 1183 i2c3: i2c@98c000 { 1184 compatible = "qcom,geni-i2c"; 1185 reg = <0 0x0098c000 0 0x4000>; 1186 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1187 clock-names = "se"; 1188 pinctrl-names = "default"; 1189 pinctrl-0 = <&qup_i2c3_data_clk>; 1190 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1191 #address-cells = <1>; 1192 #size-cells = <0>; 1193 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1194 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1195 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1196 interconnect-names = "qup-core", "qup-config", 1197 "qup-memory"; 1198 power-domains = <&rpmhpd SC7280_CX>; 1199 required-opps = <&rpmhpd_opp_low_svs>; 1200 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1201 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1202 dma-names = "tx", "rx"; 1203 status = "disabled"; 1204 }; 1205 1206 spi3: spi@98c000 { 1207 compatible = "qcom,geni-spi"; 1208 reg = <0 0x0098c000 0 0x4000>; 1209 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1210 clock-names = "se"; 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1213 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 power-domains = <&rpmhpd SC7280_CX>; 1217 operating-points-v2 = <&qup_opp_table>; 1218 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1219 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1220 interconnect-names = "qup-core", "qup-config"; 1221 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1222 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1223 dma-names = "tx", "rx"; 1224 status = "disabled"; 1225 }; 1226 1227 uart3: serial@98c000 { 1228 compatible = "qcom,geni-uart"; 1229 reg = <0 0x0098c000 0 0x4000>; 1230 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1231 clock-names = "se"; 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1234 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1235 power-domains = <&rpmhpd SC7280_CX>; 1236 operating-points-v2 = <&qup_opp_table>; 1237 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1238 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1239 interconnect-names = "qup-core", "qup-config"; 1240 status = "disabled"; 1241 }; 1242 1243 i2c4: i2c@990000 { 1244 compatible = "qcom,geni-i2c"; 1245 reg = <0 0x00990000 0 0x4000>; 1246 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1247 clock-names = "se"; 1248 pinctrl-names = "default"; 1249 pinctrl-0 = <&qup_i2c4_data_clk>; 1250 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1254 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1255 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1256 interconnect-names = "qup-core", "qup-config", 1257 "qup-memory"; 1258 power-domains = <&rpmhpd SC7280_CX>; 1259 required-opps = <&rpmhpd_opp_low_svs>; 1260 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1261 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1262 dma-names = "tx", "rx"; 1263 status = "disabled"; 1264 }; 1265 1266 spi4: spi@990000 { 1267 compatible = "qcom,geni-spi"; 1268 reg = <0 0x00990000 0 0x4000>; 1269 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1270 clock-names = "se"; 1271 pinctrl-names = "default"; 1272 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1273 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 power-domains = <&rpmhpd SC7280_CX>; 1277 operating-points-v2 = <&qup_opp_table>; 1278 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1279 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1280 interconnect-names = "qup-core", "qup-config"; 1281 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1282 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1283 dma-names = "tx", "rx"; 1284 status = "disabled"; 1285 }; 1286 1287 uart4: serial@990000 { 1288 compatible = "qcom,geni-uart"; 1289 reg = <0 0x00990000 0 0x4000>; 1290 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1291 clock-names = "se"; 1292 pinctrl-names = "default"; 1293 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1294 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1295 power-domains = <&rpmhpd SC7280_CX>; 1296 operating-points-v2 = <&qup_opp_table>; 1297 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1298 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1299 interconnect-names = "qup-core", "qup-config"; 1300 status = "disabled"; 1301 }; 1302 1303 i2c5: i2c@994000 { 1304 compatible = "qcom,geni-i2c"; 1305 reg = <0 0x00994000 0 0x4000>; 1306 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1307 clock-names = "se"; 1308 pinctrl-names = "default"; 1309 pinctrl-0 = <&qup_i2c5_data_clk>; 1310 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1314 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1315 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1316 interconnect-names = "qup-core", "qup-config", 1317 "qup-memory"; 1318 power-domains = <&rpmhpd SC7280_CX>; 1319 required-opps = <&rpmhpd_opp_low_svs>; 1320 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1321 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1322 dma-names = "tx", "rx"; 1323 status = "disabled"; 1324 }; 1325 1326 spi5: spi@994000 { 1327 compatible = "qcom,geni-spi"; 1328 reg = <0 0x00994000 0 0x4000>; 1329 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1330 clock-names = "se"; 1331 pinctrl-names = "default"; 1332 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1333 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1334 #address-cells = <1>; 1335 #size-cells = <0>; 1336 power-domains = <&rpmhpd SC7280_CX>; 1337 operating-points-v2 = <&qup_opp_table>; 1338 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1339 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1340 interconnect-names = "qup-core", "qup-config"; 1341 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1342 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1343 dma-names = "tx", "rx"; 1344 status = "disabled"; 1345 }; 1346 1347 uart5: serial@994000 { 1348 compatible = "qcom,geni-uart"; 1349 reg = <0 0x00994000 0 0x4000>; 1350 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1351 clock-names = "se"; 1352 pinctrl-names = "default"; 1353 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1354 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1355 power-domains = <&rpmhpd SC7280_CX>; 1356 operating-points-v2 = <&qup_opp_table>; 1357 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1358 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1359 interconnect-names = "qup-core", "qup-config"; 1360 status = "disabled"; 1361 }; 1362 1363 i2c6: i2c@998000 { 1364 compatible = "qcom,geni-i2c"; 1365 reg = <0 0x00998000 0 0x4000>; 1366 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1367 clock-names = "se"; 1368 pinctrl-names = "default"; 1369 pinctrl-0 = <&qup_i2c6_data_clk>; 1370 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1371 #address-cells = <1>; 1372 #size-cells = <0>; 1373 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1374 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1375 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1376 interconnect-names = "qup-core", "qup-config", 1377 "qup-memory"; 1378 power-domains = <&rpmhpd SC7280_CX>; 1379 required-opps = <&rpmhpd_opp_low_svs>; 1380 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1381 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1382 dma-names = "tx", "rx"; 1383 status = "disabled"; 1384 }; 1385 1386 spi6: spi@998000 { 1387 compatible = "qcom,geni-spi"; 1388 reg = <0 0x00998000 0 0x4000>; 1389 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1390 clock-names = "se"; 1391 pinctrl-names = "default"; 1392 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1393 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 power-domains = <&rpmhpd SC7280_CX>; 1397 operating-points-v2 = <&qup_opp_table>; 1398 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1399 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1400 interconnect-names = "qup-core", "qup-config"; 1401 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1402 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1403 dma-names = "tx", "rx"; 1404 status = "disabled"; 1405 }; 1406 1407 uart6: serial@998000 { 1408 compatible = "qcom,geni-uart"; 1409 reg = <0 0x00998000 0 0x4000>; 1410 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1411 clock-names = "se"; 1412 pinctrl-names = "default"; 1413 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1414 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1415 power-domains = <&rpmhpd SC7280_CX>; 1416 operating-points-v2 = <&qup_opp_table>; 1417 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1418 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1419 interconnect-names = "qup-core", "qup-config"; 1420 status = "disabled"; 1421 }; 1422 1423 i2c7: i2c@99c000 { 1424 compatible = "qcom,geni-i2c"; 1425 reg = <0 0x0099c000 0 0x4000>; 1426 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1427 clock-names = "se"; 1428 pinctrl-names = "default"; 1429 pinctrl-0 = <&qup_i2c7_data_clk>; 1430 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1431 #address-cells = <1>; 1432 #size-cells = <0>; 1433 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1434 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1435 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1436 interconnect-names = "qup-core", "qup-config", 1437 "qup-memory"; 1438 power-domains = <&rpmhpd SC7280_CX>; 1439 required-opps = <&rpmhpd_opp_low_svs>; 1440 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1441 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1442 dma-names = "tx", "rx"; 1443 status = "disabled"; 1444 }; 1445 1446 spi7: spi@99c000 { 1447 compatible = "qcom,geni-spi"; 1448 reg = <0 0x0099c000 0 0x4000>; 1449 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1450 clock-names = "se"; 1451 pinctrl-names = "default"; 1452 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1453 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1454 #address-cells = <1>; 1455 #size-cells = <0>; 1456 power-domains = <&rpmhpd SC7280_CX>; 1457 operating-points-v2 = <&qup_opp_table>; 1458 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1459 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1460 interconnect-names = "qup-core", "qup-config"; 1461 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1462 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1463 dma-names = "tx", "rx"; 1464 status = "disabled"; 1465 }; 1466 1467 uart7: serial@99c000 { 1468 compatible = "qcom,geni-uart"; 1469 reg = <0 0x0099c000 0 0x4000>; 1470 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1471 clock-names = "se"; 1472 pinctrl-names = "default"; 1473 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1474 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1475 power-domains = <&rpmhpd SC7280_CX>; 1476 operating-points-v2 = <&qup_opp_table>; 1477 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1478 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1479 interconnect-names = "qup-core", "qup-config"; 1480 status = "disabled"; 1481 }; 1482 }; 1483 1484 gpi_dma1: dma-controller@a00000 { 1485 #dma-cells = <3>; 1486 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1487 reg = <0 0x00a00000 0 0x60000>; 1488 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1497 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1498 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1499 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1500 dma-channels = <12>; 1501 dma-channel-mask = <0x1e>; 1502 iommus = <&apps_smmu 0x56 0x0>; 1503 status = "disabled"; 1504 }; 1505 1506 qupv3_id_1: geniqup@ac0000 { 1507 compatible = "qcom,geni-se-qup"; 1508 reg = <0 0x00ac0000 0 0x2000>; 1509 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1510 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1511 clock-names = "m-ahb", "s-ahb"; 1512 #address-cells = <2>; 1513 #size-cells = <2>; 1514 ranges; 1515 iommus = <&apps_smmu 0x43 0x0>; 1516 status = "disabled"; 1517 1518 i2c8: i2c@a80000 { 1519 compatible = "qcom,geni-i2c"; 1520 reg = <0 0x00a80000 0 0x4000>; 1521 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1522 clock-names = "se"; 1523 pinctrl-names = "default"; 1524 pinctrl-0 = <&qup_i2c8_data_clk>; 1525 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1526 #address-cells = <1>; 1527 #size-cells = <0>; 1528 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1529 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1530 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1531 interconnect-names = "qup-core", "qup-config", 1532 "qup-memory"; 1533 power-domains = <&rpmhpd SC7280_CX>; 1534 required-opps = <&rpmhpd_opp_low_svs>; 1535 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1536 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1537 dma-names = "tx", "rx"; 1538 status = "disabled"; 1539 }; 1540 1541 spi8: spi@a80000 { 1542 compatible = "qcom,geni-spi"; 1543 reg = <0 0x00a80000 0 0x4000>; 1544 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1545 clock-names = "se"; 1546 pinctrl-names = "default"; 1547 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1548 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1549 #address-cells = <1>; 1550 #size-cells = <0>; 1551 power-domains = <&rpmhpd SC7280_CX>; 1552 operating-points-v2 = <&qup_opp_table>; 1553 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1554 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1555 interconnect-names = "qup-core", "qup-config"; 1556 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1557 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1558 dma-names = "tx", "rx"; 1559 status = "disabled"; 1560 }; 1561 1562 uart8: serial@a80000 { 1563 compatible = "qcom,geni-uart"; 1564 reg = <0 0x00a80000 0 0x4000>; 1565 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1566 clock-names = "se"; 1567 pinctrl-names = "default"; 1568 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1569 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1570 power-domains = <&rpmhpd SC7280_CX>; 1571 operating-points-v2 = <&qup_opp_table>; 1572 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1573 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1574 interconnect-names = "qup-core", "qup-config"; 1575 status = "disabled"; 1576 }; 1577 1578 i2c9: i2c@a84000 { 1579 compatible = "qcom,geni-i2c"; 1580 reg = <0 0x00a84000 0 0x4000>; 1581 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1582 clock-names = "se"; 1583 pinctrl-names = "default"; 1584 pinctrl-0 = <&qup_i2c9_data_clk>; 1585 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1586 #address-cells = <1>; 1587 #size-cells = <0>; 1588 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1589 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1590 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1591 interconnect-names = "qup-core", "qup-config", 1592 "qup-memory"; 1593 power-domains = <&rpmhpd SC7280_CX>; 1594 required-opps = <&rpmhpd_opp_low_svs>; 1595 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1596 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1597 dma-names = "tx", "rx"; 1598 status = "disabled"; 1599 }; 1600 1601 spi9: spi@a84000 { 1602 compatible = "qcom,geni-spi"; 1603 reg = <0 0x00a84000 0 0x4000>; 1604 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1605 clock-names = "se"; 1606 pinctrl-names = "default"; 1607 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1608 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1609 #address-cells = <1>; 1610 #size-cells = <0>; 1611 power-domains = <&rpmhpd SC7280_CX>; 1612 operating-points-v2 = <&qup_opp_table>; 1613 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1614 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1615 interconnect-names = "qup-core", "qup-config"; 1616 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1617 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1618 dma-names = "tx", "rx"; 1619 status = "disabled"; 1620 }; 1621 1622 uart9: serial@a84000 { 1623 compatible = "qcom,geni-uart"; 1624 reg = <0 0x00a84000 0 0x4000>; 1625 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1626 clock-names = "se"; 1627 pinctrl-names = "default"; 1628 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1629 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1630 power-domains = <&rpmhpd SC7280_CX>; 1631 operating-points-v2 = <&qup_opp_table>; 1632 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1633 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1634 interconnect-names = "qup-core", "qup-config"; 1635 status = "disabled"; 1636 }; 1637 1638 i2c10: i2c@a88000 { 1639 compatible = "qcom,geni-i2c"; 1640 reg = <0 0x00a88000 0 0x4000>; 1641 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1642 clock-names = "se"; 1643 pinctrl-names = "default"; 1644 pinctrl-0 = <&qup_i2c10_data_clk>; 1645 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1646 #address-cells = <1>; 1647 #size-cells = <0>; 1648 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1649 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1650 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1651 interconnect-names = "qup-core", "qup-config", 1652 "qup-memory"; 1653 power-domains = <&rpmhpd SC7280_CX>; 1654 required-opps = <&rpmhpd_opp_low_svs>; 1655 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1656 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1657 dma-names = "tx", "rx"; 1658 status = "disabled"; 1659 }; 1660 1661 spi10: spi@a88000 { 1662 compatible = "qcom,geni-spi"; 1663 reg = <0 0x00a88000 0 0x4000>; 1664 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1665 clock-names = "se"; 1666 pinctrl-names = "default"; 1667 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1668 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1669 #address-cells = <1>; 1670 #size-cells = <0>; 1671 power-domains = <&rpmhpd SC7280_CX>; 1672 operating-points-v2 = <&qup_opp_table>; 1673 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1674 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1675 interconnect-names = "qup-core", "qup-config"; 1676 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1677 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1678 dma-names = "tx", "rx"; 1679 status = "disabled"; 1680 }; 1681 1682 uart10: serial@a88000 { 1683 compatible = "qcom,geni-uart"; 1684 reg = <0 0x00a88000 0 0x4000>; 1685 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1686 clock-names = "se"; 1687 pinctrl-names = "default"; 1688 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1689 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1690 power-domains = <&rpmhpd SC7280_CX>; 1691 operating-points-v2 = <&qup_opp_table>; 1692 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1693 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1694 interconnect-names = "qup-core", "qup-config"; 1695 status = "disabled"; 1696 }; 1697 1698 i2c11: i2c@a8c000 { 1699 compatible = "qcom,geni-i2c"; 1700 reg = <0 0x00a8c000 0 0x4000>; 1701 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1702 clock-names = "se"; 1703 pinctrl-names = "default"; 1704 pinctrl-0 = <&qup_i2c11_data_clk>; 1705 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1706 #address-cells = <1>; 1707 #size-cells = <0>; 1708 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1709 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1710 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1711 interconnect-names = "qup-core", "qup-config", 1712 "qup-memory"; 1713 power-domains = <&rpmhpd SC7280_CX>; 1714 required-opps = <&rpmhpd_opp_low_svs>; 1715 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1716 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1717 dma-names = "tx", "rx"; 1718 status = "disabled"; 1719 }; 1720 1721 spi11: spi@a8c000 { 1722 compatible = "qcom,geni-spi"; 1723 reg = <0 0x00a8c000 0 0x4000>; 1724 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1725 clock-names = "se"; 1726 pinctrl-names = "default"; 1727 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1728 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1729 #address-cells = <1>; 1730 #size-cells = <0>; 1731 power-domains = <&rpmhpd SC7280_CX>; 1732 operating-points-v2 = <&qup_opp_table>; 1733 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1734 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1735 interconnect-names = "qup-core", "qup-config"; 1736 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1737 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1738 dma-names = "tx", "rx"; 1739 status = "disabled"; 1740 }; 1741 1742 uart11: serial@a8c000 { 1743 compatible = "qcom,geni-uart"; 1744 reg = <0 0x00a8c000 0 0x4000>; 1745 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1746 clock-names = "se"; 1747 pinctrl-names = "default"; 1748 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1749 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1750 power-domains = <&rpmhpd SC7280_CX>; 1751 operating-points-v2 = <&qup_opp_table>; 1752 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1753 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1754 interconnect-names = "qup-core", "qup-config"; 1755 status = "disabled"; 1756 }; 1757 1758 i2c12: i2c@a90000 { 1759 compatible = "qcom,geni-i2c"; 1760 reg = <0 0x00a90000 0 0x4000>; 1761 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1762 clock-names = "se"; 1763 pinctrl-names = "default"; 1764 pinctrl-0 = <&qup_i2c12_data_clk>; 1765 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1766 #address-cells = <1>; 1767 #size-cells = <0>; 1768 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1769 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1770 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1771 interconnect-names = "qup-core", "qup-config", 1772 "qup-memory"; 1773 power-domains = <&rpmhpd SC7280_CX>; 1774 required-opps = <&rpmhpd_opp_low_svs>; 1775 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1776 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1777 dma-names = "tx", "rx"; 1778 status = "disabled"; 1779 }; 1780 1781 spi12: spi@a90000 { 1782 compatible = "qcom,geni-spi"; 1783 reg = <0 0x00a90000 0 0x4000>; 1784 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1785 clock-names = "se"; 1786 pinctrl-names = "default"; 1787 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1788 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1789 #address-cells = <1>; 1790 #size-cells = <0>; 1791 power-domains = <&rpmhpd SC7280_CX>; 1792 operating-points-v2 = <&qup_opp_table>; 1793 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1794 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1795 interconnect-names = "qup-core", "qup-config"; 1796 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1797 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1798 dma-names = "tx", "rx"; 1799 status = "disabled"; 1800 }; 1801 1802 uart12: serial@a90000 { 1803 compatible = "qcom,geni-uart"; 1804 reg = <0 0x00a90000 0 0x4000>; 1805 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1806 clock-names = "se"; 1807 pinctrl-names = "default"; 1808 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1809 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1810 power-domains = <&rpmhpd SC7280_CX>; 1811 operating-points-v2 = <&qup_opp_table>; 1812 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1813 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1814 interconnect-names = "qup-core", "qup-config"; 1815 status = "disabled"; 1816 }; 1817 1818 i2c13: i2c@a94000 { 1819 compatible = "qcom,geni-i2c"; 1820 reg = <0 0x00a94000 0 0x4000>; 1821 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1822 clock-names = "se"; 1823 pinctrl-names = "default"; 1824 pinctrl-0 = <&qup_i2c13_data_clk>; 1825 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1826 #address-cells = <1>; 1827 #size-cells = <0>; 1828 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1829 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1830 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1831 interconnect-names = "qup-core", "qup-config", 1832 "qup-memory"; 1833 power-domains = <&rpmhpd SC7280_CX>; 1834 required-opps = <&rpmhpd_opp_low_svs>; 1835 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1836 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1837 dma-names = "tx", "rx"; 1838 status = "disabled"; 1839 }; 1840 1841 spi13: spi@a94000 { 1842 compatible = "qcom,geni-spi"; 1843 reg = <0 0x00a94000 0 0x4000>; 1844 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1845 clock-names = "se"; 1846 pinctrl-names = "default"; 1847 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1848 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1849 #address-cells = <1>; 1850 #size-cells = <0>; 1851 power-domains = <&rpmhpd SC7280_CX>; 1852 operating-points-v2 = <&qup_opp_table>; 1853 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1854 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1855 interconnect-names = "qup-core", "qup-config"; 1856 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1857 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1858 dma-names = "tx", "rx"; 1859 status = "disabled"; 1860 }; 1861 1862 uart13: serial@a94000 { 1863 compatible = "qcom,geni-uart"; 1864 reg = <0 0x00a94000 0 0x4000>; 1865 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1866 clock-names = "se"; 1867 pinctrl-names = "default"; 1868 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1869 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1870 power-domains = <&rpmhpd SC7280_CX>; 1871 operating-points-v2 = <&qup_opp_table>; 1872 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1873 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1874 interconnect-names = "qup-core", "qup-config"; 1875 status = "disabled"; 1876 }; 1877 1878 i2c14: i2c@a98000 { 1879 compatible = "qcom,geni-i2c"; 1880 reg = <0 0x00a98000 0 0x4000>; 1881 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1882 clock-names = "se"; 1883 pinctrl-names = "default"; 1884 pinctrl-0 = <&qup_i2c14_data_clk>; 1885 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1886 #address-cells = <1>; 1887 #size-cells = <0>; 1888 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1889 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1890 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1891 interconnect-names = "qup-core", "qup-config", 1892 "qup-memory"; 1893 power-domains = <&rpmhpd SC7280_CX>; 1894 required-opps = <&rpmhpd_opp_low_svs>; 1895 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1896 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1897 dma-names = "tx", "rx"; 1898 status = "disabled"; 1899 }; 1900 1901 spi14: spi@a98000 { 1902 compatible = "qcom,geni-spi"; 1903 reg = <0 0x00a98000 0 0x4000>; 1904 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1905 clock-names = "se"; 1906 pinctrl-names = "default"; 1907 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1908 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1909 #address-cells = <1>; 1910 #size-cells = <0>; 1911 power-domains = <&rpmhpd SC7280_CX>; 1912 operating-points-v2 = <&qup_opp_table>; 1913 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1914 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1915 interconnect-names = "qup-core", "qup-config"; 1916 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1917 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1918 dma-names = "tx", "rx"; 1919 status = "disabled"; 1920 }; 1921 1922 uart14: serial@a98000 { 1923 compatible = "qcom,geni-uart"; 1924 reg = <0 0x00a98000 0 0x4000>; 1925 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1926 clock-names = "se"; 1927 pinctrl-names = "default"; 1928 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1929 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1930 power-domains = <&rpmhpd SC7280_CX>; 1931 operating-points-v2 = <&qup_opp_table>; 1932 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1933 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1934 interconnect-names = "qup-core", "qup-config"; 1935 status = "disabled"; 1936 }; 1937 1938 i2c15: i2c@a9c000 { 1939 compatible = "qcom,geni-i2c"; 1940 reg = <0 0x00a9c000 0 0x4000>; 1941 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1942 clock-names = "se"; 1943 pinctrl-names = "default"; 1944 pinctrl-0 = <&qup_i2c15_data_clk>; 1945 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1946 #address-cells = <1>; 1947 #size-cells = <0>; 1948 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1949 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1950 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1951 interconnect-names = "qup-core", "qup-config", 1952 "qup-memory"; 1953 power-domains = <&rpmhpd SC7280_CX>; 1954 required-opps = <&rpmhpd_opp_low_svs>; 1955 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1956 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1957 dma-names = "tx", "rx"; 1958 status = "disabled"; 1959 }; 1960 1961 spi15: spi@a9c000 { 1962 compatible = "qcom,geni-spi"; 1963 reg = <0 0x00a9c000 0 0x4000>; 1964 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1965 clock-names = "se"; 1966 pinctrl-names = "default"; 1967 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1968 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1969 #address-cells = <1>; 1970 #size-cells = <0>; 1971 power-domains = <&rpmhpd SC7280_CX>; 1972 operating-points-v2 = <&qup_opp_table>; 1973 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1974 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1975 interconnect-names = "qup-core", "qup-config"; 1976 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1977 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1978 dma-names = "tx", "rx"; 1979 status = "disabled"; 1980 }; 1981 1982 uart15: serial@a9c000 { 1983 compatible = "qcom,geni-uart"; 1984 reg = <0 0x00a9c000 0 0x4000>; 1985 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1986 clock-names = "se"; 1987 pinctrl-names = "default"; 1988 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1989 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1990 power-domains = <&rpmhpd SC7280_CX>; 1991 operating-points-v2 = <&qup_opp_table>; 1992 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1993 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1994 interconnect-names = "qup-core", "qup-config"; 1995 status = "disabled"; 1996 }; 1997 }; 1998 1999 cnoc2: interconnect@1500000 { 2000 reg = <0 0x01500000 0 0x1000>; 2001 compatible = "qcom,sc7280-cnoc2"; 2002 #interconnect-cells = <2>; 2003 qcom,bcm-voters = <&apps_bcm_voter>; 2004 }; 2005 2006 cnoc3: interconnect@1502000 { 2007 reg = <0 0x01502000 0 0x1000>; 2008 compatible = "qcom,sc7280-cnoc3"; 2009 #interconnect-cells = <2>; 2010 qcom,bcm-voters = <&apps_bcm_voter>; 2011 }; 2012 2013 mc_virt: interconnect@1580000 { 2014 reg = <0 0x01580000 0 0x4>; 2015 compatible = "qcom,sc7280-mc-virt"; 2016 #interconnect-cells = <2>; 2017 qcom,bcm-voters = <&apps_bcm_voter>; 2018 }; 2019 2020 system_noc: interconnect@1680000 { 2021 reg = <0 0x01680000 0 0x15480>; 2022 compatible = "qcom,sc7280-system-noc"; 2023 #interconnect-cells = <2>; 2024 qcom,bcm-voters = <&apps_bcm_voter>; 2025 }; 2026 2027 aggre1_noc: interconnect@16e0000 { 2028 compatible = "qcom,sc7280-aggre1-noc"; 2029 reg = <0 0x016e0000 0 0x1c080>; 2030 #interconnect-cells = <2>; 2031 qcom,bcm-voters = <&apps_bcm_voter>; 2032 }; 2033 2034 aggre2_noc: interconnect@1700000 { 2035 reg = <0 0x01700000 0 0x2b080>; 2036 compatible = "qcom,sc7280-aggre2-noc"; 2037 #interconnect-cells = <2>; 2038 qcom,bcm-voters = <&apps_bcm_voter>; 2039 }; 2040 2041 mmss_noc: interconnect@1740000 { 2042 reg = <0 0x01740000 0 0x1e080>; 2043 compatible = "qcom,sc7280-mmss-noc"; 2044 #interconnect-cells = <2>; 2045 qcom,bcm-voters = <&apps_bcm_voter>; 2046 }; 2047 2048 wifi: wifi@17a10040 { 2049 compatible = "qcom,wcn6750-wifi"; 2050 reg = <0 0x17a10040 0 0x0>; 2051 iommus = <&apps_smmu 0x1c00 0x1>; 2052 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2053 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2054 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2055 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2056 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2057 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2058 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2059 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2060 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2061 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2062 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2063 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2064 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2065 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2066 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2067 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2068 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2069 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2070 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2071 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2072 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2073 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2074 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2075 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2076 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2077 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2078 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2079 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2080 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2081 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2082 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2083 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2084 qcom,rproc = <&remoteproc_wpss>; 2085 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2086 status = "disabled"; 2087 qcom,smem-states = <&wlan_smp2p_out 0>; 2088 qcom,smem-state-names = "wlan-smp2p-out"; 2089 }; 2090 2091 pcie1: pci@1c08000 { 2092 compatible = "qcom,pcie-sc7280"; 2093 reg = <0 0x01c08000 0 0x3000>, 2094 <0 0x40000000 0 0xf1d>, 2095 <0 0x40000f20 0 0xa8>, 2096 <0 0x40001000 0 0x1000>, 2097 <0 0x40100000 0 0x100000>; 2098 2099 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2100 device_type = "pci"; 2101 linux,pci-domain = <1>; 2102 bus-range = <0x00 0xff>; 2103 num-lanes = <2>; 2104 2105 #address-cells = <3>; 2106 #size-cells = <2>; 2107 2108 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2109 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2110 2111 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2112 interrupt-names = "msi"; 2113 #interrupt-cells = <1>; 2114 interrupt-map-mask = <0 0 0 0x7>; 2115 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2116 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2117 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2118 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2119 2120 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2121 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2122 <&pcie1_lane>, 2123 <&rpmhcc RPMH_CXO_CLK>, 2124 <&gcc GCC_PCIE_1_AUX_CLK>, 2125 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2126 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2127 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2128 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2129 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2130 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2131 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2132 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2133 2134 clock-names = "pipe", 2135 "pipe_mux", 2136 "phy_pipe", 2137 "ref", 2138 "aux", 2139 "cfg", 2140 "bus_master", 2141 "bus_slave", 2142 "slave_q2a", 2143 "tbu", 2144 "ddrss_sf_tbu", 2145 "aggre0", 2146 "aggre1"; 2147 2148 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2149 assigned-clock-rates = <19200000>; 2150 2151 resets = <&gcc GCC_PCIE_1_BCR>; 2152 reset-names = "pci"; 2153 2154 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2155 2156 phys = <&pcie1_lane>; 2157 phy-names = "pciephy"; 2158 2159 pinctrl-names = "default"; 2160 pinctrl-0 = <&pcie1_clkreq_n>; 2161 2162 dma-coherent; 2163 2164 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2165 <0x100 &apps_smmu 0x1c81 0x1>; 2166 2167 status = "disabled"; 2168 }; 2169 2170 pcie1_phy: phy@1c0e000 { 2171 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2172 reg = <0 0x01c0e000 0 0x1c0>; 2173 #address-cells = <2>; 2174 #size-cells = <2>; 2175 ranges; 2176 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2177 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2178 <&gcc GCC_PCIE_CLKREF_EN>, 2179 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2180 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2181 2182 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2183 reset-names = "phy"; 2184 2185 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2186 assigned-clock-rates = <100000000>; 2187 2188 status = "disabled"; 2189 2190 pcie1_lane: phy@1c0e200 { 2191 reg = <0 0x01c0e200 0 0x170>, 2192 <0 0x01c0e400 0 0x200>, 2193 <0 0x01c0ea00 0 0x1f0>, 2194 <0 0x01c0e600 0 0x170>, 2195 <0 0x01c0e800 0 0x200>, 2196 <0 0x01c0ee00 0 0xf4>; 2197 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2198 clock-names = "pipe0"; 2199 2200 #phy-cells = <0>; 2201 #clock-cells = <0>; 2202 clock-output-names = "pcie_1_pipe_clk"; 2203 }; 2204 }; 2205 2206 ipa: ipa@1e40000 { 2207 compatible = "qcom,sc7280-ipa"; 2208 2209 iommus = <&apps_smmu 0x480 0x0>, 2210 <&apps_smmu 0x482 0x0>; 2211 reg = <0 0x01e40000 0 0x8000>, 2212 <0 0x01e50000 0 0x4ad0>, 2213 <0 0x01e04000 0 0x23000>; 2214 reg-names = "ipa-reg", 2215 "ipa-shared", 2216 "gsi"; 2217 2218 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2219 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2220 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2221 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2222 interrupt-names = "ipa", 2223 "gsi", 2224 "ipa-clock-query", 2225 "ipa-setup-ready"; 2226 2227 clocks = <&rpmhcc RPMH_IPA_CLK>; 2228 clock-names = "core"; 2229 2230 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2231 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2232 interconnect-names = "memory", 2233 "config"; 2234 2235 qcom,qmp = <&aoss_qmp>; 2236 2237 qcom,smem-states = <&ipa_smp2p_out 0>, 2238 <&ipa_smp2p_out 1>; 2239 qcom,smem-state-names = "ipa-clock-enabled-valid", 2240 "ipa-clock-enabled"; 2241 2242 status = "disabled"; 2243 }; 2244 2245 tcsr_mutex: hwlock@1f40000 { 2246 compatible = "qcom,tcsr-mutex"; 2247 reg = <0 0x01f40000 0 0x20000>; 2248 #hwlock-cells = <1>; 2249 }; 2250 2251 tcsr_1: syscon@1f60000 { 2252 compatible = "qcom,sc7280-tcsr", "syscon"; 2253 reg = <0 0x01f60000 0 0x20000>; 2254 }; 2255 2256 tcsr_2: syscon@1fc0000 { 2257 compatible = "qcom,sc7280-tcsr", "syscon"; 2258 reg = <0 0x01fc0000 0 0x30000>; 2259 }; 2260 2261 lpasscc: lpasscc@3000000 { 2262 compatible = "qcom,sc7280-lpasscc"; 2263 reg = <0 0x03000000 0 0x40>, 2264 <0 0x03c04000 0 0x4>; 2265 reg-names = "qdsp6ss", "top_cc"; 2266 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2267 clock-names = "iface"; 2268 #clock-cells = <1>; 2269 }; 2270 2271 lpass_rx_macro: codec@3200000 { 2272 compatible = "qcom,sc7280-lpass-rx-macro"; 2273 reg = <0 0x03200000 0 0x1000>; 2274 2275 pinctrl-names = "default"; 2276 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2277 2278 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2279 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2280 <&lpass_va_macro>; 2281 clock-names = "mclk", "npl", "fsgen"; 2282 2283 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2284 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2285 power-domain-names = "macro", "dcodec"; 2286 2287 #clock-cells = <0>; 2288 #sound-dai-cells = <1>; 2289 2290 status = "disabled"; 2291 }; 2292 2293 swr0: soundwire@3210000 { 2294 compatible = "qcom,soundwire-v1.6.0"; 2295 reg = <0 0x03210000 0 0x2000>; 2296 2297 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2298 clocks = <&lpass_rx_macro>; 2299 clock-names = "iface"; 2300 2301 qcom,din-ports = <0>; 2302 qcom,dout-ports = <5>; 2303 2304 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2305 reset-names = "swr_audio_cgcr"; 2306 2307 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2308 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2309 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2310 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2311 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2312 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2313 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2314 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2315 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2316 2317 #sound-dai-cells = <1>; 2318 #address-cells = <2>; 2319 #size-cells = <0>; 2320 2321 status = "disabled"; 2322 }; 2323 2324 lpass_tx_macro: codec@3220000 { 2325 compatible = "qcom,sc7280-lpass-tx-macro"; 2326 reg = <0 0x03220000 0 0x1000>; 2327 2328 pinctrl-names = "default"; 2329 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2330 2331 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2332 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2333 <&lpass_va_macro>; 2334 clock-names = "mclk", "npl", "fsgen"; 2335 2336 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2337 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2338 power-domain-names = "macro", "dcodec"; 2339 2340 #clock-cells = <0>; 2341 #sound-dai-cells = <1>; 2342 2343 status = "disabled"; 2344 }; 2345 2346 swr1: soundwire@3230000 { 2347 compatible = "qcom,soundwire-v1.6.0"; 2348 reg = <0 0x03230000 0 0x2000>; 2349 2350 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2351 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2352 clocks = <&lpass_tx_macro>; 2353 clock-names = "iface"; 2354 2355 qcom,din-ports = <3>; 2356 qcom,dout-ports = <0>; 2357 2358 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2359 reset-names = "swr_audio_cgcr"; 2360 2361 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2362 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2363 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2364 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2365 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2366 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2367 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2368 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2369 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2370 2371 #sound-dai-cells = <1>; 2372 #address-cells = <2>; 2373 #size-cells = <0>; 2374 2375 status = "disabled"; 2376 }; 2377 2378 lpass_audiocc: clock-controller@3300000 { 2379 compatible = "qcom,sc7280-lpassaudiocc"; 2380 reg = <0 0x03300000 0 0x30000>, 2381 <0 0x032a9000 0 0x1000>; 2382 clocks = <&rpmhcc RPMH_CXO_CLK>, 2383 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2384 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2385 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2386 #clock-cells = <1>; 2387 #power-domain-cells = <1>; 2388 #reset-cells = <1>; 2389 }; 2390 2391 lpass_va_macro: codec@3370000 { 2392 compatible = "qcom,sc7280-lpass-va-macro"; 2393 reg = <0 0x03370000 0 0x1000>; 2394 2395 pinctrl-names = "default"; 2396 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2397 2398 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2399 clock-names = "mclk"; 2400 2401 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2402 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2403 power-domain-names = "macro", "dcodec"; 2404 2405 #clock-cells = <0>; 2406 #sound-dai-cells = <1>; 2407 2408 status = "disabled"; 2409 }; 2410 2411 lpass_aon: clock-controller@3380000 { 2412 compatible = "qcom,sc7280-lpassaoncc"; 2413 reg = <0 0x03380000 0 0x30000>; 2414 clocks = <&rpmhcc RPMH_CXO_CLK>, 2415 <&rpmhcc RPMH_CXO_CLK_A>, 2416 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2417 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2418 #clock-cells = <1>; 2419 #power-domain-cells = <1>; 2420 }; 2421 2422 lpass_core: clock-controller@3900000 { 2423 compatible = "qcom,sc7280-lpasscorecc"; 2424 reg = <0 0x03900000 0 0x50000>; 2425 clocks = <&rpmhcc RPMH_CXO_CLK>; 2426 clock-names = "bi_tcxo"; 2427 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2428 #clock-cells = <1>; 2429 #power-domain-cells = <1>; 2430 }; 2431 2432 lpass_cpu: audio@3987000 { 2433 compatible = "qcom,sc7280-lpass-cpu"; 2434 2435 reg = <0 0x03987000 0 0x68000>, 2436 <0 0x03b00000 0 0x29000>, 2437 <0 0x03260000 0 0xc000>, 2438 <0 0x03280000 0 0x29000>, 2439 <0 0x03340000 0 0x29000>, 2440 <0 0x0336c000 0 0x3000>; 2441 reg-names = "lpass-hdmiif", 2442 "lpass-lpaif", 2443 "lpass-rxtx-cdc-dma-lpm", 2444 "lpass-rxtx-lpaif", 2445 "lpass-va-lpaif", 2446 "lpass-va-cdc-dma-lpm"; 2447 2448 iommus = <&apps_smmu 0x1820 0>, 2449 <&apps_smmu 0x1821 0>, 2450 <&apps_smmu 0x1832 0>; 2451 2452 power-domains = <&rpmhpd SC7280_LCX>; 2453 power-domain-names = "lcx"; 2454 required-opps = <&rpmhpd_opp_nom>; 2455 2456 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2457 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2458 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2459 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2460 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2461 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2462 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2463 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2464 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2465 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2466 clock-names = "aon_cc_audio_hm_h", 2467 "audio_cc_ext_mclk0", 2468 "core_cc_sysnoc_mport_core", 2469 "core_cc_ext_if0_ibit", 2470 "core_cc_ext_if1_ibit", 2471 "audio_cc_codec_mem", 2472 "audio_cc_codec_mem0", 2473 "audio_cc_codec_mem1", 2474 "audio_cc_codec_mem2", 2475 "aon_cc_va_mem0"; 2476 2477 #sound-dai-cells = <1>; 2478 #address-cells = <1>; 2479 #size-cells = <0>; 2480 2481 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2482 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2483 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2484 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2485 interrupt-names = "lpass-irq-lpaif", 2486 "lpass-irq-hdmi", 2487 "lpass-irq-vaif", 2488 "lpass-irq-rxtxif"; 2489 2490 status = "disabled"; 2491 }; 2492 2493 lpass_hm: clock-controller@3c00000 { 2494 compatible = "qcom,sc7280-lpasshm"; 2495 reg = <0 0x03c00000 0 0x28>; 2496 clocks = <&rpmhcc RPMH_CXO_CLK>; 2497 clock-names = "bi_tcxo"; 2498 #clock-cells = <1>; 2499 #power-domain-cells = <1>; 2500 }; 2501 2502 lpass_ag_noc: interconnect@3c40000 { 2503 reg = <0 0x03c40000 0 0xf080>; 2504 compatible = "qcom,sc7280-lpass-ag-noc"; 2505 #interconnect-cells = <2>; 2506 qcom,bcm-voters = <&apps_bcm_voter>; 2507 }; 2508 2509 lpass_tlmm: pinctrl@33c0000 { 2510 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2511 reg = <0 0x033c0000 0x0 0x20000>, 2512 <0 0x03550000 0x0 0x10000>; 2513 qcom,adsp-bypass-mode; 2514 gpio-controller; 2515 #gpio-cells = <2>; 2516 gpio-ranges = <&lpass_tlmm 0 0 15>; 2517 2518 lpass_dmic01_clk: dmic01-clk-state { 2519 pins = "gpio6"; 2520 function = "dmic1_clk"; 2521 }; 2522 2523 lpass_dmic01_data: dmic01-data-state { 2524 pins = "gpio7"; 2525 function = "dmic1_data"; 2526 }; 2527 2528 lpass_dmic23_clk: dmic23-clk-state { 2529 pins = "gpio8"; 2530 function = "dmic2_clk"; 2531 }; 2532 2533 lpass_dmic23_data: dmic23-data-state { 2534 pins = "gpio9"; 2535 function = "dmic2_data"; 2536 }; 2537 2538 lpass_rx_swr_clk: rx-swr-clk-state { 2539 pins = "gpio3"; 2540 function = "swr_rx_clk"; 2541 }; 2542 2543 lpass_rx_swr_data: rx-swr-data-state { 2544 pins = "gpio4", "gpio5"; 2545 function = "swr_rx_data"; 2546 }; 2547 2548 lpass_tx_swr_clk: tx-swr-clk-state { 2549 pins = "gpio0"; 2550 function = "swr_tx_clk"; 2551 }; 2552 2553 lpass_tx_swr_data: tx-swr-data-state { 2554 pins = "gpio1", "gpio2", "gpio14"; 2555 function = "swr_tx_data"; 2556 }; 2557 }; 2558 2559 gpu: gpu@3d00000 { 2560 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2561 reg = <0 0x03d00000 0 0x40000>, 2562 <0 0x03d9e000 0 0x1000>, 2563 <0 0x03d61000 0 0x800>; 2564 reg-names = "kgsl_3d0_reg_memory", 2565 "cx_mem", 2566 "cx_dbgc"; 2567 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2568 iommus = <&adreno_smmu 0 0x401>; 2569 operating-points-v2 = <&gpu_opp_table>; 2570 qcom,gmu = <&gmu>; 2571 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2572 interconnect-names = "gfx-mem"; 2573 #cooling-cells = <2>; 2574 2575 nvmem-cells = <&gpu_speed_bin>; 2576 nvmem-cell-names = "speed_bin"; 2577 2578 gpu_opp_table: opp-table { 2579 compatible = "operating-points-v2"; 2580 2581 opp-315000000 { 2582 opp-hz = /bits/ 64 <315000000>; 2583 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2584 opp-peak-kBps = <1804000>; 2585 opp-supported-hw = <0x03>; 2586 }; 2587 2588 opp-450000000 { 2589 opp-hz = /bits/ 64 <450000000>; 2590 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2591 opp-peak-kBps = <4068000>; 2592 opp-supported-hw = <0x03>; 2593 }; 2594 2595 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2596 opp-550000000-0 { 2597 opp-hz = /bits/ 64 <550000000>; 2598 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2599 opp-peak-kBps = <8368000>; 2600 opp-supported-hw = <0x01>; 2601 }; 2602 2603 opp-550000000-1 { 2604 opp-hz = /bits/ 64 <550000000>; 2605 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2606 opp-peak-kBps = <6832000>; 2607 opp-supported-hw = <0x02>; 2608 }; 2609 2610 opp-608000000 { 2611 opp-hz = /bits/ 64 <608000000>; 2612 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2613 opp-peak-kBps = <8368000>; 2614 opp-supported-hw = <0x02>; 2615 }; 2616 2617 opp-700000000 { 2618 opp-hz = /bits/ 64 <700000000>; 2619 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2620 opp-peak-kBps = <8532000>; 2621 opp-supported-hw = <0x02>; 2622 }; 2623 2624 opp-812000000 { 2625 opp-hz = /bits/ 64 <812000000>; 2626 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2627 opp-peak-kBps = <8532000>; 2628 opp-supported-hw = <0x02>; 2629 }; 2630 2631 opp-840000000 { 2632 opp-hz = /bits/ 64 <840000000>; 2633 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2634 opp-peak-kBps = <8532000>; 2635 opp-supported-hw = <0x02>; 2636 }; 2637 2638 opp-900000000 { 2639 opp-hz = /bits/ 64 <900000000>; 2640 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2641 opp-peak-kBps = <8532000>; 2642 opp-supported-hw = <0x02>; 2643 }; 2644 }; 2645 }; 2646 2647 gmu: gmu@3d6a000 { 2648 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2649 reg = <0 0x03d6a000 0 0x34000>, 2650 <0 0x3de0000 0 0x10000>, 2651 <0 0x0b290000 0 0x10000>; 2652 reg-names = "gmu", "rscc", "gmu_pdc"; 2653 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2654 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2655 interrupt-names = "hfi", "gmu"; 2656 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2657 <&gpucc GPU_CC_CXO_CLK>, 2658 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2659 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2660 <&gpucc GPU_CC_AHB_CLK>, 2661 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2662 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2663 clock-names = "gmu", 2664 "cxo", 2665 "axi", 2666 "memnoc", 2667 "ahb", 2668 "hub", 2669 "smmu_vote"; 2670 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2671 <&gpucc GPU_CC_GX_GDSC>; 2672 power-domain-names = "cx", 2673 "gx"; 2674 iommus = <&adreno_smmu 5 0x400>; 2675 operating-points-v2 = <&gmu_opp_table>; 2676 2677 gmu_opp_table: opp-table { 2678 compatible = "operating-points-v2"; 2679 2680 opp-200000000 { 2681 opp-hz = /bits/ 64 <200000000>; 2682 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2683 }; 2684 }; 2685 }; 2686 2687 gpucc: clock-controller@3d90000 { 2688 compatible = "qcom,sc7280-gpucc"; 2689 reg = <0 0x03d90000 0 0x9000>; 2690 clocks = <&rpmhcc RPMH_CXO_CLK>, 2691 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2692 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2693 clock-names = "bi_tcxo", 2694 "gcc_gpu_gpll0_clk_src", 2695 "gcc_gpu_gpll0_div_clk_src"; 2696 #clock-cells = <1>; 2697 #reset-cells = <1>; 2698 #power-domain-cells = <1>; 2699 }; 2700 2701 dma@117f000 { 2702 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 2703 reg = <0x0 0x0117f000 0x0 0x1000>, 2704 <0x0 0x01112000 0x0 0x6000>; 2705 }; 2706 2707 adreno_smmu: iommu@3da0000 { 2708 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", 2709 "qcom,smmu-500", "arm,mmu-500"; 2710 reg = <0 0x03da0000 0 0x20000>; 2711 #iommu-cells = <2>; 2712 #global-interrupts = <2>; 2713 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2714 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2715 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2716 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2717 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2718 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2719 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2720 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2721 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2722 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2723 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2724 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2725 2726 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2727 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2728 <&gpucc GPU_CC_AHB_CLK>, 2729 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2730 <&gpucc GPU_CC_CX_GMU_CLK>, 2731 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2732 <&gpucc GPU_CC_HUB_AON_CLK>; 2733 clock-names = "gcc_gpu_memnoc_gfx_clk", 2734 "gcc_gpu_snoc_dvm_gfx_clk", 2735 "gpu_cc_ahb_clk", 2736 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2737 "gpu_cc_cx_gmu_clk", 2738 "gpu_cc_hub_cx_int_clk", 2739 "gpu_cc_hub_aon_clk"; 2740 2741 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2742 }; 2743 2744 remoteproc_mpss: remoteproc@4080000 { 2745 compatible = "qcom,sc7280-mpss-pas"; 2746 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2747 reg-names = "qdsp6", "rmb"; 2748 2749 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2750 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2751 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2752 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2753 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2754 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2755 interrupt-names = "wdog", "fatal", "ready", "handover", 2756 "stop-ack", "shutdown-ack"; 2757 2758 clocks = <&rpmhcc RPMH_CXO_CLK>; 2759 clock-names = "xo"; 2760 2761 power-domains = <&rpmhpd SC7280_CX>, 2762 <&rpmhpd SC7280_MSS>; 2763 power-domain-names = "cx", "mss"; 2764 2765 memory-region = <&mpss_mem>; 2766 2767 qcom,qmp = <&aoss_qmp>; 2768 2769 qcom,smem-states = <&modem_smp2p_out 0>; 2770 qcom,smem-state-names = "stop"; 2771 2772 status = "disabled"; 2773 2774 glink-edge { 2775 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2776 IPCC_MPROC_SIGNAL_GLINK_QMP 2777 IRQ_TYPE_EDGE_RISING>; 2778 mboxes = <&ipcc IPCC_CLIENT_MPSS 2779 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2780 label = "modem"; 2781 qcom,remote-pid = <1>; 2782 }; 2783 }; 2784 2785 stm@6002000 { 2786 compatible = "arm,coresight-stm", "arm,primecell"; 2787 reg = <0 0x06002000 0 0x1000>, 2788 <0 0x16280000 0 0x180000>; 2789 reg-names = "stm-base", "stm-stimulus-base"; 2790 2791 clocks = <&aoss_qmp>; 2792 clock-names = "apb_pclk"; 2793 2794 out-ports { 2795 port { 2796 stm_out: endpoint { 2797 remote-endpoint = <&funnel0_in7>; 2798 }; 2799 }; 2800 }; 2801 }; 2802 2803 funnel@6041000 { 2804 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2805 reg = <0 0x06041000 0 0x1000>; 2806 2807 clocks = <&aoss_qmp>; 2808 clock-names = "apb_pclk"; 2809 2810 out-ports { 2811 port { 2812 funnel0_out: endpoint { 2813 remote-endpoint = <&merge_funnel_in0>; 2814 }; 2815 }; 2816 }; 2817 2818 in-ports { 2819 #address-cells = <1>; 2820 #size-cells = <0>; 2821 2822 port@7 { 2823 reg = <7>; 2824 funnel0_in7: endpoint { 2825 remote-endpoint = <&stm_out>; 2826 }; 2827 }; 2828 }; 2829 }; 2830 2831 funnel@6042000 { 2832 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2833 reg = <0 0x06042000 0 0x1000>; 2834 2835 clocks = <&aoss_qmp>; 2836 clock-names = "apb_pclk"; 2837 2838 out-ports { 2839 port { 2840 funnel1_out: endpoint { 2841 remote-endpoint = <&merge_funnel_in1>; 2842 }; 2843 }; 2844 }; 2845 2846 in-ports { 2847 #address-cells = <1>; 2848 #size-cells = <0>; 2849 2850 port@4 { 2851 reg = <4>; 2852 funnel1_in4: endpoint { 2853 remote-endpoint = <&apss_merge_funnel_out>; 2854 }; 2855 }; 2856 }; 2857 }; 2858 2859 funnel@6045000 { 2860 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2861 reg = <0 0x06045000 0 0x1000>; 2862 2863 clocks = <&aoss_qmp>; 2864 clock-names = "apb_pclk"; 2865 2866 out-ports { 2867 port { 2868 merge_funnel_out: endpoint { 2869 remote-endpoint = <&swao_funnel_in>; 2870 }; 2871 }; 2872 }; 2873 2874 in-ports { 2875 #address-cells = <1>; 2876 #size-cells = <0>; 2877 2878 port@0 { 2879 reg = <0>; 2880 merge_funnel_in0: endpoint { 2881 remote-endpoint = <&funnel0_out>; 2882 }; 2883 }; 2884 2885 port@1 { 2886 reg = <1>; 2887 merge_funnel_in1: endpoint { 2888 remote-endpoint = <&funnel1_out>; 2889 }; 2890 }; 2891 }; 2892 }; 2893 2894 replicator@6046000 { 2895 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2896 reg = <0 0x06046000 0 0x1000>; 2897 2898 clocks = <&aoss_qmp>; 2899 clock-names = "apb_pclk"; 2900 2901 out-ports { 2902 port { 2903 replicator_out: endpoint { 2904 remote-endpoint = <&etr_in>; 2905 }; 2906 }; 2907 }; 2908 2909 in-ports { 2910 port { 2911 replicator_in: endpoint { 2912 remote-endpoint = <&swao_replicator_out>; 2913 }; 2914 }; 2915 }; 2916 }; 2917 2918 etr@6048000 { 2919 compatible = "arm,coresight-tmc", "arm,primecell"; 2920 reg = <0 0x06048000 0 0x1000>; 2921 iommus = <&apps_smmu 0x04c0 0>; 2922 2923 clocks = <&aoss_qmp>; 2924 clock-names = "apb_pclk"; 2925 arm,scatter-gather; 2926 2927 in-ports { 2928 port { 2929 etr_in: endpoint { 2930 remote-endpoint = <&replicator_out>; 2931 }; 2932 }; 2933 }; 2934 }; 2935 2936 funnel@6b04000 { 2937 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2938 reg = <0 0x06b04000 0 0x1000>; 2939 2940 clocks = <&aoss_qmp>; 2941 clock-names = "apb_pclk"; 2942 2943 out-ports { 2944 port { 2945 swao_funnel_out: endpoint { 2946 remote-endpoint = <&etf_in>; 2947 }; 2948 }; 2949 }; 2950 2951 in-ports { 2952 #address-cells = <1>; 2953 #size-cells = <0>; 2954 2955 port@7 { 2956 reg = <7>; 2957 swao_funnel_in: endpoint { 2958 remote-endpoint = <&merge_funnel_out>; 2959 }; 2960 }; 2961 }; 2962 }; 2963 2964 etf@6b05000 { 2965 compatible = "arm,coresight-tmc", "arm,primecell"; 2966 reg = <0 0x06b05000 0 0x1000>; 2967 2968 clocks = <&aoss_qmp>; 2969 clock-names = "apb_pclk"; 2970 2971 out-ports { 2972 port { 2973 etf_out: endpoint { 2974 remote-endpoint = <&swao_replicator_in>; 2975 }; 2976 }; 2977 }; 2978 2979 in-ports { 2980 port { 2981 etf_in: endpoint { 2982 remote-endpoint = <&swao_funnel_out>; 2983 }; 2984 }; 2985 }; 2986 }; 2987 2988 replicator@6b06000 { 2989 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2990 reg = <0 0x06b06000 0 0x1000>; 2991 2992 clocks = <&aoss_qmp>; 2993 clock-names = "apb_pclk"; 2994 qcom,replicator-loses-context; 2995 2996 out-ports { 2997 port { 2998 swao_replicator_out: endpoint { 2999 remote-endpoint = <&replicator_in>; 3000 }; 3001 }; 3002 }; 3003 3004 in-ports { 3005 port { 3006 swao_replicator_in: endpoint { 3007 remote-endpoint = <&etf_out>; 3008 }; 3009 }; 3010 }; 3011 }; 3012 3013 etm@7040000 { 3014 compatible = "arm,coresight-etm4x", "arm,primecell"; 3015 reg = <0 0x07040000 0 0x1000>; 3016 3017 cpu = <&CPU0>; 3018 3019 clocks = <&aoss_qmp>; 3020 clock-names = "apb_pclk"; 3021 arm,coresight-loses-context-with-cpu; 3022 qcom,skip-power-up; 3023 3024 out-ports { 3025 port { 3026 etm0_out: endpoint { 3027 remote-endpoint = <&apss_funnel_in0>; 3028 }; 3029 }; 3030 }; 3031 }; 3032 3033 etm@7140000 { 3034 compatible = "arm,coresight-etm4x", "arm,primecell"; 3035 reg = <0 0x07140000 0 0x1000>; 3036 3037 cpu = <&CPU1>; 3038 3039 clocks = <&aoss_qmp>; 3040 clock-names = "apb_pclk"; 3041 arm,coresight-loses-context-with-cpu; 3042 qcom,skip-power-up; 3043 3044 out-ports { 3045 port { 3046 etm1_out: endpoint { 3047 remote-endpoint = <&apss_funnel_in1>; 3048 }; 3049 }; 3050 }; 3051 }; 3052 3053 etm@7240000 { 3054 compatible = "arm,coresight-etm4x", "arm,primecell"; 3055 reg = <0 0x07240000 0 0x1000>; 3056 3057 cpu = <&CPU2>; 3058 3059 clocks = <&aoss_qmp>; 3060 clock-names = "apb_pclk"; 3061 arm,coresight-loses-context-with-cpu; 3062 qcom,skip-power-up; 3063 3064 out-ports { 3065 port { 3066 etm2_out: endpoint { 3067 remote-endpoint = <&apss_funnel_in2>; 3068 }; 3069 }; 3070 }; 3071 }; 3072 3073 etm@7340000 { 3074 compatible = "arm,coresight-etm4x", "arm,primecell"; 3075 reg = <0 0x07340000 0 0x1000>; 3076 3077 cpu = <&CPU3>; 3078 3079 clocks = <&aoss_qmp>; 3080 clock-names = "apb_pclk"; 3081 arm,coresight-loses-context-with-cpu; 3082 qcom,skip-power-up; 3083 3084 out-ports { 3085 port { 3086 etm3_out: endpoint { 3087 remote-endpoint = <&apss_funnel_in3>; 3088 }; 3089 }; 3090 }; 3091 }; 3092 3093 etm@7440000 { 3094 compatible = "arm,coresight-etm4x", "arm,primecell"; 3095 reg = <0 0x07440000 0 0x1000>; 3096 3097 cpu = <&CPU4>; 3098 3099 clocks = <&aoss_qmp>; 3100 clock-names = "apb_pclk"; 3101 arm,coresight-loses-context-with-cpu; 3102 qcom,skip-power-up; 3103 3104 out-ports { 3105 port { 3106 etm4_out: endpoint { 3107 remote-endpoint = <&apss_funnel_in4>; 3108 }; 3109 }; 3110 }; 3111 }; 3112 3113 etm@7540000 { 3114 compatible = "arm,coresight-etm4x", "arm,primecell"; 3115 reg = <0 0x07540000 0 0x1000>; 3116 3117 cpu = <&CPU5>; 3118 3119 clocks = <&aoss_qmp>; 3120 clock-names = "apb_pclk"; 3121 arm,coresight-loses-context-with-cpu; 3122 qcom,skip-power-up; 3123 3124 out-ports { 3125 port { 3126 etm5_out: endpoint { 3127 remote-endpoint = <&apss_funnel_in5>; 3128 }; 3129 }; 3130 }; 3131 }; 3132 3133 etm@7640000 { 3134 compatible = "arm,coresight-etm4x", "arm,primecell"; 3135 reg = <0 0x07640000 0 0x1000>; 3136 3137 cpu = <&CPU6>; 3138 3139 clocks = <&aoss_qmp>; 3140 clock-names = "apb_pclk"; 3141 arm,coresight-loses-context-with-cpu; 3142 qcom,skip-power-up; 3143 3144 out-ports { 3145 port { 3146 etm6_out: endpoint { 3147 remote-endpoint = <&apss_funnel_in6>; 3148 }; 3149 }; 3150 }; 3151 }; 3152 3153 etm@7740000 { 3154 compatible = "arm,coresight-etm4x", "arm,primecell"; 3155 reg = <0 0x07740000 0 0x1000>; 3156 3157 cpu = <&CPU7>; 3158 3159 clocks = <&aoss_qmp>; 3160 clock-names = "apb_pclk"; 3161 arm,coresight-loses-context-with-cpu; 3162 qcom,skip-power-up; 3163 3164 out-ports { 3165 port { 3166 etm7_out: endpoint { 3167 remote-endpoint = <&apss_funnel_in7>; 3168 }; 3169 }; 3170 }; 3171 }; 3172 3173 funnel@7800000 { /* APSS Funnel */ 3174 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3175 reg = <0 0x07800000 0 0x1000>; 3176 3177 clocks = <&aoss_qmp>; 3178 clock-names = "apb_pclk"; 3179 3180 out-ports { 3181 port { 3182 apss_funnel_out: endpoint { 3183 remote-endpoint = <&apss_merge_funnel_in>; 3184 }; 3185 }; 3186 }; 3187 3188 in-ports { 3189 #address-cells = <1>; 3190 #size-cells = <0>; 3191 3192 port@0 { 3193 reg = <0>; 3194 apss_funnel_in0: endpoint { 3195 remote-endpoint = <&etm0_out>; 3196 }; 3197 }; 3198 3199 port@1 { 3200 reg = <1>; 3201 apss_funnel_in1: endpoint { 3202 remote-endpoint = <&etm1_out>; 3203 }; 3204 }; 3205 3206 port@2 { 3207 reg = <2>; 3208 apss_funnel_in2: endpoint { 3209 remote-endpoint = <&etm2_out>; 3210 }; 3211 }; 3212 3213 port@3 { 3214 reg = <3>; 3215 apss_funnel_in3: endpoint { 3216 remote-endpoint = <&etm3_out>; 3217 }; 3218 }; 3219 3220 port@4 { 3221 reg = <4>; 3222 apss_funnel_in4: endpoint { 3223 remote-endpoint = <&etm4_out>; 3224 }; 3225 }; 3226 3227 port@5 { 3228 reg = <5>; 3229 apss_funnel_in5: endpoint { 3230 remote-endpoint = <&etm5_out>; 3231 }; 3232 }; 3233 3234 port@6 { 3235 reg = <6>; 3236 apss_funnel_in6: endpoint { 3237 remote-endpoint = <&etm6_out>; 3238 }; 3239 }; 3240 3241 port@7 { 3242 reg = <7>; 3243 apss_funnel_in7: endpoint { 3244 remote-endpoint = <&etm7_out>; 3245 }; 3246 }; 3247 }; 3248 }; 3249 3250 funnel@7810000 { 3251 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3252 reg = <0 0x07810000 0 0x1000>; 3253 3254 clocks = <&aoss_qmp>; 3255 clock-names = "apb_pclk"; 3256 3257 out-ports { 3258 port { 3259 apss_merge_funnel_out: endpoint { 3260 remote-endpoint = <&funnel1_in4>; 3261 }; 3262 }; 3263 }; 3264 3265 in-ports { 3266 port { 3267 apss_merge_funnel_in: endpoint { 3268 remote-endpoint = <&apss_funnel_out>; 3269 }; 3270 }; 3271 }; 3272 }; 3273 3274 sdhc_2: mmc@8804000 { 3275 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3276 pinctrl-names = "default", "sleep"; 3277 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3278 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3279 status = "disabled"; 3280 3281 reg = <0 0x08804000 0 0x1000>; 3282 3283 iommus = <&apps_smmu 0x100 0x0>; 3284 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3285 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3286 interrupt-names = "hc_irq", "pwr_irq"; 3287 3288 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3289 <&gcc GCC_SDCC2_APPS_CLK>, 3290 <&rpmhcc RPMH_CXO_CLK>; 3291 clock-names = "iface", "core", "xo"; 3292 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3293 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3294 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3295 power-domains = <&rpmhpd SC7280_CX>; 3296 operating-points-v2 = <&sdhc2_opp_table>; 3297 3298 bus-width = <4>; 3299 3300 qcom,dll-config = <0x0007642c>; 3301 3302 resets = <&gcc GCC_SDCC2_BCR>; 3303 3304 sdhc2_opp_table: opp-table { 3305 compatible = "operating-points-v2"; 3306 3307 opp-100000000 { 3308 opp-hz = /bits/ 64 <100000000>; 3309 required-opps = <&rpmhpd_opp_low_svs>; 3310 opp-peak-kBps = <1800000 400000>; 3311 opp-avg-kBps = <100000 0>; 3312 }; 3313 3314 opp-202000000 { 3315 opp-hz = /bits/ 64 <202000000>; 3316 required-opps = <&rpmhpd_opp_nom>; 3317 opp-peak-kBps = <5400000 1600000>; 3318 opp-avg-kBps = <200000 0>; 3319 }; 3320 }; 3321 }; 3322 3323 usb_1_hsphy: phy@88e3000 { 3324 compatible = "qcom,sc7280-usb-hs-phy", 3325 "qcom,usb-snps-hs-7nm-phy"; 3326 reg = <0 0x088e3000 0 0x400>; 3327 status = "disabled"; 3328 #phy-cells = <0>; 3329 3330 clocks = <&rpmhcc RPMH_CXO_CLK>; 3331 clock-names = "ref"; 3332 3333 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3334 }; 3335 3336 usb_2_hsphy: phy@88e4000 { 3337 compatible = "qcom,sc7280-usb-hs-phy", 3338 "qcom,usb-snps-hs-7nm-phy"; 3339 reg = <0 0x088e4000 0 0x400>; 3340 status = "disabled"; 3341 #phy-cells = <0>; 3342 3343 clocks = <&rpmhcc RPMH_CXO_CLK>; 3344 clock-names = "ref"; 3345 3346 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3347 }; 3348 3349 usb_1_qmpphy: phy-wrapper@88e9000 { 3350 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3351 "qcom,sm8250-qmp-usb3-dp-phy"; 3352 reg = <0 0x088e9000 0 0x200>, 3353 <0 0x088e8000 0 0x40>, 3354 <0 0x088ea000 0 0x200>; 3355 status = "disabled"; 3356 #address-cells = <2>; 3357 #size-cells = <2>; 3358 ranges; 3359 3360 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3361 <&rpmhcc RPMH_CXO_CLK>, 3362 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3363 clock-names = "aux", "ref_clk_src", "com_aux"; 3364 3365 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3366 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3367 reset-names = "phy", "common"; 3368 3369 usb_1_ssphy: usb3-phy@88e9200 { 3370 reg = <0 0x088e9200 0 0x200>, 3371 <0 0x088e9400 0 0x200>, 3372 <0 0x088e9c00 0 0x400>, 3373 <0 0x088e9600 0 0x200>, 3374 <0 0x088e9800 0 0x200>, 3375 <0 0x088e9a00 0 0x100>; 3376 #clock-cells = <0>; 3377 #phy-cells = <0>; 3378 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3379 clock-names = "pipe0"; 3380 clock-output-names = "usb3_phy_pipe_clk_src"; 3381 }; 3382 3383 dp_phy: dp-phy@88ea200 { 3384 reg = <0 0x088ea200 0 0x200>, 3385 <0 0x088ea400 0 0x200>, 3386 <0 0x088eaa00 0 0x200>, 3387 <0 0x088ea600 0 0x200>, 3388 <0 0x088ea800 0 0x200>; 3389 #phy-cells = <0>; 3390 #clock-cells = <1>; 3391 }; 3392 }; 3393 3394 usb_2: usb@8cf8800 { 3395 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3396 reg = <0 0x08cf8800 0 0x400>; 3397 status = "disabled"; 3398 #address-cells = <2>; 3399 #size-cells = <2>; 3400 ranges; 3401 dma-ranges; 3402 3403 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3404 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3405 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3406 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3407 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3408 clock-names = "cfg_noc", 3409 "core", 3410 "iface", 3411 "sleep", 3412 "mock_utmi"; 3413 3414 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3415 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3416 assigned-clock-rates = <19200000>, <200000000>; 3417 3418 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3419 <&pdc 12 IRQ_TYPE_EDGE_RISING>, 3420 <&pdc 13 IRQ_TYPE_EDGE_RISING>; 3421 interrupt-names = "hs_phy_irq", 3422 "dp_hs_phy_irq", 3423 "dm_hs_phy_irq"; 3424 3425 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3426 required-opps = <&rpmhpd_opp_nom>; 3427 3428 resets = <&gcc GCC_USB30_SEC_BCR>; 3429 3430 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3431 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3432 interconnect-names = "usb-ddr", "apps-usb"; 3433 3434 usb_2_dwc3: usb@8c00000 { 3435 compatible = "snps,dwc3"; 3436 reg = <0 0x08c00000 0 0xe000>; 3437 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3438 iommus = <&apps_smmu 0xa0 0x0>; 3439 snps,dis_u2_susphy_quirk; 3440 snps,dis_enblslpm_quirk; 3441 phys = <&usb_2_hsphy>; 3442 phy-names = "usb2-phy"; 3443 maximum-speed = "high-speed"; 3444 usb-role-switch; 3445 3446 port { 3447 usb2_role_switch: endpoint { 3448 remote-endpoint = <&eud_ep>; 3449 }; 3450 }; 3451 }; 3452 }; 3453 3454 qspi: spi@88dc000 { 3455 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3456 reg = <0 0x088dc000 0 0x1000>; 3457 iommus = <&apps_smmu 0x20 0x0>; 3458 #address-cells = <1>; 3459 #size-cells = <0>; 3460 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3461 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3462 <&gcc GCC_QSPI_CORE_CLK>; 3463 clock-names = "iface", "core"; 3464 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3465 &cnoc2 SLAVE_QSPI_0 0>; 3466 interconnect-names = "qspi-config"; 3467 power-domains = <&rpmhpd SC7280_CX>; 3468 operating-points-v2 = <&qspi_opp_table>; 3469 status = "disabled"; 3470 }; 3471 3472 remoteproc_wpss: remoteproc@8a00000 { 3473 compatible = "qcom,sc7280-wpss-pil"; 3474 reg = <0 0x08a00000 0 0x10000>; 3475 3476 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3477 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3478 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3479 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3480 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3481 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3482 interrupt-names = "wdog", "fatal", "ready", "handover", 3483 "stop-ack", "shutdown-ack"; 3484 3485 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3486 <&gcc GCC_WPSS_AHB_CLK>, 3487 <&gcc GCC_WPSS_RSCP_CLK>, 3488 <&rpmhcc RPMH_CXO_CLK>; 3489 clock-names = "ahb_bdg", "ahb", 3490 "rscp", "xo"; 3491 3492 power-domains = <&rpmhpd SC7280_CX>, 3493 <&rpmhpd SC7280_MX>; 3494 power-domain-names = "cx", "mx"; 3495 3496 memory-region = <&wpss_mem>; 3497 3498 qcom,qmp = <&aoss_qmp>; 3499 3500 qcom,smem-states = <&wpss_smp2p_out 0>; 3501 qcom,smem-state-names = "stop"; 3502 3503 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3504 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3505 reset-names = "restart", "pdc_sync"; 3506 3507 qcom,halt-regs = <&tcsr_1 0x17000>; 3508 3509 status = "disabled"; 3510 3511 glink-edge { 3512 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3513 IPCC_MPROC_SIGNAL_GLINK_QMP 3514 IRQ_TYPE_EDGE_RISING>; 3515 mboxes = <&ipcc IPCC_CLIENT_WPSS 3516 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3517 3518 label = "wpss"; 3519 qcom,remote-pid = <13>; 3520 }; 3521 }; 3522 3523 pmu@9091000 { 3524 compatible = "qcom,sc7280-llcc-bwmon"; 3525 reg = <0 0x09091000 0 0x1000>; 3526 3527 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3528 3529 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3530 3531 operating-points-v2 = <&llcc_bwmon_opp_table>; 3532 3533 llcc_bwmon_opp_table: opp-table { 3534 compatible = "operating-points-v2"; 3535 3536 opp-0 { 3537 opp-peak-kBps = <800000>; 3538 }; 3539 opp-1 { 3540 opp-peak-kBps = <1804000>; 3541 }; 3542 opp-2 { 3543 opp-peak-kBps = <2188000>; 3544 }; 3545 opp-3 { 3546 opp-peak-kBps = <3072000>; 3547 }; 3548 opp-4 { 3549 opp-peak-kBps = <4068000>; 3550 }; 3551 opp-5 { 3552 opp-peak-kBps = <6220000>; 3553 }; 3554 opp-6 { 3555 opp-peak-kBps = <6832000>; 3556 }; 3557 opp-7 { 3558 opp-peak-kBps = <8532000>; 3559 }; 3560 }; 3561 }; 3562 3563 pmu@90b6400 { 3564 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; 3565 reg = <0 0x090b6400 0 0x600>; 3566 3567 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3568 3569 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3570 operating-points-v2 = <&cpu_bwmon_opp_table>; 3571 3572 cpu_bwmon_opp_table: opp-table { 3573 compatible = "operating-points-v2"; 3574 3575 opp-0 { 3576 opp-peak-kBps = <2400000>; 3577 }; 3578 opp-1 { 3579 opp-peak-kBps = <4800000>; 3580 }; 3581 opp-2 { 3582 opp-peak-kBps = <7456000>; 3583 }; 3584 opp-3 { 3585 opp-peak-kBps = <9600000>; 3586 }; 3587 opp-4 { 3588 opp-peak-kBps = <12896000>; 3589 }; 3590 opp-5 { 3591 opp-peak-kBps = <14928000>; 3592 }; 3593 opp-6 { 3594 opp-peak-kBps = <17056000>; 3595 }; 3596 }; 3597 }; 3598 3599 dc_noc: interconnect@90e0000 { 3600 reg = <0 0x090e0000 0 0x5080>; 3601 compatible = "qcom,sc7280-dc-noc"; 3602 #interconnect-cells = <2>; 3603 qcom,bcm-voters = <&apps_bcm_voter>; 3604 }; 3605 3606 gem_noc: interconnect@9100000 { 3607 reg = <0 0x09100000 0 0xe2200>; 3608 compatible = "qcom,sc7280-gem-noc"; 3609 #interconnect-cells = <2>; 3610 qcom,bcm-voters = <&apps_bcm_voter>; 3611 }; 3612 3613 system-cache-controller@9200000 { 3614 compatible = "qcom,sc7280-llcc"; 3615 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3616 <0 0x09600000 0 0x58000>; 3617 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; 3618 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3619 }; 3620 3621 eud: eud@88e0000 { 3622 compatible = "qcom,sc7280-eud", "qcom,eud"; 3623 reg = <0 0x88e0000 0 0x2000>, 3624 <0 0x88e2000 0 0x1000>; 3625 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3626 3627 ports { 3628 #address-cells = <1>; 3629 #size-cells = <0>; 3630 3631 port@0 { 3632 reg = <0>; 3633 eud_ep: endpoint { 3634 remote-endpoint = <&usb2_role_switch>; 3635 }; 3636 }; 3637 3638 port@1 { 3639 reg = <1>; 3640 eud_con: endpoint { 3641 remote-endpoint = <&con_eud>; 3642 }; 3643 }; 3644 }; 3645 }; 3646 3647 nsp_noc: interconnect@a0c0000 { 3648 reg = <0 0x0a0c0000 0 0x10000>; 3649 compatible = "qcom,sc7280-nsp-noc"; 3650 #interconnect-cells = <2>; 3651 qcom,bcm-voters = <&apps_bcm_voter>; 3652 }; 3653 3654 usb_1: usb@a6f8800 { 3655 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3656 reg = <0 0x0a6f8800 0 0x400>; 3657 status = "disabled"; 3658 #address-cells = <2>; 3659 #size-cells = <2>; 3660 ranges; 3661 dma-ranges; 3662 3663 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3664 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3665 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3666 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3667 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3668 clock-names = "cfg_noc", 3669 "core", 3670 "iface", 3671 "sleep", 3672 "mock_utmi"; 3673 3674 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3675 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3676 assigned-clock-rates = <19200000>, <200000000>; 3677 3678 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3679 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3680 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3681 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3682 interrupt-names = "hs_phy_irq", 3683 "dp_hs_phy_irq", 3684 "dm_hs_phy_irq", 3685 "ss_phy_irq"; 3686 3687 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3688 required-opps = <&rpmhpd_opp_nom>; 3689 3690 resets = <&gcc GCC_USB30_PRIM_BCR>; 3691 3692 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3693 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3694 interconnect-names = "usb-ddr", "apps-usb"; 3695 3696 wakeup-source; 3697 3698 usb_1_dwc3: usb@a600000 { 3699 compatible = "snps,dwc3"; 3700 reg = <0 0x0a600000 0 0xe000>; 3701 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3702 iommus = <&apps_smmu 0xe0 0x0>; 3703 snps,dis_u2_susphy_quirk; 3704 snps,dis_enblslpm_quirk; 3705 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3706 phy-names = "usb2-phy", "usb3-phy"; 3707 maximum-speed = "super-speed"; 3708 }; 3709 }; 3710 3711 venus: video-codec@aa00000 { 3712 compatible = "qcom,sc7280-venus"; 3713 reg = <0 0x0aa00000 0 0xd0600>; 3714 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3715 3716 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3717 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3718 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3719 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3720 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3721 clock-names = "core", "bus", "iface", 3722 "vcodec_core", "vcodec_bus"; 3723 3724 power-domains = <&videocc MVSC_GDSC>, 3725 <&videocc MVS0_GDSC>, 3726 <&rpmhpd SC7280_CX>; 3727 power-domain-names = "venus", "vcodec0", "cx"; 3728 operating-points-v2 = <&venus_opp_table>; 3729 3730 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3731 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3732 interconnect-names = "cpu-cfg", "video-mem"; 3733 3734 iommus = <&apps_smmu 0x2180 0x20>, 3735 <&apps_smmu 0x2184 0x20>; 3736 memory-region = <&video_mem>; 3737 3738 video-decoder { 3739 compatible = "venus-decoder"; 3740 }; 3741 3742 video-encoder { 3743 compatible = "venus-encoder"; 3744 }; 3745 3746 video-firmware { 3747 iommus = <&apps_smmu 0x21a2 0x0>; 3748 }; 3749 3750 venus_opp_table: opp-table { 3751 compatible = "operating-points-v2"; 3752 3753 opp-133330000 { 3754 opp-hz = /bits/ 64 <133330000>; 3755 required-opps = <&rpmhpd_opp_low_svs>; 3756 }; 3757 3758 opp-240000000 { 3759 opp-hz = /bits/ 64 <240000000>; 3760 required-opps = <&rpmhpd_opp_svs>; 3761 }; 3762 3763 opp-335000000 { 3764 opp-hz = /bits/ 64 <335000000>; 3765 required-opps = <&rpmhpd_opp_svs_l1>; 3766 }; 3767 3768 opp-424000000 { 3769 opp-hz = /bits/ 64 <424000000>; 3770 required-opps = <&rpmhpd_opp_nom>; 3771 }; 3772 3773 opp-460000048 { 3774 opp-hz = /bits/ 64 <460000048>; 3775 required-opps = <&rpmhpd_opp_turbo>; 3776 }; 3777 }; 3778 }; 3779 3780 videocc: clock-controller@aaf0000 { 3781 compatible = "qcom,sc7280-videocc"; 3782 reg = <0 0x0aaf0000 0 0x10000>; 3783 clocks = <&rpmhcc RPMH_CXO_CLK>, 3784 <&rpmhcc RPMH_CXO_CLK_A>; 3785 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3786 #clock-cells = <1>; 3787 #reset-cells = <1>; 3788 #power-domain-cells = <1>; 3789 }; 3790 3791 camcc: clock-controller@ad00000 { 3792 compatible = "qcom,sc7280-camcc"; 3793 reg = <0 0x0ad00000 0 0x10000>; 3794 clocks = <&rpmhcc RPMH_CXO_CLK>, 3795 <&rpmhcc RPMH_CXO_CLK_A>, 3796 <&sleep_clk>; 3797 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3798 #clock-cells = <1>; 3799 #reset-cells = <1>; 3800 #power-domain-cells = <1>; 3801 }; 3802 3803 dispcc: clock-controller@af00000 { 3804 compatible = "qcom,sc7280-dispcc"; 3805 reg = <0 0x0af00000 0 0x20000>; 3806 clocks = <&rpmhcc RPMH_CXO_CLK>, 3807 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3808 <&mdss_dsi_phy 0>, 3809 <&mdss_dsi_phy 1>, 3810 <&dp_phy 0>, 3811 <&dp_phy 1>, 3812 <&mdss_edp_phy 0>, 3813 <&mdss_edp_phy 1>; 3814 clock-names = "bi_tcxo", 3815 "gcc_disp_gpll0_clk", 3816 "dsi0_phy_pll_out_byteclk", 3817 "dsi0_phy_pll_out_dsiclk", 3818 "dp_phy_pll_link_clk", 3819 "dp_phy_pll_vco_div_clk", 3820 "edp_phy_pll_link_clk", 3821 "edp_phy_pll_vco_div_clk"; 3822 #clock-cells = <1>; 3823 #reset-cells = <1>; 3824 #power-domain-cells = <1>; 3825 }; 3826 3827 mdss: display-subsystem@ae00000 { 3828 compatible = "qcom,sc7280-mdss"; 3829 reg = <0 0x0ae00000 0 0x1000>; 3830 reg-names = "mdss"; 3831 3832 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3833 3834 clocks = <&gcc GCC_DISP_AHB_CLK>, 3835 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3836 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3837 clock-names = "iface", 3838 "ahb", 3839 "core"; 3840 3841 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3842 interrupt-controller; 3843 #interrupt-cells = <1>; 3844 3845 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3846 interconnect-names = "mdp0-mem"; 3847 3848 iommus = <&apps_smmu 0x900 0x402>; 3849 3850 #address-cells = <2>; 3851 #size-cells = <2>; 3852 ranges; 3853 3854 status = "disabled"; 3855 3856 mdss_mdp: display-controller@ae01000 { 3857 compatible = "qcom,sc7280-dpu"; 3858 reg = <0 0x0ae01000 0 0x8f030>, 3859 <0 0x0aeb0000 0 0x2008>; 3860 reg-names = "mdp", "vbif"; 3861 3862 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3863 <&gcc GCC_DISP_SF_AXI_CLK>, 3864 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3865 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3866 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3867 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3868 clock-names = "bus", 3869 "nrt_bus", 3870 "iface", 3871 "lut", 3872 "core", 3873 "vsync"; 3874 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3875 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3876 assigned-clock-rates = <19200000>, 3877 <19200000>; 3878 operating-points-v2 = <&mdp_opp_table>; 3879 power-domains = <&rpmhpd SC7280_CX>; 3880 3881 interrupt-parent = <&mdss>; 3882 interrupts = <0>; 3883 3884 ports { 3885 #address-cells = <1>; 3886 #size-cells = <0>; 3887 3888 port@0 { 3889 reg = <0>; 3890 dpu_intf1_out: endpoint { 3891 remote-endpoint = <&mdss_dsi0_in>; 3892 }; 3893 }; 3894 3895 port@1 { 3896 reg = <1>; 3897 dpu_intf5_out: endpoint { 3898 remote-endpoint = <&edp_in>; 3899 }; 3900 }; 3901 3902 port@2 { 3903 reg = <2>; 3904 dpu_intf0_out: endpoint { 3905 remote-endpoint = <&dp_in>; 3906 }; 3907 }; 3908 }; 3909 3910 mdp_opp_table: opp-table { 3911 compatible = "operating-points-v2"; 3912 3913 opp-200000000 { 3914 opp-hz = /bits/ 64 <200000000>; 3915 required-opps = <&rpmhpd_opp_low_svs>; 3916 }; 3917 3918 opp-300000000 { 3919 opp-hz = /bits/ 64 <300000000>; 3920 required-opps = <&rpmhpd_opp_svs>; 3921 }; 3922 3923 opp-380000000 { 3924 opp-hz = /bits/ 64 <380000000>; 3925 required-opps = <&rpmhpd_opp_svs_l1>; 3926 }; 3927 3928 opp-506666667 { 3929 opp-hz = /bits/ 64 <506666667>; 3930 required-opps = <&rpmhpd_opp_nom>; 3931 }; 3932 }; 3933 }; 3934 3935 mdss_dsi: dsi@ae94000 { 3936 compatible = "qcom,sc7280-dsi-ctrl", 3937 "qcom,mdss-dsi-ctrl"; 3938 reg = <0 0x0ae94000 0 0x400>; 3939 reg-names = "dsi_ctrl"; 3940 3941 interrupt-parent = <&mdss>; 3942 interrupts = <4>; 3943 3944 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3945 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3946 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3947 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3948 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3949 <&gcc GCC_DISP_HF_AXI_CLK>; 3950 clock-names = "byte", 3951 "byte_intf", 3952 "pixel", 3953 "core", 3954 "iface", 3955 "bus"; 3956 3957 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3958 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; 3959 3960 operating-points-v2 = <&dsi_opp_table>; 3961 power-domains = <&rpmhpd SC7280_CX>; 3962 3963 phys = <&mdss_dsi_phy>; 3964 3965 #address-cells = <1>; 3966 #size-cells = <0>; 3967 3968 status = "disabled"; 3969 3970 ports { 3971 #address-cells = <1>; 3972 #size-cells = <0>; 3973 3974 port@0 { 3975 reg = <0>; 3976 mdss_dsi0_in: endpoint { 3977 remote-endpoint = <&dpu_intf1_out>; 3978 }; 3979 }; 3980 3981 port@1 { 3982 reg = <1>; 3983 mdss_dsi0_out: endpoint { 3984 }; 3985 }; 3986 }; 3987 3988 dsi_opp_table: opp-table { 3989 compatible = "operating-points-v2"; 3990 3991 opp-187500000 { 3992 opp-hz = /bits/ 64 <187500000>; 3993 required-opps = <&rpmhpd_opp_low_svs>; 3994 }; 3995 3996 opp-300000000 { 3997 opp-hz = /bits/ 64 <300000000>; 3998 required-opps = <&rpmhpd_opp_svs>; 3999 }; 4000 4001 opp-358000000 { 4002 opp-hz = /bits/ 64 <358000000>; 4003 required-opps = <&rpmhpd_opp_svs_l1>; 4004 }; 4005 }; 4006 }; 4007 4008 mdss_dsi_phy: phy@ae94400 { 4009 compatible = "qcom,sc7280-dsi-phy-7nm"; 4010 reg = <0 0x0ae94400 0 0x200>, 4011 <0 0x0ae94600 0 0x280>, 4012 <0 0x0ae94900 0 0x280>; 4013 reg-names = "dsi_phy", 4014 "dsi_phy_lane", 4015 "dsi_pll"; 4016 4017 #clock-cells = <1>; 4018 #phy-cells = <0>; 4019 4020 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4021 <&rpmhcc RPMH_CXO_CLK>; 4022 clock-names = "iface", "ref"; 4023 4024 status = "disabled"; 4025 }; 4026 4027 mdss_edp: edp@aea0000 { 4028 compatible = "qcom,sc7280-edp"; 4029 pinctrl-names = "default"; 4030 pinctrl-0 = <&edp_hot_plug_det>; 4031 4032 reg = <0 0x0aea0000 0 0x200>, 4033 <0 0x0aea0200 0 0x200>, 4034 <0 0x0aea0400 0 0xc00>, 4035 <0 0x0aea1000 0 0x400>; 4036 4037 interrupt-parent = <&mdss>; 4038 interrupts = <14>; 4039 4040 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4041 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4042 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4043 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4044 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4045 clock-names = "core_iface", 4046 "core_aux", 4047 "ctrl_link", 4048 "ctrl_link_iface", 4049 "stream_pixel"; 4050 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4051 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4052 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4053 4054 phys = <&mdss_edp_phy>; 4055 phy-names = "dp"; 4056 4057 operating-points-v2 = <&edp_opp_table>; 4058 power-domains = <&rpmhpd SC7280_CX>; 4059 4060 status = "disabled"; 4061 4062 ports { 4063 #address-cells = <1>; 4064 #size-cells = <0>; 4065 4066 port@0 { 4067 reg = <0>; 4068 edp_in: endpoint { 4069 remote-endpoint = <&dpu_intf5_out>; 4070 }; 4071 }; 4072 4073 port@1 { 4074 reg = <1>; 4075 mdss_edp_out: endpoint { }; 4076 }; 4077 }; 4078 4079 edp_opp_table: opp-table { 4080 compatible = "operating-points-v2"; 4081 4082 opp-160000000 { 4083 opp-hz = /bits/ 64 <160000000>; 4084 required-opps = <&rpmhpd_opp_low_svs>; 4085 }; 4086 4087 opp-270000000 { 4088 opp-hz = /bits/ 64 <270000000>; 4089 required-opps = <&rpmhpd_opp_svs>; 4090 }; 4091 4092 opp-540000000 { 4093 opp-hz = /bits/ 64 <540000000>; 4094 required-opps = <&rpmhpd_opp_nom>; 4095 }; 4096 4097 opp-810000000 { 4098 opp-hz = /bits/ 64 <810000000>; 4099 required-opps = <&rpmhpd_opp_nom>; 4100 }; 4101 }; 4102 }; 4103 4104 mdss_edp_phy: phy@aec2a00 { 4105 compatible = "qcom,sc7280-edp-phy"; 4106 4107 reg = <0 0x0aec2a00 0 0x19c>, 4108 <0 0x0aec2200 0 0xa0>, 4109 <0 0x0aec2600 0 0xa0>, 4110 <0 0x0aec2000 0 0x1c0>; 4111 4112 clocks = <&rpmhcc RPMH_CXO_CLK>, 4113 <&gcc GCC_EDP_CLKREF_EN>; 4114 clock-names = "aux", 4115 "cfg_ahb"; 4116 4117 #clock-cells = <1>; 4118 #phy-cells = <0>; 4119 4120 status = "disabled"; 4121 }; 4122 4123 mdss_dp: displayport-controller@ae90000 { 4124 compatible = "qcom,sc7280-dp"; 4125 4126 reg = <0 0x0ae90000 0 0x200>, 4127 <0 0x0ae90200 0 0x200>, 4128 <0 0x0ae90400 0 0xc00>, 4129 <0 0x0ae91000 0 0x400>, 4130 <0 0x0ae91400 0 0x400>; 4131 4132 interrupt-parent = <&mdss>; 4133 interrupts = <12>; 4134 4135 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4136 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4137 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4138 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4139 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4140 clock-names = "core_iface", 4141 "core_aux", 4142 "ctrl_link", 4143 "ctrl_link_iface", 4144 "stream_pixel"; 4145 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4146 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4147 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4148 phys = <&dp_phy>; 4149 phy-names = "dp"; 4150 4151 operating-points-v2 = <&dp_opp_table>; 4152 power-domains = <&rpmhpd SC7280_CX>; 4153 4154 #sound-dai-cells = <0>; 4155 4156 status = "disabled"; 4157 4158 ports { 4159 #address-cells = <1>; 4160 #size-cells = <0>; 4161 4162 port@0 { 4163 reg = <0>; 4164 dp_in: endpoint { 4165 remote-endpoint = <&dpu_intf0_out>; 4166 }; 4167 }; 4168 4169 port@1 { 4170 reg = <1>; 4171 mdss_dp_out: endpoint { }; 4172 }; 4173 }; 4174 4175 dp_opp_table: opp-table { 4176 compatible = "operating-points-v2"; 4177 4178 opp-160000000 { 4179 opp-hz = /bits/ 64 <160000000>; 4180 required-opps = <&rpmhpd_opp_low_svs>; 4181 }; 4182 4183 opp-270000000 { 4184 opp-hz = /bits/ 64 <270000000>; 4185 required-opps = <&rpmhpd_opp_svs>; 4186 }; 4187 4188 opp-540000000 { 4189 opp-hz = /bits/ 64 <540000000>; 4190 required-opps = <&rpmhpd_opp_svs_l1>; 4191 }; 4192 4193 opp-810000000 { 4194 opp-hz = /bits/ 64 <810000000>; 4195 required-opps = <&rpmhpd_opp_nom>; 4196 }; 4197 }; 4198 }; 4199 }; 4200 4201 pdc: interrupt-controller@b220000 { 4202 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4203 reg = <0 0x0b220000 0 0x30000>; 4204 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4205 <55 306 4>, <59 312 3>, <62 374 2>, 4206 <64 434 2>, <66 438 3>, <69 86 1>, 4207 <70 520 54>, <124 609 31>, <155 63 1>, 4208 <156 716 12>; 4209 #interrupt-cells = <2>; 4210 interrupt-parent = <&intc>; 4211 interrupt-controller; 4212 }; 4213 4214 pdc_reset: reset-controller@b5e0000 { 4215 compatible = "qcom,sc7280-pdc-global"; 4216 reg = <0 0x0b5e0000 0 0x20000>; 4217 #reset-cells = <1>; 4218 }; 4219 4220 tsens0: thermal-sensor@c263000 { 4221 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4222 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4223 <0 0x0c222000 0 0x1ff>; /* SROT */ 4224 #qcom,sensors = <15>; 4225 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4226 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4227 interrupt-names = "uplow","critical"; 4228 #thermal-sensor-cells = <1>; 4229 }; 4230 4231 tsens1: thermal-sensor@c265000 { 4232 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4233 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4234 <0 0x0c223000 0 0x1ff>; /* SROT */ 4235 #qcom,sensors = <12>; 4236 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4237 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4238 interrupt-names = "uplow","critical"; 4239 #thermal-sensor-cells = <1>; 4240 }; 4241 4242 aoss_reset: reset-controller@c2a0000 { 4243 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4244 reg = <0 0x0c2a0000 0 0x31000>; 4245 #reset-cells = <1>; 4246 }; 4247 4248 aoss_qmp: power-management@c300000 { 4249 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4250 reg = <0 0x0c300000 0 0x400>; 4251 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4252 IPCC_MPROC_SIGNAL_GLINK_QMP 4253 IRQ_TYPE_EDGE_RISING>; 4254 mboxes = <&ipcc IPCC_CLIENT_AOP 4255 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4256 4257 #clock-cells = <0>; 4258 }; 4259 4260 sram@c3f0000 { 4261 compatible = "qcom,rpmh-stats"; 4262 reg = <0 0x0c3f0000 0 0x400>; 4263 }; 4264 4265 spmi_bus: spmi@c440000 { 4266 compatible = "qcom,spmi-pmic-arb"; 4267 reg = <0 0x0c440000 0 0x1100>, 4268 <0 0x0c600000 0 0x2000000>, 4269 <0 0x0e600000 0 0x100000>, 4270 <0 0x0e700000 0 0xa0000>, 4271 <0 0x0c40a000 0 0x26000>; 4272 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4273 interrupt-names = "periph_irq"; 4274 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4275 qcom,ee = <0>; 4276 qcom,channel = <0>; 4277 #address-cells = <2>; 4278 #size-cells = <0>; 4279 interrupt-controller; 4280 #interrupt-cells = <4>; 4281 }; 4282 4283 tlmm: pinctrl@f100000 { 4284 compatible = "qcom,sc7280-pinctrl"; 4285 reg = <0 0x0f100000 0 0x300000>; 4286 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4287 gpio-controller; 4288 #gpio-cells = <2>; 4289 interrupt-controller; 4290 #interrupt-cells = <2>; 4291 gpio-ranges = <&tlmm 0 0 175>; 4292 wakeup-parent = <&pdc>; 4293 4294 dp_hot_plug_det: dp-hot-plug-det-state { 4295 pins = "gpio47"; 4296 function = "dp_hot"; 4297 }; 4298 4299 edp_hot_plug_det: edp-hot-plug-det-state { 4300 pins = "gpio60"; 4301 function = "edp_hot"; 4302 }; 4303 4304 mi2s0_data0: mi2s0-data0-state { 4305 pins = "gpio98"; 4306 function = "mi2s0_data0"; 4307 }; 4308 4309 mi2s0_data1: mi2s0-data1-state { 4310 pins = "gpio99"; 4311 function = "mi2s0_data1"; 4312 }; 4313 4314 mi2s0_mclk: mi2s0-mclk-state { 4315 pins = "gpio96"; 4316 function = "pri_mi2s"; 4317 }; 4318 4319 mi2s0_sclk: mi2s0-sclk-state { 4320 pins = "gpio97"; 4321 function = "mi2s0_sck"; 4322 }; 4323 4324 mi2s0_ws: mi2s0-ws-state { 4325 pins = "gpio100"; 4326 function = "mi2s0_ws"; 4327 }; 4328 4329 mi2s1_data0: mi2s1-data0-state { 4330 pins = "gpio107"; 4331 function = "mi2s1_data0"; 4332 }; 4333 4334 mi2s1_sclk: mi2s1-sclk-state { 4335 pins = "gpio106"; 4336 function = "mi2s1_sck"; 4337 }; 4338 4339 mi2s1_ws: mi2s1-ws-state { 4340 pins = "gpio108"; 4341 function = "mi2s1_ws"; 4342 }; 4343 4344 pcie1_clkreq_n: pcie1-clkreq-n-state { 4345 pins = "gpio79"; 4346 function = "pcie1_clkreqn"; 4347 }; 4348 4349 qspi_clk: qspi-clk-state { 4350 pins = "gpio14"; 4351 function = "qspi_clk"; 4352 }; 4353 4354 qspi_cs0: qspi-cs0-state { 4355 pins = "gpio15"; 4356 function = "qspi_cs"; 4357 }; 4358 4359 qspi_cs1: qspi-cs1-state { 4360 pins = "gpio19"; 4361 function = "qspi_cs"; 4362 }; 4363 4364 qspi_data0: qspi-data0-state { 4365 pins = "gpio12"; 4366 function = "qspi_data"; 4367 }; 4368 4369 qspi_data1: qspi-data1-state { 4370 pins = "gpio13"; 4371 function = "qspi_data"; 4372 }; 4373 4374 qspi_data23: qspi-data23-state { 4375 pins = "gpio16", "gpio17"; 4376 function = "qspi_data"; 4377 }; 4378 4379 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4380 pins = "gpio0", "gpio1"; 4381 function = "qup00"; 4382 }; 4383 4384 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4385 pins = "gpio4", "gpio5"; 4386 function = "qup01"; 4387 }; 4388 4389 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4390 pins = "gpio8", "gpio9"; 4391 function = "qup02"; 4392 }; 4393 4394 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4395 pins = "gpio12", "gpio13"; 4396 function = "qup03"; 4397 }; 4398 4399 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4400 pins = "gpio16", "gpio17"; 4401 function = "qup04"; 4402 }; 4403 4404 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4405 pins = "gpio20", "gpio21"; 4406 function = "qup05"; 4407 }; 4408 4409 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4410 pins = "gpio24", "gpio25"; 4411 function = "qup06"; 4412 }; 4413 4414 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4415 pins = "gpio28", "gpio29"; 4416 function = "qup07"; 4417 }; 4418 4419 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4420 pins = "gpio32", "gpio33"; 4421 function = "qup10"; 4422 }; 4423 4424 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4425 pins = "gpio36", "gpio37"; 4426 function = "qup11"; 4427 }; 4428 4429 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4430 pins = "gpio40", "gpio41"; 4431 function = "qup12"; 4432 }; 4433 4434 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4435 pins = "gpio44", "gpio45"; 4436 function = "qup13"; 4437 }; 4438 4439 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4440 pins = "gpio48", "gpio49"; 4441 function = "qup14"; 4442 }; 4443 4444 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4445 pins = "gpio52", "gpio53"; 4446 function = "qup15"; 4447 }; 4448 4449 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4450 pins = "gpio56", "gpio57"; 4451 function = "qup16"; 4452 }; 4453 4454 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4455 pins = "gpio60", "gpio61"; 4456 function = "qup17"; 4457 }; 4458 4459 qup_spi0_data_clk: qup-spi0-data-clk-state { 4460 pins = "gpio0", "gpio1", "gpio2"; 4461 function = "qup00"; 4462 }; 4463 4464 qup_spi0_cs: qup-spi0-cs-state { 4465 pins = "gpio3"; 4466 function = "qup00"; 4467 }; 4468 4469 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4470 pins = "gpio3"; 4471 function = "gpio"; 4472 }; 4473 4474 qup_spi1_data_clk: qup-spi1-data-clk-state { 4475 pins = "gpio4", "gpio5", "gpio6"; 4476 function = "qup01"; 4477 }; 4478 4479 qup_spi1_cs: qup-spi1-cs-state { 4480 pins = "gpio7"; 4481 function = "qup01"; 4482 }; 4483 4484 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4485 pins = "gpio7"; 4486 function = "gpio"; 4487 }; 4488 4489 qup_spi2_data_clk: qup-spi2-data-clk-state { 4490 pins = "gpio8", "gpio9", "gpio10"; 4491 function = "qup02"; 4492 }; 4493 4494 qup_spi2_cs: qup-spi2-cs-state { 4495 pins = "gpio11"; 4496 function = "qup02"; 4497 }; 4498 4499 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4500 pins = "gpio11"; 4501 function = "gpio"; 4502 }; 4503 4504 qup_spi3_data_clk: qup-spi3-data-clk-state { 4505 pins = "gpio12", "gpio13", "gpio14"; 4506 function = "qup03"; 4507 }; 4508 4509 qup_spi3_cs: qup-spi3-cs-state { 4510 pins = "gpio15"; 4511 function = "qup03"; 4512 }; 4513 4514 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4515 pins = "gpio15"; 4516 function = "gpio"; 4517 }; 4518 4519 qup_spi4_data_clk: qup-spi4-data-clk-state { 4520 pins = "gpio16", "gpio17", "gpio18"; 4521 function = "qup04"; 4522 }; 4523 4524 qup_spi4_cs: qup-spi4-cs-state { 4525 pins = "gpio19"; 4526 function = "qup04"; 4527 }; 4528 4529 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4530 pins = "gpio19"; 4531 function = "gpio"; 4532 }; 4533 4534 qup_spi5_data_clk: qup-spi5-data-clk-state { 4535 pins = "gpio20", "gpio21", "gpio22"; 4536 function = "qup05"; 4537 }; 4538 4539 qup_spi5_cs: qup-spi5-cs-state { 4540 pins = "gpio23"; 4541 function = "qup05"; 4542 }; 4543 4544 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4545 pins = "gpio23"; 4546 function = "gpio"; 4547 }; 4548 4549 qup_spi6_data_clk: qup-spi6-data-clk-state { 4550 pins = "gpio24", "gpio25", "gpio26"; 4551 function = "qup06"; 4552 }; 4553 4554 qup_spi6_cs: qup-spi6-cs-state { 4555 pins = "gpio27"; 4556 function = "qup06"; 4557 }; 4558 4559 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4560 pins = "gpio27"; 4561 function = "gpio"; 4562 }; 4563 4564 qup_spi7_data_clk: qup-spi7-data-clk-state { 4565 pins = "gpio28", "gpio29", "gpio30"; 4566 function = "qup07"; 4567 }; 4568 4569 qup_spi7_cs: qup-spi7-cs-state { 4570 pins = "gpio31"; 4571 function = "qup07"; 4572 }; 4573 4574 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4575 pins = "gpio31"; 4576 function = "gpio"; 4577 }; 4578 4579 qup_spi8_data_clk: qup-spi8-data-clk-state { 4580 pins = "gpio32", "gpio33", "gpio34"; 4581 function = "qup10"; 4582 }; 4583 4584 qup_spi8_cs: qup-spi8-cs-state { 4585 pins = "gpio35"; 4586 function = "qup10"; 4587 }; 4588 4589 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4590 pins = "gpio35"; 4591 function = "gpio"; 4592 }; 4593 4594 qup_spi9_data_clk: qup-spi9-data-clk-state { 4595 pins = "gpio36", "gpio37", "gpio38"; 4596 function = "qup11"; 4597 }; 4598 4599 qup_spi9_cs: qup-spi9-cs-state { 4600 pins = "gpio39"; 4601 function = "qup11"; 4602 }; 4603 4604 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4605 pins = "gpio39"; 4606 function = "gpio"; 4607 }; 4608 4609 qup_spi10_data_clk: qup-spi10-data-clk-state { 4610 pins = "gpio40", "gpio41", "gpio42"; 4611 function = "qup12"; 4612 }; 4613 4614 qup_spi10_cs: qup-spi10-cs-state { 4615 pins = "gpio43"; 4616 function = "qup12"; 4617 }; 4618 4619 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4620 pins = "gpio43"; 4621 function = "gpio"; 4622 }; 4623 4624 qup_spi11_data_clk: qup-spi11-data-clk-state { 4625 pins = "gpio44", "gpio45", "gpio46"; 4626 function = "qup13"; 4627 }; 4628 4629 qup_spi11_cs: qup-spi11-cs-state { 4630 pins = "gpio47"; 4631 function = "qup13"; 4632 }; 4633 4634 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 4635 pins = "gpio47"; 4636 function = "gpio"; 4637 }; 4638 4639 qup_spi12_data_clk: qup-spi12-data-clk-state { 4640 pins = "gpio48", "gpio49", "gpio50"; 4641 function = "qup14"; 4642 }; 4643 4644 qup_spi12_cs: qup-spi12-cs-state { 4645 pins = "gpio51"; 4646 function = "qup14"; 4647 }; 4648 4649 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4650 pins = "gpio51"; 4651 function = "gpio"; 4652 }; 4653 4654 qup_spi13_data_clk: qup-spi13-data-clk-state { 4655 pins = "gpio52", "gpio53", "gpio54"; 4656 function = "qup15"; 4657 }; 4658 4659 qup_spi13_cs: qup-spi13-cs-state { 4660 pins = "gpio55"; 4661 function = "qup15"; 4662 }; 4663 4664 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 4665 pins = "gpio55"; 4666 function = "gpio"; 4667 }; 4668 4669 qup_spi14_data_clk: qup-spi14-data-clk-state { 4670 pins = "gpio56", "gpio57", "gpio58"; 4671 function = "qup16"; 4672 }; 4673 4674 qup_spi14_cs: qup-spi14-cs-state { 4675 pins = "gpio59"; 4676 function = "qup16"; 4677 }; 4678 4679 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 4680 pins = "gpio59"; 4681 function = "gpio"; 4682 }; 4683 4684 qup_spi15_data_clk: qup-spi15-data-clk-state { 4685 pins = "gpio60", "gpio61", "gpio62"; 4686 function = "qup17"; 4687 }; 4688 4689 qup_spi15_cs: qup-spi15-cs-state { 4690 pins = "gpio63"; 4691 function = "qup17"; 4692 }; 4693 4694 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 4695 pins = "gpio63"; 4696 function = "gpio"; 4697 }; 4698 4699 qup_uart0_cts: qup-uart0-cts-state { 4700 pins = "gpio0"; 4701 function = "qup00"; 4702 }; 4703 4704 qup_uart0_rts: qup-uart0-rts-state { 4705 pins = "gpio1"; 4706 function = "qup00"; 4707 }; 4708 4709 qup_uart0_tx: qup-uart0-tx-state { 4710 pins = "gpio2"; 4711 function = "qup00"; 4712 }; 4713 4714 qup_uart0_rx: qup-uart0-rx-state { 4715 pins = "gpio3"; 4716 function = "qup00"; 4717 }; 4718 4719 qup_uart1_cts: qup-uart1-cts-state { 4720 pins = "gpio4"; 4721 function = "qup01"; 4722 }; 4723 4724 qup_uart1_rts: qup-uart1-rts-state { 4725 pins = "gpio5"; 4726 function = "qup01"; 4727 }; 4728 4729 qup_uart1_tx: qup-uart1-tx-state { 4730 pins = "gpio6"; 4731 function = "qup01"; 4732 }; 4733 4734 qup_uart1_rx: qup-uart1-rx-state { 4735 pins = "gpio7"; 4736 function = "qup01"; 4737 }; 4738 4739 qup_uart2_cts: qup-uart2-cts-state { 4740 pins = "gpio8"; 4741 function = "qup02"; 4742 }; 4743 4744 qup_uart2_rts: qup-uart2-rts-state { 4745 pins = "gpio9"; 4746 function = "qup02"; 4747 }; 4748 4749 qup_uart2_tx: qup-uart2-tx-state { 4750 pins = "gpio10"; 4751 function = "qup02"; 4752 }; 4753 4754 qup_uart2_rx: qup-uart2-rx-state { 4755 pins = "gpio11"; 4756 function = "qup02"; 4757 }; 4758 4759 qup_uart3_cts: qup-uart3-cts-state { 4760 pins = "gpio12"; 4761 function = "qup03"; 4762 }; 4763 4764 qup_uart3_rts: qup-uart3-rts-state { 4765 pins = "gpio13"; 4766 function = "qup03"; 4767 }; 4768 4769 qup_uart3_tx: qup-uart3-tx-state { 4770 pins = "gpio14"; 4771 function = "qup03"; 4772 }; 4773 4774 qup_uart3_rx: qup-uart3-rx-state { 4775 pins = "gpio15"; 4776 function = "qup03"; 4777 }; 4778 4779 qup_uart4_cts: qup-uart4-cts-state { 4780 pins = "gpio16"; 4781 function = "qup04"; 4782 }; 4783 4784 qup_uart4_rts: qup-uart4-rts-state { 4785 pins = "gpio17"; 4786 function = "qup04"; 4787 }; 4788 4789 qup_uart4_tx: qup-uart4-tx-state { 4790 pins = "gpio18"; 4791 function = "qup04"; 4792 }; 4793 4794 qup_uart4_rx: qup-uart4-rx-state { 4795 pins = "gpio19"; 4796 function = "qup04"; 4797 }; 4798 4799 qup_uart5_cts: qup-uart5-cts-state { 4800 pins = "gpio20"; 4801 function = "qup05"; 4802 }; 4803 4804 qup_uart5_rts: qup-uart5-rts-state { 4805 pins = "gpio21"; 4806 function = "qup05"; 4807 }; 4808 4809 qup_uart5_tx: qup-uart5-tx-state { 4810 pins = "gpio22"; 4811 function = "qup05"; 4812 }; 4813 4814 qup_uart5_rx: qup-uart5-rx-state { 4815 pins = "gpio23"; 4816 function = "qup05"; 4817 }; 4818 4819 qup_uart6_cts: qup-uart6-cts-state { 4820 pins = "gpio24"; 4821 function = "qup06"; 4822 }; 4823 4824 qup_uart6_rts: qup-uart6-rts-state { 4825 pins = "gpio25"; 4826 function = "qup06"; 4827 }; 4828 4829 qup_uart6_tx: qup-uart6-tx-state { 4830 pins = "gpio26"; 4831 function = "qup06"; 4832 }; 4833 4834 qup_uart6_rx: qup-uart6-rx-state { 4835 pins = "gpio27"; 4836 function = "qup06"; 4837 }; 4838 4839 qup_uart7_cts: qup-uart7-cts-state { 4840 pins = "gpio28"; 4841 function = "qup07"; 4842 }; 4843 4844 qup_uart7_rts: qup-uart7-rts-state { 4845 pins = "gpio29"; 4846 function = "qup07"; 4847 }; 4848 4849 qup_uart7_tx: qup-uart7-tx-state { 4850 pins = "gpio30"; 4851 function = "qup07"; 4852 }; 4853 4854 qup_uart7_rx: qup-uart7-rx-state { 4855 pins = "gpio31"; 4856 function = "qup07"; 4857 }; 4858 4859 qup_uart8_cts: qup-uart8-cts-state { 4860 pins = "gpio32"; 4861 function = "qup10"; 4862 }; 4863 4864 qup_uart8_rts: qup-uart8-rts-state { 4865 pins = "gpio33"; 4866 function = "qup10"; 4867 }; 4868 4869 qup_uart8_tx: qup-uart8-tx-state { 4870 pins = "gpio34"; 4871 function = "qup10"; 4872 }; 4873 4874 qup_uart8_rx: qup-uart8-rx-state { 4875 pins = "gpio35"; 4876 function = "qup10"; 4877 }; 4878 4879 qup_uart9_cts: qup-uart9-cts-state { 4880 pins = "gpio36"; 4881 function = "qup11"; 4882 }; 4883 4884 qup_uart9_rts: qup-uart9-rts-state { 4885 pins = "gpio37"; 4886 function = "qup11"; 4887 }; 4888 4889 qup_uart9_tx: qup-uart9-tx-state { 4890 pins = "gpio38"; 4891 function = "qup11"; 4892 }; 4893 4894 qup_uart9_rx: qup-uart9-rx-state { 4895 pins = "gpio39"; 4896 function = "qup11"; 4897 }; 4898 4899 qup_uart10_cts: qup-uart10-cts-state { 4900 pins = "gpio40"; 4901 function = "qup12"; 4902 }; 4903 4904 qup_uart10_rts: qup-uart10-rts-state { 4905 pins = "gpio41"; 4906 function = "qup12"; 4907 }; 4908 4909 qup_uart10_tx: qup-uart10-tx-state { 4910 pins = "gpio42"; 4911 function = "qup12"; 4912 }; 4913 4914 qup_uart10_rx: qup-uart10-rx-state { 4915 pins = "gpio43"; 4916 function = "qup12"; 4917 }; 4918 4919 qup_uart11_cts: qup-uart11-cts-state { 4920 pins = "gpio44"; 4921 function = "qup13"; 4922 }; 4923 4924 qup_uart11_rts: qup-uart11-rts-state { 4925 pins = "gpio45"; 4926 function = "qup13"; 4927 }; 4928 4929 qup_uart11_tx: qup-uart11-tx-state { 4930 pins = "gpio46"; 4931 function = "qup13"; 4932 }; 4933 4934 qup_uart11_rx: qup-uart11-rx-state { 4935 pins = "gpio47"; 4936 function = "qup13"; 4937 }; 4938 4939 qup_uart12_cts: qup-uart12-cts-state { 4940 pins = "gpio48"; 4941 function = "qup14"; 4942 }; 4943 4944 qup_uart12_rts: qup-uart12-rts-state { 4945 pins = "gpio49"; 4946 function = "qup14"; 4947 }; 4948 4949 qup_uart12_tx: qup-uart12-tx-state { 4950 pins = "gpio50"; 4951 function = "qup14"; 4952 }; 4953 4954 qup_uart12_rx: qup-uart12-rx-state { 4955 pins = "gpio51"; 4956 function = "qup14"; 4957 }; 4958 4959 qup_uart13_cts: qup-uart13-cts-state { 4960 pins = "gpio52"; 4961 function = "qup15"; 4962 }; 4963 4964 qup_uart13_rts: qup-uart13-rts-state { 4965 pins = "gpio53"; 4966 function = "qup15"; 4967 }; 4968 4969 qup_uart13_tx: qup-uart13-tx-state { 4970 pins = "gpio54"; 4971 function = "qup15"; 4972 }; 4973 4974 qup_uart13_rx: qup-uart13-rx-state { 4975 pins = "gpio55"; 4976 function = "qup15"; 4977 }; 4978 4979 qup_uart14_cts: qup-uart14-cts-state { 4980 pins = "gpio56"; 4981 function = "qup16"; 4982 }; 4983 4984 qup_uart14_rts: qup-uart14-rts-state { 4985 pins = "gpio57"; 4986 function = "qup16"; 4987 }; 4988 4989 qup_uart14_tx: qup-uart14-tx-state { 4990 pins = "gpio58"; 4991 function = "qup16"; 4992 }; 4993 4994 qup_uart14_rx: qup-uart14-rx-state { 4995 pins = "gpio59"; 4996 function = "qup16"; 4997 }; 4998 4999 qup_uart15_cts: qup-uart15-cts-state { 5000 pins = "gpio60"; 5001 function = "qup17"; 5002 }; 5003 5004 qup_uart15_rts: qup-uart15-rts-state { 5005 pins = "gpio61"; 5006 function = "qup17"; 5007 }; 5008 5009 qup_uart15_tx: qup-uart15-tx-state { 5010 pins = "gpio62"; 5011 function = "qup17"; 5012 }; 5013 5014 qup_uart15_rx: qup-uart15-rx-state { 5015 pins = "gpio63"; 5016 function = "qup17"; 5017 }; 5018 5019 sdc1_clk: sdc1-clk-state { 5020 pins = "sdc1_clk"; 5021 }; 5022 5023 sdc1_cmd: sdc1-cmd-state { 5024 pins = "sdc1_cmd"; 5025 }; 5026 5027 sdc1_data: sdc1-data-state { 5028 pins = "sdc1_data"; 5029 }; 5030 5031 sdc1_rclk: sdc1-rclk-state { 5032 pins = "sdc1_rclk"; 5033 }; 5034 5035 sdc1_clk_sleep: sdc1-clk-sleep-state { 5036 pins = "sdc1_clk"; 5037 drive-strength = <2>; 5038 bias-bus-hold; 5039 }; 5040 5041 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5042 pins = "sdc1_cmd"; 5043 drive-strength = <2>; 5044 bias-bus-hold; 5045 }; 5046 5047 sdc1_data_sleep: sdc1-data-sleep-state { 5048 pins = "sdc1_data"; 5049 drive-strength = <2>; 5050 bias-bus-hold; 5051 }; 5052 5053 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5054 pins = "sdc1_rclk"; 5055 drive-strength = <2>; 5056 bias-bus-hold; 5057 }; 5058 5059 sdc2_clk: sdc2-clk-state { 5060 pins = "sdc2_clk"; 5061 }; 5062 5063 sdc2_cmd: sdc2-cmd-state { 5064 pins = "sdc2_cmd"; 5065 }; 5066 5067 sdc2_data: sdc2-data-state { 5068 pins = "sdc2_data"; 5069 }; 5070 5071 sdc2_clk_sleep: sdc2-clk-sleep-state { 5072 pins = "sdc2_clk"; 5073 drive-strength = <2>; 5074 bias-bus-hold; 5075 }; 5076 5077 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 5078 pins = "sdc2_cmd"; 5079 drive-strength = <2>; 5080 bias-bus-hold; 5081 }; 5082 5083 sdc2_data_sleep: sdc2-data-sleep-state { 5084 pins = "sdc2_data"; 5085 drive-strength = <2>; 5086 bias-bus-hold; 5087 }; 5088 }; 5089 5090 sram@146a5000 { 5091 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5092 reg = <0 0x146a5000 0 0x6000>; 5093 5094 #address-cells = <1>; 5095 #size-cells = <1>; 5096 5097 ranges = <0 0 0x146a5000 0x6000>; 5098 5099 pil-reloc@594c { 5100 compatible = "qcom,pil-reloc-info"; 5101 reg = <0x594c 0xc8>; 5102 }; 5103 }; 5104 5105 apps_smmu: iommu@15000000 { 5106 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5107 reg = <0 0x15000000 0 0x100000>; 5108 #iommu-cells = <2>; 5109 #global-interrupts = <1>; 5110 dma-coherent; 5111 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5169 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5170 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5171 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5172 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5173 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5174 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5175 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5176 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5177 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5178 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5179 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5180 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5181 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5182 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5183 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5184 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5185 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5186 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5187 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5188 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5189 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5190 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5191 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5192 }; 5193 5194 intc: interrupt-controller@17a00000 { 5195 compatible = "arm,gic-v3"; 5196 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5197 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5198 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5199 #interrupt-cells = <3>; 5200 interrupt-controller; 5201 #address-cells = <2>; 5202 #size-cells = <2>; 5203 ranges; 5204 5205 msi-controller@17a40000 { 5206 compatible = "arm,gic-v3-its"; 5207 reg = <0 0x17a40000 0 0x20000>; 5208 msi-controller; 5209 #msi-cells = <1>; 5210 status = "disabled"; 5211 }; 5212 }; 5213 5214 watchdog@17c10000 { 5215 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5216 reg = <0 0x17c10000 0 0x1000>; 5217 clocks = <&sleep_clk>; 5218 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5219 }; 5220 5221 timer@17c20000 { 5222 #address-cells = <1>; 5223 #size-cells = <1>; 5224 ranges = <0 0 0 0x20000000>; 5225 compatible = "arm,armv7-timer-mem"; 5226 reg = <0 0x17c20000 0 0x1000>; 5227 5228 frame@17c21000 { 5229 frame-number = <0>; 5230 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5231 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5232 reg = <0x17c21000 0x1000>, 5233 <0x17c22000 0x1000>; 5234 }; 5235 5236 frame@17c23000 { 5237 frame-number = <1>; 5238 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5239 reg = <0x17c23000 0x1000>; 5240 status = "disabled"; 5241 }; 5242 5243 frame@17c25000 { 5244 frame-number = <2>; 5245 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5246 reg = <0x17c25000 0x1000>; 5247 status = "disabled"; 5248 }; 5249 5250 frame@17c27000 { 5251 frame-number = <3>; 5252 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5253 reg = <0x17c27000 0x1000>; 5254 status = "disabled"; 5255 }; 5256 5257 frame@17c29000 { 5258 frame-number = <4>; 5259 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5260 reg = <0x17c29000 0x1000>; 5261 status = "disabled"; 5262 }; 5263 5264 frame@17c2b000 { 5265 frame-number = <5>; 5266 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5267 reg = <0x17c2b000 0x1000>; 5268 status = "disabled"; 5269 }; 5270 5271 frame@17c2d000 { 5272 frame-number = <6>; 5273 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5274 reg = <0x17c2d000 0x1000>; 5275 status = "disabled"; 5276 }; 5277 }; 5278 5279 apps_rsc: rsc@18200000 { 5280 compatible = "qcom,rpmh-rsc"; 5281 reg = <0 0x18200000 0 0x10000>, 5282 <0 0x18210000 0 0x10000>, 5283 <0 0x18220000 0 0x10000>; 5284 reg-names = "drv-0", "drv-1", "drv-2"; 5285 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5286 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5287 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5288 qcom,tcs-offset = <0xd00>; 5289 qcom,drv-id = <2>; 5290 qcom,tcs-config = <ACTIVE_TCS 2>, 5291 <SLEEP_TCS 3>, 5292 <WAKE_TCS 3>, 5293 <CONTROL_TCS 1>; 5294 5295 apps_bcm_voter: bcm-voter { 5296 compatible = "qcom,bcm-voter"; 5297 }; 5298 5299 rpmhpd: power-controller { 5300 compatible = "qcom,sc7280-rpmhpd"; 5301 #power-domain-cells = <1>; 5302 operating-points-v2 = <&rpmhpd_opp_table>; 5303 5304 rpmhpd_opp_table: opp-table { 5305 compatible = "operating-points-v2"; 5306 5307 rpmhpd_opp_ret: opp1 { 5308 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5309 }; 5310 5311 rpmhpd_opp_low_svs: opp2 { 5312 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5313 }; 5314 5315 rpmhpd_opp_svs: opp3 { 5316 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5317 }; 5318 5319 rpmhpd_opp_svs_l1: opp4 { 5320 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5321 }; 5322 5323 rpmhpd_opp_svs_l2: opp5 { 5324 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5325 }; 5326 5327 rpmhpd_opp_nom: opp6 { 5328 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5329 }; 5330 5331 rpmhpd_opp_nom_l1: opp7 { 5332 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5333 }; 5334 5335 rpmhpd_opp_turbo: opp8 { 5336 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5337 }; 5338 5339 rpmhpd_opp_turbo_l1: opp9 { 5340 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5341 }; 5342 }; 5343 }; 5344 5345 rpmhcc: clock-controller { 5346 compatible = "qcom,sc7280-rpmh-clk"; 5347 clocks = <&xo_board>; 5348 clock-names = "xo"; 5349 #clock-cells = <1>; 5350 }; 5351 }; 5352 5353 epss_l3: interconnect@18590000 { 5354 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 5355 reg = <0 0x18590000 0 0x1000>; 5356 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5357 clock-names = "xo", "alternate"; 5358 #interconnect-cells = <1>; 5359 }; 5360 5361 cpufreq_hw: cpufreq@18591000 { 5362 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 5363 reg = <0 0x18591000 0 0x1000>, 5364 <0 0x18592000 0 0x1000>, 5365 <0 0x18593000 0 0x1000>; 5366 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5367 clock-names = "xo", "alternate"; 5368 #freq-domain-cells = <1>; 5369 #clock-cells = <1>; 5370 }; 5371 }; 5372 5373 thermal_zones: thermal-zones { 5374 cpu0-thermal { 5375 polling-delay-passive = <250>; 5376 polling-delay = <0>; 5377 5378 thermal-sensors = <&tsens0 1>; 5379 5380 trips { 5381 cpu0_alert0: trip-point0 { 5382 temperature = <90000>; 5383 hysteresis = <2000>; 5384 type = "passive"; 5385 }; 5386 5387 cpu0_alert1: trip-point1 { 5388 temperature = <95000>; 5389 hysteresis = <2000>; 5390 type = "passive"; 5391 }; 5392 5393 cpu0_crit: cpu-crit { 5394 temperature = <110000>; 5395 hysteresis = <0>; 5396 type = "critical"; 5397 }; 5398 }; 5399 5400 cooling-maps { 5401 map0 { 5402 trip = <&cpu0_alert0>; 5403 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5404 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5405 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5406 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5407 }; 5408 map1 { 5409 trip = <&cpu0_alert1>; 5410 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5411 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5412 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5413 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5414 }; 5415 }; 5416 }; 5417 5418 cpu1-thermal { 5419 polling-delay-passive = <250>; 5420 polling-delay = <0>; 5421 5422 thermal-sensors = <&tsens0 2>; 5423 5424 trips { 5425 cpu1_alert0: trip-point0 { 5426 temperature = <90000>; 5427 hysteresis = <2000>; 5428 type = "passive"; 5429 }; 5430 5431 cpu1_alert1: trip-point1 { 5432 temperature = <95000>; 5433 hysteresis = <2000>; 5434 type = "passive"; 5435 }; 5436 5437 cpu1_crit: cpu-crit { 5438 temperature = <110000>; 5439 hysteresis = <0>; 5440 type = "critical"; 5441 }; 5442 }; 5443 5444 cooling-maps { 5445 map0 { 5446 trip = <&cpu1_alert0>; 5447 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5448 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5449 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5450 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5451 }; 5452 map1 { 5453 trip = <&cpu1_alert1>; 5454 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5455 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5456 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5457 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5458 }; 5459 }; 5460 }; 5461 5462 cpu2-thermal { 5463 polling-delay-passive = <250>; 5464 polling-delay = <0>; 5465 5466 thermal-sensors = <&tsens0 3>; 5467 5468 trips { 5469 cpu2_alert0: trip-point0 { 5470 temperature = <90000>; 5471 hysteresis = <2000>; 5472 type = "passive"; 5473 }; 5474 5475 cpu2_alert1: trip-point1 { 5476 temperature = <95000>; 5477 hysteresis = <2000>; 5478 type = "passive"; 5479 }; 5480 5481 cpu2_crit: cpu-crit { 5482 temperature = <110000>; 5483 hysteresis = <0>; 5484 type = "critical"; 5485 }; 5486 }; 5487 5488 cooling-maps { 5489 map0 { 5490 trip = <&cpu2_alert0>; 5491 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5492 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5493 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5494 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5495 }; 5496 map1 { 5497 trip = <&cpu2_alert1>; 5498 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5499 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5500 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5501 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5502 }; 5503 }; 5504 }; 5505 5506 cpu3-thermal { 5507 polling-delay-passive = <250>; 5508 polling-delay = <0>; 5509 5510 thermal-sensors = <&tsens0 4>; 5511 5512 trips { 5513 cpu3_alert0: trip-point0 { 5514 temperature = <90000>; 5515 hysteresis = <2000>; 5516 type = "passive"; 5517 }; 5518 5519 cpu3_alert1: trip-point1 { 5520 temperature = <95000>; 5521 hysteresis = <2000>; 5522 type = "passive"; 5523 }; 5524 5525 cpu3_crit: cpu-crit { 5526 temperature = <110000>; 5527 hysteresis = <0>; 5528 type = "critical"; 5529 }; 5530 }; 5531 5532 cooling-maps { 5533 map0 { 5534 trip = <&cpu3_alert0>; 5535 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5536 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5537 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5538 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5539 }; 5540 map1 { 5541 trip = <&cpu3_alert1>; 5542 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5543 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5544 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5545 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5546 }; 5547 }; 5548 }; 5549 5550 cpu4-thermal { 5551 polling-delay-passive = <250>; 5552 polling-delay = <0>; 5553 5554 thermal-sensors = <&tsens0 7>; 5555 5556 trips { 5557 cpu4_alert0: trip-point0 { 5558 temperature = <90000>; 5559 hysteresis = <2000>; 5560 type = "passive"; 5561 }; 5562 5563 cpu4_alert1: trip-point1 { 5564 temperature = <95000>; 5565 hysteresis = <2000>; 5566 type = "passive"; 5567 }; 5568 5569 cpu4_crit: cpu-crit { 5570 temperature = <110000>; 5571 hysteresis = <0>; 5572 type = "critical"; 5573 }; 5574 }; 5575 5576 cooling-maps { 5577 map0 { 5578 trip = <&cpu4_alert0>; 5579 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5580 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5581 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5582 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5583 }; 5584 map1 { 5585 trip = <&cpu4_alert1>; 5586 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5587 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5588 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5589 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5590 }; 5591 }; 5592 }; 5593 5594 cpu5-thermal { 5595 polling-delay-passive = <250>; 5596 polling-delay = <0>; 5597 5598 thermal-sensors = <&tsens0 8>; 5599 5600 trips { 5601 cpu5_alert0: trip-point0 { 5602 temperature = <90000>; 5603 hysteresis = <2000>; 5604 type = "passive"; 5605 }; 5606 5607 cpu5_alert1: trip-point1 { 5608 temperature = <95000>; 5609 hysteresis = <2000>; 5610 type = "passive"; 5611 }; 5612 5613 cpu5_crit: cpu-crit { 5614 temperature = <110000>; 5615 hysteresis = <0>; 5616 type = "critical"; 5617 }; 5618 }; 5619 5620 cooling-maps { 5621 map0 { 5622 trip = <&cpu5_alert0>; 5623 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5624 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5625 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5626 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5627 }; 5628 map1 { 5629 trip = <&cpu5_alert1>; 5630 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5631 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5632 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5633 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5634 }; 5635 }; 5636 }; 5637 5638 cpu6-thermal { 5639 polling-delay-passive = <250>; 5640 polling-delay = <0>; 5641 5642 thermal-sensors = <&tsens0 9>; 5643 5644 trips { 5645 cpu6_alert0: trip-point0 { 5646 temperature = <90000>; 5647 hysteresis = <2000>; 5648 type = "passive"; 5649 }; 5650 5651 cpu6_alert1: trip-point1 { 5652 temperature = <95000>; 5653 hysteresis = <2000>; 5654 type = "passive"; 5655 }; 5656 5657 cpu6_crit: cpu-crit { 5658 temperature = <110000>; 5659 hysteresis = <0>; 5660 type = "critical"; 5661 }; 5662 }; 5663 5664 cooling-maps { 5665 map0 { 5666 trip = <&cpu6_alert0>; 5667 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5668 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5669 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5670 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5671 }; 5672 map1 { 5673 trip = <&cpu6_alert1>; 5674 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5675 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5676 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5677 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5678 }; 5679 }; 5680 }; 5681 5682 cpu7-thermal { 5683 polling-delay-passive = <250>; 5684 polling-delay = <0>; 5685 5686 thermal-sensors = <&tsens0 10>; 5687 5688 trips { 5689 cpu7_alert0: trip-point0 { 5690 temperature = <90000>; 5691 hysteresis = <2000>; 5692 type = "passive"; 5693 }; 5694 5695 cpu7_alert1: trip-point1 { 5696 temperature = <95000>; 5697 hysteresis = <2000>; 5698 type = "passive"; 5699 }; 5700 5701 cpu7_crit: cpu-crit { 5702 temperature = <110000>; 5703 hysteresis = <0>; 5704 type = "critical"; 5705 }; 5706 }; 5707 5708 cooling-maps { 5709 map0 { 5710 trip = <&cpu7_alert0>; 5711 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5712 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5713 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5714 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5715 }; 5716 map1 { 5717 trip = <&cpu7_alert1>; 5718 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5719 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5720 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5721 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5722 }; 5723 }; 5724 }; 5725 5726 cpu8-thermal { 5727 polling-delay-passive = <250>; 5728 polling-delay = <0>; 5729 5730 thermal-sensors = <&tsens0 11>; 5731 5732 trips { 5733 cpu8_alert0: trip-point0 { 5734 temperature = <90000>; 5735 hysteresis = <2000>; 5736 type = "passive"; 5737 }; 5738 5739 cpu8_alert1: trip-point1 { 5740 temperature = <95000>; 5741 hysteresis = <2000>; 5742 type = "passive"; 5743 }; 5744 5745 cpu8_crit: cpu-crit { 5746 temperature = <110000>; 5747 hysteresis = <0>; 5748 type = "critical"; 5749 }; 5750 }; 5751 5752 cooling-maps { 5753 map0 { 5754 trip = <&cpu8_alert0>; 5755 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5756 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5757 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5758 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5759 }; 5760 map1 { 5761 trip = <&cpu8_alert1>; 5762 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5763 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5764 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5765 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5766 }; 5767 }; 5768 }; 5769 5770 cpu9-thermal { 5771 polling-delay-passive = <250>; 5772 polling-delay = <0>; 5773 5774 thermal-sensors = <&tsens0 12>; 5775 5776 trips { 5777 cpu9_alert0: trip-point0 { 5778 temperature = <90000>; 5779 hysteresis = <2000>; 5780 type = "passive"; 5781 }; 5782 5783 cpu9_alert1: trip-point1 { 5784 temperature = <95000>; 5785 hysteresis = <2000>; 5786 type = "passive"; 5787 }; 5788 5789 cpu9_crit: cpu-crit { 5790 temperature = <110000>; 5791 hysteresis = <0>; 5792 type = "critical"; 5793 }; 5794 }; 5795 5796 cooling-maps { 5797 map0 { 5798 trip = <&cpu9_alert0>; 5799 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5800 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5801 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5802 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5803 }; 5804 map1 { 5805 trip = <&cpu9_alert1>; 5806 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5807 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5808 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5809 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5810 }; 5811 }; 5812 }; 5813 5814 cpu10-thermal { 5815 polling-delay-passive = <250>; 5816 polling-delay = <0>; 5817 5818 thermal-sensors = <&tsens0 13>; 5819 5820 trips { 5821 cpu10_alert0: trip-point0 { 5822 temperature = <90000>; 5823 hysteresis = <2000>; 5824 type = "passive"; 5825 }; 5826 5827 cpu10_alert1: trip-point1 { 5828 temperature = <95000>; 5829 hysteresis = <2000>; 5830 type = "passive"; 5831 }; 5832 5833 cpu10_crit: cpu-crit { 5834 temperature = <110000>; 5835 hysteresis = <0>; 5836 type = "critical"; 5837 }; 5838 }; 5839 5840 cooling-maps { 5841 map0 { 5842 trip = <&cpu10_alert0>; 5843 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5844 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5845 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5846 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5847 }; 5848 map1 { 5849 trip = <&cpu10_alert1>; 5850 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5851 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5852 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5853 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5854 }; 5855 }; 5856 }; 5857 5858 cpu11-thermal { 5859 polling-delay-passive = <250>; 5860 polling-delay = <0>; 5861 5862 thermal-sensors = <&tsens0 14>; 5863 5864 trips { 5865 cpu11_alert0: trip-point0 { 5866 temperature = <90000>; 5867 hysteresis = <2000>; 5868 type = "passive"; 5869 }; 5870 5871 cpu11_alert1: trip-point1 { 5872 temperature = <95000>; 5873 hysteresis = <2000>; 5874 type = "passive"; 5875 }; 5876 5877 cpu11_crit: cpu-crit { 5878 temperature = <110000>; 5879 hysteresis = <0>; 5880 type = "critical"; 5881 }; 5882 }; 5883 5884 cooling-maps { 5885 map0 { 5886 trip = <&cpu11_alert0>; 5887 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5888 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5889 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5890 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5891 }; 5892 map1 { 5893 trip = <&cpu11_alert1>; 5894 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5895 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5896 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5897 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5898 }; 5899 }; 5900 }; 5901 5902 aoss0-thermal { 5903 polling-delay-passive = <0>; 5904 polling-delay = <0>; 5905 5906 thermal-sensors = <&tsens0 0>; 5907 5908 trips { 5909 aoss0_alert0: trip-point0 { 5910 temperature = <90000>; 5911 hysteresis = <2000>; 5912 type = "hot"; 5913 }; 5914 5915 aoss0_crit: aoss0-crit { 5916 temperature = <110000>; 5917 hysteresis = <0>; 5918 type = "critical"; 5919 }; 5920 }; 5921 }; 5922 5923 aoss1-thermal { 5924 polling-delay-passive = <0>; 5925 polling-delay = <0>; 5926 5927 thermal-sensors = <&tsens1 0>; 5928 5929 trips { 5930 aoss1_alert0: trip-point0 { 5931 temperature = <90000>; 5932 hysteresis = <2000>; 5933 type = "hot"; 5934 }; 5935 5936 aoss1_crit: aoss1-crit { 5937 temperature = <110000>; 5938 hysteresis = <0>; 5939 type = "critical"; 5940 }; 5941 }; 5942 }; 5943 5944 cpuss0-thermal { 5945 polling-delay-passive = <0>; 5946 polling-delay = <0>; 5947 5948 thermal-sensors = <&tsens0 5>; 5949 5950 trips { 5951 cpuss0_alert0: trip-point0 { 5952 temperature = <90000>; 5953 hysteresis = <2000>; 5954 type = "hot"; 5955 }; 5956 cpuss0_crit: cluster0-crit { 5957 temperature = <110000>; 5958 hysteresis = <0>; 5959 type = "critical"; 5960 }; 5961 }; 5962 }; 5963 5964 cpuss1-thermal { 5965 polling-delay-passive = <0>; 5966 polling-delay = <0>; 5967 5968 thermal-sensors = <&tsens0 6>; 5969 5970 trips { 5971 cpuss1_alert0: trip-point0 { 5972 temperature = <90000>; 5973 hysteresis = <2000>; 5974 type = "hot"; 5975 }; 5976 cpuss1_crit: cluster0-crit { 5977 temperature = <110000>; 5978 hysteresis = <0>; 5979 type = "critical"; 5980 }; 5981 }; 5982 }; 5983 5984 gpuss0-thermal { 5985 polling-delay-passive = <100>; 5986 polling-delay = <0>; 5987 5988 thermal-sensors = <&tsens1 1>; 5989 5990 trips { 5991 gpuss0_alert0: trip-point0 { 5992 temperature = <95000>; 5993 hysteresis = <2000>; 5994 type = "passive"; 5995 }; 5996 5997 gpuss0_crit: gpuss0-crit { 5998 temperature = <110000>; 5999 hysteresis = <0>; 6000 type = "critical"; 6001 }; 6002 }; 6003 6004 cooling-maps { 6005 map0 { 6006 trip = <&gpuss0_alert0>; 6007 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6008 }; 6009 }; 6010 }; 6011 6012 gpuss1-thermal { 6013 polling-delay-passive = <100>; 6014 polling-delay = <0>; 6015 6016 thermal-sensors = <&tsens1 2>; 6017 6018 trips { 6019 gpuss1_alert0: trip-point0 { 6020 temperature = <95000>; 6021 hysteresis = <2000>; 6022 type = "passive"; 6023 }; 6024 6025 gpuss1_crit: gpuss1-crit { 6026 temperature = <110000>; 6027 hysteresis = <0>; 6028 type = "critical"; 6029 }; 6030 }; 6031 6032 cooling-maps { 6033 map0 { 6034 trip = <&gpuss1_alert0>; 6035 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6036 }; 6037 }; 6038 }; 6039 6040 nspss0-thermal { 6041 polling-delay-passive = <0>; 6042 polling-delay = <0>; 6043 6044 thermal-sensors = <&tsens1 3>; 6045 6046 trips { 6047 nspss0_alert0: trip-point0 { 6048 temperature = <90000>; 6049 hysteresis = <2000>; 6050 type = "hot"; 6051 }; 6052 6053 nspss0_crit: nspss0-crit { 6054 temperature = <110000>; 6055 hysteresis = <0>; 6056 type = "critical"; 6057 }; 6058 }; 6059 }; 6060 6061 nspss1-thermal { 6062 polling-delay-passive = <0>; 6063 polling-delay = <0>; 6064 6065 thermal-sensors = <&tsens1 4>; 6066 6067 trips { 6068 nspss1_alert0: trip-point0 { 6069 temperature = <90000>; 6070 hysteresis = <2000>; 6071 type = "hot"; 6072 }; 6073 6074 nspss1_crit: nspss1-crit { 6075 temperature = <110000>; 6076 hysteresis = <0>; 6077 type = "critical"; 6078 }; 6079 }; 6080 }; 6081 6082 video-thermal { 6083 polling-delay-passive = <0>; 6084 polling-delay = <0>; 6085 6086 thermal-sensors = <&tsens1 5>; 6087 6088 trips { 6089 video_alert0: trip-point0 { 6090 temperature = <90000>; 6091 hysteresis = <2000>; 6092 type = "hot"; 6093 }; 6094 6095 video_crit: video-crit { 6096 temperature = <110000>; 6097 hysteresis = <0>; 6098 type = "critical"; 6099 }; 6100 }; 6101 }; 6102 6103 ddr-thermal { 6104 polling-delay-passive = <0>; 6105 polling-delay = <0>; 6106 6107 thermal-sensors = <&tsens1 6>; 6108 6109 trips { 6110 ddr_alert0: trip-point0 { 6111 temperature = <90000>; 6112 hysteresis = <2000>; 6113 type = "hot"; 6114 }; 6115 6116 ddr_crit: ddr-crit { 6117 temperature = <110000>; 6118 hysteresis = <0>; 6119 type = "critical"; 6120 }; 6121 }; 6122 }; 6123 6124 mdmss0-thermal { 6125 polling-delay-passive = <0>; 6126 polling-delay = <0>; 6127 6128 thermal-sensors = <&tsens1 7>; 6129 6130 trips { 6131 mdmss0_alert0: trip-point0 { 6132 temperature = <90000>; 6133 hysteresis = <2000>; 6134 type = "hot"; 6135 }; 6136 6137 mdmss0_crit: mdmss0-crit { 6138 temperature = <110000>; 6139 hysteresis = <0>; 6140 type = "critical"; 6141 }; 6142 }; 6143 }; 6144 6145 mdmss1-thermal { 6146 polling-delay-passive = <0>; 6147 polling-delay = <0>; 6148 6149 thermal-sensors = <&tsens1 8>; 6150 6151 trips { 6152 mdmss1_alert0: trip-point0 { 6153 temperature = <90000>; 6154 hysteresis = <2000>; 6155 type = "hot"; 6156 }; 6157 6158 mdmss1_crit: mdmss1-crit { 6159 temperature = <110000>; 6160 hysteresis = <0>; 6161 type = "critical"; 6162 }; 6163 }; 6164 }; 6165 6166 mdmss2-thermal { 6167 polling-delay-passive = <0>; 6168 polling-delay = <0>; 6169 6170 thermal-sensors = <&tsens1 9>; 6171 6172 trips { 6173 mdmss2_alert0: trip-point0 { 6174 temperature = <90000>; 6175 hysteresis = <2000>; 6176 type = "hot"; 6177 }; 6178 6179 mdmss2_crit: mdmss2-crit { 6180 temperature = <110000>; 6181 hysteresis = <0>; 6182 type = "critical"; 6183 }; 6184 }; 6185 }; 6186 6187 mdmss3-thermal { 6188 polling-delay-passive = <0>; 6189 polling-delay = <0>; 6190 6191 thermal-sensors = <&tsens1 10>; 6192 6193 trips { 6194 mdmss3_alert0: trip-point0 { 6195 temperature = <90000>; 6196 hysteresis = <2000>; 6197 type = "hot"; 6198 }; 6199 6200 mdmss3_crit: mdmss3-crit { 6201 temperature = <110000>; 6202 hysteresis = <0>; 6203 type = "critical"; 6204 }; 6205 }; 6206 }; 6207 6208 camera0-thermal { 6209 polling-delay-passive = <0>; 6210 polling-delay = <0>; 6211 6212 thermal-sensors = <&tsens1 11>; 6213 6214 trips { 6215 camera0_alert0: trip-point0 { 6216 temperature = <90000>; 6217 hysteresis = <2000>; 6218 type = "hot"; 6219 }; 6220 6221 camera0_crit: camera0-crit { 6222 temperature = <110000>; 6223 hysteresis = <0>; 6224 type = "critical"; 6225 }; 6226 }; 6227 }; 6228 }; 6229 6230 timer { 6231 compatible = "arm,armv8-timer"; 6232 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6233 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6234 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6235 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6236 }; 6237}; 6238