1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-sc7280.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/interconnect/qcom,sc7280.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/mailbox/qcom-ipcc.h> 13#include <dt-bindings/power/qcom-aoss-qmp.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/reset/qcom,sdm845-aoss.h> 16#include <dt-bindings/reset/qcom,sdm845-pdc.h> 17#include <dt-bindings/soc/qcom,rpmh-rsc.h> 18#include <dt-bindings/thermal/thermal.h> 19 20/ { 21 interrupt-parent = <&intc>; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 chosen { }; 27 28 aliases { 29 mmc1 = &sdhc_1; 30 mmc2 = &sdhc_2; 31 }; 32 33 clocks { 34 xo_board: xo-board { 35 compatible = "fixed-clock"; 36 clock-frequency = <76800000>; 37 #clock-cells = <0>; 38 }; 39 40 sleep_clk: sleep-clk { 41 compatible = "fixed-clock"; 42 clock-frequency = <32000>; 43 #clock-cells = <0>; 44 }; 45 }; 46 47 reserved-memory { 48 #address-cells = <2>; 49 #size-cells = <2>; 50 ranges; 51 52 aop_mem: memory@80800000 { 53 reg = <0x0 0x80800000 0x0 0x60000>; 54 no-map; 55 }; 56 57 aop_cmd_db_mem: memory@80860000 { 58 reg = <0x0 0x80860000 0x0 0x20000>; 59 compatible = "qcom,cmd-db"; 60 no-map; 61 }; 62 63 smem_mem: memory@80900000 { 64 reg = <0x0 0x80900000 0x0 0x200000>; 65 no-map; 66 }; 67 68 cpucp_mem: memory@80b00000 { 69 no-map; 70 reg = <0x0 0x80b00000 0x0 0x100000>; 71 }; 72 }; 73 74 cpus { 75 #address-cells = <2>; 76 #size-cells = <0>; 77 78 CPU0: cpu@0 { 79 device_type = "cpu"; 80 compatible = "arm,kryo"; 81 reg = <0x0 0x0>; 82 enable-method = "psci"; 83 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 84 &LITTLE_CPU_SLEEP_1 85 &CLUSTER_SLEEP_0>; 86 next-level-cache = <&L2_0>; 87 qcom,freq-domain = <&cpufreq_hw 0>; 88 #cooling-cells = <2>; 89 L2_0: l2-cache { 90 compatible = "cache"; 91 next-level-cache = <&L3_0>; 92 L3_0: l3-cache { 93 compatible = "cache"; 94 }; 95 }; 96 }; 97 98 CPU1: cpu@100 { 99 device_type = "cpu"; 100 compatible = "arm,kryo"; 101 reg = <0x0 0x100>; 102 enable-method = "psci"; 103 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 104 &LITTLE_CPU_SLEEP_1 105 &CLUSTER_SLEEP_0>; 106 next-level-cache = <&L2_100>; 107 qcom,freq-domain = <&cpufreq_hw 0>; 108 #cooling-cells = <2>; 109 L2_100: l2-cache { 110 compatible = "cache"; 111 next-level-cache = <&L3_0>; 112 }; 113 }; 114 115 CPU2: cpu@200 { 116 device_type = "cpu"; 117 compatible = "arm,kryo"; 118 reg = <0x0 0x200>; 119 enable-method = "psci"; 120 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 121 &LITTLE_CPU_SLEEP_1 122 &CLUSTER_SLEEP_0>; 123 next-level-cache = <&L2_200>; 124 qcom,freq-domain = <&cpufreq_hw 0>; 125 #cooling-cells = <2>; 126 L2_200: l2-cache { 127 compatible = "cache"; 128 next-level-cache = <&L3_0>; 129 }; 130 }; 131 132 CPU3: cpu@300 { 133 device_type = "cpu"; 134 compatible = "arm,kryo"; 135 reg = <0x0 0x300>; 136 enable-method = "psci"; 137 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 138 &LITTLE_CPU_SLEEP_1 139 &CLUSTER_SLEEP_0>; 140 next-level-cache = <&L2_300>; 141 qcom,freq-domain = <&cpufreq_hw 0>; 142 #cooling-cells = <2>; 143 L2_300: l2-cache { 144 compatible = "cache"; 145 next-level-cache = <&L3_0>; 146 }; 147 }; 148 149 CPU4: cpu@400 { 150 device_type = "cpu"; 151 compatible = "arm,kryo"; 152 reg = <0x0 0x400>; 153 enable-method = "psci"; 154 cpu-idle-states = <&BIG_CPU_SLEEP_0 155 &BIG_CPU_SLEEP_1 156 &CLUSTER_SLEEP_0>; 157 next-level-cache = <&L2_400>; 158 qcom,freq-domain = <&cpufreq_hw 1>; 159 #cooling-cells = <2>; 160 L2_400: l2-cache { 161 compatible = "cache"; 162 next-level-cache = <&L3_0>; 163 }; 164 }; 165 166 CPU5: cpu@500 { 167 device_type = "cpu"; 168 compatible = "arm,kryo"; 169 reg = <0x0 0x500>; 170 enable-method = "psci"; 171 cpu-idle-states = <&BIG_CPU_SLEEP_0 172 &BIG_CPU_SLEEP_1 173 &CLUSTER_SLEEP_0>; 174 next-level-cache = <&L2_500>; 175 qcom,freq-domain = <&cpufreq_hw 1>; 176 #cooling-cells = <2>; 177 L2_500: l2-cache { 178 compatible = "cache"; 179 next-level-cache = <&L3_0>; 180 }; 181 }; 182 183 CPU6: cpu@600 { 184 device_type = "cpu"; 185 compatible = "arm,kryo"; 186 reg = <0x0 0x600>; 187 enable-method = "psci"; 188 cpu-idle-states = <&BIG_CPU_SLEEP_0 189 &BIG_CPU_SLEEP_1 190 &CLUSTER_SLEEP_0>; 191 next-level-cache = <&L2_600>; 192 qcom,freq-domain = <&cpufreq_hw 1>; 193 #cooling-cells = <2>; 194 L2_600: l2-cache { 195 compatible = "cache"; 196 next-level-cache = <&L3_0>; 197 }; 198 }; 199 200 CPU7: cpu@700 { 201 device_type = "cpu"; 202 compatible = "arm,kryo"; 203 reg = <0x0 0x700>; 204 enable-method = "psci"; 205 cpu-idle-states = <&BIG_CPU_SLEEP_0 206 &BIG_CPU_SLEEP_1 207 &CLUSTER_SLEEP_0>; 208 next-level-cache = <&L2_700>; 209 qcom,freq-domain = <&cpufreq_hw 1>; 210 #cooling-cells = <2>; 211 L2_700: l2-cache { 212 compatible = "cache"; 213 next-level-cache = <&L3_0>; 214 }; 215 }; 216 217 idle-states { 218 entry-method = "psci"; 219 220 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 221 compatible = "arm,idle-state"; 222 idle-state-name = "little-power-down"; 223 arm,psci-suspend-param = <0x40000003>; 224 entry-latency-us = <549>; 225 exit-latency-us = <901>; 226 min-residency-us = <1774>; 227 local-timer-stop; 228 }; 229 230 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 231 compatible = "arm,idle-state"; 232 idle-state-name = "little-rail-power-down"; 233 arm,psci-suspend-param = <0x40000004>; 234 entry-latency-us = <702>; 235 exit-latency-us = <915>; 236 min-residency-us = <4001>; 237 local-timer-stop; 238 }; 239 240 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 241 compatible = "arm,idle-state"; 242 idle-state-name = "big-power-down"; 243 arm,psci-suspend-param = <0x40000003>; 244 entry-latency-us = <523>; 245 exit-latency-us = <1244>; 246 min-residency-us = <2207>; 247 local-timer-stop; 248 }; 249 250 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 251 compatible = "arm,idle-state"; 252 idle-state-name = "big-rail-power-down"; 253 arm,psci-suspend-param = <0x40000004>; 254 entry-latency-us = <526>; 255 exit-latency-us = <1854>; 256 min-residency-us = <5555>; 257 local-timer-stop; 258 }; 259 260 CLUSTER_SLEEP_0: cluster-sleep-0 { 261 compatible = "arm,idle-state"; 262 idle-state-name = "cluster-power-down"; 263 arm,psci-suspend-param = <0x40003444>; 264 entry-latency-us = <3263>; 265 exit-latency-us = <6562>; 266 min-residency-us = <9926>; 267 local-timer-stop; 268 }; 269 }; 270 }; 271 272 memory@80000000 { 273 device_type = "memory"; 274 /* We expect the bootloader to fill in the size */ 275 reg = <0 0x80000000 0 0>; 276 }; 277 278 firmware { 279 scm { 280 compatible = "qcom,scm-sc7280", "qcom,scm"; 281 }; 282 }; 283 284 clk_virt: interconnect { 285 compatible = "qcom,sc7280-clk-virt"; 286 #interconnect-cells = <2>; 287 qcom,bcm-voters = <&apps_bcm_voter>; 288 }; 289 290 smem { 291 compatible = "qcom,smem"; 292 memory-region = <&smem_mem>; 293 hwlocks = <&tcsr_mutex 3>; 294 }; 295 296 smp2p-adsp { 297 compatible = "qcom,smp2p"; 298 qcom,smem = <443>, <429>; 299 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 300 IPCC_MPROC_SIGNAL_SMP2P 301 IRQ_TYPE_EDGE_RISING>; 302 mboxes = <&ipcc IPCC_CLIENT_LPASS 303 IPCC_MPROC_SIGNAL_SMP2P>; 304 305 qcom,local-pid = <0>; 306 qcom,remote-pid = <2>; 307 308 adsp_smp2p_out: master-kernel { 309 qcom,entry-name = "master-kernel"; 310 #qcom,smem-state-cells = <1>; 311 }; 312 313 adsp_smp2p_in: slave-kernel { 314 qcom,entry-name = "slave-kernel"; 315 interrupt-controller; 316 #interrupt-cells = <2>; 317 }; 318 }; 319 320 smp2p-cdsp { 321 compatible = "qcom,smp2p"; 322 qcom,smem = <94>, <432>; 323 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 324 IPCC_MPROC_SIGNAL_SMP2P 325 IRQ_TYPE_EDGE_RISING>; 326 mboxes = <&ipcc IPCC_CLIENT_CDSP 327 IPCC_MPROC_SIGNAL_SMP2P>; 328 329 qcom,local-pid = <0>; 330 qcom,remote-pid = <5>; 331 332 cdsp_smp2p_out: master-kernel { 333 qcom,entry-name = "master-kernel"; 334 #qcom,smem-state-cells = <1>; 335 }; 336 337 cdsp_smp2p_in: slave-kernel { 338 qcom,entry-name = "slave-kernel"; 339 interrupt-controller; 340 #interrupt-cells = <2>; 341 }; 342 }; 343 344 smp2p-mpss { 345 compatible = "qcom,smp2p"; 346 qcom,smem = <435>, <428>; 347 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 348 IPCC_MPROC_SIGNAL_SMP2P 349 IRQ_TYPE_EDGE_RISING>; 350 mboxes = <&ipcc IPCC_CLIENT_MPSS 351 IPCC_MPROC_SIGNAL_SMP2P>; 352 353 qcom,local-pid = <0>; 354 qcom,remote-pid = <1>; 355 356 modem_smp2p_out: master-kernel { 357 qcom,entry-name = "master-kernel"; 358 #qcom,smem-state-cells = <1>; 359 }; 360 361 modem_smp2p_in: slave-kernel { 362 qcom,entry-name = "slave-kernel"; 363 interrupt-controller; 364 #interrupt-cells = <2>; 365 }; 366 367 ipa_smp2p_out: ipa-ap-to-modem { 368 qcom,entry-name = "ipa"; 369 #qcom,smem-state-cells = <1>; 370 }; 371 372 ipa_smp2p_in: ipa-modem-to-ap { 373 qcom,entry-name = "ipa"; 374 interrupt-controller; 375 #interrupt-cells = <2>; 376 }; 377 }; 378 379 smp2p-wpss { 380 compatible = "qcom,smp2p"; 381 qcom,smem = <617>, <616>; 382 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 383 IPCC_MPROC_SIGNAL_SMP2P 384 IRQ_TYPE_EDGE_RISING>; 385 mboxes = <&ipcc IPCC_CLIENT_WPSS 386 IPCC_MPROC_SIGNAL_SMP2P>; 387 388 qcom,local-pid = <0>; 389 qcom,remote-pid = <13>; 390 391 wpss_smp2p_out: master-kernel { 392 qcom,entry-name = "master-kernel"; 393 #qcom,smem-state-cells = <1>; 394 }; 395 396 wpss_smp2p_in: slave-kernel { 397 qcom,entry-name = "slave-kernel"; 398 interrupt-controller; 399 #interrupt-cells = <2>; 400 }; 401 }; 402 403 pmu { 404 compatible = "arm,armv8-pmuv3"; 405 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 406 }; 407 408 psci { 409 compatible = "arm,psci-1.0"; 410 method = "smc"; 411 }; 412 413 soc: soc@0 { 414 #address-cells = <2>; 415 #size-cells = <2>; 416 ranges = <0 0 0 0 0x10 0>; 417 dma-ranges = <0 0 0 0 0x10 0>; 418 compatible = "simple-bus"; 419 420 gcc: clock-controller@100000 { 421 compatible = "qcom,gcc-sc7280"; 422 reg = <0 0x00100000 0 0x1f0000>; 423 clocks = <&rpmhcc RPMH_CXO_CLK>, 424 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 425 <0>, <0>, <0>, <0>, <0>, <0>; 426 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 427 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 428 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 429 "ufs_phy_tx_symbol_0_clk", 430 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 431 #clock-cells = <1>; 432 #reset-cells = <1>; 433 #power-domain-cells = <1>; 434 }; 435 436 ipcc: mailbox@408000 { 437 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 438 reg = <0 0x00408000 0 0x1000>; 439 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 440 interrupt-controller; 441 #interrupt-cells = <3>; 442 #mbox-cells = <2>; 443 }; 444 445 sdhc_1: sdhci@7c4000 { 446 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 447 status = "disabled"; 448 449 reg = <0 0x007c4000 0 0x1000>, 450 <0 0x007c5000 0 0x1000>; 451 reg-names = "hc", "cqhci"; 452 453 iommus = <&apps_smmu 0xc0 0x0>; 454 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 456 interrupt-names = "hc_irq", "pwr_irq"; 457 458 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 459 <&gcc GCC_SDCC1_AHB_CLK>, 460 <&rpmhcc RPMH_CXO_CLK>; 461 clock-names = "core", "iface", "xo"; 462 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 463 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 464 interconnect-names = "sdhc-ddr","cpu-sdhc"; 465 power-domains = <&rpmhpd SC7280_CX>; 466 operating-points-v2 = <&sdhc1_opp_table>; 467 468 bus-width = <8>; 469 supports-cqe; 470 471 qcom,dll-config = <0x0007642c>; 472 qcom,ddr-config = <0x80040868>; 473 474 mmc-ddr-1_8v; 475 mmc-hs200-1_8v; 476 mmc-hs400-1_8v; 477 mmc-hs400-enhanced-strobe; 478 479 sdhc1_opp_table: opp-table { 480 compatible = "operating-points-v2"; 481 482 opp-100000000 { 483 opp-hz = /bits/ 64 <100000000>; 484 required-opps = <&rpmhpd_opp_low_svs>; 485 opp-peak-kBps = <1800000 400000>; 486 opp-avg-kBps = <100000 0>; 487 }; 488 489 opp-384000000 { 490 opp-hz = /bits/ 64 <384000000>; 491 required-opps = <&rpmhpd_opp_nom>; 492 opp-peak-kBps = <5400000 1600000>; 493 opp-avg-kBps = <390000 0>; 494 }; 495 }; 496 497 }; 498 499 qupv3_id_0: geniqup@9c0000 { 500 compatible = "qcom,geni-se-qup"; 501 reg = <0 0x009c0000 0 0x2000>; 502 clock-names = "m-ahb", "s-ahb"; 503 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 504 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 505 #address-cells = <2>; 506 #size-cells = <2>; 507 ranges; 508 status = "disabled"; 509 510 uart5: serial@994000 { 511 compatible = "qcom,geni-debug-uart"; 512 reg = <0 0x00994000 0 0x4000>; 513 clock-names = "se"; 514 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 515 pinctrl-names = "default"; 516 pinctrl-0 = <&qup_uart5_default>; 517 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 518 status = "disabled"; 519 }; 520 }; 521 522 cnoc2: interconnect@1500000 { 523 reg = <0 0x01500000 0 0x1000>; 524 compatible = "qcom,sc7280-cnoc2"; 525 #interconnect-cells = <2>; 526 qcom,bcm-voters = <&apps_bcm_voter>; 527 }; 528 529 cnoc3: interconnect@1502000 { 530 reg = <0 0x01502000 0 0x1000>; 531 compatible = "qcom,sc7280-cnoc3"; 532 #interconnect-cells = <2>; 533 qcom,bcm-voters = <&apps_bcm_voter>; 534 }; 535 536 mc_virt: interconnect@1580000 { 537 reg = <0 0x01580000 0 0x4>; 538 compatible = "qcom,sc7280-mc-virt"; 539 #interconnect-cells = <2>; 540 qcom,bcm-voters = <&apps_bcm_voter>; 541 }; 542 543 system_noc: interconnect@1680000 { 544 reg = <0 0x01680000 0 0x15480>; 545 compatible = "qcom,sc7280-system-noc"; 546 #interconnect-cells = <2>; 547 qcom,bcm-voters = <&apps_bcm_voter>; 548 }; 549 550 aggre1_noc: interconnect@16e0000 { 551 compatible = "qcom,sc7280-aggre1-noc"; 552 reg = <0 0x016e0000 0 0x1c080>; 553 #interconnect-cells = <2>; 554 qcom,bcm-voters = <&apps_bcm_voter>; 555 }; 556 557 aggre2_noc: interconnect@1700000 { 558 reg = <0 0x01700000 0 0x2b080>; 559 compatible = "qcom,sc7280-aggre2-noc"; 560 #interconnect-cells = <2>; 561 qcom,bcm-voters = <&apps_bcm_voter>; 562 }; 563 564 mmss_noc: interconnect@1740000 { 565 reg = <0 0x01740000 0 0x1e080>; 566 compatible = "qcom,sc7280-mmss-noc"; 567 #interconnect-cells = <2>; 568 qcom,bcm-voters = <&apps_bcm_voter>; 569 }; 570 571 tcsr_mutex: hwlock@1f40000 { 572 compatible = "qcom,tcsr-mutex", "syscon"; 573 reg = <0 0x01f40000 0 0x40000>; 574 #hwlock-cells = <1>; 575 }; 576 577 lpasscc: lpasscc@3000000 { 578 compatible = "qcom,sc7280-lpasscc"; 579 reg = <0 0x03000000 0 0x40>, 580 <0 0x03c04000 0 0x4>, 581 <0 0x03389000 0 0x24>; 582 reg-names = "qdsp6ss", "top_cc", "cc"; 583 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 584 clock-names = "iface"; 585 #clock-cells = <1>; 586 }; 587 588 lpass_ag_noc: interconnect@3c40000 { 589 reg = <0 0x03c40000 0 0xf080>; 590 compatible = "qcom,sc7280-lpass-ag-noc"; 591 #interconnect-cells = <2>; 592 qcom,bcm-voters = <&apps_bcm_voter>; 593 }; 594 595 gpucc: clock-controller@3d90000 { 596 compatible = "qcom,sc7280-gpucc"; 597 reg = <0 0x03d90000 0 0x9000>; 598 clocks = <&rpmhcc RPMH_CXO_CLK>, 599 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 600 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 601 clock-names = "bi_tcxo", 602 "gcc_gpu_gpll0_clk_src", 603 "gcc_gpu_gpll0_div_clk_src"; 604 #clock-cells = <1>; 605 #reset-cells = <1>; 606 #power-domain-cells = <1>; 607 }; 608 609 stm@6002000 { 610 compatible = "arm,coresight-stm", "arm,primecell"; 611 reg = <0 0x06002000 0 0x1000>, 612 <0 0x16280000 0 0x180000>; 613 reg-names = "stm-base", "stm-stimulus-base"; 614 615 clocks = <&aoss_qmp>; 616 clock-names = "apb_pclk"; 617 618 out-ports { 619 port { 620 stm_out: endpoint { 621 remote-endpoint = <&funnel0_in7>; 622 }; 623 }; 624 }; 625 }; 626 627 funnel@6041000 { 628 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 629 reg = <0 0x06041000 0 0x1000>; 630 631 clocks = <&aoss_qmp>; 632 clock-names = "apb_pclk"; 633 634 out-ports { 635 port { 636 funnel0_out: endpoint { 637 remote-endpoint = <&merge_funnel_in0>; 638 }; 639 }; 640 }; 641 642 in-ports { 643 #address-cells = <1>; 644 #size-cells = <0>; 645 646 port@7 { 647 reg = <7>; 648 funnel0_in7: endpoint { 649 remote-endpoint = <&stm_out>; 650 }; 651 }; 652 }; 653 }; 654 655 funnel@6042000 { 656 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 657 reg = <0 0x06042000 0 0x1000>; 658 659 clocks = <&aoss_qmp>; 660 clock-names = "apb_pclk"; 661 662 out-ports { 663 port { 664 funnel1_out: endpoint { 665 remote-endpoint = <&merge_funnel_in1>; 666 }; 667 }; 668 }; 669 670 in-ports { 671 #address-cells = <1>; 672 #size-cells = <0>; 673 674 port@4 { 675 reg = <4>; 676 funnel1_in4: endpoint { 677 remote-endpoint = <&apss_merge_funnel_out>; 678 }; 679 }; 680 }; 681 }; 682 683 funnel@6045000 { 684 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 685 reg = <0 0x06045000 0 0x1000>; 686 687 clocks = <&aoss_qmp>; 688 clock-names = "apb_pclk"; 689 690 out-ports { 691 port { 692 merge_funnel_out: endpoint { 693 remote-endpoint = <&swao_funnel_in>; 694 }; 695 }; 696 }; 697 698 in-ports { 699 #address-cells = <1>; 700 #size-cells = <0>; 701 702 port@0 { 703 reg = <0>; 704 merge_funnel_in0: endpoint { 705 remote-endpoint = <&funnel0_out>; 706 }; 707 }; 708 709 port@1 { 710 reg = <1>; 711 merge_funnel_in1: endpoint { 712 remote-endpoint = <&funnel1_out>; 713 }; 714 }; 715 }; 716 }; 717 718 replicator@6046000 { 719 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 720 reg = <0 0x06046000 0 0x1000>; 721 722 clocks = <&aoss_qmp>; 723 clock-names = "apb_pclk"; 724 725 out-ports { 726 port { 727 replicator_out: endpoint { 728 remote-endpoint = <&etr_in>; 729 }; 730 }; 731 }; 732 733 in-ports { 734 port { 735 replicator_in: endpoint { 736 remote-endpoint = <&swao_replicator_out>; 737 }; 738 }; 739 }; 740 }; 741 742 etr@6048000 { 743 compatible = "arm,coresight-tmc", "arm,primecell"; 744 reg = <0 0x06048000 0 0x1000>; 745 iommus = <&apps_smmu 0x04c0 0>; 746 747 clocks = <&aoss_qmp>; 748 clock-names = "apb_pclk"; 749 arm,scatter-gather; 750 751 in-ports { 752 port { 753 etr_in: endpoint { 754 remote-endpoint = <&replicator_out>; 755 }; 756 }; 757 }; 758 }; 759 760 funnel@6b04000 { 761 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 762 reg = <0 0x06b04000 0 0x1000>; 763 764 clocks = <&aoss_qmp>; 765 clock-names = "apb_pclk"; 766 767 out-ports { 768 port { 769 swao_funnel_out: endpoint { 770 remote-endpoint = <&etf_in>; 771 }; 772 }; 773 }; 774 775 in-ports { 776 #address-cells = <1>; 777 #size-cells = <0>; 778 779 port@7 { 780 reg = <7>; 781 swao_funnel_in: endpoint { 782 remote-endpoint = <&merge_funnel_out>; 783 }; 784 }; 785 }; 786 }; 787 788 etf@6b05000 { 789 compatible = "arm,coresight-tmc", "arm,primecell"; 790 reg = <0 0x06b05000 0 0x1000>; 791 792 clocks = <&aoss_qmp>; 793 clock-names = "apb_pclk"; 794 795 out-ports { 796 port { 797 etf_out: endpoint { 798 remote-endpoint = <&swao_replicator_in>; 799 }; 800 }; 801 }; 802 803 in-ports { 804 port { 805 etf_in: endpoint { 806 remote-endpoint = <&swao_funnel_out>; 807 }; 808 }; 809 }; 810 }; 811 812 replicator@6b06000 { 813 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 814 reg = <0 0x06b06000 0 0x1000>; 815 816 clocks = <&aoss_qmp>; 817 clock-names = "apb_pclk"; 818 qcom,replicator-loses-context; 819 820 out-ports { 821 port { 822 swao_replicator_out: endpoint { 823 remote-endpoint = <&replicator_in>; 824 }; 825 }; 826 }; 827 828 in-ports { 829 port { 830 swao_replicator_in: endpoint { 831 remote-endpoint = <&etf_out>; 832 }; 833 }; 834 }; 835 }; 836 837 etm@7040000 { 838 compatible = "arm,coresight-etm4x", "arm,primecell"; 839 reg = <0 0x07040000 0 0x1000>; 840 841 cpu = <&CPU0>; 842 843 clocks = <&aoss_qmp>; 844 clock-names = "apb_pclk"; 845 arm,coresight-loses-context-with-cpu; 846 qcom,skip-power-up; 847 848 out-ports { 849 port { 850 etm0_out: endpoint { 851 remote-endpoint = <&apss_funnel_in0>; 852 }; 853 }; 854 }; 855 }; 856 857 etm@7140000 { 858 compatible = "arm,coresight-etm4x", "arm,primecell"; 859 reg = <0 0x07140000 0 0x1000>; 860 861 cpu = <&CPU1>; 862 863 clocks = <&aoss_qmp>; 864 clock-names = "apb_pclk"; 865 arm,coresight-loses-context-with-cpu; 866 qcom,skip-power-up; 867 868 out-ports { 869 port { 870 etm1_out: endpoint { 871 remote-endpoint = <&apss_funnel_in1>; 872 }; 873 }; 874 }; 875 }; 876 877 etm@7240000 { 878 compatible = "arm,coresight-etm4x", "arm,primecell"; 879 reg = <0 0x07240000 0 0x1000>; 880 881 cpu = <&CPU2>; 882 883 clocks = <&aoss_qmp>; 884 clock-names = "apb_pclk"; 885 arm,coresight-loses-context-with-cpu; 886 qcom,skip-power-up; 887 888 out-ports { 889 port { 890 etm2_out: endpoint { 891 remote-endpoint = <&apss_funnel_in2>; 892 }; 893 }; 894 }; 895 }; 896 897 etm@7340000 { 898 compatible = "arm,coresight-etm4x", "arm,primecell"; 899 reg = <0 0x07340000 0 0x1000>; 900 901 cpu = <&CPU3>; 902 903 clocks = <&aoss_qmp>; 904 clock-names = "apb_pclk"; 905 arm,coresight-loses-context-with-cpu; 906 qcom,skip-power-up; 907 908 out-ports { 909 port { 910 etm3_out: endpoint { 911 remote-endpoint = <&apss_funnel_in3>; 912 }; 913 }; 914 }; 915 }; 916 917 etm@7440000 { 918 compatible = "arm,coresight-etm4x", "arm,primecell"; 919 reg = <0 0x07440000 0 0x1000>; 920 921 cpu = <&CPU4>; 922 923 clocks = <&aoss_qmp>; 924 clock-names = "apb_pclk"; 925 arm,coresight-loses-context-with-cpu; 926 qcom,skip-power-up; 927 928 out-ports { 929 port { 930 etm4_out: endpoint { 931 remote-endpoint = <&apss_funnel_in4>; 932 }; 933 }; 934 }; 935 }; 936 937 etm@7540000 { 938 compatible = "arm,coresight-etm4x", "arm,primecell"; 939 reg = <0 0x07540000 0 0x1000>; 940 941 cpu = <&CPU5>; 942 943 clocks = <&aoss_qmp>; 944 clock-names = "apb_pclk"; 945 arm,coresight-loses-context-with-cpu; 946 qcom,skip-power-up; 947 948 out-ports { 949 port { 950 etm5_out: endpoint { 951 remote-endpoint = <&apss_funnel_in5>; 952 }; 953 }; 954 }; 955 }; 956 957 etm@7640000 { 958 compatible = "arm,coresight-etm4x", "arm,primecell"; 959 reg = <0 0x07640000 0 0x1000>; 960 961 cpu = <&CPU6>; 962 963 clocks = <&aoss_qmp>; 964 clock-names = "apb_pclk"; 965 arm,coresight-loses-context-with-cpu; 966 qcom,skip-power-up; 967 968 out-ports { 969 port { 970 etm6_out: endpoint { 971 remote-endpoint = <&apss_funnel_in6>; 972 }; 973 }; 974 }; 975 }; 976 977 etm@7740000 { 978 compatible = "arm,coresight-etm4x", "arm,primecell"; 979 reg = <0 0x07740000 0 0x1000>; 980 981 cpu = <&CPU7>; 982 983 clocks = <&aoss_qmp>; 984 clock-names = "apb_pclk"; 985 arm,coresight-loses-context-with-cpu; 986 qcom,skip-power-up; 987 988 out-ports { 989 port { 990 etm7_out: endpoint { 991 remote-endpoint = <&apss_funnel_in7>; 992 }; 993 }; 994 }; 995 }; 996 997 funnel@7800000 { /* APSS Funnel */ 998 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 999 reg = <0 0x07800000 0 0x1000>; 1000 1001 clocks = <&aoss_qmp>; 1002 clock-names = "apb_pclk"; 1003 1004 out-ports { 1005 port { 1006 apss_funnel_out: endpoint { 1007 remote-endpoint = <&apss_merge_funnel_in>; 1008 }; 1009 }; 1010 }; 1011 1012 in-ports { 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 1016 port@0 { 1017 reg = <0>; 1018 apss_funnel_in0: endpoint { 1019 remote-endpoint = <&etm0_out>; 1020 }; 1021 }; 1022 1023 port@1 { 1024 reg = <1>; 1025 apss_funnel_in1: endpoint { 1026 remote-endpoint = <&etm1_out>; 1027 }; 1028 }; 1029 1030 port@2 { 1031 reg = <2>; 1032 apss_funnel_in2: endpoint { 1033 remote-endpoint = <&etm2_out>; 1034 }; 1035 }; 1036 1037 port@3 { 1038 reg = <3>; 1039 apss_funnel_in3: endpoint { 1040 remote-endpoint = <&etm3_out>; 1041 }; 1042 }; 1043 1044 port@4 { 1045 reg = <4>; 1046 apss_funnel_in4: endpoint { 1047 remote-endpoint = <&etm4_out>; 1048 }; 1049 }; 1050 1051 port@5 { 1052 reg = <5>; 1053 apss_funnel_in5: endpoint { 1054 remote-endpoint = <&etm5_out>; 1055 }; 1056 }; 1057 1058 port@6 { 1059 reg = <6>; 1060 apss_funnel_in6: endpoint { 1061 remote-endpoint = <&etm6_out>; 1062 }; 1063 }; 1064 1065 port@7 { 1066 reg = <7>; 1067 apss_funnel_in7: endpoint { 1068 remote-endpoint = <&etm7_out>; 1069 }; 1070 }; 1071 }; 1072 }; 1073 1074 funnel@7810000 { 1075 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1076 reg = <0 0x07810000 0 0x1000>; 1077 1078 clocks = <&aoss_qmp>; 1079 clock-names = "apb_pclk"; 1080 1081 out-ports { 1082 port { 1083 apss_merge_funnel_out: endpoint { 1084 remote-endpoint = <&funnel1_in4>; 1085 }; 1086 }; 1087 }; 1088 1089 in-ports { 1090 port { 1091 apss_merge_funnel_in: endpoint { 1092 remote-endpoint = <&apss_funnel_out>; 1093 }; 1094 }; 1095 }; 1096 }; 1097 1098 sdhc_2: sdhci@8804000 { 1099 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 1100 status = "disabled"; 1101 1102 reg = <0 0x08804000 0 0x1000>; 1103 1104 iommus = <&apps_smmu 0x100 0x0>; 1105 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1107 interrupt-names = "hc_irq", "pwr_irq"; 1108 1109 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 1110 <&gcc GCC_SDCC2_AHB_CLK>, 1111 <&rpmhcc RPMH_CXO_CLK>; 1112 clock-names = "core", "iface", "xo"; 1113 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 1114 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 1115 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1116 power-domains = <&rpmhpd SC7280_CX>; 1117 operating-points-v2 = <&sdhc2_opp_table>; 1118 1119 bus-width = <4>; 1120 1121 qcom,dll-config = <0x0007642c>; 1122 1123 sdhc2_opp_table: opp-table { 1124 compatible = "operating-points-v2"; 1125 1126 opp-100000000 { 1127 opp-hz = /bits/ 64 <100000000>; 1128 required-opps = <&rpmhpd_opp_low_svs>; 1129 opp-peak-kBps = <1800000 400000>; 1130 opp-avg-kBps = <100000 0>; 1131 }; 1132 1133 opp-202000000 { 1134 opp-hz = /bits/ 64 <202000000>; 1135 required-opps = <&rpmhpd_opp_nom>; 1136 opp-peak-kBps = <5400000 1600000>; 1137 opp-avg-kBps = <200000 0>; 1138 }; 1139 }; 1140 1141 }; 1142 1143 dc_noc: interconnect@90e0000 { 1144 reg = <0 0x090e0000 0 0x5080>; 1145 compatible = "qcom,sc7280-dc-noc"; 1146 #interconnect-cells = <2>; 1147 qcom,bcm-voters = <&apps_bcm_voter>; 1148 }; 1149 1150 gem_noc: interconnect@9100000 { 1151 reg = <0 0x9100000 0 0xe2200>; 1152 compatible = "qcom,sc7280-gem-noc"; 1153 #interconnect-cells = <2>; 1154 qcom,bcm-voters = <&apps_bcm_voter>; 1155 }; 1156 1157 system-cache-controller@9200000 { 1158 compatible = "qcom,sc7280-llcc"; 1159 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 1160 reg-names = "llcc_base", "llcc_broadcast_base"; 1161 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1162 }; 1163 1164 nsp_noc: interconnect@a0c0000 { 1165 reg = <0 0x0a0c0000 0 0x10000>; 1166 compatible = "qcom,sc7280-nsp-noc"; 1167 #interconnect-cells = <2>; 1168 qcom,bcm-voters = <&apps_bcm_voter>; 1169 }; 1170 1171 videocc: clock-controller@aaf0000 { 1172 compatible = "qcom,sc7280-videocc"; 1173 reg = <0 0xaaf0000 0 0x10000>; 1174 clocks = <&rpmhcc RPMH_CXO_CLK>, 1175 <&rpmhcc RPMH_CXO_CLK_A>; 1176 clock-names = "bi_tcxo", "bi_tcxo_ao"; 1177 #clock-cells = <1>; 1178 #reset-cells = <1>; 1179 #power-domain-cells = <1>; 1180 }; 1181 1182 dispcc: clock-controller@af00000 { 1183 compatible = "qcom,sc7280-dispcc"; 1184 reg = <0 0xaf00000 0 0x20000>; 1185 clocks = <&rpmhcc RPMH_CXO_CLK>, 1186 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 1187 <0>, <0>, <0>, <0>, <0>, <0>; 1188 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 1189 "dsi0_phy_pll_out_byteclk", 1190 "dsi0_phy_pll_out_dsiclk", 1191 "dp_phy_pll_link_clk", 1192 "dp_phy_pll_vco_div_clk", 1193 "edp_phy_pll_link_clk", 1194 "edp_phy_pll_vco_div_clk"; 1195 #clock-cells = <1>; 1196 #reset-cells = <1>; 1197 #power-domain-cells = <1>; 1198 }; 1199 1200 pdc: interrupt-controller@b220000 { 1201 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 1202 reg = <0 0x0b220000 0 0x30000>; 1203 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 1204 <55 306 4>, <59 312 3>, <62 374 2>, 1205 <64 434 2>, <66 438 3>, <69 86 1>, 1206 <70 520 54>, <124 609 31>, <155 63 1>, 1207 <156 716 12>; 1208 #interrupt-cells = <2>; 1209 interrupt-parent = <&intc>; 1210 interrupt-controller; 1211 }; 1212 1213 pdc_reset: reset-controller@b5e0000 { 1214 compatible = "qcom,sc7280-pdc-global"; 1215 reg = <0 0x0b5e0000 0 0x20000>; 1216 #reset-cells = <1>; 1217 }; 1218 1219 tsens0: thermal-sensor@c263000 { 1220 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 1221 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1222 <0 0x0c222000 0 0x1ff>; /* SROT */ 1223 #qcom,sensors = <15>; 1224 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1226 interrupt-names = "uplow","critical"; 1227 #thermal-sensor-cells = <1>; 1228 }; 1229 1230 tsens1: thermal-sensor@c265000 { 1231 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 1232 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1233 <0 0x0c223000 0 0x1ff>; /* SROT */ 1234 #qcom,sensors = <12>; 1235 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1237 interrupt-names = "uplow","critical"; 1238 #thermal-sensor-cells = <1>; 1239 }; 1240 1241 aoss_reset: reset-controller@c2a0000 { 1242 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 1243 reg = <0 0x0c2a0000 0 0x31000>; 1244 #reset-cells = <1>; 1245 }; 1246 1247 aoss_qmp: power-controller@c300000 { 1248 compatible = "qcom,sc7280-aoss-qmp"; 1249 reg = <0 0x0c300000 0 0x100000>; 1250 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 1251 IPCC_MPROC_SIGNAL_GLINK_QMP 1252 IRQ_TYPE_EDGE_RISING>; 1253 mboxes = <&ipcc IPCC_CLIENT_AOP 1254 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1255 1256 #clock-cells = <0>; 1257 #power-domain-cells = <1>; 1258 }; 1259 1260 spmi_bus: spmi@c440000 { 1261 compatible = "qcom,spmi-pmic-arb"; 1262 reg = <0 0x0c440000 0 0x1100>, 1263 <0 0x0c600000 0 0x2000000>, 1264 <0 0x0e600000 0 0x100000>, 1265 <0 0x0e700000 0 0xa0000>, 1266 <0 0x0c40a000 0 0x26000>; 1267 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1268 interrupt-names = "periph_irq"; 1269 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1270 qcom,ee = <0>; 1271 qcom,channel = <0>; 1272 #address-cells = <1>; 1273 #size-cells = <1>; 1274 interrupt-controller; 1275 #interrupt-cells = <4>; 1276 }; 1277 1278 tlmm: pinctrl@f100000 { 1279 compatible = "qcom,sc7280-pinctrl"; 1280 reg = <0 0x0f100000 0 0x300000>; 1281 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1282 gpio-controller; 1283 #gpio-cells = <2>; 1284 interrupt-controller; 1285 #interrupt-cells = <2>; 1286 gpio-ranges = <&tlmm 0 0 175>; 1287 wakeup-parent = <&pdc>; 1288 1289 qup_uart5_default: qup-uart5-default { 1290 pins = "gpio46", "gpio47"; 1291 function = "qup13"; 1292 }; 1293 1294 sdc1_on: sdc1-on { 1295 clk { 1296 pins = "sdc1_clk"; 1297 }; 1298 1299 cmd { 1300 pins = "sdc1_cmd"; 1301 }; 1302 1303 data { 1304 pins = "sdc1_data"; 1305 }; 1306 1307 rclk { 1308 pins = "sdc1_rclk"; 1309 }; 1310 }; 1311 1312 sdc1_off: sdc1-off { 1313 clk { 1314 pins = "sdc1_clk"; 1315 drive-strength = <2>; 1316 bias-bus-hold; 1317 }; 1318 1319 cmd { 1320 pins = "sdc1_cmd"; 1321 drive-strength = <2>; 1322 bias-bus-hold; 1323 }; 1324 1325 data { 1326 pins = "sdc1_data"; 1327 drive-strength = <2>; 1328 bias-bus-hold; 1329 }; 1330 1331 rclk { 1332 pins = "sdc1_rclk"; 1333 bias-bus-hold; 1334 }; 1335 }; 1336 1337 sdc2_on: sdc2-on { 1338 clk { 1339 pins = "sdc2_clk"; 1340 }; 1341 1342 cmd { 1343 pins = "sdc2_cmd"; 1344 }; 1345 1346 data { 1347 pins = "sdc2_data"; 1348 }; 1349 1350 sd-cd { 1351 pins = "gpio91"; 1352 }; 1353 }; 1354 1355 sdc2_off: sdc2-off { 1356 clk { 1357 pins = "sdc2_clk"; 1358 drive-strength = <2>; 1359 bias-bus-hold; 1360 }; 1361 1362 cmd { 1363 pins ="sdc2_cmd"; 1364 drive-strength = <2>; 1365 bias-bus-hold; 1366 }; 1367 1368 data { 1369 pins ="sdc2_data"; 1370 drive-strength = <2>; 1371 bias-bus-hold; 1372 }; 1373 }; 1374 }; 1375 1376 apps_smmu: iommu@15000000 { 1377 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 1378 reg = <0 0x15000000 0 0x100000>; 1379 #iommu-cells = <2>; 1380 #global-interrupts = <1>; 1381 dma-coherent; 1382 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1385 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1386 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1387 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1388 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1389 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1390 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1391 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1392 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1393 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1394 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1395 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1398 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1400 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1401 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1402 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1403 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1409 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1410 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1411 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1412 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1413 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1414 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1415 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1416 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1417 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1418 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1420 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1436 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1437 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1438 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1439 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1440 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1463 }; 1464 1465 intc: interrupt-controller@17a00000 { 1466 compatible = "arm,gic-v3"; 1467 #address-cells = <2>; 1468 #size-cells = <2>; 1469 ranges; 1470 #interrupt-cells = <3>; 1471 interrupt-controller; 1472 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 1473 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 1474 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 1475 1476 gic-its@17a40000 { 1477 compatible = "arm,gic-v3-its"; 1478 msi-controller; 1479 #msi-cells = <1>; 1480 reg = <0 0x17a40000 0 0x20000>; 1481 status = "disabled"; 1482 }; 1483 }; 1484 1485 watchdog@17c10000 { 1486 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 1487 reg = <0 0x17c10000 0 0x1000>; 1488 clocks = <&sleep_clk>; 1489 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1490 }; 1491 1492 timer@17c20000 { 1493 #address-cells = <2>; 1494 #size-cells = <2>; 1495 ranges; 1496 compatible = "arm,armv7-timer-mem"; 1497 reg = <0 0x17c20000 0 0x1000>; 1498 1499 frame@17c21000 { 1500 frame-number = <0>; 1501 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1503 reg = <0 0x17c21000 0 0x1000>, 1504 <0 0x17c22000 0 0x1000>; 1505 }; 1506 1507 frame@17c23000 { 1508 frame-number = <1>; 1509 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1510 reg = <0 0x17c23000 0 0x1000>; 1511 status = "disabled"; 1512 }; 1513 1514 frame@17c25000 { 1515 frame-number = <2>; 1516 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1517 reg = <0 0x17c25000 0 0x1000>; 1518 status = "disabled"; 1519 }; 1520 1521 frame@17c27000 { 1522 frame-number = <3>; 1523 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1524 reg = <0 0x17c27000 0 0x1000>; 1525 status = "disabled"; 1526 }; 1527 1528 frame@17c29000 { 1529 frame-number = <4>; 1530 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1531 reg = <0 0x17c29000 0 0x1000>; 1532 status = "disabled"; 1533 }; 1534 1535 frame@17c2b000 { 1536 frame-number = <5>; 1537 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1538 reg = <0 0x17c2b000 0 0x1000>; 1539 status = "disabled"; 1540 }; 1541 1542 frame@17c2d000 { 1543 frame-number = <6>; 1544 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1545 reg = <0 0x17c2d000 0 0x1000>; 1546 status = "disabled"; 1547 }; 1548 }; 1549 1550 apps_rsc: rsc@18200000 { 1551 compatible = "qcom,rpmh-rsc"; 1552 reg = <0 0x18200000 0 0x10000>, 1553 <0 0x18210000 0 0x10000>, 1554 <0 0x18220000 0 0x10000>; 1555 reg-names = "drv-0", "drv-1", "drv-2"; 1556 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1559 qcom,tcs-offset = <0xd00>; 1560 qcom,drv-id = <2>; 1561 qcom,tcs-config = <ACTIVE_TCS 2>, 1562 <SLEEP_TCS 3>, 1563 <WAKE_TCS 3>, 1564 <CONTROL_TCS 1>; 1565 1566 apps_bcm_voter: bcm-voter { 1567 compatible = "qcom,bcm-voter"; 1568 }; 1569 1570 rpmhpd: power-controller { 1571 compatible = "qcom,sc7280-rpmhpd"; 1572 #power-domain-cells = <1>; 1573 operating-points-v2 = <&rpmhpd_opp_table>; 1574 1575 rpmhpd_opp_table: opp-table { 1576 compatible = "operating-points-v2"; 1577 1578 rpmhpd_opp_ret: opp1 { 1579 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1580 }; 1581 1582 rpmhpd_opp_low_svs: opp2 { 1583 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1584 }; 1585 1586 rpmhpd_opp_svs: opp3 { 1587 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1588 }; 1589 1590 rpmhpd_opp_svs_l1: opp4 { 1591 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1592 }; 1593 1594 rpmhpd_opp_svs_l2: opp5 { 1595 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1596 }; 1597 1598 rpmhpd_opp_nom: opp6 { 1599 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1600 }; 1601 1602 rpmhpd_opp_nom_l1: opp7 { 1603 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1604 }; 1605 1606 rpmhpd_opp_turbo: opp8 { 1607 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1608 }; 1609 1610 rpmhpd_opp_turbo_l1: opp9 { 1611 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1612 }; 1613 }; 1614 }; 1615 1616 rpmhcc: clock-controller { 1617 compatible = "qcom,sc7280-rpmh-clk"; 1618 clocks = <&xo_board>; 1619 clock-names = "xo"; 1620 #clock-cells = <1>; 1621 }; 1622 }; 1623 1624 cpufreq_hw: cpufreq@18591000 { 1625 compatible = "qcom,cpufreq-epss"; 1626 reg = <0 0x18591000 0 0x1000>, 1627 <0 0x18592000 0 0x1000>, 1628 <0 0x18593000 0 0x1000>; 1629 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 1630 clock-names = "xo", "alternate"; 1631 #freq-domain-cells = <1>; 1632 }; 1633 }; 1634 1635 thermal_zones: thermal-zones { 1636 cpu0-thermal { 1637 polling-delay-passive = <250>; 1638 polling-delay = <0>; 1639 1640 thermal-sensors = <&tsens0 1>; 1641 1642 trips { 1643 cpu0_alert0: trip-point0 { 1644 temperature = <90000>; 1645 hysteresis = <2000>; 1646 type = "passive"; 1647 }; 1648 1649 cpu0_alert1: trip-point1 { 1650 temperature = <95000>; 1651 hysteresis = <2000>; 1652 type = "passive"; 1653 }; 1654 1655 cpu0_crit: cpu-crit { 1656 temperature = <110000>; 1657 hysteresis = <0>; 1658 type = "critical"; 1659 }; 1660 }; 1661 1662 cooling-maps { 1663 map0 { 1664 trip = <&cpu0_alert0>; 1665 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1666 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1667 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1668 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1669 }; 1670 map1 { 1671 trip = <&cpu0_alert1>; 1672 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1673 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1674 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1675 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1676 }; 1677 }; 1678 }; 1679 1680 cpu1-thermal { 1681 polling-delay-passive = <250>; 1682 polling-delay = <0>; 1683 1684 thermal-sensors = <&tsens0 2>; 1685 1686 trips { 1687 cpu1_alert0: trip-point0 { 1688 temperature = <90000>; 1689 hysteresis = <2000>; 1690 type = "passive"; 1691 }; 1692 1693 cpu1_alert1: trip-point1 { 1694 temperature = <95000>; 1695 hysteresis = <2000>; 1696 type = "passive"; 1697 }; 1698 1699 cpu1_crit: cpu-crit { 1700 temperature = <110000>; 1701 hysteresis = <0>; 1702 type = "critical"; 1703 }; 1704 }; 1705 1706 cooling-maps { 1707 map0 { 1708 trip = <&cpu1_alert0>; 1709 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1710 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1711 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1712 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1713 }; 1714 map1 { 1715 trip = <&cpu1_alert1>; 1716 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1717 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1718 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1719 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1720 }; 1721 }; 1722 }; 1723 1724 cpu2-thermal { 1725 polling-delay-passive = <250>; 1726 polling-delay = <0>; 1727 1728 thermal-sensors = <&tsens0 3>; 1729 1730 trips { 1731 cpu2_alert0: trip-point0 { 1732 temperature = <90000>; 1733 hysteresis = <2000>; 1734 type = "passive"; 1735 }; 1736 1737 cpu2_alert1: trip-point1 { 1738 temperature = <95000>; 1739 hysteresis = <2000>; 1740 type = "passive"; 1741 }; 1742 1743 cpu2_crit: cpu-crit { 1744 temperature = <110000>; 1745 hysteresis = <0>; 1746 type = "critical"; 1747 }; 1748 }; 1749 1750 cooling-maps { 1751 map0 { 1752 trip = <&cpu2_alert0>; 1753 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1754 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1755 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1756 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1757 }; 1758 map1 { 1759 trip = <&cpu2_alert1>; 1760 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1761 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1762 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1763 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1764 }; 1765 }; 1766 }; 1767 1768 cpu3-thermal { 1769 polling-delay-passive = <250>; 1770 polling-delay = <0>; 1771 1772 thermal-sensors = <&tsens0 4>; 1773 1774 trips { 1775 cpu3_alert0: trip-point0 { 1776 temperature = <90000>; 1777 hysteresis = <2000>; 1778 type = "passive"; 1779 }; 1780 1781 cpu3_alert1: trip-point1 { 1782 temperature = <95000>; 1783 hysteresis = <2000>; 1784 type = "passive"; 1785 }; 1786 1787 cpu3_crit: cpu-crit { 1788 temperature = <110000>; 1789 hysteresis = <0>; 1790 type = "critical"; 1791 }; 1792 }; 1793 1794 cooling-maps { 1795 map0 { 1796 trip = <&cpu3_alert0>; 1797 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1798 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1799 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1800 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1801 }; 1802 map1 { 1803 trip = <&cpu3_alert1>; 1804 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1805 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1806 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1807 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1808 }; 1809 }; 1810 }; 1811 1812 cpu4-thermal { 1813 polling-delay-passive = <250>; 1814 polling-delay = <0>; 1815 1816 thermal-sensors = <&tsens0 7>; 1817 1818 trips { 1819 cpu4_alert0: trip-point0 { 1820 temperature = <90000>; 1821 hysteresis = <2000>; 1822 type = "passive"; 1823 }; 1824 1825 cpu4_alert1: trip-point1 { 1826 temperature = <95000>; 1827 hysteresis = <2000>; 1828 type = "passive"; 1829 }; 1830 1831 cpu4_crit: cpu-crit { 1832 temperature = <110000>; 1833 hysteresis = <0>; 1834 type = "critical"; 1835 }; 1836 }; 1837 1838 cooling-maps { 1839 map0 { 1840 trip = <&cpu4_alert0>; 1841 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1842 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1843 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1844 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1845 }; 1846 map1 { 1847 trip = <&cpu4_alert1>; 1848 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1849 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1850 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1851 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1852 }; 1853 }; 1854 }; 1855 1856 cpu5-thermal { 1857 polling-delay-passive = <250>; 1858 polling-delay = <0>; 1859 1860 thermal-sensors = <&tsens0 8>; 1861 1862 trips { 1863 cpu5_alert0: trip-point0 { 1864 temperature = <90000>; 1865 hysteresis = <2000>; 1866 type = "passive"; 1867 }; 1868 1869 cpu5_alert1: trip-point1 { 1870 temperature = <95000>; 1871 hysteresis = <2000>; 1872 type = "passive"; 1873 }; 1874 1875 cpu5_crit: cpu-crit { 1876 temperature = <110000>; 1877 hysteresis = <0>; 1878 type = "critical"; 1879 }; 1880 }; 1881 1882 cooling-maps { 1883 map0 { 1884 trip = <&cpu5_alert0>; 1885 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1886 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1887 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1888 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1889 }; 1890 map1 { 1891 trip = <&cpu5_alert1>; 1892 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1893 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1894 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1895 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1896 }; 1897 }; 1898 }; 1899 1900 cpu6-thermal { 1901 polling-delay-passive = <250>; 1902 polling-delay = <0>; 1903 1904 thermal-sensors = <&tsens0 9>; 1905 1906 trips { 1907 cpu6_alert0: trip-point0 { 1908 temperature = <90000>; 1909 hysteresis = <2000>; 1910 type = "passive"; 1911 }; 1912 1913 cpu6_alert1: trip-point1 { 1914 temperature = <95000>; 1915 hysteresis = <2000>; 1916 type = "passive"; 1917 }; 1918 1919 cpu6_crit: cpu-crit { 1920 temperature = <110000>; 1921 hysteresis = <0>; 1922 type = "critical"; 1923 }; 1924 }; 1925 1926 cooling-maps { 1927 map0 { 1928 trip = <&cpu6_alert0>; 1929 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1930 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1931 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1932 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1933 }; 1934 map1 { 1935 trip = <&cpu6_alert1>; 1936 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1937 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1938 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1939 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1940 }; 1941 }; 1942 }; 1943 1944 cpu7-thermal { 1945 polling-delay-passive = <250>; 1946 polling-delay = <0>; 1947 1948 thermal-sensors = <&tsens0 10>; 1949 1950 trips { 1951 cpu7_alert0: trip-point0 { 1952 temperature = <90000>; 1953 hysteresis = <2000>; 1954 type = "passive"; 1955 }; 1956 1957 cpu7_alert1: trip-point1 { 1958 temperature = <95000>; 1959 hysteresis = <2000>; 1960 type = "passive"; 1961 }; 1962 1963 cpu7_crit: cpu-crit { 1964 temperature = <110000>; 1965 hysteresis = <0>; 1966 type = "critical"; 1967 }; 1968 }; 1969 1970 cooling-maps { 1971 map0 { 1972 trip = <&cpu7_alert0>; 1973 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1974 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1975 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1976 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1977 }; 1978 map1 { 1979 trip = <&cpu7_alert1>; 1980 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1981 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1982 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1983 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1984 }; 1985 }; 1986 }; 1987 1988 cpu8-thermal { 1989 polling-delay-passive = <250>; 1990 polling-delay = <0>; 1991 1992 thermal-sensors = <&tsens0 11>; 1993 1994 trips { 1995 cpu8_alert0: trip-point0 { 1996 temperature = <90000>; 1997 hysteresis = <2000>; 1998 type = "passive"; 1999 }; 2000 2001 cpu8_alert1: trip-point1 { 2002 temperature = <95000>; 2003 hysteresis = <2000>; 2004 type = "passive"; 2005 }; 2006 2007 cpu8_crit: cpu-crit { 2008 temperature = <110000>; 2009 hysteresis = <0>; 2010 type = "critical"; 2011 }; 2012 }; 2013 2014 cooling-maps { 2015 map0 { 2016 trip = <&cpu8_alert0>; 2017 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2018 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2019 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2020 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2021 }; 2022 map1 { 2023 trip = <&cpu8_alert1>; 2024 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2025 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2026 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2027 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2028 }; 2029 }; 2030 }; 2031 2032 cpu9-thermal { 2033 polling-delay-passive = <250>; 2034 polling-delay = <0>; 2035 2036 thermal-sensors = <&tsens0 12>; 2037 2038 trips { 2039 cpu9_alert0: trip-point0 { 2040 temperature = <90000>; 2041 hysteresis = <2000>; 2042 type = "passive"; 2043 }; 2044 2045 cpu9_alert1: trip-point1 { 2046 temperature = <95000>; 2047 hysteresis = <2000>; 2048 type = "passive"; 2049 }; 2050 2051 cpu9_crit: cpu-crit { 2052 temperature = <110000>; 2053 hysteresis = <0>; 2054 type = "critical"; 2055 }; 2056 }; 2057 2058 cooling-maps { 2059 map0 { 2060 trip = <&cpu9_alert0>; 2061 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2062 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2063 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2064 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2065 }; 2066 map1 { 2067 trip = <&cpu9_alert1>; 2068 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2069 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2070 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2071 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2072 }; 2073 }; 2074 }; 2075 2076 cpu10-thermal { 2077 polling-delay-passive = <250>; 2078 polling-delay = <0>; 2079 2080 thermal-sensors = <&tsens0 13>; 2081 2082 trips { 2083 cpu10_alert0: trip-point0 { 2084 temperature = <90000>; 2085 hysteresis = <2000>; 2086 type = "passive"; 2087 }; 2088 2089 cpu10_alert1: trip-point1 { 2090 temperature = <95000>; 2091 hysteresis = <2000>; 2092 type = "passive"; 2093 }; 2094 2095 cpu10_crit: cpu-crit { 2096 temperature = <110000>; 2097 hysteresis = <0>; 2098 type = "critical"; 2099 }; 2100 }; 2101 2102 cooling-maps { 2103 map0 { 2104 trip = <&cpu10_alert0>; 2105 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2106 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2107 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2108 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2109 }; 2110 map1 { 2111 trip = <&cpu10_alert1>; 2112 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2113 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2114 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2115 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2116 }; 2117 }; 2118 }; 2119 2120 cpu11-thermal { 2121 polling-delay-passive = <250>; 2122 polling-delay = <0>; 2123 2124 thermal-sensors = <&tsens0 14>; 2125 2126 trips { 2127 cpu11_alert0: trip-point0 { 2128 temperature = <90000>; 2129 hysteresis = <2000>; 2130 type = "passive"; 2131 }; 2132 2133 cpu11_alert1: trip-point1 { 2134 temperature = <95000>; 2135 hysteresis = <2000>; 2136 type = "passive"; 2137 }; 2138 2139 cpu11_crit: cpu-crit { 2140 temperature = <110000>; 2141 hysteresis = <0>; 2142 type = "critical"; 2143 }; 2144 }; 2145 2146 cooling-maps { 2147 map0 { 2148 trip = <&cpu11_alert0>; 2149 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2150 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2151 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2152 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2153 }; 2154 map1 { 2155 trip = <&cpu11_alert1>; 2156 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2157 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2158 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2159 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2160 }; 2161 }; 2162 }; 2163 2164 aoss0-thermal { 2165 polling-delay-passive = <0>; 2166 polling-delay = <0>; 2167 2168 thermal-sensors = <&tsens0 0>; 2169 2170 trips { 2171 aoss0_alert0: trip-point0 { 2172 temperature = <90000>; 2173 hysteresis = <2000>; 2174 type = "hot"; 2175 }; 2176 2177 aoss0_crit: aoss0-crit { 2178 temperature = <110000>; 2179 hysteresis = <0>; 2180 type = "critical"; 2181 }; 2182 }; 2183 }; 2184 2185 aoss1-thermal { 2186 polling-delay-passive = <0>; 2187 polling-delay = <0>; 2188 2189 thermal-sensors = <&tsens1 0>; 2190 2191 trips { 2192 aoss1_alert0: trip-point0 { 2193 temperature = <90000>; 2194 hysteresis = <2000>; 2195 type = "hot"; 2196 }; 2197 2198 aoss1_crit: aoss1-crit { 2199 temperature = <110000>; 2200 hysteresis = <0>; 2201 type = "critical"; 2202 }; 2203 }; 2204 }; 2205 2206 cpuss0-thermal { 2207 polling-delay-passive = <0>; 2208 polling-delay = <0>; 2209 2210 thermal-sensors = <&tsens0 5>; 2211 2212 trips { 2213 cpuss0_alert0: trip-point0 { 2214 temperature = <90000>; 2215 hysteresis = <2000>; 2216 type = "hot"; 2217 }; 2218 cpuss0_crit: cluster0-crit { 2219 temperature = <110000>; 2220 hysteresis = <0>; 2221 type = "critical"; 2222 }; 2223 }; 2224 }; 2225 2226 cpuss1-thermal { 2227 polling-delay-passive = <0>; 2228 polling-delay = <0>; 2229 2230 thermal-sensors = <&tsens0 6>; 2231 2232 trips { 2233 cpuss1_alert0: trip-point0 { 2234 temperature = <90000>; 2235 hysteresis = <2000>; 2236 type = "hot"; 2237 }; 2238 cpuss1_crit: cluster0-crit { 2239 temperature = <110000>; 2240 hysteresis = <0>; 2241 type = "critical"; 2242 }; 2243 }; 2244 }; 2245 2246 gpuss0-thermal { 2247 polling-delay-passive = <0>; 2248 polling-delay = <0>; 2249 2250 thermal-sensors = <&tsens1 1>; 2251 2252 trips { 2253 gpuss0_alert0: trip-point0 { 2254 temperature = <90000>; 2255 hysteresis = <2000>; 2256 type = "hot"; 2257 }; 2258 2259 gpuss0_crit: gpuss0-crit { 2260 temperature = <110000>; 2261 hysteresis = <0>; 2262 type = "critical"; 2263 }; 2264 }; 2265 }; 2266 2267 gpuss1-thermal { 2268 polling-delay-passive = <0>; 2269 polling-delay = <0>; 2270 2271 thermal-sensors = <&tsens1 2>; 2272 2273 trips { 2274 gpuss1_alert0: trip-point0 { 2275 temperature = <90000>; 2276 hysteresis = <2000>; 2277 type = "hot"; 2278 }; 2279 2280 gpuss1_crit: gpuss1-crit { 2281 temperature = <110000>; 2282 hysteresis = <0>; 2283 type = "critical"; 2284 }; 2285 }; 2286 }; 2287 2288 nspss0-thermal { 2289 polling-delay-passive = <0>; 2290 polling-delay = <0>; 2291 2292 thermal-sensors = <&tsens1 3>; 2293 2294 trips { 2295 nspss0_alert0: trip-point0 { 2296 temperature = <90000>; 2297 hysteresis = <2000>; 2298 type = "hot"; 2299 }; 2300 2301 nspss0_crit: nspss0-crit { 2302 temperature = <110000>; 2303 hysteresis = <0>; 2304 type = "critical"; 2305 }; 2306 }; 2307 }; 2308 2309 nspss1-thermal { 2310 polling-delay-passive = <0>; 2311 polling-delay = <0>; 2312 2313 thermal-sensors = <&tsens1 4>; 2314 2315 trips { 2316 nspss1_alert0: trip-point0 { 2317 temperature = <90000>; 2318 hysteresis = <2000>; 2319 type = "hot"; 2320 }; 2321 2322 nspss1_crit: nspss1-crit { 2323 temperature = <110000>; 2324 hysteresis = <0>; 2325 type = "critical"; 2326 }; 2327 }; 2328 }; 2329 2330 video-thermal { 2331 polling-delay-passive = <0>; 2332 polling-delay = <0>; 2333 2334 thermal-sensors = <&tsens1 5>; 2335 2336 trips { 2337 video_alert0: trip-point0 { 2338 temperature = <90000>; 2339 hysteresis = <2000>; 2340 type = "hot"; 2341 }; 2342 2343 video_crit: video-crit { 2344 temperature = <110000>; 2345 hysteresis = <0>; 2346 type = "critical"; 2347 }; 2348 }; 2349 }; 2350 2351 ddr-thermal { 2352 polling-delay-passive = <0>; 2353 polling-delay = <0>; 2354 2355 thermal-sensors = <&tsens1 6>; 2356 2357 trips { 2358 ddr_alert0: trip-point0 { 2359 temperature = <90000>; 2360 hysteresis = <2000>; 2361 type = "hot"; 2362 }; 2363 2364 ddr_crit: ddr-crit { 2365 temperature = <110000>; 2366 hysteresis = <0>; 2367 type = "critical"; 2368 }; 2369 }; 2370 }; 2371 2372 mdmss0-thermal { 2373 polling-delay-passive = <0>; 2374 polling-delay = <0>; 2375 2376 thermal-sensors = <&tsens1 7>; 2377 2378 trips { 2379 mdmss0_alert0: trip-point0 { 2380 temperature = <90000>; 2381 hysteresis = <2000>; 2382 type = "hot"; 2383 }; 2384 2385 mdmss0_crit: mdmss0-crit { 2386 temperature = <110000>; 2387 hysteresis = <0>; 2388 type = "critical"; 2389 }; 2390 }; 2391 }; 2392 2393 mdmss1-thermal { 2394 polling-delay-passive = <0>; 2395 polling-delay = <0>; 2396 2397 thermal-sensors = <&tsens1 8>; 2398 2399 trips { 2400 mdmss1_alert0: trip-point0 { 2401 temperature = <90000>; 2402 hysteresis = <2000>; 2403 type = "hot"; 2404 }; 2405 2406 mdmss1_crit: mdmss1-crit { 2407 temperature = <110000>; 2408 hysteresis = <0>; 2409 type = "critical"; 2410 }; 2411 }; 2412 }; 2413 2414 mdmss2-thermal { 2415 polling-delay-passive = <0>; 2416 polling-delay = <0>; 2417 2418 thermal-sensors = <&tsens1 9>; 2419 2420 trips { 2421 mdmss2_alert0: trip-point0 { 2422 temperature = <90000>; 2423 hysteresis = <2000>; 2424 type = "hot"; 2425 }; 2426 2427 mdmss2_crit: mdmss2-crit { 2428 temperature = <110000>; 2429 hysteresis = <0>; 2430 type = "critical"; 2431 }; 2432 }; 2433 }; 2434 2435 mdmss3-thermal { 2436 polling-delay-passive = <0>; 2437 polling-delay = <0>; 2438 2439 thermal-sensors = <&tsens1 10>; 2440 2441 trips { 2442 mdmss3_alert0: trip-point0 { 2443 temperature = <90000>; 2444 hysteresis = <2000>; 2445 type = "hot"; 2446 }; 2447 2448 mdmss3_crit: mdmss3-crit { 2449 temperature = <110000>; 2450 hysteresis = <0>; 2451 type = "critical"; 2452 }; 2453 }; 2454 }; 2455 2456 camera0-thermal { 2457 polling-delay-passive = <0>; 2458 polling-delay = <0>; 2459 2460 thermal-sensors = <&tsens1 11>; 2461 2462 trips { 2463 camera0_alert0: trip-point0 { 2464 temperature = <90000>; 2465 hysteresis = <2000>; 2466 type = "hot"; 2467 }; 2468 2469 camera0_crit: camera0-crit { 2470 temperature = <110000>; 2471 hysteresis = <0>; 2472 type = "critical"; 2473 }; 2474 }; 2475 }; 2476 }; 2477 2478 timer { 2479 compatible = "arm,armv8-timer"; 2480 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 2481 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 2482 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 2483 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 2484 }; 2485}; 2486