1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-sc7280.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/mailbox/qcom-ipcc.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13#include <dt-bindings/soc/qcom,rpmh-rsc.h> 14 15/ { 16 interrupt-parent = <&intc>; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { }; 22 23 clocks { 24 xo_board: xo-board { 25 compatible = "fixed-clock"; 26 clock-frequency = <76800000>; 27 #clock-cells = <0>; 28 }; 29 30 sleep_clk: sleep-clk { 31 compatible = "fixed-clock"; 32 clock-frequency = <32000>; 33 #clock-cells = <0>; 34 }; 35 }; 36 37 reserved-memory { 38 #address-cells = <2>; 39 #size-cells = <2>; 40 ranges; 41 42 aop_mem: memory@80800000 { 43 reg = <0x0 0x80800000 0x0 0x60000>; 44 no-map; 45 }; 46 47 aop_cmd_db_mem: memory@80860000 { 48 reg = <0x0 0x80860000 0x0 0x20000>; 49 compatible = "qcom,cmd-db"; 50 no-map; 51 }; 52 53 cpucp_mem: memory@80b00000 { 54 no-map; 55 reg = <0x0 0x80b00000 0x0 0x100000>; 56 }; 57 }; 58 59 cpus { 60 #address-cells = <2>; 61 #size-cells = <0>; 62 63 CPU0: cpu@0 { 64 device_type = "cpu"; 65 compatible = "arm,kryo"; 66 reg = <0x0 0x0>; 67 enable-method = "psci"; 68 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 69 &LITTLE_CPU_SLEEP_1 70 &CLUSTER_SLEEP_0>; 71 next-level-cache = <&L2_0>; 72 L2_0: l2-cache { 73 compatible = "cache"; 74 next-level-cache = <&L3_0>; 75 L3_0: l3-cache { 76 compatible = "cache"; 77 }; 78 }; 79 }; 80 81 CPU1: cpu@100 { 82 device_type = "cpu"; 83 compatible = "arm,kryo"; 84 reg = <0x0 0x100>; 85 enable-method = "psci"; 86 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 87 &LITTLE_CPU_SLEEP_1 88 &CLUSTER_SLEEP_0>; 89 next-level-cache = <&L2_100>; 90 L2_100: l2-cache { 91 compatible = "cache"; 92 next-level-cache = <&L3_0>; 93 }; 94 }; 95 96 CPU2: cpu@200 { 97 device_type = "cpu"; 98 compatible = "arm,kryo"; 99 reg = <0x0 0x200>; 100 enable-method = "psci"; 101 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 102 &LITTLE_CPU_SLEEP_1 103 &CLUSTER_SLEEP_0>; 104 next-level-cache = <&L2_200>; 105 L2_200: l2-cache { 106 compatible = "cache"; 107 next-level-cache = <&L3_0>; 108 }; 109 }; 110 111 CPU3: cpu@300 { 112 device_type = "cpu"; 113 compatible = "arm,kryo"; 114 reg = <0x0 0x300>; 115 enable-method = "psci"; 116 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 117 &LITTLE_CPU_SLEEP_1 118 &CLUSTER_SLEEP_0>; 119 next-level-cache = <&L2_300>; 120 L2_300: l2-cache { 121 compatible = "cache"; 122 next-level-cache = <&L3_0>; 123 }; 124 }; 125 126 CPU4: cpu@400 { 127 device_type = "cpu"; 128 compatible = "arm,kryo"; 129 reg = <0x0 0x400>; 130 enable-method = "psci"; 131 cpu-idle-states = <&BIG_CPU_SLEEP_0 132 &BIG_CPU_SLEEP_1 133 &CLUSTER_SLEEP_0>; 134 next-level-cache = <&L2_400>; 135 L2_400: l2-cache { 136 compatible = "cache"; 137 next-level-cache = <&L3_0>; 138 }; 139 }; 140 141 CPU5: cpu@500 { 142 device_type = "cpu"; 143 compatible = "arm,kryo"; 144 reg = <0x0 0x500>; 145 enable-method = "psci"; 146 cpu-idle-states = <&BIG_CPU_SLEEP_0 147 &BIG_CPU_SLEEP_1 148 &CLUSTER_SLEEP_0>; 149 next-level-cache = <&L2_500>; 150 L2_500: l2-cache { 151 compatible = "cache"; 152 next-level-cache = <&L3_0>; 153 }; 154 }; 155 156 CPU6: cpu@600 { 157 device_type = "cpu"; 158 compatible = "arm,kryo"; 159 reg = <0x0 0x600>; 160 enable-method = "psci"; 161 cpu-idle-states = <&BIG_CPU_SLEEP_0 162 &BIG_CPU_SLEEP_1 163 &CLUSTER_SLEEP_0>; 164 next-level-cache = <&L2_600>; 165 L2_600: l2-cache { 166 compatible = "cache"; 167 next-level-cache = <&L3_0>; 168 }; 169 }; 170 171 CPU7: cpu@700 { 172 device_type = "cpu"; 173 compatible = "arm,kryo"; 174 reg = <0x0 0x700>; 175 enable-method = "psci"; 176 cpu-idle-states = <&BIG_CPU_SLEEP_0 177 &BIG_CPU_SLEEP_1 178 &CLUSTER_SLEEP_0>; 179 next-level-cache = <&L2_700>; 180 L2_700: l2-cache { 181 compatible = "cache"; 182 next-level-cache = <&L3_0>; 183 }; 184 }; 185 186 idle-states { 187 entry-method = "psci"; 188 189 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 190 compatible = "arm,idle-state"; 191 idle-state-name = "little-power-down"; 192 arm,psci-suspend-param = <0x40000003>; 193 entry-latency-us = <549>; 194 exit-latency-us = <901>; 195 min-residency-us = <1774>; 196 local-timer-stop; 197 }; 198 199 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 200 compatible = "arm,idle-state"; 201 idle-state-name = "little-rail-power-down"; 202 arm,psci-suspend-param = <0x40000004>; 203 entry-latency-us = <702>; 204 exit-latency-us = <915>; 205 min-residency-us = <4001>; 206 local-timer-stop; 207 }; 208 209 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 210 compatible = "arm,idle-state"; 211 idle-state-name = "big-power-down"; 212 arm,psci-suspend-param = <0x40000003>; 213 entry-latency-us = <523>; 214 exit-latency-us = <1244>; 215 min-residency-us = <2207>; 216 local-timer-stop; 217 }; 218 219 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 220 compatible = "arm,idle-state"; 221 idle-state-name = "big-rail-power-down"; 222 arm,psci-suspend-param = <0x40000004>; 223 entry-latency-us = <526>; 224 exit-latency-us = <1854>; 225 min-residency-us = <5555>; 226 local-timer-stop; 227 }; 228 229 CLUSTER_SLEEP_0: cluster-sleep-0 { 230 compatible = "arm,idle-state"; 231 idle-state-name = "cluster-power-down"; 232 arm,psci-suspend-param = <0x40003444>; 233 entry-latency-us = <3263>; 234 exit-latency-us = <6562>; 235 min-residency-us = <9926>; 236 local-timer-stop; 237 }; 238 }; 239 }; 240 241 memory@80000000 { 242 device_type = "memory"; 243 /* We expect the bootloader to fill in the size */ 244 reg = <0 0x80000000 0 0>; 245 }; 246 247 firmware { 248 scm { 249 compatible = "qcom,scm-sc7280", "qcom,scm"; 250 }; 251 }; 252 253 pmu { 254 compatible = "arm,armv8-pmuv3"; 255 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 256 }; 257 258 psci { 259 compatible = "arm,psci-1.0"; 260 method = "smc"; 261 }; 262 263 soc: soc@0 { 264 #address-cells = <2>; 265 #size-cells = <2>; 266 ranges = <0 0 0 0 0x10 0>; 267 dma-ranges = <0 0 0 0 0x10 0>; 268 compatible = "simple-bus"; 269 270 gcc: clock-controller@100000 { 271 compatible = "qcom,gcc-sc7280"; 272 reg = <0 0x00100000 0 0x1f0000>; 273 clocks = <&rpmhcc RPMH_CXO_CLK>, 274 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 275 <0>, <0>, <0>, <0>, <0>, <0>; 276 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 277 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 278 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 279 "ufs_phy_tx_symbol_0_clk", 280 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 281 #clock-cells = <1>; 282 #reset-cells = <1>; 283 #power-domain-cells = <1>; 284 }; 285 286 ipcc: mailbox@408000 { 287 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 288 reg = <0 0x00408000 0 0x1000>; 289 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 290 interrupt-controller; 291 #interrupt-cells = <3>; 292 #mbox-cells = <2>; 293 }; 294 295 qupv3_id_0: geniqup@9c0000 { 296 compatible = "qcom,geni-se-qup"; 297 reg = <0 0x009c0000 0 0x2000>; 298 clock-names = "m-ahb", "s-ahb"; 299 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 300 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 301 #address-cells = <2>; 302 #size-cells = <2>; 303 ranges; 304 status = "disabled"; 305 306 uart5: serial@994000 { 307 compatible = "qcom,geni-debug-uart"; 308 reg = <0 0x00994000 0 0x4000>; 309 clock-names = "se"; 310 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 311 pinctrl-names = "default"; 312 pinctrl-0 = <&qup_uart5_default>; 313 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 314 status = "disabled"; 315 }; 316 }; 317 318 system-cache-controller@9200000 { 319 compatible = "qcom,sc7280-llcc"; 320 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 321 reg-names = "llcc_base", "llcc_broadcast_base"; 322 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 323 }; 324 325 pdc: interrupt-controller@b220000 { 326 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 327 reg = <0 0x0b220000 0 0x30000>; 328 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 329 <55 306 4>, <59 312 3>, <62 374 2>, 330 <64 434 2>, <66 438 3>, <69 86 1>, 331 <70 520 54>, <124 609 31>, <155 63 1>, 332 <156 716 12>; 333 #interrupt-cells = <2>; 334 interrupt-parent = <&intc>; 335 interrupt-controller; 336 }; 337 338 spmi_bus: spmi@c440000 { 339 compatible = "qcom,spmi-pmic-arb"; 340 reg = <0 0x0c440000 0 0x1100>, 341 <0 0x0c600000 0 0x2000000>, 342 <0 0x0e600000 0 0x100000>, 343 <0 0x0e700000 0 0xa0000>, 344 <0 0x0c40a000 0 0x26000>; 345 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 346 interrupt-names = "periph_irq"; 347 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 348 qcom,ee = <0>; 349 qcom,channel = <0>; 350 #address-cells = <1>; 351 #size-cells = <1>; 352 interrupt-controller; 353 #interrupt-cells = <4>; 354 }; 355 356 tlmm: pinctrl@f100000 { 357 compatible = "qcom,sc7280-pinctrl"; 358 reg = <0 0x0f100000 0 0x300000>; 359 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 360 gpio-controller; 361 #gpio-cells = <2>; 362 interrupt-controller; 363 #interrupt-cells = <2>; 364 gpio-ranges = <&tlmm 0 0 175>; 365 wakeup-parent = <&pdc>; 366 367 qup_uart5_default: qup-uart5-default { 368 pins = "gpio46", "gpio47"; 369 function = "qup13"; 370 }; 371 }; 372 373 apps_smmu: iommu@15000000 { 374 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 375 reg = <0 0x15000000 0 0x100000>; 376 #iommu-cells = <2>; 377 #global-interrupts = <1>; 378 dma-coherent; 379 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 395 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 460 }; 461 462 intc: interrupt-controller@17a00000 { 463 compatible = "arm,gic-v3"; 464 #address-cells = <2>; 465 #size-cells = <2>; 466 ranges; 467 #interrupt-cells = <3>; 468 interrupt-controller; 469 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 470 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 471 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 472 473 gic-its@17a40000 { 474 compatible = "arm,gic-v3-its"; 475 msi-controller; 476 #msi-cells = <1>; 477 reg = <0 0x17a40000 0 0x20000>; 478 status = "disabled"; 479 }; 480 }; 481 482 watchdog@17c10000 { 483 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 484 reg = <0 0x17c10000 0 0x1000>; 485 clocks = <&sleep_clk>; 486 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 487 }; 488 489 timer@17c20000 { 490 #address-cells = <2>; 491 #size-cells = <2>; 492 ranges; 493 compatible = "arm,armv7-timer-mem"; 494 reg = <0 0x17c20000 0 0x1000>; 495 496 frame@17c21000 { 497 frame-number = <0>; 498 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 500 reg = <0 0x17c21000 0 0x1000>, 501 <0 0x17c22000 0 0x1000>; 502 }; 503 504 frame@17c23000 { 505 frame-number = <1>; 506 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 507 reg = <0 0x17c23000 0 0x1000>; 508 status = "disabled"; 509 }; 510 511 frame@17c25000 { 512 frame-number = <2>; 513 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 514 reg = <0 0x17c25000 0 0x1000>; 515 status = "disabled"; 516 }; 517 518 frame@17c27000 { 519 frame-number = <3>; 520 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 521 reg = <0 0x17c27000 0 0x1000>; 522 status = "disabled"; 523 }; 524 525 frame@17c29000 { 526 frame-number = <4>; 527 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 528 reg = <0 0x17c29000 0 0x1000>; 529 status = "disabled"; 530 }; 531 532 frame@17c2b000 { 533 frame-number = <5>; 534 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 535 reg = <0 0x17c2b000 0 0x1000>; 536 status = "disabled"; 537 }; 538 539 frame@17c2d000 { 540 frame-number = <6>; 541 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 542 reg = <0 0x17c2d000 0 0x1000>; 543 status = "disabled"; 544 }; 545 }; 546 547 apps_rsc: rsc@18200000 { 548 compatible = "qcom,rpmh-rsc"; 549 reg = <0 0x18200000 0 0x10000>, 550 <0 0x18210000 0 0x10000>, 551 <0 0x18220000 0 0x10000>; 552 reg-names = "drv-0", "drv-1", "drv-2"; 553 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 556 qcom,tcs-offset = <0xd00>; 557 qcom,drv-id = <2>; 558 qcom,tcs-config = <ACTIVE_TCS 2>, 559 <SLEEP_TCS 3>, 560 <WAKE_TCS 3>, 561 <CONTROL_TCS 1>; 562 563 rpmhpd: power-controller { 564 compatible = "qcom,sc7280-rpmhpd"; 565 #power-domain-cells = <1>; 566 operating-points-v2 = <&rpmhpd_opp_table>; 567 568 rpmhpd_opp_table: opp-table { 569 compatible = "operating-points-v2"; 570 571 rpmhpd_opp_ret: opp1 { 572 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 573 }; 574 575 rpmhpd_opp_low_svs: opp2 { 576 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 577 }; 578 579 rpmhpd_opp_svs: opp3 { 580 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 581 }; 582 583 rpmhpd_opp_svs_l1: opp4 { 584 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 585 }; 586 587 rpmhpd_opp_svs_l2: opp5 { 588 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 589 }; 590 591 rpmhpd_opp_nom: opp6 { 592 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 593 }; 594 595 rpmhpd_opp_nom_l1: opp7 { 596 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 597 }; 598 599 rpmhpd_opp_turbo: opp8 { 600 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 601 }; 602 603 rpmhpd_opp_turbo_l1: opp9 { 604 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 605 }; 606 }; 607 }; 608 609 rpmhcc: clock-controller { 610 compatible = "qcom,sc7280-rpmh-clk"; 611 clocks = <&xo_board>; 612 clock-names = "xo"; 613 #clock-cells = <1>; 614 }; 615 }; 616 }; 617 618 timer { 619 compatible = "arm,armv8-timer"; 620 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 621 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 622 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 623 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 624 }; 625}; 626