1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-sc7280.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/mailbox/qcom-ipcc.h> 12#include <dt-bindings/power/qcom-aoss-qmp.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/soc/qcom,rpmh-rsc.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 clock-frequency = <76800000>; 28 #clock-cells = <0>; 29 }; 30 31 sleep_clk: sleep-clk { 32 compatible = "fixed-clock"; 33 clock-frequency = <32000>; 34 #clock-cells = <0>; 35 }; 36 }; 37 38 reserved-memory { 39 #address-cells = <2>; 40 #size-cells = <2>; 41 ranges; 42 43 aop_mem: memory@80800000 { 44 reg = <0x0 0x80800000 0x0 0x60000>; 45 no-map; 46 }; 47 48 aop_cmd_db_mem: memory@80860000 { 49 reg = <0x0 0x80860000 0x0 0x20000>; 50 compatible = "qcom,cmd-db"; 51 no-map; 52 }; 53 54 cpucp_mem: memory@80b00000 { 55 no-map; 56 reg = <0x0 0x80b00000 0x0 0x100000>; 57 }; 58 }; 59 60 cpus { 61 #address-cells = <2>; 62 #size-cells = <0>; 63 64 CPU0: cpu@0 { 65 device_type = "cpu"; 66 compatible = "arm,kryo"; 67 reg = <0x0 0x0>; 68 enable-method = "psci"; 69 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 70 &LITTLE_CPU_SLEEP_1 71 &CLUSTER_SLEEP_0>; 72 next-level-cache = <&L2_0>; 73 L2_0: l2-cache { 74 compatible = "cache"; 75 next-level-cache = <&L3_0>; 76 L3_0: l3-cache { 77 compatible = "cache"; 78 }; 79 }; 80 }; 81 82 CPU1: cpu@100 { 83 device_type = "cpu"; 84 compatible = "arm,kryo"; 85 reg = <0x0 0x100>; 86 enable-method = "psci"; 87 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 88 &LITTLE_CPU_SLEEP_1 89 &CLUSTER_SLEEP_0>; 90 next-level-cache = <&L2_100>; 91 L2_100: l2-cache { 92 compatible = "cache"; 93 next-level-cache = <&L3_0>; 94 }; 95 }; 96 97 CPU2: cpu@200 { 98 device_type = "cpu"; 99 compatible = "arm,kryo"; 100 reg = <0x0 0x200>; 101 enable-method = "psci"; 102 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 103 &LITTLE_CPU_SLEEP_1 104 &CLUSTER_SLEEP_0>; 105 next-level-cache = <&L2_200>; 106 L2_200: l2-cache { 107 compatible = "cache"; 108 next-level-cache = <&L3_0>; 109 }; 110 }; 111 112 CPU3: cpu@300 { 113 device_type = "cpu"; 114 compatible = "arm,kryo"; 115 reg = <0x0 0x300>; 116 enable-method = "psci"; 117 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 118 &LITTLE_CPU_SLEEP_1 119 &CLUSTER_SLEEP_0>; 120 next-level-cache = <&L2_300>; 121 L2_300: l2-cache { 122 compatible = "cache"; 123 next-level-cache = <&L3_0>; 124 }; 125 }; 126 127 CPU4: cpu@400 { 128 device_type = "cpu"; 129 compatible = "arm,kryo"; 130 reg = <0x0 0x400>; 131 enable-method = "psci"; 132 cpu-idle-states = <&BIG_CPU_SLEEP_0 133 &BIG_CPU_SLEEP_1 134 &CLUSTER_SLEEP_0>; 135 next-level-cache = <&L2_400>; 136 L2_400: l2-cache { 137 compatible = "cache"; 138 next-level-cache = <&L3_0>; 139 }; 140 }; 141 142 CPU5: cpu@500 { 143 device_type = "cpu"; 144 compatible = "arm,kryo"; 145 reg = <0x0 0x500>; 146 enable-method = "psci"; 147 cpu-idle-states = <&BIG_CPU_SLEEP_0 148 &BIG_CPU_SLEEP_1 149 &CLUSTER_SLEEP_0>; 150 next-level-cache = <&L2_500>; 151 L2_500: l2-cache { 152 compatible = "cache"; 153 next-level-cache = <&L3_0>; 154 }; 155 }; 156 157 CPU6: cpu@600 { 158 device_type = "cpu"; 159 compatible = "arm,kryo"; 160 reg = <0x0 0x600>; 161 enable-method = "psci"; 162 cpu-idle-states = <&BIG_CPU_SLEEP_0 163 &BIG_CPU_SLEEP_1 164 &CLUSTER_SLEEP_0>; 165 next-level-cache = <&L2_600>; 166 L2_600: l2-cache { 167 compatible = "cache"; 168 next-level-cache = <&L3_0>; 169 }; 170 }; 171 172 CPU7: cpu@700 { 173 device_type = "cpu"; 174 compatible = "arm,kryo"; 175 reg = <0x0 0x700>; 176 enable-method = "psci"; 177 cpu-idle-states = <&BIG_CPU_SLEEP_0 178 &BIG_CPU_SLEEP_1 179 &CLUSTER_SLEEP_0>; 180 next-level-cache = <&L2_700>; 181 L2_700: l2-cache { 182 compatible = "cache"; 183 next-level-cache = <&L3_0>; 184 }; 185 }; 186 187 idle-states { 188 entry-method = "psci"; 189 190 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 191 compatible = "arm,idle-state"; 192 idle-state-name = "little-power-down"; 193 arm,psci-suspend-param = <0x40000003>; 194 entry-latency-us = <549>; 195 exit-latency-us = <901>; 196 min-residency-us = <1774>; 197 local-timer-stop; 198 }; 199 200 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 201 compatible = "arm,idle-state"; 202 idle-state-name = "little-rail-power-down"; 203 arm,psci-suspend-param = <0x40000004>; 204 entry-latency-us = <702>; 205 exit-latency-us = <915>; 206 min-residency-us = <4001>; 207 local-timer-stop; 208 }; 209 210 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 211 compatible = "arm,idle-state"; 212 idle-state-name = "big-power-down"; 213 arm,psci-suspend-param = <0x40000003>; 214 entry-latency-us = <523>; 215 exit-latency-us = <1244>; 216 min-residency-us = <2207>; 217 local-timer-stop; 218 }; 219 220 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 221 compatible = "arm,idle-state"; 222 idle-state-name = "big-rail-power-down"; 223 arm,psci-suspend-param = <0x40000004>; 224 entry-latency-us = <526>; 225 exit-latency-us = <1854>; 226 min-residency-us = <5555>; 227 local-timer-stop; 228 }; 229 230 CLUSTER_SLEEP_0: cluster-sleep-0 { 231 compatible = "arm,idle-state"; 232 idle-state-name = "cluster-power-down"; 233 arm,psci-suspend-param = <0x40003444>; 234 entry-latency-us = <3263>; 235 exit-latency-us = <6562>; 236 min-residency-us = <9926>; 237 local-timer-stop; 238 }; 239 }; 240 }; 241 242 memory@80000000 { 243 device_type = "memory"; 244 /* We expect the bootloader to fill in the size */ 245 reg = <0 0x80000000 0 0>; 246 }; 247 248 firmware { 249 scm { 250 compatible = "qcom,scm-sc7280", "qcom,scm"; 251 }; 252 }; 253 254 pmu { 255 compatible = "arm,armv8-pmuv3"; 256 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 257 }; 258 259 psci { 260 compatible = "arm,psci-1.0"; 261 method = "smc"; 262 }; 263 264 soc: soc@0 { 265 #address-cells = <2>; 266 #size-cells = <2>; 267 ranges = <0 0 0 0 0x10 0>; 268 dma-ranges = <0 0 0 0 0x10 0>; 269 compatible = "simple-bus"; 270 271 gcc: clock-controller@100000 { 272 compatible = "qcom,gcc-sc7280"; 273 reg = <0 0x00100000 0 0x1f0000>; 274 clocks = <&rpmhcc RPMH_CXO_CLK>, 275 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 276 <0>, <0>, <0>, <0>, <0>, <0>; 277 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 278 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 279 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 280 "ufs_phy_tx_symbol_0_clk", 281 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 282 #clock-cells = <1>; 283 #reset-cells = <1>; 284 #power-domain-cells = <1>; 285 }; 286 287 ipcc: mailbox@408000 { 288 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 289 reg = <0 0x00408000 0 0x1000>; 290 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 291 interrupt-controller; 292 #interrupt-cells = <3>; 293 #mbox-cells = <2>; 294 }; 295 296 qupv3_id_0: geniqup@9c0000 { 297 compatible = "qcom,geni-se-qup"; 298 reg = <0 0x009c0000 0 0x2000>; 299 clock-names = "m-ahb", "s-ahb"; 300 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 301 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 302 #address-cells = <2>; 303 #size-cells = <2>; 304 ranges; 305 status = "disabled"; 306 307 uart5: serial@994000 { 308 compatible = "qcom,geni-debug-uart"; 309 reg = <0 0x00994000 0 0x4000>; 310 clock-names = "se"; 311 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 312 pinctrl-names = "default"; 313 pinctrl-0 = <&qup_uart5_default>; 314 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 315 status = "disabled"; 316 }; 317 }; 318 319 system-cache-controller@9200000 { 320 compatible = "qcom,sc7280-llcc"; 321 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 322 reg-names = "llcc_base", "llcc_broadcast_base"; 323 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 324 }; 325 326 pdc: interrupt-controller@b220000 { 327 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 328 reg = <0 0x0b220000 0 0x30000>; 329 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 330 <55 306 4>, <59 312 3>, <62 374 2>, 331 <64 434 2>, <66 438 3>, <69 86 1>, 332 <70 520 54>, <124 609 31>, <155 63 1>, 333 <156 716 12>; 334 #interrupt-cells = <2>; 335 interrupt-parent = <&intc>; 336 interrupt-controller; 337 }; 338 339 aoss_qmp: power-controller@c300000 { 340 compatible = "qcom,sc7280-aoss-qmp"; 341 reg = <0 0x0c300000 0 0x100000>; 342 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 343 IPCC_MPROC_SIGNAL_GLINK_QMP 344 IRQ_TYPE_EDGE_RISING>; 345 mboxes = <&ipcc IPCC_CLIENT_AOP 346 IPCC_MPROC_SIGNAL_GLINK_QMP>; 347 348 #clock-cells = <0>; 349 #power-domain-cells = <1>; 350 }; 351 352 spmi_bus: spmi@c440000 { 353 compatible = "qcom,spmi-pmic-arb"; 354 reg = <0 0x0c440000 0 0x1100>, 355 <0 0x0c600000 0 0x2000000>, 356 <0 0x0e600000 0 0x100000>, 357 <0 0x0e700000 0 0xa0000>, 358 <0 0x0c40a000 0 0x26000>; 359 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 360 interrupt-names = "periph_irq"; 361 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 362 qcom,ee = <0>; 363 qcom,channel = <0>; 364 #address-cells = <1>; 365 #size-cells = <1>; 366 interrupt-controller; 367 #interrupt-cells = <4>; 368 }; 369 370 tlmm: pinctrl@f100000 { 371 compatible = "qcom,sc7280-pinctrl"; 372 reg = <0 0x0f100000 0 0x300000>; 373 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 374 gpio-controller; 375 #gpio-cells = <2>; 376 interrupt-controller; 377 #interrupt-cells = <2>; 378 gpio-ranges = <&tlmm 0 0 175>; 379 wakeup-parent = <&pdc>; 380 381 qup_uart5_default: qup-uart5-default { 382 pins = "gpio46", "gpio47"; 383 function = "qup13"; 384 }; 385 }; 386 387 apps_smmu: iommu@15000000 { 388 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 389 reg = <0 0x15000000 0 0x100000>; 390 #iommu-cells = <2>; 391 #global-interrupts = <1>; 392 dma-coherent; 393 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 395 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 474 }; 475 476 intc: interrupt-controller@17a00000 { 477 compatible = "arm,gic-v3"; 478 #address-cells = <2>; 479 #size-cells = <2>; 480 ranges; 481 #interrupt-cells = <3>; 482 interrupt-controller; 483 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 484 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 485 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 486 487 gic-its@17a40000 { 488 compatible = "arm,gic-v3-its"; 489 msi-controller; 490 #msi-cells = <1>; 491 reg = <0 0x17a40000 0 0x20000>; 492 status = "disabled"; 493 }; 494 }; 495 496 watchdog@17c10000 { 497 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 498 reg = <0 0x17c10000 0 0x1000>; 499 clocks = <&sleep_clk>; 500 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 501 }; 502 503 timer@17c20000 { 504 #address-cells = <2>; 505 #size-cells = <2>; 506 ranges; 507 compatible = "arm,armv7-timer-mem"; 508 reg = <0 0x17c20000 0 0x1000>; 509 510 frame@17c21000 { 511 frame-number = <0>; 512 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 514 reg = <0 0x17c21000 0 0x1000>, 515 <0 0x17c22000 0 0x1000>; 516 }; 517 518 frame@17c23000 { 519 frame-number = <1>; 520 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 521 reg = <0 0x17c23000 0 0x1000>; 522 status = "disabled"; 523 }; 524 525 frame@17c25000 { 526 frame-number = <2>; 527 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 528 reg = <0 0x17c25000 0 0x1000>; 529 status = "disabled"; 530 }; 531 532 frame@17c27000 { 533 frame-number = <3>; 534 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 535 reg = <0 0x17c27000 0 0x1000>; 536 status = "disabled"; 537 }; 538 539 frame@17c29000 { 540 frame-number = <4>; 541 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 542 reg = <0 0x17c29000 0 0x1000>; 543 status = "disabled"; 544 }; 545 546 frame@17c2b000 { 547 frame-number = <5>; 548 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 549 reg = <0 0x17c2b000 0 0x1000>; 550 status = "disabled"; 551 }; 552 553 frame@17c2d000 { 554 frame-number = <6>; 555 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 556 reg = <0 0x17c2d000 0 0x1000>; 557 status = "disabled"; 558 }; 559 }; 560 561 apps_rsc: rsc@18200000 { 562 compatible = "qcom,rpmh-rsc"; 563 reg = <0 0x18200000 0 0x10000>, 564 <0 0x18210000 0 0x10000>, 565 <0 0x18220000 0 0x10000>; 566 reg-names = "drv-0", "drv-1", "drv-2"; 567 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 570 qcom,tcs-offset = <0xd00>; 571 qcom,drv-id = <2>; 572 qcom,tcs-config = <ACTIVE_TCS 2>, 573 <SLEEP_TCS 3>, 574 <WAKE_TCS 3>, 575 <CONTROL_TCS 1>; 576 577 rpmhpd: power-controller { 578 compatible = "qcom,sc7280-rpmhpd"; 579 #power-domain-cells = <1>; 580 operating-points-v2 = <&rpmhpd_opp_table>; 581 582 rpmhpd_opp_table: opp-table { 583 compatible = "operating-points-v2"; 584 585 rpmhpd_opp_ret: opp1 { 586 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 587 }; 588 589 rpmhpd_opp_low_svs: opp2 { 590 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 591 }; 592 593 rpmhpd_opp_svs: opp3 { 594 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 595 }; 596 597 rpmhpd_opp_svs_l1: opp4 { 598 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 599 }; 600 601 rpmhpd_opp_svs_l2: opp5 { 602 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 603 }; 604 605 rpmhpd_opp_nom: opp6 { 606 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 607 }; 608 609 rpmhpd_opp_nom_l1: opp7 { 610 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 611 }; 612 613 rpmhpd_opp_turbo: opp8 { 614 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 615 }; 616 617 rpmhpd_opp_turbo_l1: opp9 { 618 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 619 }; 620 }; 621 }; 622 623 rpmhcc: clock-controller { 624 compatible = "qcom,sc7280-rpmh-clk"; 625 clocks = <&xo_board>; 626 clock-names = "xo"; 627 #clock-cells = <1>; 628 }; 629 }; 630 }; 631 632 timer { 633 compatible = "arm,armv8-timer"; 634 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 635 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 636 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 637 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 638 }; 639}; 640