1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/thermal/thermal.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 chosen { }; 34 35 aliases { 36 i2c0 = &i2c0; 37 i2c1 = &i2c1; 38 i2c2 = &i2c2; 39 i2c3 = &i2c3; 40 i2c4 = &i2c4; 41 i2c5 = &i2c5; 42 i2c6 = &i2c6; 43 i2c7 = &i2c7; 44 i2c8 = &i2c8; 45 i2c9 = &i2c9; 46 i2c10 = &i2c10; 47 i2c11 = &i2c11; 48 i2c12 = &i2c12; 49 i2c13 = &i2c13; 50 i2c14 = &i2c14; 51 i2c15 = &i2c15; 52 mmc1 = &sdhc_1; 53 mmc2 = &sdhc_2; 54 spi0 = &spi0; 55 spi1 = &spi1; 56 spi2 = &spi2; 57 spi3 = &spi3; 58 spi4 = &spi4; 59 spi5 = &spi5; 60 spi6 = &spi6; 61 spi7 = &spi7; 62 spi8 = &spi8; 63 spi9 = &spi9; 64 spi10 = &spi10; 65 spi11 = &spi11; 66 spi12 = &spi12; 67 spi13 = &spi13; 68 spi14 = &spi14; 69 spi15 = &spi15; 70 }; 71 72 clocks { 73 xo_board: xo-board { 74 compatible = "fixed-clock"; 75 clock-frequency = <76800000>; 76 #clock-cells = <0>; 77 }; 78 79 sleep_clk: sleep-clk { 80 compatible = "fixed-clock"; 81 clock-frequency = <32000>; 82 #clock-cells = <0>; 83 }; 84 }; 85 86 reserved-memory { 87 #address-cells = <2>; 88 #size-cells = <2>; 89 ranges; 90 91 wlan_ce_mem: memory@4cd000 { 92 no-map; 93 reg = <0x0 0x004cd000 0x0 0x1000>; 94 }; 95 96 hyp_mem: memory@80000000 { 97 reg = <0x0 0x80000000 0x0 0x600000>; 98 no-map; 99 }; 100 101 xbl_mem: memory@80600000 { 102 reg = <0x0 0x80600000 0x0 0x200000>; 103 no-map; 104 }; 105 106 aop_mem: memory@80800000 { 107 reg = <0x0 0x80800000 0x0 0x60000>; 108 no-map; 109 }; 110 111 aop_cmd_db_mem: memory@80860000 { 112 reg = <0x0 0x80860000 0x0 0x20000>; 113 compatible = "qcom,cmd-db"; 114 no-map; 115 }; 116 117 reserved_xbl_uefi_log: memory@80880000 { 118 reg = <0x0 0x80884000 0x0 0x10000>; 119 no-map; 120 }; 121 122 sec_apps_mem: memory@808ff000 { 123 reg = <0x0 0x808ff000 0x0 0x1000>; 124 no-map; 125 }; 126 127 smem_mem: memory@80900000 { 128 reg = <0x0 0x80900000 0x0 0x200000>; 129 no-map; 130 }; 131 132 cpucp_mem: memory@80b00000 { 133 no-map; 134 reg = <0x0 0x80b00000 0x0 0x100000>; 135 }; 136 137 wlan_fw_mem: memory@80c00000 { 138 reg = <0x0 0x80c00000 0x0 0xc00000>; 139 no-map; 140 }; 141 142 video_mem: memory@8b200000 { 143 reg = <0x0 0x8b200000 0x0 0x500000>; 144 no-map; 145 }; 146 147 ipa_fw_mem: memory@8b700000 { 148 reg = <0 0x8b700000 0 0x10000>; 149 no-map; 150 }; 151 152 rmtfs_mem: memory@9c900000 { 153 compatible = "qcom,rmtfs-mem"; 154 reg = <0x0 0x9c900000 0x0 0x280000>; 155 no-map; 156 157 qcom,client-id = <1>; 158 qcom,vmid = <15>; 159 }; 160 }; 161 162 cpus { 163 #address-cells = <2>; 164 #size-cells = <0>; 165 166 CPU0: cpu@0 { 167 device_type = "cpu"; 168 compatible = "arm,kryo"; 169 reg = <0x0 0x0>; 170 enable-method = "psci"; 171 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 172 &LITTLE_CPU_SLEEP_1 173 &CLUSTER_SLEEP_0>; 174 next-level-cache = <&L2_0>; 175 operating-points-v2 = <&cpu0_opp_table>; 176 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 177 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 178 qcom,freq-domain = <&cpufreq_hw 0>; 179 #cooling-cells = <2>; 180 L2_0: l2-cache { 181 compatible = "cache"; 182 next-level-cache = <&L3_0>; 183 L3_0: l3-cache { 184 compatible = "cache"; 185 }; 186 }; 187 }; 188 189 CPU1: cpu@100 { 190 device_type = "cpu"; 191 compatible = "arm,kryo"; 192 reg = <0x0 0x100>; 193 enable-method = "psci"; 194 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 195 &LITTLE_CPU_SLEEP_1 196 &CLUSTER_SLEEP_0>; 197 next-level-cache = <&L2_100>; 198 operating-points-v2 = <&cpu0_opp_table>; 199 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 200 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 201 qcom,freq-domain = <&cpufreq_hw 0>; 202 #cooling-cells = <2>; 203 L2_100: l2-cache { 204 compatible = "cache"; 205 next-level-cache = <&L3_0>; 206 }; 207 }; 208 209 CPU2: cpu@200 { 210 device_type = "cpu"; 211 compatible = "arm,kryo"; 212 reg = <0x0 0x200>; 213 enable-method = "psci"; 214 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 215 &LITTLE_CPU_SLEEP_1 216 &CLUSTER_SLEEP_0>; 217 next-level-cache = <&L2_200>; 218 operating-points-v2 = <&cpu0_opp_table>; 219 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 220 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 221 qcom,freq-domain = <&cpufreq_hw 0>; 222 #cooling-cells = <2>; 223 L2_200: l2-cache { 224 compatible = "cache"; 225 next-level-cache = <&L3_0>; 226 }; 227 }; 228 229 CPU3: cpu@300 { 230 device_type = "cpu"; 231 compatible = "arm,kryo"; 232 reg = <0x0 0x300>; 233 enable-method = "psci"; 234 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 235 &LITTLE_CPU_SLEEP_1 236 &CLUSTER_SLEEP_0>; 237 next-level-cache = <&L2_300>; 238 operating-points-v2 = <&cpu0_opp_table>; 239 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 240 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 241 qcom,freq-domain = <&cpufreq_hw 0>; 242 #cooling-cells = <2>; 243 L2_300: l2-cache { 244 compatible = "cache"; 245 next-level-cache = <&L3_0>; 246 }; 247 }; 248 249 CPU4: cpu@400 { 250 device_type = "cpu"; 251 compatible = "arm,kryo"; 252 reg = <0x0 0x400>; 253 enable-method = "psci"; 254 cpu-idle-states = <&BIG_CPU_SLEEP_0 255 &BIG_CPU_SLEEP_1 256 &CLUSTER_SLEEP_0>; 257 next-level-cache = <&L2_400>; 258 operating-points-v2 = <&cpu4_opp_table>; 259 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 260 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 261 qcom,freq-domain = <&cpufreq_hw 1>; 262 #cooling-cells = <2>; 263 L2_400: l2-cache { 264 compatible = "cache"; 265 next-level-cache = <&L3_0>; 266 }; 267 }; 268 269 CPU5: cpu@500 { 270 device_type = "cpu"; 271 compatible = "arm,kryo"; 272 reg = <0x0 0x500>; 273 enable-method = "psci"; 274 cpu-idle-states = <&BIG_CPU_SLEEP_0 275 &BIG_CPU_SLEEP_1 276 &CLUSTER_SLEEP_0>; 277 next-level-cache = <&L2_500>; 278 operating-points-v2 = <&cpu4_opp_table>; 279 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 280 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 281 qcom,freq-domain = <&cpufreq_hw 1>; 282 #cooling-cells = <2>; 283 L2_500: l2-cache { 284 compatible = "cache"; 285 next-level-cache = <&L3_0>; 286 }; 287 }; 288 289 CPU6: cpu@600 { 290 device_type = "cpu"; 291 compatible = "arm,kryo"; 292 reg = <0x0 0x600>; 293 enable-method = "psci"; 294 cpu-idle-states = <&BIG_CPU_SLEEP_0 295 &BIG_CPU_SLEEP_1 296 &CLUSTER_SLEEP_0>; 297 next-level-cache = <&L2_600>; 298 operating-points-v2 = <&cpu4_opp_table>; 299 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 300 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 301 qcom,freq-domain = <&cpufreq_hw 1>; 302 #cooling-cells = <2>; 303 L2_600: l2-cache { 304 compatible = "cache"; 305 next-level-cache = <&L3_0>; 306 }; 307 }; 308 309 CPU7: cpu@700 { 310 device_type = "cpu"; 311 compatible = "arm,kryo"; 312 reg = <0x0 0x700>; 313 enable-method = "psci"; 314 cpu-idle-states = <&BIG_CPU_SLEEP_0 315 &BIG_CPU_SLEEP_1 316 &CLUSTER_SLEEP_0>; 317 next-level-cache = <&L2_700>; 318 operating-points-v2 = <&cpu7_opp_table>; 319 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 320 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 321 qcom,freq-domain = <&cpufreq_hw 2>; 322 #cooling-cells = <2>; 323 L2_700: l2-cache { 324 compatible = "cache"; 325 next-level-cache = <&L3_0>; 326 }; 327 }; 328 329 cpu-map { 330 cluster0 { 331 core0 { 332 cpu = <&CPU0>; 333 }; 334 335 core1 { 336 cpu = <&CPU1>; 337 }; 338 339 core2 { 340 cpu = <&CPU2>; 341 }; 342 343 core3 { 344 cpu = <&CPU3>; 345 }; 346 347 core4 { 348 cpu = <&CPU4>; 349 }; 350 351 core5 { 352 cpu = <&CPU5>; 353 }; 354 355 core6 { 356 cpu = <&CPU6>; 357 }; 358 359 core7 { 360 cpu = <&CPU7>; 361 }; 362 }; 363 }; 364 365 idle-states { 366 entry-method = "psci"; 367 368 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 369 compatible = "arm,idle-state"; 370 idle-state-name = "little-power-down"; 371 arm,psci-suspend-param = <0x40000003>; 372 entry-latency-us = <549>; 373 exit-latency-us = <901>; 374 min-residency-us = <1774>; 375 local-timer-stop; 376 }; 377 378 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 379 compatible = "arm,idle-state"; 380 idle-state-name = "little-rail-power-down"; 381 arm,psci-suspend-param = <0x40000004>; 382 entry-latency-us = <702>; 383 exit-latency-us = <915>; 384 min-residency-us = <4001>; 385 local-timer-stop; 386 }; 387 388 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 389 compatible = "arm,idle-state"; 390 idle-state-name = "big-power-down"; 391 arm,psci-suspend-param = <0x40000003>; 392 entry-latency-us = <523>; 393 exit-latency-us = <1244>; 394 min-residency-us = <2207>; 395 local-timer-stop; 396 }; 397 398 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 399 compatible = "arm,idle-state"; 400 idle-state-name = "big-rail-power-down"; 401 arm,psci-suspend-param = <0x40000004>; 402 entry-latency-us = <526>; 403 exit-latency-us = <1854>; 404 min-residency-us = <5555>; 405 local-timer-stop; 406 }; 407 408 CLUSTER_SLEEP_0: cluster-sleep-0 { 409 compatible = "arm,idle-state"; 410 idle-state-name = "cluster-power-down"; 411 arm,psci-suspend-param = <0x40003444>; 412 entry-latency-us = <3263>; 413 exit-latency-us = <6562>; 414 min-residency-us = <9926>; 415 local-timer-stop; 416 }; 417 }; 418 }; 419 420 cpu0_opp_table: opp-table-cpu0 { 421 compatible = "operating-points-v2"; 422 opp-shared; 423 424 cpu0_opp_300mhz: opp-300000000 { 425 opp-hz = /bits/ 64 <300000000>; 426 opp-peak-kBps = <800000 9600000>; 427 }; 428 429 cpu0_opp_691mhz: opp-691200000 { 430 opp-hz = /bits/ 64 <691200000>; 431 opp-peak-kBps = <800000 17817600>; 432 }; 433 434 cpu0_opp_806mhz: opp-806400000 { 435 opp-hz = /bits/ 64 <806400000>; 436 opp-peak-kBps = <800000 20889600>; 437 }; 438 439 cpu0_opp_941mhz: opp-940800000 { 440 opp-hz = /bits/ 64 <940800000>; 441 opp-peak-kBps = <1804000 24576000>; 442 }; 443 444 cpu0_opp_1152mhz: opp-1152000000 { 445 opp-hz = /bits/ 64 <1152000000>; 446 opp-peak-kBps = <2188000 27033600>; 447 }; 448 449 cpu0_opp_1325mhz: opp-1324800000 { 450 opp-hz = /bits/ 64 <1324800000>; 451 opp-peak-kBps = <2188000 33792000>; 452 }; 453 454 cpu0_opp_1517mhz: opp-1516800000 { 455 opp-hz = /bits/ 64 <1516800000>; 456 opp-peak-kBps = <3072000 38092800>; 457 }; 458 459 cpu0_opp_1651mhz: opp-1651200000 { 460 opp-hz = /bits/ 64 <1651200000>; 461 opp-peak-kBps = <3072000 41779200>; 462 }; 463 464 cpu0_opp_1805mhz: opp-1804800000 { 465 opp-hz = /bits/ 64 <1804800000>; 466 opp-peak-kBps = <4068000 48537600>; 467 }; 468 469 cpu0_opp_1958mhz: opp-1958400000 { 470 opp-hz = /bits/ 64 <1958400000>; 471 opp-peak-kBps = <4068000 48537600>; 472 }; 473 474 cpu0_opp_2016mhz: opp-2016000000 { 475 opp-hz = /bits/ 64 <2016000000>; 476 opp-peak-kBps = <6220000 48537600>; 477 }; 478 }; 479 480 cpu4_opp_table: opp-table-cpu4 { 481 compatible = "operating-points-v2"; 482 opp-shared; 483 484 cpu4_opp_691mhz: opp-691200000 { 485 opp-hz = /bits/ 64 <691200000>; 486 opp-peak-kBps = <1804000 9600000>; 487 }; 488 489 cpu4_opp_941mhz: opp-940800000 { 490 opp-hz = /bits/ 64 <940800000>; 491 opp-peak-kBps = <2188000 17817600>; 492 }; 493 494 cpu4_opp_1229mhz: opp-1228800000 { 495 opp-hz = /bits/ 64 <1228800000>; 496 opp-peak-kBps = <4068000 24576000>; 497 }; 498 499 cpu4_opp_1344mhz: opp-1344000000 { 500 opp-hz = /bits/ 64 <1344000000>; 501 opp-peak-kBps = <4068000 24576000>; 502 }; 503 504 cpu4_opp_1517mhz: opp-1516800000 { 505 opp-hz = /bits/ 64 <1516800000>; 506 opp-peak-kBps = <4068000 24576000>; 507 }; 508 509 cpu4_opp_1651mhz: opp-1651200000 { 510 opp-hz = /bits/ 64 <1651200000>; 511 opp-peak-kBps = <6220000 38092800>; 512 }; 513 514 cpu4_opp_1901mhz: opp-1900800000 { 515 opp-hz = /bits/ 64 <1900800000>; 516 opp-peak-kBps = <6220000 44851200>; 517 }; 518 519 cpu4_opp_2054mhz: opp-2054400000 { 520 opp-hz = /bits/ 64 <2054400000>; 521 opp-peak-kBps = <6220000 44851200>; 522 }; 523 524 cpu4_opp_2112mhz: opp-2112000000 { 525 opp-hz = /bits/ 64 <2112000000>; 526 opp-peak-kBps = <6220000 44851200>; 527 }; 528 529 cpu4_opp_2131mhz: opp-2131200000 { 530 opp-hz = /bits/ 64 <2131200000>; 531 opp-peak-kBps = <6220000 44851200>; 532 }; 533 534 cpu4_opp_2208mhz: opp-2208000000 { 535 opp-hz = /bits/ 64 <2208000000>; 536 opp-peak-kBps = <6220000 44851200>; 537 }; 538 539 cpu4_opp_2400mhz: opp-2400000000 { 540 opp-hz = /bits/ 64 <2400000000>; 541 opp-peak-kBps = <8532000 48537600>; 542 }; 543 544 cpu4_opp_2611mhz: opp-2611200000 { 545 opp-hz = /bits/ 64 <2611200000>; 546 opp-peak-kBps = <8532000 48537600>; 547 }; 548 }; 549 550 cpu7_opp_table: opp-table-cpu7 { 551 compatible = "operating-points-v2"; 552 opp-shared; 553 554 cpu7_opp_806mhz: opp-806400000 { 555 opp-hz = /bits/ 64 <806400000>; 556 opp-peak-kBps = <1804000 9600000>; 557 }; 558 559 cpu7_opp_1056mhz: opp-1056000000 { 560 opp-hz = /bits/ 64 <1056000000>; 561 opp-peak-kBps = <2188000 17817600>; 562 }; 563 564 cpu7_opp_1325mhz: opp-1324800000 { 565 opp-hz = /bits/ 64 <1324800000>; 566 opp-peak-kBps = <4068000 24576000>; 567 }; 568 569 cpu7_opp_1517mhz: opp-1516800000 { 570 opp-hz = /bits/ 64 <1516800000>; 571 opp-peak-kBps = <4068000 24576000>; 572 }; 573 574 cpu7_opp_1766mhz: opp-1766400000 { 575 opp-hz = /bits/ 64 <1766400000>; 576 opp-peak-kBps = <6220000 38092800>; 577 }; 578 579 cpu7_opp_1862mhz: opp-1862400000 { 580 opp-hz = /bits/ 64 <1862400000>; 581 opp-peak-kBps = <6220000 38092800>; 582 }; 583 584 cpu7_opp_2035mhz: opp-2035200000 { 585 opp-hz = /bits/ 64 <2035200000>; 586 opp-peak-kBps = <6220000 38092800>; 587 }; 588 589 cpu7_opp_2112mhz: opp-2112000000 { 590 opp-hz = /bits/ 64 <2112000000>; 591 opp-peak-kBps = <6220000 44851200>; 592 }; 593 594 cpu7_opp_2208mhz: opp-2208000000 { 595 opp-hz = /bits/ 64 <2208000000>; 596 opp-peak-kBps = <6220000 44851200>; 597 }; 598 599 cpu7_opp_2381mhz: opp-2380800000 { 600 opp-hz = /bits/ 64 <2380800000>; 601 opp-peak-kBps = <6832000 44851200>; 602 }; 603 604 cpu7_opp_2400mhz: opp-2400000000 { 605 opp-hz = /bits/ 64 <2400000000>; 606 opp-peak-kBps = <8532000 48537600>; 607 }; 608 609 cpu7_opp_2515mhz: opp-2515200000 { 610 opp-hz = /bits/ 64 <2515200000>; 611 opp-peak-kBps = <8532000 48537600>; 612 }; 613 614 cpu7_opp_2707mhz: opp-2707200000 { 615 opp-hz = /bits/ 64 <2707200000>; 616 opp-peak-kBps = <8532000 48537600>; 617 }; 618 619 cpu7_opp_3014mhz: opp-3014400000 { 620 opp-hz = /bits/ 64 <3014400000>; 621 opp-peak-kBps = <8532000 48537600>; 622 }; 623 }; 624 625 memory@80000000 { 626 device_type = "memory"; 627 /* We expect the bootloader to fill in the size */ 628 reg = <0 0x80000000 0 0>; 629 }; 630 631 firmware { 632 scm { 633 compatible = "qcom,scm-sc7280", "qcom,scm"; 634 }; 635 }; 636 637 clk_virt: interconnect { 638 compatible = "qcom,sc7280-clk-virt"; 639 #interconnect-cells = <2>; 640 qcom,bcm-voters = <&apps_bcm_voter>; 641 }; 642 643 smem { 644 compatible = "qcom,smem"; 645 memory-region = <&smem_mem>; 646 hwlocks = <&tcsr_mutex 3>; 647 }; 648 649 smp2p-adsp { 650 compatible = "qcom,smp2p"; 651 qcom,smem = <443>, <429>; 652 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 653 IPCC_MPROC_SIGNAL_SMP2P 654 IRQ_TYPE_EDGE_RISING>; 655 mboxes = <&ipcc IPCC_CLIENT_LPASS 656 IPCC_MPROC_SIGNAL_SMP2P>; 657 658 qcom,local-pid = <0>; 659 qcom,remote-pid = <2>; 660 661 adsp_smp2p_out: master-kernel { 662 qcom,entry-name = "master-kernel"; 663 #qcom,smem-state-cells = <1>; 664 }; 665 666 adsp_smp2p_in: slave-kernel { 667 qcom,entry-name = "slave-kernel"; 668 interrupt-controller; 669 #interrupt-cells = <2>; 670 }; 671 }; 672 673 smp2p-cdsp { 674 compatible = "qcom,smp2p"; 675 qcom,smem = <94>, <432>; 676 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 677 IPCC_MPROC_SIGNAL_SMP2P 678 IRQ_TYPE_EDGE_RISING>; 679 mboxes = <&ipcc IPCC_CLIENT_CDSP 680 IPCC_MPROC_SIGNAL_SMP2P>; 681 682 qcom,local-pid = <0>; 683 qcom,remote-pid = <5>; 684 685 cdsp_smp2p_out: master-kernel { 686 qcom,entry-name = "master-kernel"; 687 #qcom,smem-state-cells = <1>; 688 }; 689 690 cdsp_smp2p_in: slave-kernel { 691 qcom,entry-name = "slave-kernel"; 692 interrupt-controller; 693 #interrupt-cells = <2>; 694 }; 695 }; 696 697 smp2p-mpss { 698 compatible = "qcom,smp2p"; 699 qcom,smem = <435>, <428>; 700 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 701 IPCC_MPROC_SIGNAL_SMP2P 702 IRQ_TYPE_EDGE_RISING>; 703 mboxes = <&ipcc IPCC_CLIENT_MPSS 704 IPCC_MPROC_SIGNAL_SMP2P>; 705 706 qcom,local-pid = <0>; 707 qcom,remote-pid = <1>; 708 709 modem_smp2p_out: master-kernel { 710 qcom,entry-name = "master-kernel"; 711 #qcom,smem-state-cells = <1>; 712 }; 713 714 modem_smp2p_in: slave-kernel { 715 qcom,entry-name = "slave-kernel"; 716 interrupt-controller; 717 #interrupt-cells = <2>; 718 }; 719 720 ipa_smp2p_out: ipa-ap-to-modem { 721 qcom,entry-name = "ipa"; 722 #qcom,smem-state-cells = <1>; 723 }; 724 725 ipa_smp2p_in: ipa-modem-to-ap { 726 qcom,entry-name = "ipa"; 727 interrupt-controller; 728 #interrupt-cells = <2>; 729 }; 730 }; 731 732 smp2p-wpss { 733 compatible = "qcom,smp2p"; 734 qcom,smem = <617>, <616>; 735 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 736 IPCC_MPROC_SIGNAL_SMP2P 737 IRQ_TYPE_EDGE_RISING>; 738 mboxes = <&ipcc IPCC_CLIENT_WPSS 739 IPCC_MPROC_SIGNAL_SMP2P>; 740 741 qcom,local-pid = <0>; 742 qcom,remote-pid = <13>; 743 744 wpss_smp2p_out: master-kernel { 745 qcom,entry-name = "master-kernel"; 746 #qcom,smem-state-cells = <1>; 747 }; 748 749 wpss_smp2p_in: slave-kernel { 750 qcom,entry-name = "slave-kernel"; 751 interrupt-controller; 752 #interrupt-cells = <2>; 753 }; 754 }; 755 756 pmu { 757 compatible = "arm,armv8-pmuv3"; 758 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 759 }; 760 761 psci { 762 compatible = "arm,psci-1.0"; 763 method = "smc"; 764 }; 765 766 qspi_opp_table: opp-table-qspi { 767 compatible = "operating-points-v2"; 768 769 opp-75000000 { 770 opp-hz = /bits/ 64 <75000000>; 771 required-opps = <&rpmhpd_opp_low_svs>; 772 }; 773 774 opp-150000000 { 775 opp-hz = /bits/ 64 <150000000>; 776 required-opps = <&rpmhpd_opp_svs>; 777 }; 778 779 opp-200000000 { 780 opp-hz = /bits/ 64 <200000000>; 781 required-opps = <&rpmhpd_opp_svs_l1>; 782 }; 783 784 opp-300000000 { 785 opp-hz = /bits/ 64 <300000000>; 786 required-opps = <&rpmhpd_opp_nom>; 787 }; 788 }; 789 790 qup_opp_table: opp-table-qup { 791 compatible = "operating-points-v2"; 792 793 opp-75000000 { 794 opp-hz = /bits/ 64 <75000000>; 795 required-opps = <&rpmhpd_opp_low_svs>; 796 }; 797 798 opp-100000000 { 799 opp-hz = /bits/ 64 <100000000>; 800 required-opps = <&rpmhpd_opp_svs>; 801 }; 802 803 opp-128000000 { 804 opp-hz = /bits/ 64 <128000000>; 805 required-opps = <&rpmhpd_opp_nom>; 806 }; 807 }; 808 809 soc: soc@0 { 810 #address-cells = <2>; 811 #size-cells = <2>; 812 ranges = <0 0 0 0 0x10 0>; 813 dma-ranges = <0 0 0 0 0x10 0>; 814 compatible = "simple-bus"; 815 816 gcc: clock-controller@100000 { 817 compatible = "qcom,gcc-sc7280"; 818 reg = <0 0x00100000 0 0x1f0000>; 819 clocks = <&rpmhcc RPMH_CXO_CLK>, 820 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 821 <0>, <&pcie1_lane>, 822 <0>, <0>, <0>, <0>; 823 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 824 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 825 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 826 "ufs_phy_tx_symbol_0_clk", 827 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 828 #clock-cells = <1>; 829 #reset-cells = <1>; 830 #power-domain-cells = <1>; 831 }; 832 833 ipcc: mailbox@408000 { 834 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 835 reg = <0 0x00408000 0 0x1000>; 836 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 837 interrupt-controller; 838 #interrupt-cells = <3>; 839 #mbox-cells = <2>; 840 }; 841 842 qfprom: efuse@784000 { 843 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 844 reg = <0 0x00784000 0 0xa20>, 845 <0 0x00780000 0 0xa20>, 846 <0 0x00782000 0 0x120>, 847 <0 0x00786000 0 0x1fff>; 848 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 849 clock-names = "core"; 850 power-domains = <&rpmhpd SC7280_MX>; 851 #address-cells = <1>; 852 #size-cells = <1>; 853 854 gpu_speed_bin: gpu_speed_bin@1e9 { 855 reg = <0x1e9 0x2>; 856 bits = <5 8>; 857 }; 858 }; 859 860 sdhc_1: mmc@7c4000 { 861 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 862 pinctrl-names = "default", "sleep"; 863 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 864 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 865 status = "disabled"; 866 867 reg = <0 0x007c4000 0 0x1000>, 868 <0 0x007c5000 0 0x1000>; 869 reg-names = "hc", "cqhci"; 870 871 iommus = <&apps_smmu 0xc0 0x0>; 872 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 874 interrupt-names = "hc_irq", "pwr_irq"; 875 876 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 877 <&gcc GCC_SDCC1_APPS_CLK>, 878 <&rpmhcc RPMH_CXO_CLK>; 879 clock-names = "iface", "core", "xo"; 880 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 881 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 882 interconnect-names = "sdhc-ddr","cpu-sdhc"; 883 power-domains = <&rpmhpd SC7280_CX>; 884 operating-points-v2 = <&sdhc1_opp_table>; 885 886 bus-width = <8>; 887 supports-cqe; 888 889 qcom,dll-config = <0x0007642c>; 890 qcom,ddr-config = <0x80040868>; 891 892 mmc-ddr-1_8v; 893 mmc-hs200-1_8v; 894 mmc-hs400-1_8v; 895 mmc-hs400-enhanced-strobe; 896 897 resets = <&gcc GCC_SDCC1_BCR>; 898 899 sdhc1_opp_table: opp-table { 900 compatible = "operating-points-v2"; 901 902 opp-100000000 { 903 opp-hz = /bits/ 64 <100000000>; 904 required-opps = <&rpmhpd_opp_low_svs>; 905 opp-peak-kBps = <1800000 400000>; 906 opp-avg-kBps = <100000 0>; 907 }; 908 909 opp-384000000 { 910 opp-hz = /bits/ 64 <384000000>; 911 required-opps = <&rpmhpd_opp_nom>; 912 opp-peak-kBps = <5400000 1600000>; 913 opp-avg-kBps = <390000 0>; 914 }; 915 }; 916 917 }; 918 919 gpi_dma0: dma-controller@900000 { 920 #dma-cells = <3>; 921 compatible = "qcom,sc7280-gpi-dma"; 922 reg = <0 0x00900000 0 0x60000>; 923 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 935 dma-channels = <12>; 936 dma-channel-mask = <0x7f>; 937 iommus = <&apps_smmu 0x0136 0x0>; 938 status = "disabled"; 939 }; 940 941 qupv3_id_0: geniqup@9c0000 { 942 compatible = "qcom,geni-se-qup"; 943 reg = <0 0x009c0000 0 0x2000>; 944 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 945 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 946 clock-names = "m-ahb", "s-ahb"; 947 #address-cells = <2>; 948 #size-cells = <2>; 949 ranges; 950 iommus = <&apps_smmu 0x123 0x0>; 951 status = "disabled"; 952 953 i2c0: i2c@980000 { 954 compatible = "qcom,geni-i2c"; 955 reg = <0 0x00980000 0 0x4000>; 956 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 957 clock-names = "se"; 958 pinctrl-names = "default"; 959 pinctrl-0 = <&qup_i2c0_data_clk>; 960 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 961 #address-cells = <1>; 962 #size-cells = <0>; 963 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 964 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 965 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 966 interconnect-names = "qup-core", "qup-config", 967 "qup-memory"; 968 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 969 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 970 dma-names = "tx", "rx"; 971 status = "disabled"; 972 }; 973 974 spi0: spi@980000 { 975 compatible = "qcom,geni-spi"; 976 reg = <0 0x00980000 0 0x4000>; 977 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 978 clock-names = "se"; 979 pinctrl-names = "default"; 980 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 981 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 power-domains = <&rpmhpd SC7280_CX>; 985 operating-points-v2 = <&qup_opp_table>; 986 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 987 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 988 interconnect-names = "qup-core", "qup-config"; 989 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 990 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 991 dma-names = "tx", "rx"; 992 status = "disabled"; 993 }; 994 995 uart0: serial@980000 { 996 compatible = "qcom,geni-uart"; 997 reg = <0 0x00980000 0 0x4000>; 998 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 999 clock-names = "se"; 1000 pinctrl-names = "default"; 1001 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1002 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1003 power-domains = <&rpmhpd SC7280_CX>; 1004 operating-points-v2 = <&qup_opp_table>; 1005 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1006 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1007 interconnect-names = "qup-core", "qup-config"; 1008 status = "disabled"; 1009 }; 1010 1011 i2c1: i2c@984000 { 1012 compatible = "qcom,geni-i2c"; 1013 reg = <0 0x00984000 0 0x4000>; 1014 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1015 clock-names = "se"; 1016 pinctrl-names = "default"; 1017 pinctrl-0 = <&qup_i2c1_data_clk>; 1018 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1022 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1023 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1024 interconnect-names = "qup-core", "qup-config", 1025 "qup-memory"; 1026 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1027 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1028 dma-names = "tx", "rx"; 1029 status = "disabled"; 1030 }; 1031 1032 spi1: spi@984000 { 1033 compatible = "qcom,geni-spi"; 1034 reg = <0 0x00984000 0 0x4000>; 1035 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1036 clock-names = "se"; 1037 pinctrl-names = "default"; 1038 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1039 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 power-domains = <&rpmhpd SC7280_CX>; 1043 operating-points-v2 = <&qup_opp_table>; 1044 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1045 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1046 interconnect-names = "qup-core", "qup-config"; 1047 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1048 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1049 dma-names = "tx", "rx"; 1050 status = "disabled"; 1051 }; 1052 1053 uart1: serial@984000 { 1054 compatible = "qcom,geni-uart"; 1055 reg = <0 0x00984000 0 0x4000>; 1056 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1057 clock-names = "se"; 1058 pinctrl-names = "default"; 1059 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1060 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1061 power-domains = <&rpmhpd SC7280_CX>; 1062 operating-points-v2 = <&qup_opp_table>; 1063 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1064 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1065 interconnect-names = "qup-core", "qup-config"; 1066 status = "disabled"; 1067 }; 1068 1069 i2c2: i2c@988000 { 1070 compatible = "qcom,geni-i2c"; 1071 reg = <0 0x00988000 0 0x4000>; 1072 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1073 clock-names = "se"; 1074 pinctrl-names = "default"; 1075 pinctrl-0 = <&qup_i2c2_data_clk>; 1076 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1077 #address-cells = <1>; 1078 #size-cells = <0>; 1079 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1080 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1081 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1082 interconnect-names = "qup-core", "qup-config", 1083 "qup-memory"; 1084 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1085 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1086 dma-names = "tx", "rx"; 1087 status = "disabled"; 1088 }; 1089 1090 spi2: spi@988000 { 1091 compatible = "qcom,geni-spi"; 1092 reg = <0 0x00988000 0 0x4000>; 1093 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1094 clock-names = "se"; 1095 pinctrl-names = "default"; 1096 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1097 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 power-domains = <&rpmhpd SC7280_CX>; 1101 operating-points-v2 = <&qup_opp_table>; 1102 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1103 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1104 interconnect-names = "qup-core", "qup-config"; 1105 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1106 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1107 dma-names = "tx", "rx"; 1108 status = "disabled"; 1109 }; 1110 1111 uart2: serial@988000 { 1112 compatible = "qcom,geni-uart"; 1113 reg = <0 0x00988000 0 0x4000>; 1114 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1115 clock-names = "se"; 1116 pinctrl-names = "default"; 1117 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1118 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1119 power-domains = <&rpmhpd SC7280_CX>; 1120 operating-points-v2 = <&qup_opp_table>; 1121 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1122 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1123 interconnect-names = "qup-core", "qup-config"; 1124 status = "disabled"; 1125 }; 1126 1127 i2c3: i2c@98c000 { 1128 compatible = "qcom,geni-i2c"; 1129 reg = <0 0x0098c000 0 0x4000>; 1130 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1131 clock-names = "se"; 1132 pinctrl-names = "default"; 1133 pinctrl-0 = <&qup_i2c3_data_clk>; 1134 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1138 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1139 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1140 interconnect-names = "qup-core", "qup-config", 1141 "qup-memory"; 1142 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1143 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1144 dma-names = "tx", "rx"; 1145 status = "disabled"; 1146 }; 1147 1148 spi3: spi@98c000 { 1149 compatible = "qcom,geni-spi"; 1150 reg = <0 0x0098c000 0 0x4000>; 1151 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1152 clock-names = "se"; 1153 pinctrl-names = "default"; 1154 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1155 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 power-domains = <&rpmhpd SC7280_CX>; 1159 operating-points-v2 = <&qup_opp_table>; 1160 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1161 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1162 interconnect-names = "qup-core", "qup-config"; 1163 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1164 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1165 dma-names = "tx", "rx"; 1166 status = "disabled"; 1167 }; 1168 1169 uart3: serial@98c000 { 1170 compatible = "qcom,geni-uart"; 1171 reg = <0 0x0098c000 0 0x4000>; 1172 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1173 clock-names = "se"; 1174 pinctrl-names = "default"; 1175 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1176 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1177 power-domains = <&rpmhpd SC7280_CX>; 1178 operating-points-v2 = <&qup_opp_table>; 1179 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1180 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1181 interconnect-names = "qup-core", "qup-config"; 1182 status = "disabled"; 1183 }; 1184 1185 i2c4: i2c@990000 { 1186 compatible = "qcom,geni-i2c"; 1187 reg = <0 0x00990000 0 0x4000>; 1188 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1189 clock-names = "se"; 1190 pinctrl-names = "default"; 1191 pinctrl-0 = <&qup_i2c4_data_clk>; 1192 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1193 #address-cells = <1>; 1194 #size-cells = <0>; 1195 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1196 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1197 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1198 interconnect-names = "qup-core", "qup-config", 1199 "qup-memory"; 1200 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1201 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1202 dma-names = "tx", "rx"; 1203 status = "disabled"; 1204 }; 1205 1206 spi4: spi@990000 { 1207 compatible = "qcom,geni-spi"; 1208 reg = <0 0x00990000 0 0x4000>; 1209 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1210 clock-names = "se"; 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1213 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 power-domains = <&rpmhpd SC7280_CX>; 1217 operating-points-v2 = <&qup_opp_table>; 1218 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1219 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1220 interconnect-names = "qup-core", "qup-config"; 1221 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1222 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1223 dma-names = "tx", "rx"; 1224 status = "disabled"; 1225 }; 1226 1227 uart4: serial@990000 { 1228 compatible = "qcom,geni-uart"; 1229 reg = <0 0x00990000 0 0x4000>; 1230 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1231 clock-names = "se"; 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1234 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1235 power-domains = <&rpmhpd SC7280_CX>; 1236 operating-points-v2 = <&qup_opp_table>; 1237 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1238 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1239 interconnect-names = "qup-core", "qup-config"; 1240 status = "disabled"; 1241 }; 1242 1243 i2c5: i2c@994000 { 1244 compatible = "qcom,geni-i2c"; 1245 reg = <0 0x00994000 0 0x4000>; 1246 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1247 clock-names = "se"; 1248 pinctrl-names = "default"; 1249 pinctrl-0 = <&qup_i2c5_data_clk>; 1250 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1254 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1255 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1256 interconnect-names = "qup-core", "qup-config", 1257 "qup-memory"; 1258 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1259 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1260 dma-names = "tx", "rx"; 1261 status = "disabled"; 1262 }; 1263 1264 spi5: spi@994000 { 1265 compatible = "qcom,geni-spi"; 1266 reg = <0 0x00994000 0 0x4000>; 1267 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1268 clock-names = "se"; 1269 pinctrl-names = "default"; 1270 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1271 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1272 #address-cells = <1>; 1273 #size-cells = <0>; 1274 power-domains = <&rpmhpd SC7280_CX>; 1275 operating-points-v2 = <&qup_opp_table>; 1276 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1277 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1278 interconnect-names = "qup-core", "qup-config"; 1279 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1280 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1281 dma-names = "tx", "rx"; 1282 status = "disabled"; 1283 }; 1284 1285 uart5: serial@994000 { 1286 compatible = "qcom,geni-uart"; 1287 reg = <0 0x00994000 0 0x4000>; 1288 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1289 clock-names = "se"; 1290 pinctrl-names = "default"; 1291 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1292 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1293 power-domains = <&rpmhpd SC7280_CX>; 1294 operating-points-v2 = <&qup_opp_table>; 1295 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1296 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1297 interconnect-names = "qup-core", "qup-config"; 1298 status = "disabled"; 1299 }; 1300 1301 i2c6: i2c@998000 { 1302 compatible = "qcom,geni-i2c"; 1303 reg = <0 0x00998000 0 0x4000>; 1304 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1305 clock-names = "se"; 1306 pinctrl-names = "default"; 1307 pinctrl-0 = <&qup_i2c6_data_clk>; 1308 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1309 #address-cells = <1>; 1310 #size-cells = <0>; 1311 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1312 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1313 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1314 interconnect-names = "qup-core", "qup-config", 1315 "qup-memory"; 1316 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1317 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1318 dma-names = "tx", "rx"; 1319 status = "disabled"; 1320 }; 1321 1322 spi6: spi@998000 { 1323 compatible = "qcom,geni-spi"; 1324 reg = <0 0x00998000 0 0x4000>; 1325 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1326 clock-names = "se"; 1327 pinctrl-names = "default"; 1328 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1329 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 power-domains = <&rpmhpd SC7280_CX>; 1333 operating-points-v2 = <&qup_opp_table>; 1334 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1335 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1336 interconnect-names = "qup-core", "qup-config"; 1337 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1338 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1339 dma-names = "tx", "rx"; 1340 status = "disabled"; 1341 }; 1342 1343 uart6: serial@998000 { 1344 compatible = "qcom,geni-uart"; 1345 reg = <0 0x00998000 0 0x4000>; 1346 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1347 clock-names = "se"; 1348 pinctrl-names = "default"; 1349 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1350 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1351 power-domains = <&rpmhpd SC7280_CX>; 1352 operating-points-v2 = <&qup_opp_table>; 1353 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1354 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1355 interconnect-names = "qup-core", "qup-config"; 1356 status = "disabled"; 1357 }; 1358 1359 i2c7: i2c@99c000 { 1360 compatible = "qcom,geni-i2c"; 1361 reg = <0 0x0099c000 0 0x4000>; 1362 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1363 clock-names = "se"; 1364 pinctrl-names = "default"; 1365 pinctrl-0 = <&qup_i2c7_data_clk>; 1366 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1367 #address-cells = <1>; 1368 #size-cells = <0>; 1369 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1370 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1371 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1372 interconnect-names = "qup-core", "qup-config", 1373 "qup-memory"; 1374 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1375 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1376 dma-names = "tx", "rx"; 1377 status = "disabled"; 1378 }; 1379 1380 spi7: spi@99c000 { 1381 compatible = "qcom,geni-spi"; 1382 reg = <0 0x0099c000 0 0x4000>; 1383 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1384 clock-names = "se"; 1385 pinctrl-names = "default"; 1386 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1387 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1388 #address-cells = <1>; 1389 #size-cells = <0>; 1390 power-domains = <&rpmhpd SC7280_CX>; 1391 operating-points-v2 = <&qup_opp_table>; 1392 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1393 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1394 interconnect-names = "qup-core", "qup-config"; 1395 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1396 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1397 dma-names = "tx", "rx"; 1398 status = "disabled"; 1399 }; 1400 1401 uart7: serial@99c000 { 1402 compatible = "qcom,geni-uart"; 1403 reg = <0 0x0099c000 0 0x4000>; 1404 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1405 clock-names = "se"; 1406 pinctrl-names = "default"; 1407 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1408 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1409 power-domains = <&rpmhpd SC7280_CX>; 1410 operating-points-v2 = <&qup_opp_table>; 1411 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1412 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1413 interconnect-names = "qup-core", "qup-config"; 1414 status = "disabled"; 1415 }; 1416 }; 1417 1418 gpi_dma1: dma-controller@a00000 { 1419 #dma-cells = <3>; 1420 compatible = "qcom,sc7280-gpi-dma"; 1421 reg = <0 0x00a00000 0 0x60000>; 1422 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1434 dma-channels = <12>; 1435 dma-channel-mask = <0x1e>; 1436 iommus = <&apps_smmu 0x56 0x0>; 1437 status = "disabled"; 1438 }; 1439 1440 qupv3_id_1: geniqup@ac0000 { 1441 compatible = "qcom,geni-se-qup"; 1442 reg = <0 0x00ac0000 0 0x2000>; 1443 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1444 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1445 clock-names = "m-ahb", "s-ahb"; 1446 #address-cells = <2>; 1447 #size-cells = <2>; 1448 ranges; 1449 iommus = <&apps_smmu 0x43 0x0>; 1450 status = "disabled"; 1451 1452 i2c8: i2c@a80000 { 1453 compatible = "qcom,geni-i2c"; 1454 reg = <0 0x00a80000 0 0x4000>; 1455 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1456 clock-names = "se"; 1457 pinctrl-names = "default"; 1458 pinctrl-0 = <&qup_i2c8_data_clk>; 1459 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1460 #address-cells = <1>; 1461 #size-cells = <0>; 1462 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1463 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1464 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1465 interconnect-names = "qup-core", "qup-config", 1466 "qup-memory"; 1467 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1468 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1469 dma-names = "tx", "rx"; 1470 status = "disabled"; 1471 }; 1472 1473 spi8: spi@a80000 { 1474 compatible = "qcom,geni-spi"; 1475 reg = <0 0x00a80000 0 0x4000>; 1476 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1477 clock-names = "se"; 1478 pinctrl-names = "default"; 1479 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1480 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1481 #address-cells = <1>; 1482 #size-cells = <0>; 1483 power-domains = <&rpmhpd SC7280_CX>; 1484 operating-points-v2 = <&qup_opp_table>; 1485 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1486 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1487 interconnect-names = "qup-core", "qup-config"; 1488 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1489 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1490 dma-names = "tx", "rx"; 1491 status = "disabled"; 1492 }; 1493 1494 uart8: serial@a80000 { 1495 compatible = "qcom,geni-uart"; 1496 reg = <0 0x00a80000 0 0x4000>; 1497 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1498 clock-names = "se"; 1499 pinctrl-names = "default"; 1500 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1501 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1502 power-domains = <&rpmhpd SC7280_CX>; 1503 operating-points-v2 = <&qup_opp_table>; 1504 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1505 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1506 interconnect-names = "qup-core", "qup-config"; 1507 status = "disabled"; 1508 }; 1509 1510 i2c9: i2c@a84000 { 1511 compatible = "qcom,geni-i2c"; 1512 reg = <0 0x00a84000 0 0x4000>; 1513 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1514 clock-names = "se"; 1515 pinctrl-names = "default"; 1516 pinctrl-0 = <&qup_i2c9_data_clk>; 1517 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1518 #address-cells = <1>; 1519 #size-cells = <0>; 1520 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1521 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1522 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1523 interconnect-names = "qup-core", "qup-config", 1524 "qup-memory"; 1525 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1526 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1527 dma-names = "tx", "rx"; 1528 status = "disabled"; 1529 }; 1530 1531 spi9: spi@a84000 { 1532 compatible = "qcom,geni-spi"; 1533 reg = <0 0x00a84000 0 0x4000>; 1534 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1535 clock-names = "se"; 1536 pinctrl-names = "default"; 1537 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1538 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1539 #address-cells = <1>; 1540 #size-cells = <0>; 1541 power-domains = <&rpmhpd SC7280_CX>; 1542 operating-points-v2 = <&qup_opp_table>; 1543 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1544 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1545 interconnect-names = "qup-core", "qup-config"; 1546 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1547 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1548 dma-names = "tx", "rx"; 1549 status = "disabled"; 1550 }; 1551 1552 uart9: serial@a84000 { 1553 compatible = "qcom,geni-uart"; 1554 reg = <0 0x00a84000 0 0x4000>; 1555 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1556 clock-names = "se"; 1557 pinctrl-names = "default"; 1558 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1559 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1560 power-domains = <&rpmhpd SC7280_CX>; 1561 operating-points-v2 = <&qup_opp_table>; 1562 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1563 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1564 interconnect-names = "qup-core", "qup-config"; 1565 status = "disabled"; 1566 }; 1567 1568 i2c10: i2c@a88000 { 1569 compatible = "qcom,geni-i2c"; 1570 reg = <0 0x00a88000 0 0x4000>; 1571 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1572 clock-names = "se"; 1573 pinctrl-names = "default"; 1574 pinctrl-0 = <&qup_i2c10_data_clk>; 1575 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1576 #address-cells = <1>; 1577 #size-cells = <0>; 1578 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1579 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1580 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1581 interconnect-names = "qup-core", "qup-config", 1582 "qup-memory"; 1583 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1584 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1585 dma-names = "tx", "rx"; 1586 status = "disabled"; 1587 }; 1588 1589 spi10: spi@a88000 { 1590 compatible = "qcom,geni-spi"; 1591 reg = <0 0x00a88000 0 0x4000>; 1592 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1593 clock-names = "se"; 1594 pinctrl-names = "default"; 1595 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1596 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1597 #address-cells = <1>; 1598 #size-cells = <0>; 1599 power-domains = <&rpmhpd SC7280_CX>; 1600 operating-points-v2 = <&qup_opp_table>; 1601 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1602 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1603 interconnect-names = "qup-core", "qup-config"; 1604 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1605 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1606 dma-names = "tx", "rx"; 1607 status = "disabled"; 1608 }; 1609 1610 uart10: serial@a88000 { 1611 compatible = "qcom,geni-uart"; 1612 reg = <0 0x00a88000 0 0x4000>; 1613 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1614 clock-names = "se"; 1615 pinctrl-names = "default"; 1616 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1617 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1618 power-domains = <&rpmhpd SC7280_CX>; 1619 operating-points-v2 = <&qup_opp_table>; 1620 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1621 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1622 interconnect-names = "qup-core", "qup-config"; 1623 status = "disabled"; 1624 }; 1625 1626 i2c11: i2c@a8c000 { 1627 compatible = "qcom,geni-i2c"; 1628 reg = <0 0x00a8c000 0 0x4000>; 1629 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1630 clock-names = "se"; 1631 pinctrl-names = "default"; 1632 pinctrl-0 = <&qup_i2c11_data_clk>; 1633 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1634 #address-cells = <1>; 1635 #size-cells = <0>; 1636 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1637 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1638 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1639 interconnect-names = "qup-core", "qup-config", 1640 "qup-memory"; 1641 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1642 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1643 dma-names = "tx", "rx"; 1644 status = "disabled"; 1645 }; 1646 1647 spi11: spi@a8c000 { 1648 compatible = "qcom,geni-spi"; 1649 reg = <0 0x00a8c000 0 0x4000>; 1650 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1651 clock-names = "se"; 1652 pinctrl-names = "default"; 1653 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1654 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1655 #address-cells = <1>; 1656 #size-cells = <0>; 1657 power-domains = <&rpmhpd SC7280_CX>; 1658 operating-points-v2 = <&qup_opp_table>; 1659 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1660 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1661 interconnect-names = "qup-core", "qup-config"; 1662 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1663 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1664 dma-names = "tx", "rx"; 1665 status = "disabled"; 1666 }; 1667 1668 uart11: serial@a8c000 { 1669 compatible = "qcom,geni-uart"; 1670 reg = <0 0x00a8c000 0 0x4000>; 1671 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1672 clock-names = "se"; 1673 pinctrl-names = "default"; 1674 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1675 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1676 power-domains = <&rpmhpd SC7280_CX>; 1677 operating-points-v2 = <&qup_opp_table>; 1678 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1679 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1680 interconnect-names = "qup-core", "qup-config"; 1681 status = "disabled"; 1682 }; 1683 1684 i2c12: i2c@a90000 { 1685 compatible = "qcom,geni-i2c"; 1686 reg = <0 0x00a90000 0 0x4000>; 1687 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1688 clock-names = "se"; 1689 pinctrl-names = "default"; 1690 pinctrl-0 = <&qup_i2c12_data_clk>; 1691 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1692 #address-cells = <1>; 1693 #size-cells = <0>; 1694 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1695 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1696 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1697 interconnect-names = "qup-core", "qup-config", 1698 "qup-memory"; 1699 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1700 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1701 dma-names = "tx", "rx"; 1702 status = "disabled"; 1703 }; 1704 1705 spi12: spi@a90000 { 1706 compatible = "qcom,geni-spi"; 1707 reg = <0 0x00a90000 0 0x4000>; 1708 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1709 clock-names = "se"; 1710 pinctrl-names = "default"; 1711 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1712 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1713 #address-cells = <1>; 1714 #size-cells = <0>; 1715 power-domains = <&rpmhpd SC7280_CX>; 1716 operating-points-v2 = <&qup_opp_table>; 1717 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1718 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1719 interconnect-names = "qup-core", "qup-config"; 1720 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1721 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1722 dma-names = "tx", "rx"; 1723 status = "disabled"; 1724 }; 1725 1726 uart12: serial@a90000 { 1727 compatible = "qcom,geni-uart"; 1728 reg = <0 0x00a90000 0 0x4000>; 1729 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1730 clock-names = "se"; 1731 pinctrl-names = "default"; 1732 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1733 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1734 power-domains = <&rpmhpd SC7280_CX>; 1735 operating-points-v2 = <&qup_opp_table>; 1736 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1737 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1738 interconnect-names = "qup-core", "qup-config"; 1739 status = "disabled"; 1740 }; 1741 1742 i2c13: i2c@a94000 { 1743 compatible = "qcom,geni-i2c"; 1744 reg = <0 0x00a94000 0 0x4000>; 1745 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1746 clock-names = "se"; 1747 pinctrl-names = "default"; 1748 pinctrl-0 = <&qup_i2c13_data_clk>; 1749 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1750 #address-cells = <1>; 1751 #size-cells = <0>; 1752 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1753 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1754 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1755 interconnect-names = "qup-core", "qup-config", 1756 "qup-memory"; 1757 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1758 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1759 dma-names = "tx", "rx"; 1760 status = "disabled"; 1761 }; 1762 1763 spi13: spi@a94000 { 1764 compatible = "qcom,geni-spi"; 1765 reg = <0 0x00a94000 0 0x4000>; 1766 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1767 clock-names = "se"; 1768 pinctrl-names = "default"; 1769 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1770 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1771 #address-cells = <1>; 1772 #size-cells = <0>; 1773 power-domains = <&rpmhpd SC7280_CX>; 1774 operating-points-v2 = <&qup_opp_table>; 1775 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1776 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1777 interconnect-names = "qup-core", "qup-config"; 1778 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1779 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1780 dma-names = "tx", "rx"; 1781 status = "disabled"; 1782 }; 1783 1784 uart13: serial@a94000 { 1785 compatible = "qcom,geni-uart"; 1786 reg = <0 0x00a94000 0 0x4000>; 1787 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1788 clock-names = "se"; 1789 pinctrl-names = "default"; 1790 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1791 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1792 power-domains = <&rpmhpd SC7280_CX>; 1793 operating-points-v2 = <&qup_opp_table>; 1794 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1795 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1796 interconnect-names = "qup-core", "qup-config"; 1797 status = "disabled"; 1798 }; 1799 1800 i2c14: i2c@a98000 { 1801 compatible = "qcom,geni-i2c"; 1802 reg = <0 0x00a98000 0 0x4000>; 1803 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1804 clock-names = "se"; 1805 pinctrl-names = "default"; 1806 pinctrl-0 = <&qup_i2c14_data_clk>; 1807 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1808 #address-cells = <1>; 1809 #size-cells = <0>; 1810 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1811 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1812 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1813 interconnect-names = "qup-core", "qup-config", 1814 "qup-memory"; 1815 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1816 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1817 dma-names = "tx", "rx"; 1818 status = "disabled"; 1819 }; 1820 1821 spi14: spi@a98000 { 1822 compatible = "qcom,geni-spi"; 1823 reg = <0 0x00a98000 0 0x4000>; 1824 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1825 clock-names = "se"; 1826 pinctrl-names = "default"; 1827 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1828 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1829 #address-cells = <1>; 1830 #size-cells = <0>; 1831 power-domains = <&rpmhpd SC7280_CX>; 1832 operating-points-v2 = <&qup_opp_table>; 1833 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1834 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1835 interconnect-names = "qup-core", "qup-config"; 1836 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1837 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1838 dma-names = "tx", "rx"; 1839 status = "disabled"; 1840 }; 1841 1842 uart14: serial@a98000 { 1843 compatible = "qcom,geni-uart"; 1844 reg = <0 0x00a98000 0 0x4000>; 1845 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1846 clock-names = "se"; 1847 pinctrl-names = "default"; 1848 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1849 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1850 power-domains = <&rpmhpd SC7280_CX>; 1851 operating-points-v2 = <&qup_opp_table>; 1852 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1853 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1854 interconnect-names = "qup-core", "qup-config"; 1855 status = "disabled"; 1856 }; 1857 1858 i2c15: i2c@a9c000 { 1859 compatible = "qcom,geni-i2c"; 1860 reg = <0 0x00a9c000 0 0x4000>; 1861 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1862 clock-names = "se"; 1863 pinctrl-names = "default"; 1864 pinctrl-0 = <&qup_i2c15_data_clk>; 1865 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1866 #address-cells = <1>; 1867 #size-cells = <0>; 1868 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1869 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1870 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1871 interconnect-names = "qup-core", "qup-config", 1872 "qup-memory"; 1873 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1874 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1875 dma-names = "tx", "rx"; 1876 status = "disabled"; 1877 }; 1878 1879 spi15: spi@a9c000 { 1880 compatible = "qcom,geni-spi"; 1881 reg = <0 0x00a9c000 0 0x4000>; 1882 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1883 clock-names = "se"; 1884 pinctrl-names = "default"; 1885 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1886 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1887 #address-cells = <1>; 1888 #size-cells = <0>; 1889 power-domains = <&rpmhpd SC7280_CX>; 1890 operating-points-v2 = <&qup_opp_table>; 1891 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1892 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1893 interconnect-names = "qup-core", "qup-config"; 1894 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1895 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1896 dma-names = "tx", "rx"; 1897 status = "disabled"; 1898 }; 1899 1900 uart15: serial@a9c000 { 1901 compatible = "qcom,geni-uart"; 1902 reg = <0 0x00a9c000 0 0x4000>; 1903 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1904 clock-names = "se"; 1905 pinctrl-names = "default"; 1906 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1907 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1908 power-domains = <&rpmhpd SC7280_CX>; 1909 operating-points-v2 = <&qup_opp_table>; 1910 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1911 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1912 interconnect-names = "qup-core", "qup-config"; 1913 status = "disabled"; 1914 }; 1915 }; 1916 1917 cnoc2: interconnect@1500000 { 1918 reg = <0 0x01500000 0 0x1000>; 1919 compatible = "qcom,sc7280-cnoc2"; 1920 #interconnect-cells = <2>; 1921 qcom,bcm-voters = <&apps_bcm_voter>; 1922 }; 1923 1924 cnoc3: interconnect@1502000 { 1925 reg = <0 0x01502000 0 0x1000>; 1926 compatible = "qcom,sc7280-cnoc3"; 1927 #interconnect-cells = <2>; 1928 qcom,bcm-voters = <&apps_bcm_voter>; 1929 }; 1930 1931 mc_virt: interconnect@1580000 { 1932 reg = <0 0x01580000 0 0x4>; 1933 compatible = "qcom,sc7280-mc-virt"; 1934 #interconnect-cells = <2>; 1935 qcom,bcm-voters = <&apps_bcm_voter>; 1936 }; 1937 1938 system_noc: interconnect@1680000 { 1939 reg = <0 0x01680000 0 0x15480>; 1940 compatible = "qcom,sc7280-system-noc"; 1941 #interconnect-cells = <2>; 1942 qcom,bcm-voters = <&apps_bcm_voter>; 1943 }; 1944 1945 aggre1_noc: interconnect@16e0000 { 1946 compatible = "qcom,sc7280-aggre1-noc"; 1947 reg = <0 0x016e0000 0 0x1c080>; 1948 #interconnect-cells = <2>; 1949 qcom,bcm-voters = <&apps_bcm_voter>; 1950 }; 1951 1952 aggre2_noc: interconnect@1700000 { 1953 reg = <0 0x01700000 0 0x2b080>; 1954 compatible = "qcom,sc7280-aggre2-noc"; 1955 #interconnect-cells = <2>; 1956 qcom,bcm-voters = <&apps_bcm_voter>; 1957 }; 1958 1959 mmss_noc: interconnect@1740000 { 1960 reg = <0 0x01740000 0 0x1e080>; 1961 compatible = "qcom,sc7280-mmss-noc"; 1962 #interconnect-cells = <2>; 1963 qcom,bcm-voters = <&apps_bcm_voter>; 1964 }; 1965 1966 wifi: wifi@17a10040 { 1967 compatible = "qcom,wcn6750-wifi"; 1968 reg = <0 0x17a10040 0 0x0>; 1969 iommus = <&apps_smmu 0x1c00 0x1>; 1970 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 1971 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 1972 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 1973 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 1974 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 1975 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 1976 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 1977 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 1978 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 1979 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 1980 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 1981 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 1982 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 1983 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 1984 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 1985 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 1986 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 1987 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 1988 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 1989 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 1990 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 1991 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 1992 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 1993 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 1994 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 1995 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 1996 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 1997 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 1998 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 1999 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2000 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2001 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2002 qcom,rproc = <&remoteproc_wpss>; 2003 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2004 status = "disabled"; 2005 }; 2006 2007 pcie1: pci@1c08000 { 2008 compatible = "qcom,pcie-sc7280"; 2009 reg = <0 0x01c08000 0 0x3000>, 2010 <0 0x40000000 0 0xf1d>, 2011 <0 0x40000f20 0 0xa8>, 2012 <0 0x40001000 0 0x1000>, 2013 <0 0x40100000 0 0x100000>; 2014 2015 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2016 device_type = "pci"; 2017 linux,pci-domain = <1>; 2018 bus-range = <0x00 0xff>; 2019 num-lanes = <2>; 2020 2021 #address-cells = <3>; 2022 #size-cells = <2>; 2023 2024 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 2025 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2026 2027 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2028 interrupt-names = "msi"; 2029 #interrupt-cells = <1>; 2030 interrupt-map-mask = <0 0 0 0x7>; 2031 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2032 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2033 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2034 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2035 2036 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2037 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2038 <&pcie1_lane>, 2039 <&rpmhcc RPMH_CXO_CLK>, 2040 <&gcc GCC_PCIE_1_AUX_CLK>, 2041 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2042 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2043 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2044 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2045 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2046 <&gcc GCC_DDRSS_PCIE_SF_CLK>; 2047 2048 clock-names = "pipe", 2049 "pipe_mux", 2050 "phy_pipe", 2051 "ref", 2052 "aux", 2053 "cfg", 2054 "bus_master", 2055 "bus_slave", 2056 "slave_q2a", 2057 "tbu", 2058 "ddrss_sf_tbu"; 2059 2060 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2061 assigned-clock-rates = <19200000>; 2062 2063 resets = <&gcc GCC_PCIE_1_BCR>; 2064 reset-names = "pci"; 2065 2066 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2067 2068 phys = <&pcie1_lane>; 2069 phy-names = "pciephy"; 2070 2071 pinctrl-names = "default"; 2072 pinctrl-0 = <&pcie1_clkreq_n>; 2073 2074 iommus = <&apps_smmu 0x1c80 0x1>; 2075 2076 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2077 <0x100 &apps_smmu 0x1c81 0x1>; 2078 2079 status = "disabled"; 2080 }; 2081 2082 pcie1_phy: phy@1c0e000 { 2083 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2084 reg = <0 0x01c0e000 0 0x1c0>; 2085 #address-cells = <2>; 2086 #size-cells = <2>; 2087 ranges; 2088 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2089 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2090 <&gcc GCC_PCIE_CLKREF_EN>, 2091 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2092 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2093 2094 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2095 reset-names = "phy"; 2096 2097 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2098 assigned-clock-rates = <100000000>; 2099 2100 status = "disabled"; 2101 2102 pcie1_lane: phy@1c0e200 { 2103 reg = <0 0x01c0e200 0 0x170>, 2104 <0 0x01c0e400 0 0x200>, 2105 <0 0x01c0ea00 0 0x1f0>, 2106 <0 0x01c0e600 0 0x170>, 2107 <0 0x01c0e800 0 0x200>, 2108 <0 0x01c0ee00 0 0xf4>; 2109 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2110 clock-names = "pipe0"; 2111 2112 #phy-cells = <0>; 2113 #clock-cells = <0>; 2114 clock-output-names = "pcie_1_pipe_clk"; 2115 }; 2116 }; 2117 2118 ipa: ipa@1e40000 { 2119 compatible = "qcom,sc7280-ipa"; 2120 2121 iommus = <&apps_smmu 0x480 0x0>, 2122 <&apps_smmu 0x482 0x0>; 2123 reg = <0 0x1e40000 0 0x8000>, 2124 <0 0x1e50000 0 0x4ad0>, 2125 <0 0x1e04000 0 0x23000>; 2126 reg-names = "ipa-reg", 2127 "ipa-shared", 2128 "gsi"; 2129 2130 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2131 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2132 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2133 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2134 interrupt-names = "ipa", 2135 "gsi", 2136 "ipa-clock-query", 2137 "ipa-setup-ready"; 2138 2139 clocks = <&rpmhcc RPMH_IPA_CLK>; 2140 clock-names = "core"; 2141 2142 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2143 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2144 interconnect-names = "memory", 2145 "config"; 2146 2147 qcom,qmp = <&aoss_qmp>; 2148 2149 qcom,smem-states = <&ipa_smp2p_out 0>, 2150 <&ipa_smp2p_out 1>; 2151 qcom,smem-state-names = "ipa-clock-enabled-valid", 2152 "ipa-clock-enabled"; 2153 2154 status = "disabled"; 2155 }; 2156 2157 tcsr_mutex: hwlock@1f40000 { 2158 compatible = "qcom,tcsr-mutex"; 2159 reg = <0 0x01f40000 0 0x20000>; 2160 #hwlock-cells = <1>; 2161 }; 2162 2163 tcsr_1: syscon@1f60000 { 2164 compatible = "qcom,sc7280-tcsr", "syscon"; 2165 reg = <0 0x01f60000 0 0x20000>; 2166 }; 2167 2168 tcsr_2: syscon@1fc0000 { 2169 compatible = "qcom,sc7280-tcsr", "syscon"; 2170 reg = <0 0x01fc0000 0 0x30000>; 2171 }; 2172 2173 lpasscc: lpasscc@3000000 { 2174 compatible = "qcom,sc7280-lpasscc"; 2175 reg = <0 0x03000000 0 0x40>, 2176 <0 0x03c04000 0 0x4>; 2177 reg-names = "qdsp6ss", "top_cc"; 2178 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2179 clock-names = "iface"; 2180 #clock-cells = <1>; 2181 }; 2182 2183 lpass_rx_macro: codec@3200000 { 2184 compatible = "qcom,sc7280-lpass-rx-macro"; 2185 reg = <0 0x03200000 0 0x1000>; 2186 2187 pinctrl-names = "default"; 2188 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2189 2190 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2191 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2192 <&lpass_va_macro>; 2193 clock-names = "mclk", "npl", "fsgen"; 2194 2195 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2196 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2197 power-domain-names = "macro", "dcodec"; 2198 2199 #clock-cells = <0>; 2200 #sound-dai-cells = <1>; 2201 2202 status = "disabled"; 2203 }; 2204 2205 swr0: soundwire@3210000 { 2206 compatible = "qcom,soundwire-v1.6.0"; 2207 reg = <0 0x03210000 0 0x2000>; 2208 2209 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2210 clocks = <&lpass_rx_macro>; 2211 clock-names = "iface"; 2212 2213 qcom,din-ports = <0>; 2214 qcom,dout-ports = <5>; 2215 2216 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2217 reset-names = "swr_audio_cgcr"; 2218 2219 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2220 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2221 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2222 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2223 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2224 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2225 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2226 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2227 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2228 2229 #sound-dai-cells = <1>; 2230 #address-cells = <2>; 2231 #size-cells = <0>; 2232 2233 status = "disabled"; 2234 }; 2235 2236 lpass_tx_macro: codec@3220000 { 2237 compatible = "qcom,sc7280-lpass-tx-macro"; 2238 reg = <0 0x03220000 0 0x1000>; 2239 2240 pinctrl-names = "default"; 2241 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2242 2243 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2244 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2245 <&lpass_va_macro>; 2246 clock-names = "mclk", "npl", "fsgen"; 2247 2248 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2249 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2250 power-domain-names = "macro", "dcodec"; 2251 2252 #clock-cells = <0>; 2253 #sound-dai-cells = <1>; 2254 2255 status = "disabled"; 2256 }; 2257 2258 swr1: soundwire@3230000 { 2259 compatible = "qcom,soundwire-v1.6.0"; 2260 reg = <0 0x03230000 0 0x2000>; 2261 2262 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2263 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2264 clocks = <&lpass_tx_macro>; 2265 clock-names = "iface"; 2266 2267 qcom,din-ports = <3>; 2268 qcom,dout-ports = <0>; 2269 2270 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2271 reset-names = "swr_audio_cgcr"; 2272 2273 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2274 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2275 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2276 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2277 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2278 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2279 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2280 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2281 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2282 qcom,port-offset = <1>; 2283 2284 #sound-dai-cells = <1>; 2285 #address-cells = <2>; 2286 #size-cells = <0>; 2287 2288 status = "disabled"; 2289 }; 2290 2291 lpass_audiocc: clock-controller@3300000 { 2292 compatible = "qcom,sc7280-lpassaudiocc"; 2293 reg = <0 0x03300000 0 0x30000>; 2294 clocks = <&rpmhcc RPMH_CXO_CLK>, 2295 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2296 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2297 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2298 #clock-cells = <1>; 2299 #power-domain-cells = <1>; 2300 #reset-cells = <1>; 2301 }; 2302 2303 lpass_va_macro: codec@3370000 { 2304 compatible = "qcom,sc7280-lpass-va-macro"; 2305 reg = <0 0x03370000 0 0x1000>; 2306 2307 pinctrl-names = "default"; 2308 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2309 2310 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2311 clock-names = "mclk"; 2312 2313 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2314 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2315 power-domain-names = "macro", "dcodec"; 2316 2317 #clock-cells = <0>; 2318 #sound-dai-cells = <1>; 2319 2320 status = "disabled"; 2321 }; 2322 2323 lpass_aon: clock-controller@3380000 { 2324 compatible = "qcom,sc7280-lpassaoncc"; 2325 reg = <0 0x03380000 0 0x30000>; 2326 clocks = <&rpmhcc RPMH_CXO_CLK>, 2327 <&rpmhcc RPMH_CXO_CLK_A>, 2328 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2329 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2330 #clock-cells = <1>; 2331 #power-domain-cells = <1>; 2332 }; 2333 2334 lpass_core: clock-controller@3900000 { 2335 compatible = "qcom,sc7280-lpasscorecc"; 2336 reg = <0 0x03900000 0 0x50000>; 2337 clocks = <&rpmhcc RPMH_CXO_CLK>; 2338 clock-names = "bi_tcxo"; 2339 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2340 #clock-cells = <1>; 2341 #power-domain-cells = <1>; 2342 }; 2343 2344 lpass_hm: clock-controller@3c00000 { 2345 compatible = "qcom,sc7280-lpasshm"; 2346 reg = <0 0x3c00000 0 0x28>; 2347 clocks = <&rpmhcc RPMH_CXO_CLK>; 2348 clock-names = "bi_tcxo"; 2349 #clock-cells = <1>; 2350 #power-domain-cells = <1>; 2351 }; 2352 2353 lpass_ag_noc: interconnect@3c40000 { 2354 reg = <0 0x03c40000 0 0xf080>; 2355 compatible = "qcom,sc7280-lpass-ag-noc"; 2356 #interconnect-cells = <2>; 2357 qcom,bcm-voters = <&apps_bcm_voter>; 2358 }; 2359 2360 lpass_tlmm: pinctrl@33c0000 { 2361 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2362 reg = <0 0x033c0000 0x0 0x20000>, 2363 <0 0x03550000 0x0 0x10000>; 2364 qcom,adsp-bypass-mode; 2365 gpio-controller; 2366 #gpio-cells = <2>; 2367 gpio-ranges = <&lpass_tlmm 0 0 15>; 2368 2369 #clock-cells = <1>; 2370 2371 lpass_dmic01_clk: dmic01-clk { 2372 pins = "gpio6"; 2373 function = "dmic1_clk"; 2374 }; 2375 2376 lpass_dmic01_clk_sleep: dmic01-clk-sleep { 2377 pins = "gpio6"; 2378 function = "dmic1_clk"; 2379 }; 2380 2381 lpass_dmic01_data: dmic01-data { 2382 pins = "gpio7"; 2383 function = "dmic1_data"; 2384 }; 2385 2386 lpass_dmic01_data_sleep: dmic01-data-sleep { 2387 pins = "gpio7"; 2388 function = "dmic1_data"; 2389 }; 2390 2391 lpass_dmic23_clk: dmic23-clk { 2392 pins = "gpio8"; 2393 function = "dmic2_clk"; 2394 }; 2395 2396 lpass_dmic23_clk_sleep: dmic23-clk-sleep { 2397 pins = "gpio8"; 2398 function = "dmic2_clk"; 2399 }; 2400 2401 lpass_dmic23_data: dmic23-data { 2402 pins = "gpio9"; 2403 function = "dmic2_data"; 2404 }; 2405 2406 lpass_dmic23_data_sleep: dmic23-data-sleep { 2407 pins = "gpio9"; 2408 function = "dmic2_data"; 2409 }; 2410 2411 lpass_rx_swr_clk: rx-swr-clk { 2412 pins = "gpio3"; 2413 function = "swr_rx_clk"; 2414 }; 2415 2416 lpass_rx_swr_clk_sleep: rx-swr-clk-sleep { 2417 pins = "gpio3"; 2418 function = "swr_rx_clk"; 2419 }; 2420 2421 lpass_rx_swr_data: rx-swr-data { 2422 pins = "gpio4", "gpio5"; 2423 function = "swr_rx_data"; 2424 }; 2425 2426 lpass_rx_swr_data_sleep: rx-swr-data-sleep { 2427 pins = "gpio4", "gpio5"; 2428 function = "swr_rx_data"; 2429 }; 2430 2431 lpass_tx_swr_clk: tx-swr-clk { 2432 pins = "gpio0"; 2433 function = "swr_tx_clk"; 2434 }; 2435 2436 lpass_tx_swr_clk_sleep: tx-swr-clk-sleep { 2437 pins = "gpio0"; 2438 function = "swr_tx_clk"; 2439 }; 2440 2441 lpass_tx_swr_data: tx-swr-data { 2442 pins = "gpio1", "gpio2", "gpio14"; 2443 function = "swr_tx_data"; 2444 }; 2445 2446 lpass_tx_swr_data_sleep: tx-swr-data-sleep { 2447 pins = "gpio1", "gpio2", "gpio14"; 2448 function = "swr_tx_data"; 2449 }; 2450 }; 2451 2452 gpu: gpu@3d00000 { 2453 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2454 reg = <0 0x03d00000 0 0x40000>, 2455 <0 0x03d9e000 0 0x1000>, 2456 <0 0x03d61000 0 0x800>; 2457 reg-names = "kgsl_3d0_reg_memory", 2458 "cx_mem", 2459 "cx_dbgc"; 2460 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2461 iommus = <&adreno_smmu 0 0x401>; 2462 operating-points-v2 = <&gpu_opp_table>; 2463 qcom,gmu = <&gmu>; 2464 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2465 interconnect-names = "gfx-mem"; 2466 #cooling-cells = <2>; 2467 2468 nvmem-cells = <&gpu_speed_bin>; 2469 nvmem-cell-names = "speed_bin"; 2470 2471 gpu_opp_table: opp-table { 2472 compatible = "operating-points-v2"; 2473 2474 opp-315000000 { 2475 opp-hz = /bits/ 64 <315000000>; 2476 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2477 opp-peak-kBps = <1804000>; 2478 opp-supported-hw = <0x03>; 2479 }; 2480 2481 opp-450000000 { 2482 opp-hz = /bits/ 64 <450000000>; 2483 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2484 opp-peak-kBps = <4068000>; 2485 opp-supported-hw = <0x03>; 2486 }; 2487 2488 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2489 opp-550000000-0 { 2490 opp-hz = /bits/ 64 <550000000>; 2491 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2492 opp-peak-kBps = <8368000>; 2493 opp-supported-hw = <0x01>; 2494 }; 2495 2496 opp-550000000-1 { 2497 opp-hz = /bits/ 64 <550000000>; 2498 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2499 opp-peak-kBps = <6832000>; 2500 opp-supported-hw = <0x02>; 2501 }; 2502 2503 opp-608000000 { 2504 opp-hz = /bits/ 64 <608000000>; 2505 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2506 opp-peak-kBps = <8368000>; 2507 opp-supported-hw = <0x02>; 2508 }; 2509 2510 opp-700000000 { 2511 opp-hz = /bits/ 64 <700000000>; 2512 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2513 opp-peak-kBps = <8532000>; 2514 opp-supported-hw = <0x02>; 2515 }; 2516 2517 opp-812000000 { 2518 opp-hz = /bits/ 64 <812000000>; 2519 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2520 opp-peak-kBps = <8532000>; 2521 opp-supported-hw = <0x02>; 2522 }; 2523 2524 opp-840000000 { 2525 opp-hz = /bits/ 64 <840000000>; 2526 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2527 opp-peak-kBps = <8532000>; 2528 opp-supported-hw = <0x02>; 2529 }; 2530 2531 opp-900000000 { 2532 opp-hz = /bits/ 64 <900000000>; 2533 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2534 opp-peak-kBps = <8532000>; 2535 opp-supported-hw = <0x02>; 2536 }; 2537 }; 2538 }; 2539 2540 gmu: gmu@3d6a000 { 2541 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2542 reg = <0 0x03d6a000 0 0x34000>, 2543 <0 0x3de0000 0 0x10000>, 2544 <0 0x0b290000 0 0x10000>; 2545 reg-names = "gmu", "rscc", "gmu_pdc"; 2546 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2547 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2548 interrupt-names = "hfi", "gmu"; 2549 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2550 <&gpucc GPU_CC_CXO_CLK>, 2551 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2552 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2553 <&gpucc GPU_CC_AHB_CLK>, 2554 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2555 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2556 clock-names = "gmu", 2557 "cxo", 2558 "axi", 2559 "memnoc", 2560 "ahb", 2561 "hub", 2562 "smmu_vote"; 2563 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2564 <&gpucc GPU_CC_GX_GDSC>; 2565 power-domain-names = "cx", 2566 "gx"; 2567 iommus = <&adreno_smmu 5 0x400>; 2568 operating-points-v2 = <&gmu_opp_table>; 2569 2570 gmu_opp_table: opp-table { 2571 compatible = "operating-points-v2"; 2572 2573 opp-200000000 { 2574 opp-hz = /bits/ 64 <200000000>; 2575 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2576 }; 2577 }; 2578 }; 2579 2580 gpucc: clock-controller@3d90000 { 2581 compatible = "qcom,sc7280-gpucc"; 2582 reg = <0 0x03d90000 0 0x9000>; 2583 clocks = <&rpmhcc RPMH_CXO_CLK>, 2584 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2585 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2586 clock-names = "bi_tcxo", 2587 "gcc_gpu_gpll0_clk_src", 2588 "gcc_gpu_gpll0_div_clk_src"; 2589 #clock-cells = <1>; 2590 #reset-cells = <1>; 2591 #power-domain-cells = <1>; 2592 }; 2593 2594 adreno_smmu: iommu@3da0000 { 2595 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2596 reg = <0 0x03da0000 0 0x20000>; 2597 #iommu-cells = <2>; 2598 #global-interrupts = <2>; 2599 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2600 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2601 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2602 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2603 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2604 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2605 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2606 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2607 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2608 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2609 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2610 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2611 2612 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2613 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2614 <&gpucc GPU_CC_AHB_CLK>, 2615 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2616 <&gpucc GPU_CC_CX_GMU_CLK>, 2617 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2618 <&gpucc GPU_CC_HUB_AON_CLK>; 2619 clock-names = "gcc_gpu_memnoc_gfx_clk", 2620 "gcc_gpu_snoc_dvm_gfx_clk", 2621 "gpu_cc_ahb_clk", 2622 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2623 "gpu_cc_cx_gmu_clk", 2624 "gpu_cc_hub_cx_int_clk", 2625 "gpu_cc_hub_aon_clk"; 2626 2627 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2628 }; 2629 2630 remoteproc_mpss: remoteproc@4080000 { 2631 compatible = "qcom,sc7280-mpss-pas"; 2632 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2633 reg-names = "qdsp6", "rmb"; 2634 2635 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2636 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2637 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2638 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2639 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2640 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2641 interrupt-names = "wdog", "fatal", "ready", "handover", 2642 "stop-ack", "shutdown-ack"; 2643 2644 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2645 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 2646 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2647 <&rpmhcc RPMH_PKA_CLK>, 2648 <&rpmhcc RPMH_CXO_CLK>; 2649 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 2650 2651 power-domains = <&rpmhpd SC7280_CX>, 2652 <&rpmhpd SC7280_MSS>; 2653 power-domain-names = "cx", "mss"; 2654 2655 memory-region = <&mpss_mem>; 2656 2657 qcom,qmp = <&aoss_qmp>; 2658 2659 qcom,smem-states = <&modem_smp2p_out 0>; 2660 qcom,smem-state-names = "stop"; 2661 2662 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2663 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2664 reset-names = "mss_restart", "pdc_reset"; 2665 2666 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>; 2667 qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>; 2668 qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>; 2669 2670 status = "disabled"; 2671 2672 glink-edge { 2673 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2674 IPCC_MPROC_SIGNAL_GLINK_QMP 2675 IRQ_TYPE_EDGE_RISING>; 2676 mboxes = <&ipcc IPCC_CLIENT_MPSS 2677 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2678 label = "modem"; 2679 qcom,remote-pid = <1>; 2680 }; 2681 }; 2682 2683 stm@6002000 { 2684 compatible = "arm,coresight-stm", "arm,primecell"; 2685 reg = <0 0x06002000 0 0x1000>, 2686 <0 0x16280000 0 0x180000>; 2687 reg-names = "stm-base", "stm-stimulus-base"; 2688 2689 clocks = <&aoss_qmp>; 2690 clock-names = "apb_pclk"; 2691 2692 out-ports { 2693 port { 2694 stm_out: endpoint { 2695 remote-endpoint = <&funnel0_in7>; 2696 }; 2697 }; 2698 }; 2699 }; 2700 2701 funnel@6041000 { 2702 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2703 reg = <0 0x06041000 0 0x1000>; 2704 2705 clocks = <&aoss_qmp>; 2706 clock-names = "apb_pclk"; 2707 2708 out-ports { 2709 port { 2710 funnel0_out: endpoint { 2711 remote-endpoint = <&merge_funnel_in0>; 2712 }; 2713 }; 2714 }; 2715 2716 in-ports { 2717 #address-cells = <1>; 2718 #size-cells = <0>; 2719 2720 port@7 { 2721 reg = <7>; 2722 funnel0_in7: endpoint { 2723 remote-endpoint = <&stm_out>; 2724 }; 2725 }; 2726 }; 2727 }; 2728 2729 funnel@6042000 { 2730 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2731 reg = <0 0x06042000 0 0x1000>; 2732 2733 clocks = <&aoss_qmp>; 2734 clock-names = "apb_pclk"; 2735 2736 out-ports { 2737 port { 2738 funnel1_out: endpoint { 2739 remote-endpoint = <&merge_funnel_in1>; 2740 }; 2741 }; 2742 }; 2743 2744 in-ports { 2745 #address-cells = <1>; 2746 #size-cells = <0>; 2747 2748 port@4 { 2749 reg = <4>; 2750 funnel1_in4: endpoint { 2751 remote-endpoint = <&apss_merge_funnel_out>; 2752 }; 2753 }; 2754 }; 2755 }; 2756 2757 funnel@6045000 { 2758 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2759 reg = <0 0x06045000 0 0x1000>; 2760 2761 clocks = <&aoss_qmp>; 2762 clock-names = "apb_pclk"; 2763 2764 out-ports { 2765 port { 2766 merge_funnel_out: endpoint { 2767 remote-endpoint = <&swao_funnel_in>; 2768 }; 2769 }; 2770 }; 2771 2772 in-ports { 2773 #address-cells = <1>; 2774 #size-cells = <0>; 2775 2776 port@0 { 2777 reg = <0>; 2778 merge_funnel_in0: endpoint { 2779 remote-endpoint = <&funnel0_out>; 2780 }; 2781 }; 2782 2783 port@1 { 2784 reg = <1>; 2785 merge_funnel_in1: endpoint { 2786 remote-endpoint = <&funnel1_out>; 2787 }; 2788 }; 2789 }; 2790 }; 2791 2792 replicator@6046000 { 2793 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2794 reg = <0 0x06046000 0 0x1000>; 2795 2796 clocks = <&aoss_qmp>; 2797 clock-names = "apb_pclk"; 2798 2799 out-ports { 2800 port { 2801 replicator_out: endpoint { 2802 remote-endpoint = <&etr_in>; 2803 }; 2804 }; 2805 }; 2806 2807 in-ports { 2808 port { 2809 replicator_in: endpoint { 2810 remote-endpoint = <&swao_replicator_out>; 2811 }; 2812 }; 2813 }; 2814 }; 2815 2816 etr@6048000 { 2817 compatible = "arm,coresight-tmc", "arm,primecell"; 2818 reg = <0 0x06048000 0 0x1000>; 2819 iommus = <&apps_smmu 0x04c0 0>; 2820 2821 clocks = <&aoss_qmp>; 2822 clock-names = "apb_pclk"; 2823 arm,scatter-gather; 2824 2825 in-ports { 2826 port { 2827 etr_in: endpoint { 2828 remote-endpoint = <&replicator_out>; 2829 }; 2830 }; 2831 }; 2832 }; 2833 2834 funnel@6b04000 { 2835 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2836 reg = <0 0x06b04000 0 0x1000>; 2837 2838 clocks = <&aoss_qmp>; 2839 clock-names = "apb_pclk"; 2840 2841 out-ports { 2842 port { 2843 swao_funnel_out: endpoint { 2844 remote-endpoint = <&etf_in>; 2845 }; 2846 }; 2847 }; 2848 2849 in-ports { 2850 #address-cells = <1>; 2851 #size-cells = <0>; 2852 2853 port@7 { 2854 reg = <7>; 2855 swao_funnel_in: endpoint { 2856 remote-endpoint = <&merge_funnel_out>; 2857 }; 2858 }; 2859 }; 2860 }; 2861 2862 etf@6b05000 { 2863 compatible = "arm,coresight-tmc", "arm,primecell"; 2864 reg = <0 0x06b05000 0 0x1000>; 2865 2866 clocks = <&aoss_qmp>; 2867 clock-names = "apb_pclk"; 2868 2869 out-ports { 2870 port { 2871 etf_out: endpoint { 2872 remote-endpoint = <&swao_replicator_in>; 2873 }; 2874 }; 2875 }; 2876 2877 in-ports { 2878 port { 2879 etf_in: endpoint { 2880 remote-endpoint = <&swao_funnel_out>; 2881 }; 2882 }; 2883 }; 2884 }; 2885 2886 replicator@6b06000 { 2887 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2888 reg = <0 0x06b06000 0 0x1000>; 2889 2890 clocks = <&aoss_qmp>; 2891 clock-names = "apb_pclk"; 2892 qcom,replicator-loses-context; 2893 2894 out-ports { 2895 port { 2896 swao_replicator_out: endpoint { 2897 remote-endpoint = <&replicator_in>; 2898 }; 2899 }; 2900 }; 2901 2902 in-ports { 2903 port { 2904 swao_replicator_in: endpoint { 2905 remote-endpoint = <&etf_out>; 2906 }; 2907 }; 2908 }; 2909 }; 2910 2911 etm@7040000 { 2912 compatible = "arm,coresight-etm4x", "arm,primecell"; 2913 reg = <0 0x07040000 0 0x1000>; 2914 2915 cpu = <&CPU0>; 2916 2917 clocks = <&aoss_qmp>; 2918 clock-names = "apb_pclk"; 2919 arm,coresight-loses-context-with-cpu; 2920 qcom,skip-power-up; 2921 2922 out-ports { 2923 port { 2924 etm0_out: endpoint { 2925 remote-endpoint = <&apss_funnel_in0>; 2926 }; 2927 }; 2928 }; 2929 }; 2930 2931 etm@7140000 { 2932 compatible = "arm,coresight-etm4x", "arm,primecell"; 2933 reg = <0 0x07140000 0 0x1000>; 2934 2935 cpu = <&CPU1>; 2936 2937 clocks = <&aoss_qmp>; 2938 clock-names = "apb_pclk"; 2939 arm,coresight-loses-context-with-cpu; 2940 qcom,skip-power-up; 2941 2942 out-ports { 2943 port { 2944 etm1_out: endpoint { 2945 remote-endpoint = <&apss_funnel_in1>; 2946 }; 2947 }; 2948 }; 2949 }; 2950 2951 etm@7240000 { 2952 compatible = "arm,coresight-etm4x", "arm,primecell"; 2953 reg = <0 0x07240000 0 0x1000>; 2954 2955 cpu = <&CPU2>; 2956 2957 clocks = <&aoss_qmp>; 2958 clock-names = "apb_pclk"; 2959 arm,coresight-loses-context-with-cpu; 2960 qcom,skip-power-up; 2961 2962 out-ports { 2963 port { 2964 etm2_out: endpoint { 2965 remote-endpoint = <&apss_funnel_in2>; 2966 }; 2967 }; 2968 }; 2969 }; 2970 2971 etm@7340000 { 2972 compatible = "arm,coresight-etm4x", "arm,primecell"; 2973 reg = <0 0x07340000 0 0x1000>; 2974 2975 cpu = <&CPU3>; 2976 2977 clocks = <&aoss_qmp>; 2978 clock-names = "apb_pclk"; 2979 arm,coresight-loses-context-with-cpu; 2980 qcom,skip-power-up; 2981 2982 out-ports { 2983 port { 2984 etm3_out: endpoint { 2985 remote-endpoint = <&apss_funnel_in3>; 2986 }; 2987 }; 2988 }; 2989 }; 2990 2991 etm@7440000 { 2992 compatible = "arm,coresight-etm4x", "arm,primecell"; 2993 reg = <0 0x07440000 0 0x1000>; 2994 2995 cpu = <&CPU4>; 2996 2997 clocks = <&aoss_qmp>; 2998 clock-names = "apb_pclk"; 2999 arm,coresight-loses-context-with-cpu; 3000 qcom,skip-power-up; 3001 3002 out-ports { 3003 port { 3004 etm4_out: endpoint { 3005 remote-endpoint = <&apss_funnel_in4>; 3006 }; 3007 }; 3008 }; 3009 }; 3010 3011 etm@7540000 { 3012 compatible = "arm,coresight-etm4x", "arm,primecell"; 3013 reg = <0 0x07540000 0 0x1000>; 3014 3015 cpu = <&CPU5>; 3016 3017 clocks = <&aoss_qmp>; 3018 clock-names = "apb_pclk"; 3019 arm,coresight-loses-context-with-cpu; 3020 qcom,skip-power-up; 3021 3022 out-ports { 3023 port { 3024 etm5_out: endpoint { 3025 remote-endpoint = <&apss_funnel_in5>; 3026 }; 3027 }; 3028 }; 3029 }; 3030 3031 etm@7640000 { 3032 compatible = "arm,coresight-etm4x", "arm,primecell"; 3033 reg = <0 0x07640000 0 0x1000>; 3034 3035 cpu = <&CPU6>; 3036 3037 clocks = <&aoss_qmp>; 3038 clock-names = "apb_pclk"; 3039 arm,coresight-loses-context-with-cpu; 3040 qcom,skip-power-up; 3041 3042 out-ports { 3043 port { 3044 etm6_out: endpoint { 3045 remote-endpoint = <&apss_funnel_in6>; 3046 }; 3047 }; 3048 }; 3049 }; 3050 3051 etm@7740000 { 3052 compatible = "arm,coresight-etm4x", "arm,primecell"; 3053 reg = <0 0x07740000 0 0x1000>; 3054 3055 cpu = <&CPU7>; 3056 3057 clocks = <&aoss_qmp>; 3058 clock-names = "apb_pclk"; 3059 arm,coresight-loses-context-with-cpu; 3060 qcom,skip-power-up; 3061 3062 out-ports { 3063 port { 3064 etm7_out: endpoint { 3065 remote-endpoint = <&apss_funnel_in7>; 3066 }; 3067 }; 3068 }; 3069 }; 3070 3071 funnel@7800000 { /* APSS Funnel */ 3072 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3073 reg = <0 0x07800000 0 0x1000>; 3074 3075 clocks = <&aoss_qmp>; 3076 clock-names = "apb_pclk"; 3077 3078 out-ports { 3079 port { 3080 apss_funnel_out: endpoint { 3081 remote-endpoint = <&apss_merge_funnel_in>; 3082 }; 3083 }; 3084 }; 3085 3086 in-ports { 3087 #address-cells = <1>; 3088 #size-cells = <0>; 3089 3090 port@0 { 3091 reg = <0>; 3092 apss_funnel_in0: endpoint { 3093 remote-endpoint = <&etm0_out>; 3094 }; 3095 }; 3096 3097 port@1 { 3098 reg = <1>; 3099 apss_funnel_in1: endpoint { 3100 remote-endpoint = <&etm1_out>; 3101 }; 3102 }; 3103 3104 port@2 { 3105 reg = <2>; 3106 apss_funnel_in2: endpoint { 3107 remote-endpoint = <&etm2_out>; 3108 }; 3109 }; 3110 3111 port@3 { 3112 reg = <3>; 3113 apss_funnel_in3: endpoint { 3114 remote-endpoint = <&etm3_out>; 3115 }; 3116 }; 3117 3118 port@4 { 3119 reg = <4>; 3120 apss_funnel_in4: endpoint { 3121 remote-endpoint = <&etm4_out>; 3122 }; 3123 }; 3124 3125 port@5 { 3126 reg = <5>; 3127 apss_funnel_in5: endpoint { 3128 remote-endpoint = <&etm5_out>; 3129 }; 3130 }; 3131 3132 port@6 { 3133 reg = <6>; 3134 apss_funnel_in6: endpoint { 3135 remote-endpoint = <&etm6_out>; 3136 }; 3137 }; 3138 3139 port@7 { 3140 reg = <7>; 3141 apss_funnel_in7: endpoint { 3142 remote-endpoint = <&etm7_out>; 3143 }; 3144 }; 3145 }; 3146 }; 3147 3148 funnel@7810000 { 3149 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3150 reg = <0 0x07810000 0 0x1000>; 3151 3152 clocks = <&aoss_qmp>; 3153 clock-names = "apb_pclk"; 3154 3155 out-ports { 3156 port { 3157 apss_merge_funnel_out: endpoint { 3158 remote-endpoint = <&funnel1_in4>; 3159 }; 3160 }; 3161 }; 3162 3163 in-ports { 3164 port { 3165 apss_merge_funnel_in: endpoint { 3166 remote-endpoint = <&apss_funnel_out>; 3167 }; 3168 }; 3169 }; 3170 }; 3171 3172 sdhc_2: mmc@8804000 { 3173 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3174 pinctrl-names = "default", "sleep"; 3175 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3176 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3177 status = "disabled"; 3178 3179 reg = <0 0x08804000 0 0x1000>; 3180 3181 iommus = <&apps_smmu 0x100 0x0>; 3182 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3183 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3184 interrupt-names = "hc_irq", "pwr_irq"; 3185 3186 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3187 <&gcc GCC_SDCC2_APPS_CLK>, 3188 <&rpmhcc RPMH_CXO_CLK>; 3189 clock-names = "iface", "core", "xo"; 3190 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3191 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3192 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3193 power-domains = <&rpmhpd SC7280_CX>; 3194 operating-points-v2 = <&sdhc2_opp_table>; 3195 3196 bus-width = <4>; 3197 3198 qcom,dll-config = <0x0007642c>; 3199 3200 resets = <&gcc GCC_SDCC2_BCR>; 3201 3202 sdhc2_opp_table: opp-table { 3203 compatible = "operating-points-v2"; 3204 3205 opp-100000000 { 3206 opp-hz = /bits/ 64 <100000000>; 3207 required-opps = <&rpmhpd_opp_low_svs>; 3208 opp-peak-kBps = <1800000 400000>; 3209 opp-avg-kBps = <100000 0>; 3210 }; 3211 3212 opp-202000000 { 3213 opp-hz = /bits/ 64 <202000000>; 3214 required-opps = <&rpmhpd_opp_nom>; 3215 opp-peak-kBps = <5400000 1600000>; 3216 opp-avg-kBps = <200000 0>; 3217 }; 3218 }; 3219 3220 }; 3221 3222 usb_1_hsphy: phy@88e3000 { 3223 compatible = "qcom,sc7280-usb-hs-phy", 3224 "qcom,usb-snps-hs-7nm-phy"; 3225 reg = <0 0x088e3000 0 0x400>; 3226 status = "disabled"; 3227 #phy-cells = <0>; 3228 3229 clocks = <&rpmhcc RPMH_CXO_CLK>; 3230 clock-names = "ref"; 3231 3232 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3233 }; 3234 3235 usb_2_hsphy: phy@88e4000 { 3236 compatible = "qcom,sc7280-usb-hs-phy", 3237 "qcom,usb-snps-hs-7nm-phy"; 3238 reg = <0 0x088e4000 0 0x400>; 3239 status = "disabled"; 3240 #phy-cells = <0>; 3241 3242 clocks = <&rpmhcc RPMH_CXO_CLK>; 3243 clock-names = "ref"; 3244 3245 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3246 }; 3247 3248 usb_1_qmpphy: phy-wrapper@88e9000 { 3249 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3250 "qcom,sm8250-qmp-usb3-dp-phy"; 3251 reg = <0 0x088e9000 0 0x200>, 3252 <0 0x088e8000 0 0x40>, 3253 <0 0x088ea000 0 0x200>; 3254 status = "disabled"; 3255 #address-cells = <2>; 3256 #size-cells = <2>; 3257 ranges; 3258 3259 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3260 <&rpmhcc RPMH_CXO_CLK>, 3261 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3262 clock-names = "aux", "ref_clk_src", "com_aux"; 3263 3264 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3265 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3266 reset-names = "phy", "common"; 3267 3268 usb_1_ssphy: usb3-phy@88e9200 { 3269 reg = <0 0x088e9200 0 0x200>, 3270 <0 0x088e9400 0 0x200>, 3271 <0 0x088e9c00 0 0x400>, 3272 <0 0x088e9600 0 0x200>, 3273 <0 0x088e9800 0 0x200>, 3274 <0 0x088e9a00 0 0x100>; 3275 #clock-cells = <0>; 3276 #phy-cells = <0>; 3277 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3278 clock-names = "pipe0"; 3279 clock-output-names = "usb3_phy_pipe_clk_src"; 3280 }; 3281 3282 dp_phy: dp-phy@88ea200 { 3283 reg = <0 0x088ea200 0 0x200>, 3284 <0 0x088ea400 0 0x200>, 3285 <0 0x088eaa00 0 0x200>, 3286 <0 0x088ea600 0 0x200>, 3287 <0 0x088ea800 0 0x200>; 3288 #phy-cells = <0>; 3289 #clock-cells = <1>; 3290 }; 3291 }; 3292 3293 usb_2: usb@8cf8800 { 3294 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3295 reg = <0 0x08cf8800 0 0x400>; 3296 status = "disabled"; 3297 #address-cells = <2>; 3298 #size-cells = <2>; 3299 ranges; 3300 dma-ranges; 3301 3302 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3303 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3304 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3305 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3306 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3307 clock-names = "cfg_noc", 3308 "core", 3309 "iface", 3310 "sleep", 3311 "mock_utmi"; 3312 3313 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3314 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3315 assigned-clock-rates = <19200000>, <200000000>; 3316 3317 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3318 <&pdc 12 IRQ_TYPE_EDGE_RISING>, 3319 <&pdc 13 IRQ_TYPE_EDGE_RISING>; 3320 interrupt-names = "hs_phy_irq", 3321 "dp_hs_phy_irq", 3322 "dm_hs_phy_irq"; 3323 3324 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3325 3326 resets = <&gcc GCC_USB30_SEC_BCR>; 3327 3328 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3329 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3330 interconnect-names = "usb-ddr", "apps-usb"; 3331 3332 usb_2_dwc3: usb@8c00000 { 3333 compatible = "snps,dwc3"; 3334 reg = <0 0x08c00000 0 0xe000>; 3335 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3336 iommus = <&apps_smmu 0xa0 0x0>; 3337 snps,dis_u2_susphy_quirk; 3338 snps,dis_enblslpm_quirk; 3339 phys = <&usb_2_hsphy>; 3340 phy-names = "usb2-phy"; 3341 maximum-speed = "high-speed"; 3342 usb-role-switch; 3343 port { 3344 usb2_role_switch: endpoint { 3345 remote-endpoint = <&eud_ep>; 3346 }; 3347 }; 3348 }; 3349 }; 3350 3351 qspi: spi@88dc000 { 3352 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3353 reg = <0 0x088dc000 0 0x1000>; 3354 #address-cells = <1>; 3355 #size-cells = <0>; 3356 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3357 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3358 <&gcc GCC_QSPI_CORE_CLK>; 3359 clock-names = "iface", "core"; 3360 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3361 &cnoc2 SLAVE_QSPI_0 0>; 3362 interconnect-names = "qspi-config"; 3363 power-domains = <&rpmhpd SC7280_CX>; 3364 operating-points-v2 = <&qspi_opp_table>; 3365 status = "disabled"; 3366 }; 3367 3368 remoteproc_wpss: remoteproc@8a00000 { 3369 compatible = "qcom,sc7280-wpss-pil"; 3370 reg = <0 0x08a00000 0 0x10000>; 3371 3372 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3373 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3374 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3375 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3376 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3377 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3378 interrupt-names = "wdog", "fatal", "ready", "handover", 3379 "stop-ack", "shutdown-ack"; 3380 3381 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3382 <&gcc GCC_WPSS_AHB_CLK>, 3383 <&gcc GCC_WPSS_RSCP_CLK>, 3384 <&rpmhcc RPMH_CXO_CLK>; 3385 clock-names = "ahb_bdg", "ahb", 3386 "rscp", "xo"; 3387 3388 power-domains = <&rpmhpd SC7280_CX>, 3389 <&rpmhpd SC7280_MX>; 3390 power-domain-names = "cx", "mx"; 3391 3392 memory-region = <&wpss_mem>; 3393 3394 qcom,qmp = <&aoss_qmp>; 3395 3396 qcom,smem-states = <&wpss_smp2p_out 0>; 3397 qcom,smem-state-names = "stop"; 3398 3399 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3400 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3401 reset-names = "restart", "pdc_sync"; 3402 3403 qcom,halt-regs = <&tcsr_1 0x17000>; 3404 3405 status = "disabled"; 3406 3407 glink-edge { 3408 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3409 IPCC_MPROC_SIGNAL_GLINK_QMP 3410 IRQ_TYPE_EDGE_RISING>; 3411 mboxes = <&ipcc IPCC_CLIENT_WPSS 3412 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3413 3414 label = "wpss"; 3415 qcom,remote-pid = <13>; 3416 }; 3417 }; 3418 3419 pmu@9091000 { 3420 compatible = "qcom,sc7280-llcc-bwmon"; 3421 reg = <0 0x9091000 0 0x1000>; 3422 3423 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3424 3425 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3426 3427 operating-points-v2 = <&llcc_bwmon_opp_table>; 3428 3429 llcc_bwmon_opp_table: opp-table { 3430 compatible = "operating-points-v2"; 3431 3432 opp-0 { 3433 opp-peak-kBps = <800000>; 3434 }; 3435 opp-1 { 3436 opp-peak-kBps = <1804000>; 3437 }; 3438 opp-2 { 3439 opp-peak-kBps = <2188000>; 3440 }; 3441 opp-3 { 3442 opp-peak-kBps = <3072000>; 3443 }; 3444 opp-4 { 3445 opp-peak-kBps = <4068000>; 3446 }; 3447 opp-5 { 3448 opp-peak-kBps = <6220000>; 3449 }; 3450 opp-6 { 3451 opp-peak-kBps = <6832000>; 3452 }; 3453 opp-7 { 3454 opp-peak-kBps = <8532000>; 3455 }; 3456 }; 3457 }; 3458 3459 pmu@90b6400 { 3460 compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon"; 3461 reg = <0 0x090b6400 0 0x600>; 3462 3463 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3464 3465 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3466 operating-points-v2 = <&cpu_bwmon_opp_table>; 3467 3468 cpu_bwmon_opp_table: opp-table { 3469 compatible = "operating-points-v2"; 3470 3471 opp-0 { 3472 opp-peak-kBps = <2400000>; 3473 }; 3474 opp-1 { 3475 opp-peak-kBps = <4800000>; 3476 }; 3477 opp-2 { 3478 opp-peak-kBps = <7456000>; 3479 }; 3480 opp-3 { 3481 opp-peak-kBps = <9600000>; 3482 }; 3483 opp-4 { 3484 opp-peak-kBps = <12896000>; 3485 }; 3486 opp-5 { 3487 opp-peak-kBps = <14928000>; 3488 }; 3489 opp-6 { 3490 opp-peak-kBps = <17056000>; 3491 }; 3492 }; 3493 }; 3494 3495 dc_noc: interconnect@90e0000 { 3496 reg = <0 0x090e0000 0 0x5080>; 3497 compatible = "qcom,sc7280-dc-noc"; 3498 #interconnect-cells = <2>; 3499 qcom,bcm-voters = <&apps_bcm_voter>; 3500 }; 3501 3502 gem_noc: interconnect@9100000 { 3503 reg = <0 0x9100000 0 0xe2200>; 3504 compatible = "qcom,sc7280-gem-noc"; 3505 #interconnect-cells = <2>; 3506 qcom,bcm-voters = <&apps_bcm_voter>; 3507 }; 3508 3509 system-cache-controller@9200000 { 3510 compatible = "qcom,sc7280-llcc"; 3511 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 3512 reg-names = "llcc_base", "llcc_broadcast_base"; 3513 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3514 }; 3515 3516 eud: eud@88e0000 { 3517 compatible = "qcom,sc7280-eud","qcom,eud"; 3518 reg = <0 0x88e0000 0 0x2000>, 3519 <0 0x88e2000 0 0x1000>; 3520 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3521 ports { 3522 port@0 { 3523 eud_ep: endpoint { 3524 remote-endpoint = <&usb2_role_switch>; 3525 }; 3526 }; 3527 port@1 { 3528 eud_con: endpoint { 3529 remote-endpoint = <&con_eud>; 3530 }; 3531 }; 3532 }; 3533 }; 3534 3535 eud_typec: connector { 3536 compatible = "usb-c-connector"; 3537 ports { 3538 port@0 { 3539 con_eud: endpoint { 3540 remote-endpoint = <&eud_con>; 3541 }; 3542 }; 3543 }; 3544 }; 3545 3546 nsp_noc: interconnect@a0c0000 { 3547 reg = <0 0x0a0c0000 0 0x10000>; 3548 compatible = "qcom,sc7280-nsp-noc"; 3549 #interconnect-cells = <2>; 3550 qcom,bcm-voters = <&apps_bcm_voter>; 3551 }; 3552 3553 usb_1: usb@a6f8800 { 3554 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3555 reg = <0 0x0a6f8800 0 0x400>; 3556 status = "disabled"; 3557 #address-cells = <2>; 3558 #size-cells = <2>; 3559 ranges; 3560 dma-ranges; 3561 3562 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3563 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3564 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3565 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3566 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3567 clock-names = "cfg_noc", 3568 "core", 3569 "iface", 3570 "sleep", 3571 "mock_utmi"; 3572 3573 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3574 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3575 assigned-clock-rates = <19200000>, <200000000>; 3576 3577 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3578 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3579 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3580 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3581 interrupt-names = "hs_phy_irq", 3582 "dp_hs_phy_irq", 3583 "dm_hs_phy_irq", 3584 "ss_phy_irq"; 3585 3586 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3587 3588 resets = <&gcc GCC_USB30_PRIM_BCR>; 3589 3590 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3591 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3592 interconnect-names = "usb-ddr", "apps-usb"; 3593 3594 usb_1_dwc3: usb@a600000 { 3595 compatible = "snps,dwc3"; 3596 reg = <0 0x0a600000 0 0xe000>; 3597 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3598 iommus = <&apps_smmu 0xe0 0x0>; 3599 snps,dis_u2_susphy_quirk; 3600 snps,dis_enblslpm_quirk; 3601 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3602 phy-names = "usb2-phy", "usb3-phy"; 3603 maximum-speed = "super-speed"; 3604 wakeup-source; 3605 }; 3606 }; 3607 3608 venus: video-codec@aa00000 { 3609 compatible = "qcom,sc7280-venus"; 3610 reg = <0 0x0aa00000 0 0xd0600>; 3611 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3612 3613 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3614 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3615 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3616 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3617 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3618 clock-names = "core", "bus", "iface", 3619 "vcodec_core", "vcodec_bus"; 3620 3621 power-domains = <&videocc MVSC_GDSC>, 3622 <&videocc MVS0_GDSC>, 3623 <&rpmhpd SC7280_CX>; 3624 power-domain-names = "venus", "vcodec0", "cx"; 3625 operating-points-v2 = <&venus_opp_table>; 3626 3627 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3628 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3629 interconnect-names = "cpu-cfg", "video-mem"; 3630 3631 iommus = <&apps_smmu 0x2180 0x20>, 3632 <&apps_smmu 0x2184 0x20>; 3633 memory-region = <&video_mem>; 3634 3635 video-decoder { 3636 compatible = "venus-decoder"; 3637 }; 3638 3639 video-encoder { 3640 compatible = "venus-encoder"; 3641 }; 3642 3643 video-firmware { 3644 iommus = <&apps_smmu 0x21a2 0x0>; 3645 }; 3646 3647 venus_opp_table: opp-table { 3648 compatible = "operating-points-v2"; 3649 3650 opp-133330000 { 3651 opp-hz = /bits/ 64 <133330000>; 3652 required-opps = <&rpmhpd_opp_low_svs>; 3653 }; 3654 3655 opp-240000000 { 3656 opp-hz = /bits/ 64 <240000000>; 3657 required-opps = <&rpmhpd_opp_svs>; 3658 }; 3659 3660 opp-335000000 { 3661 opp-hz = /bits/ 64 <335000000>; 3662 required-opps = <&rpmhpd_opp_svs_l1>; 3663 }; 3664 3665 opp-424000000 { 3666 opp-hz = /bits/ 64 <424000000>; 3667 required-opps = <&rpmhpd_opp_nom>; 3668 }; 3669 3670 opp-460000048 { 3671 opp-hz = /bits/ 64 <460000048>; 3672 required-opps = <&rpmhpd_opp_turbo>; 3673 }; 3674 }; 3675 3676 }; 3677 3678 videocc: clock-controller@aaf0000 { 3679 compatible = "qcom,sc7280-videocc"; 3680 reg = <0 0xaaf0000 0 0x10000>; 3681 clocks = <&rpmhcc RPMH_CXO_CLK>, 3682 <&rpmhcc RPMH_CXO_CLK_A>; 3683 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3684 #clock-cells = <1>; 3685 #reset-cells = <1>; 3686 #power-domain-cells = <1>; 3687 }; 3688 3689 camcc: clock-controller@ad00000 { 3690 compatible = "qcom,sc7280-camcc"; 3691 reg = <0 0x0ad00000 0 0x10000>; 3692 clocks = <&rpmhcc RPMH_CXO_CLK>, 3693 <&rpmhcc RPMH_CXO_CLK_A>, 3694 <&sleep_clk>; 3695 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3696 #clock-cells = <1>; 3697 #reset-cells = <1>; 3698 #power-domain-cells = <1>; 3699 }; 3700 3701 dispcc: clock-controller@af00000 { 3702 compatible = "qcom,sc7280-dispcc"; 3703 reg = <0 0xaf00000 0 0x20000>; 3704 clocks = <&rpmhcc RPMH_CXO_CLK>, 3705 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3706 <&mdss_dsi_phy 0>, 3707 <&mdss_dsi_phy 1>, 3708 <&dp_phy 0>, 3709 <&dp_phy 1>, 3710 <&mdss_edp_phy 0>, 3711 <&mdss_edp_phy 1>; 3712 clock-names = "bi_tcxo", 3713 "gcc_disp_gpll0_clk", 3714 "dsi0_phy_pll_out_byteclk", 3715 "dsi0_phy_pll_out_dsiclk", 3716 "dp_phy_pll_link_clk", 3717 "dp_phy_pll_vco_div_clk", 3718 "edp_phy_pll_link_clk", 3719 "edp_phy_pll_vco_div_clk"; 3720 #clock-cells = <1>; 3721 #reset-cells = <1>; 3722 #power-domain-cells = <1>; 3723 }; 3724 3725 mdss: display-subsystem@ae00000 { 3726 compatible = "qcom,sc7280-mdss"; 3727 reg = <0 0x0ae00000 0 0x1000>; 3728 reg-names = "mdss"; 3729 3730 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3731 3732 clocks = <&gcc GCC_DISP_AHB_CLK>, 3733 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3734 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3735 clock-names = "iface", 3736 "ahb", 3737 "core"; 3738 3739 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3740 interrupt-controller; 3741 #interrupt-cells = <1>; 3742 3743 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3744 interconnect-names = "mdp0-mem"; 3745 3746 iommus = <&apps_smmu 0x900 0x402>; 3747 3748 #address-cells = <2>; 3749 #size-cells = <2>; 3750 ranges; 3751 3752 status = "disabled"; 3753 3754 mdss_mdp: display-controller@ae01000 { 3755 compatible = "qcom,sc7280-dpu"; 3756 reg = <0 0x0ae01000 0 0x8f030>, 3757 <0 0x0aeb0000 0 0x2008>; 3758 reg-names = "mdp", "vbif"; 3759 3760 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3761 <&gcc GCC_DISP_SF_AXI_CLK>, 3762 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3763 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3764 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3765 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3766 clock-names = "bus", 3767 "nrt_bus", 3768 "iface", 3769 "lut", 3770 "core", 3771 "vsync"; 3772 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3773 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3774 assigned-clock-rates = <19200000>, 3775 <19200000>; 3776 operating-points-v2 = <&mdp_opp_table>; 3777 power-domains = <&rpmhpd SC7280_CX>; 3778 3779 interrupt-parent = <&mdss>; 3780 interrupts = <0>; 3781 3782 status = "disabled"; 3783 3784 ports { 3785 #address-cells = <1>; 3786 #size-cells = <0>; 3787 3788 port@0 { 3789 reg = <0>; 3790 dpu_intf1_out: endpoint { 3791 remote-endpoint = <&dsi0_in>; 3792 }; 3793 }; 3794 3795 port@1 { 3796 reg = <1>; 3797 dpu_intf5_out: endpoint { 3798 remote-endpoint = <&edp_in>; 3799 }; 3800 }; 3801 3802 port@2 { 3803 reg = <2>; 3804 dpu_intf0_out: endpoint { 3805 remote-endpoint = <&dp_in>; 3806 }; 3807 }; 3808 }; 3809 3810 mdp_opp_table: opp-table { 3811 compatible = "operating-points-v2"; 3812 3813 opp-200000000 { 3814 opp-hz = /bits/ 64 <200000000>; 3815 required-opps = <&rpmhpd_opp_low_svs>; 3816 }; 3817 3818 opp-300000000 { 3819 opp-hz = /bits/ 64 <300000000>; 3820 required-opps = <&rpmhpd_opp_svs>; 3821 }; 3822 3823 opp-380000000 { 3824 opp-hz = /bits/ 64 <380000000>; 3825 required-opps = <&rpmhpd_opp_svs_l1>; 3826 }; 3827 3828 opp-506666667 { 3829 opp-hz = /bits/ 64 <506666667>; 3830 required-opps = <&rpmhpd_opp_nom>; 3831 }; 3832 }; 3833 }; 3834 3835 mdss_dsi: dsi@ae94000 { 3836 compatible = "qcom,mdss-dsi-ctrl"; 3837 reg = <0 0x0ae94000 0 0x400>; 3838 reg-names = "dsi_ctrl"; 3839 3840 interrupt-parent = <&mdss>; 3841 interrupts = <4>; 3842 3843 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3844 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3845 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3846 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3847 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3848 <&gcc GCC_DISP_HF_AXI_CLK>; 3849 clock-names = "byte", 3850 "byte_intf", 3851 "pixel", 3852 "core", 3853 "iface", 3854 "bus"; 3855 3856 operating-points-v2 = <&dsi_opp_table>; 3857 power-domains = <&rpmhpd SC7280_CX>; 3858 3859 phys = <&mdss_dsi_phy>; 3860 phy-names = "dsi"; 3861 3862 #address-cells = <1>; 3863 #size-cells = <0>; 3864 3865 status = "disabled"; 3866 3867 ports { 3868 #address-cells = <1>; 3869 #size-cells = <0>; 3870 3871 port@0 { 3872 reg = <0>; 3873 dsi0_in: endpoint { 3874 remote-endpoint = <&dpu_intf1_out>; 3875 }; 3876 }; 3877 3878 port@1 { 3879 reg = <1>; 3880 dsi0_out: endpoint { 3881 }; 3882 }; 3883 }; 3884 3885 dsi_opp_table: opp-table { 3886 compatible = "operating-points-v2"; 3887 3888 opp-187500000 { 3889 opp-hz = /bits/ 64 <187500000>; 3890 required-opps = <&rpmhpd_opp_low_svs>; 3891 }; 3892 3893 opp-300000000 { 3894 opp-hz = /bits/ 64 <300000000>; 3895 required-opps = <&rpmhpd_opp_svs>; 3896 }; 3897 3898 opp-358000000 { 3899 opp-hz = /bits/ 64 <358000000>; 3900 required-opps = <&rpmhpd_opp_svs_l1>; 3901 }; 3902 }; 3903 }; 3904 3905 mdss_dsi_phy: phy@ae94400 { 3906 compatible = "qcom,sc7280-dsi-phy-7nm"; 3907 reg = <0 0x0ae94400 0 0x200>, 3908 <0 0x0ae94600 0 0x280>, 3909 <0 0x0ae94900 0 0x280>; 3910 reg-names = "dsi_phy", 3911 "dsi_phy_lane", 3912 "dsi_pll"; 3913 3914 #clock-cells = <1>; 3915 #phy-cells = <0>; 3916 3917 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3918 <&rpmhcc RPMH_CXO_CLK>; 3919 clock-names = "iface", "ref"; 3920 3921 status = "disabled"; 3922 }; 3923 3924 mdss_edp: edp@aea0000 { 3925 compatible = "qcom,sc7280-edp"; 3926 pinctrl-names = "default"; 3927 pinctrl-0 = <&edp_hot_plug_det>; 3928 3929 reg = <0 0xaea0000 0 0x200>, 3930 <0 0xaea0200 0 0x200>, 3931 <0 0xaea0400 0 0xc00>, 3932 <0 0xaea1000 0 0x400>; 3933 3934 interrupt-parent = <&mdss>; 3935 interrupts = <14>; 3936 3937 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3938 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3939 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 3940 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 3941 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 3942 clock-names = "core_iface", 3943 "core_aux", 3944 "ctrl_link", 3945 "ctrl_link_iface", 3946 "stream_pixel"; 3947 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 3948 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 3949 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 3950 3951 phys = <&mdss_edp_phy>; 3952 phy-names = "dp"; 3953 3954 operating-points-v2 = <&edp_opp_table>; 3955 power-domains = <&rpmhpd SC7280_CX>; 3956 3957 status = "disabled"; 3958 3959 ports { 3960 #address-cells = <1>; 3961 #size-cells = <0>; 3962 3963 port@0 { 3964 reg = <0>; 3965 edp_in: endpoint { 3966 remote-endpoint = <&dpu_intf5_out>; 3967 }; 3968 }; 3969 3970 port@1 { 3971 reg = <1>; 3972 mdss_edp_out: endpoint { }; 3973 }; 3974 }; 3975 3976 edp_opp_table: opp-table { 3977 compatible = "operating-points-v2"; 3978 3979 opp-160000000 { 3980 opp-hz = /bits/ 64 <160000000>; 3981 required-opps = <&rpmhpd_opp_low_svs>; 3982 }; 3983 3984 opp-270000000 { 3985 opp-hz = /bits/ 64 <270000000>; 3986 required-opps = <&rpmhpd_opp_svs>; 3987 }; 3988 3989 opp-540000000 { 3990 opp-hz = /bits/ 64 <540000000>; 3991 required-opps = <&rpmhpd_opp_nom>; 3992 }; 3993 3994 opp-810000000 { 3995 opp-hz = /bits/ 64 <810000000>; 3996 required-opps = <&rpmhpd_opp_nom>; 3997 }; 3998 }; 3999 }; 4000 4001 mdss_edp_phy: phy@aec2a00 { 4002 compatible = "qcom,sc7280-edp-phy"; 4003 4004 reg = <0 0xaec2a00 0 0x19c>, 4005 <0 0xaec2200 0 0xa0>, 4006 <0 0xaec2600 0 0xa0>, 4007 <0 0xaec2000 0 0x1c0>; 4008 4009 clocks = <&rpmhcc RPMH_CXO_CLK>, 4010 <&gcc GCC_EDP_CLKREF_EN>; 4011 clock-names = "aux", 4012 "cfg_ahb"; 4013 4014 #clock-cells = <1>; 4015 #phy-cells = <0>; 4016 4017 status = "disabled"; 4018 }; 4019 4020 mdss_dp: displayport-controller@ae90000 { 4021 compatible = "qcom,sc7280-dp"; 4022 4023 reg = <0 0xae90000 0 0x200>, 4024 <0 0xae90200 0 0x200>, 4025 <0 0xae90400 0 0xc00>, 4026 <0 0xae91000 0 0x400>, 4027 <0 0xae91400 0 0x400>; 4028 4029 interrupt-parent = <&mdss>; 4030 interrupts = <12>; 4031 4032 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4033 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4034 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4035 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4036 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4037 clock-names = "core_iface", 4038 "core_aux", 4039 "ctrl_link", 4040 "ctrl_link_iface", 4041 "stream_pixel"; 4042 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4043 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4044 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4045 phys = <&dp_phy>; 4046 phy-names = "dp"; 4047 4048 operating-points-v2 = <&dp_opp_table>; 4049 power-domains = <&rpmhpd SC7280_CX>; 4050 4051 #sound-dai-cells = <0>; 4052 4053 status = "disabled"; 4054 4055 ports { 4056 #address-cells = <1>; 4057 #size-cells = <0>; 4058 4059 port@0 { 4060 reg = <0>; 4061 dp_in: endpoint { 4062 remote-endpoint = <&dpu_intf0_out>; 4063 }; 4064 }; 4065 4066 port@1 { 4067 reg = <1>; 4068 dp_out: endpoint { }; 4069 }; 4070 }; 4071 4072 dp_opp_table: opp-table { 4073 compatible = "operating-points-v2"; 4074 4075 opp-160000000 { 4076 opp-hz = /bits/ 64 <160000000>; 4077 required-opps = <&rpmhpd_opp_low_svs>; 4078 }; 4079 4080 opp-270000000 { 4081 opp-hz = /bits/ 64 <270000000>; 4082 required-opps = <&rpmhpd_opp_svs>; 4083 }; 4084 4085 opp-540000000 { 4086 opp-hz = /bits/ 64 <540000000>; 4087 required-opps = <&rpmhpd_opp_svs_l1>; 4088 }; 4089 4090 opp-810000000 { 4091 opp-hz = /bits/ 64 <810000000>; 4092 required-opps = <&rpmhpd_opp_nom>; 4093 }; 4094 }; 4095 }; 4096 }; 4097 4098 pdc: interrupt-controller@b220000 { 4099 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4100 reg = <0 0x0b220000 0 0x30000>; 4101 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4102 <55 306 4>, <59 312 3>, <62 374 2>, 4103 <64 434 2>, <66 438 3>, <69 86 1>, 4104 <70 520 54>, <124 609 31>, <155 63 1>, 4105 <156 716 12>; 4106 #interrupt-cells = <2>; 4107 interrupt-parent = <&intc>; 4108 interrupt-controller; 4109 }; 4110 4111 pdc_reset: reset-controller@b5e0000 { 4112 compatible = "qcom,sc7280-pdc-global"; 4113 reg = <0 0x0b5e0000 0 0x20000>; 4114 #reset-cells = <1>; 4115 }; 4116 4117 tsens0: thermal-sensor@c263000 { 4118 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4119 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4120 <0 0x0c222000 0 0x1ff>; /* SROT */ 4121 #qcom,sensors = <15>; 4122 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4123 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4124 interrupt-names = "uplow","critical"; 4125 #thermal-sensor-cells = <1>; 4126 }; 4127 4128 tsens1: thermal-sensor@c265000 { 4129 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4130 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4131 <0 0x0c223000 0 0x1ff>; /* SROT */ 4132 #qcom,sensors = <12>; 4133 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4134 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4135 interrupt-names = "uplow","critical"; 4136 #thermal-sensor-cells = <1>; 4137 }; 4138 4139 aoss_reset: reset-controller@c2a0000 { 4140 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4141 reg = <0 0x0c2a0000 0 0x31000>; 4142 #reset-cells = <1>; 4143 }; 4144 4145 aoss_qmp: power-controller@c300000 { 4146 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4147 reg = <0 0x0c300000 0 0x400>; 4148 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4149 IPCC_MPROC_SIGNAL_GLINK_QMP 4150 IRQ_TYPE_EDGE_RISING>; 4151 mboxes = <&ipcc IPCC_CLIENT_AOP 4152 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4153 4154 #clock-cells = <0>; 4155 }; 4156 4157 sram@c3f0000 { 4158 compatible = "qcom,rpmh-stats"; 4159 reg = <0 0x0c3f0000 0 0x400>; 4160 }; 4161 4162 spmi_bus: spmi@c440000 { 4163 compatible = "qcom,spmi-pmic-arb"; 4164 reg = <0 0x0c440000 0 0x1100>, 4165 <0 0x0c600000 0 0x2000000>, 4166 <0 0x0e600000 0 0x100000>, 4167 <0 0x0e700000 0 0xa0000>, 4168 <0 0x0c40a000 0 0x26000>; 4169 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4170 interrupt-names = "periph_irq"; 4171 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4172 qcom,ee = <0>; 4173 qcom,channel = <0>; 4174 #address-cells = <1>; 4175 #size-cells = <1>; 4176 interrupt-controller; 4177 #interrupt-cells = <4>; 4178 }; 4179 4180 tlmm: pinctrl@f100000 { 4181 compatible = "qcom,sc7280-pinctrl"; 4182 reg = <0 0x0f100000 0 0x300000>; 4183 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4184 gpio-controller; 4185 #gpio-cells = <2>; 4186 interrupt-controller; 4187 #interrupt-cells = <2>; 4188 gpio-ranges = <&tlmm 0 0 175>; 4189 wakeup-parent = <&pdc>; 4190 4191 dp_hot_plug_det: dp-hot-plug-det { 4192 pins = "gpio47"; 4193 function = "dp_hot"; 4194 }; 4195 4196 edp_hot_plug_det: edp-hot-plug-det { 4197 pins = "gpio60"; 4198 function = "edp_hot"; 4199 }; 4200 4201 mi2s0_data0: mi2s0-data0 { 4202 pins = "gpio98"; 4203 function = "mi2s0_data0"; 4204 }; 4205 4206 mi2s0_data1: mi2s0-data1 { 4207 pins = "gpio99"; 4208 function = "mi2s0_data1"; 4209 }; 4210 4211 mi2s0_mclk: mi2s0-mclk { 4212 pins = "gpio96"; 4213 function = "pri_mi2s"; 4214 }; 4215 4216 mi2s0_sclk: mi2s0-sclk { 4217 pins = "gpio97"; 4218 function = "mi2s0_sck"; 4219 }; 4220 4221 mi2s0_ws: mi2s0-ws { 4222 pins = "gpio100"; 4223 function = "mi2s0_ws"; 4224 }; 4225 4226 mi2s1_data0: mi2s1-data0 { 4227 pins = "gpio107"; 4228 function = "mi2s1_data0"; 4229 }; 4230 4231 mi2s1_sclk: mi2s1-sclk { 4232 pins = "gpio106"; 4233 function = "mi2s1_sck"; 4234 }; 4235 4236 mi2s1_ws: mi2s1-ws { 4237 pins = "gpio108"; 4238 function = "mi2s1_ws"; 4239 }; 4240 4241 pcie1_clkreq_n: pcie1-clkreq-n { 4242 pins = "gpio79"; 4243 function = "pcie1_clkreqn"; 4244 }; 4245 4246 qspi_clk: qspi-clk { 4247 pins = "gpio14"; 4248 function = "qspi_clk"; 4249 }; 4250 4251 qspi_cs0: qspi-cs0 { 4252 pins = "gpio15"; 4253 function = "qspi_cs"; 4254 }; 4255 4256 qspi_cs1: qspi-cs1 { 4257 pins = "gpio19"; 4258 function = "qspi_cs"; 4259 }; 4260 4261 qspi_data01: qspi-data01 { 4262 pins = "gpio12", "gpio13"; 4263 function = "qspi_data"; 4264 }; 4265 4266 qspi_data12: qspi-data12 { 4267 pins = "gpio16", "gpio17"; 4268 function = "qspi_data"; 4269 }; 4270 4271 qup_i2c0_data_clk: qup-i2c0-data-clk { 4272 pins = "gpio0", "gpio1"; 4273 function = "qup00"; 4274 }; 4275 4276 qup_i2c1_data_clk: qup-i2c1-data-clk { 4277 pins = "gpio4", "gpio5"; 4278 function = "qup01"; 4279 }; 4280 4281 qup_i2c2_data_clk: qup-i2c2-data-clk { 4282 pins = "gpio8", "gpio9"; 4283 function = "qup02"; 4284 }; 4285 4286 qup_i2c3_data_clk: qup-i2c3-data-clk { 4287 pins = "gpio12", "gpio13"; 4288 function = "qup03"; 4289 }; 4290 4291 qup_i2c4_data_clk: qup-i2c4-data-clk { 4292 pins = "gpio16", "gpio17"; 4293 function = "qup04"; 4294 }; 4295 4296 qup_i2c5_data_clk: qup-i2c5-data-clk { 4297 pins = "gpio20", "gpio21"; 4298 function = "qup05"; 4299 }; 4300 4301 qup_i2c6_data_clk: qup-i2c6-data-clk { 4302 pins = "gpio24", "gpio25"; 4303 function = "qup06"; 4304 }; 4305 4306 qup_i2c7_data_clk: qup-i2c7-data-clk { 4307 pins = "gpio28", "gpio29"; 4308 function = "qup07"; 4309 }; 4310 4311 qup_i2c8_data_clk: qup-i2c8-data-clk { 4312 pins = "gpio32", "gpio33"; 4313 function = "qup10"; 4314 }; 4315 4316 qup_i2c9_data_clk: qup-i2c9-data-clk { 4317 pins = "gpio36", "gpio37"; 4318 function = "qup11"; 4319 }; 4320 4321 qup_i2c10_data_clk: qup-i2c10-data-clk { 4322 pins = "gpio40", "gpio41"; 4323 function = "qup12"; 4324 }; 4325 4326 qup_i2c11_data_clk: qup-i2c11-data-clk { 4327 pins = "gpio44", "gpio45"; 4328 function = "qup13"; 4329 }; 4330 4331 qup_i2c12_data_clk: qup-i2c12-data-clk { 4332 pins = "gpio48", "gpio49"; 4333 function = "qup14"; 4334 }; 4335 4336 qup_i2c13_data_clk: qup-i2c13-data-clk { 4337 pins = "gpio52", "gpio53"; 4338 function = "qup15"; 4339 }; 4340 4341 qup_i2c14_data_clk: qup-i2c14-data-clk { 4342 pins = "gpio56", "gpio57"; 4343 function = "qup16"; 4344 }; 4345 4346 qup_i2c15_data_clk: qup-i2c15-data-clk { 4347 pins = "gpio60", "gpio61"; 4348 function = "qup17"; 4349 }; 4350 4351 qup_spi0_data_clk: qup-spi0-data-clk { 4352 pins = "gpio0", "gpio1", "gpio2"; 4353 function = "qup00"; 4354 }; 4355 4356 qup_spi0_cs: qup-spi0-cs { 4357 pins = "gpio3"; 4358 function = "qup00"; 4359 }; 4360 4361 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 4362 pins = "gpio3"; 4363 function = "gpio"; 4364 }; 4365 4366 qup_spi1_data_clk: qup-spi1-data-clk { 4367 pins = "gpio4", "gpio5", "gpio6"; 4368 function = "qup01"; 4369 }; 4370 4371 qup_spi1_cs: qup-spi1-cs { 4372 pins = "gpio7"; 4373 function = "qup01"; 4374 }; 4375 4376 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 4377 pins = "gpio7"; 4378 function = "gpio"; 4379 }; 4380 4381 qup_spi2_data_clk: qup-spi2-data-clk { 4382 pins = "gpio8", "gpio9", "gpio10"; 4383 function = "qup02"; 4384 }; 4385 4386 qup_spi2_cs: qup-spi2-cs { 4387 pins = "gpio11"; 4388 function = "qup02"; 4389 }; 4390 4391 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 4392 pins = "gpio11"; 4393 function = "gpio"; 4394 }; 4395 4396 qup_spi3_data_clk: qup-spi3-data-clk { 4397 pins = "gpio12", "gpio13", "gpio14"; 4398 function = "qup03"; 4399 }; 4400 4401 qup_spi3_cs: qup-spi3-cs { 4402 pins = "gpio15"; 4403 function = "qup03"; 4404 }; 4405 4406 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 4407 pins = "gpio15"; 4408 function = "gpio"; 4409 }; 4410 4411 qup_spi4_data_clk: qup-spi4-data-clk { 4412 pins = "gpio16", "gpio17", "gpio18"; 4413 function = "qup04"; 4414 }; 4415 4416 qup_spi4_cs: qup-spi4-cs { 4417 pins = "gpio19"; 4418 function = "qup04"; 4419 }; 4420 4421 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 4422 pins = "gpio19"; 4423 function = "gpio"; 4424 }; 4425 4426 qup_spi5_data_clk: qup-spi5-data-clk { 4427 pins = "gpio20", "gpio21", "gpio22"; 4428 function = "qup05"; 4429 }; 4430 4431 qup_spi5_cs: qup-spi5-cs { 4432 pins = "gpio23"; 4433 function = "qup05"; 4434 }; 4435 4436 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 4437 pins = "gpio23"; 4438 function = "gpio"; 4439 }; 4440 4441 qup_spi6_data_clk: qup-spi6-data-clk { 4442 pins = "gpio24", "gpio25", "gpio26"; 4443 function = "qup06"; 4444 }; 4445 4446 qup_spi6_cs: qup-spi6-cs { 4447 pins = "gpio27"; 4448 function = "qup06"; 4449 }; 4450 4451 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 4452 pins = "gpio27"; 4453 function = "gpio"; 4454 }; 4455 4456 qup_spi7_data_clk: qup-spi7-data-clk { 4457 pins = "gpio28", "gpio29", "gpio30"; 4458 function = "qup07"; 4459 }; 4460 4461 qup_spi7_cs: qup-spi7-cs { 4462 pins = "gpio31"; 4463 function = "qup07"; 4464 }; 4465 4466 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 4467 pins = "gpio31"; 4468 function = "gpio"; 4469 }; 4470 4471 qup_spi8_data_clk: qup-spi8-data-clk { 4472 pins = "gpio32", "gpio33", "gpio34"; 4473 function = "qup10"; 4474 }; 4475 4476 qup_spi8_cs: qup-spi8-cs { 4477 pins = "gpio35"; 4478 function = "qup10"; 4479 }; 4480 4481 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 4482 pins = "gpio35"; 4483 function = "gpio"; 4484 }; 4485 4486 qup_spi9_data_clk: qup-spi9-data-clk { 4487 pins = "gpio36", "gpio37", "gpio38"; 4488 function = "qup11"; 4489 }; 4490 4491 qup_spi9_cs: qup-spi9-cs { 4492 pins = "gpio39"; 4493 function = "qup11"; 4494 }; 4495 4496 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 4497 pins = "gpio39"; 4498 function = "gpio"; 4499 }; 4500 4501 qup_spi10_data_clk: qup-spi10-data-clk { 4502 pins = "gpio40", "gpio41", "gpio42"; 4503 function = "qup12"; 4504 }; 4505 4506 qup_spi10_cs: qup-spi10-cs { 4507 pins = "gpio43"; 4508 function = "qup12"; 4509 }; 4510 4511 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 4512 pins = "gpio43"; 4513 function = "gpio"; 4514 }; 4515 4516 qup_spi11_data_clk: qup-spi11-data-clk { 4517 pins = "gpio44", "gpio45", "gpio46"; 4518 function = "qup13"; 4519 }; 4520 4521 qup_spi11_cs: qup-spi11-cs { 4522 pins = "gpio47"; 4523 function = "qup13"; 4524 }; 4525 4526 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 4527 pins = "gpio47"; 4528 function = "gpio"; 4529 }; 4530 4531 qup_spi12_data_clk: qup-spi12-data-clk { 4532 pins = "gpio48", "gpio49", "gpio50"; 4533 function = "qup14"; 4534 }; 4535 4536 qup_spi12_cs: qup-spi12-cs { 4537 pins = "gpio51"; 4538 function = "qup14"; 4539 }; 4540 4541 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 4542 pins = "gpio51"; 4543 function = "gpio"; 4544 }; 4545 4546 qup_spi13_data_clk: qup-spi13-data-clk { 4547 pins = "gpio52", "gpio53", "gpio54"; 4548 function = "qup15"; 4549 }; 4550 4551 qup_spi13_cs: qup-spi13-cs { 4552 pins = "gpio55"; 4553 function = "qup15"; 4554 }; 4555 4556 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 4557 pins = "gpio55"; 4558 function = "gpio"; 4559 }; 4560 4561 qup_spi14_data_clk: qup-spi14-data-clk { 4562 pins = "gpio56", "gpio57", "gpio58"; 4563 function = "qup16"; 4564 }; 4565 4566 qup_spi14_cs: qup-spi14-cs { 4567 pins = "gpio59"; 4568 function = "qup16"; 4569 }; 4570 4571 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 4572 pins = "gpio59"; 4573 function = "gpio"; 4574 }; 4575 4576 qup_spi15_data_clk: qup-spi15-data-clk { 4577 pins = "gpio60", "gpio61", "gpio62"; 4578 function = "qup17"; 4579 }; 4580 4581 qup_spi15_cs: qup-spi15-cs { 4582 pins = "gpio63"; 4583 function = "qup17"; 4584 }; 4585 4586 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 4587 pins = "gpio63"; 4588 function = "gpio"; 4589 }; 4590 4591 qup_uart0_cts: qup-uart0-cts { 4592 pins = "gpio0"; 4593 function = "qup00"; 4594 }; 4595 4596 qup_uart0_rts: qup-uart0-rts { 4597 pins = "gpio1"; 4598 function = "qup00"; 4599 }; 4600 4601 qup_uart0_tx: qup-uart0-tx { 4602 pins = "gpio2"; 4603 function = "qup00"; 4604 }; 4605 4606 qup_uart0_rx: qup-uart0-rx { 4607 pins = "gpio3"; 4608 function = "qup00"; 4609 }; 4610 4611 qup_uart1_cts: qup-uart1-cts { 4612 pins = "gpio4"; 4613 function = "qup01"; 4614 }; 4615 4616 qup_uart1_rts: qup-uart1-rts { 4617 pins = "gpio5"; 4618 function = "qup01"; 4619 }; 4620 4621 qup_uart1_tx: qup-uart1-tx { 4622 pins = "gpio6"; 4623 function = "qup01"; 4624 }; 4625 4626 qup_uart1_rx: qup-uart1-rx { 4627 pins = "gpio7"; 4628 function = "qup01"; 4629 }; 4630 4631 qup_uart2_cts: qup-uart2-cts { 4632 pins = "gpio8"; 4633 function = "qup02"; 4634 }; 4635 4636 qup_uart2_rts: qup-uart2-rts { 4637 pins = "gpio9"; 4638 function = "qup02"; 4639 }; 4640 4641 qup_uart2_tx: qup-uart2-tx { 4642 pins = "gpio10"; 4643 function = "qup02"; 4644 }; 4645 4646 qup_uart2_rx: qup-uart2-rx { 4647 pins = "gpio11"; 4648 function = "qup02"; 4649 }; 4650 4651 qup_uart3_cts: qup-uart3-cts { 4652 pins = "gpio12"; 4653 function = "qup03"; 4654 }; 4655 4656 qup_uart3_rts: qup-uart3-rts { 4657 pins = "gpio13"; 4658 function = "qup03"; 4659 }; 4660 4661 qup_uart3_tx: qup-uart3-tx { 4662 pins = "gpio14"; 4663 function = "qup03"; 4664 }; 4665 4666 qup_uart3_rx: qup-uart3-rx { 4667 pins = "gpio15"; 4668 function = "qup03"; 4669 }; 4670 4671 qup_uart4_cts: qup-uart4-cts { 4672 pins = "gpio16"; 4673 function = "qup04"; 4674 }; 4675 4676 qup_uart4_rts: qup-uart4-rts { 4677 pins = "gpio17"; 4678 function = "qup04"; 4679 }; 4680 4681 qup_uart4_tx: qup-uart4-tx { 4682 pins = "gpio18"; 4683 function = "qup04"; 4684 }; 4685 4686 qup_uart4_rx: qup-uart4-rx { 4687 pins = "gpio19"; 4688 function = "qup04"; 4689 }; 4690 4691 qup_uart5_cts: qup-uart5-cts { 4692 pins = "gpio20"; 4693 function = "qup05"; 4694 }; 4695 4696 qup_uart5_rts: qup-uart5-rts { 4697 pins = "gpio21"; 4698 function = "qup05"; 4699 }; 4700 4701 qup_uart5_tx: qup-uart5-tx { 4702 pins = "gpio22"; 4703 function = "qup05"; 4704 }; 4705 4706 qup_uart5_rx: qup-uart5-rx { 4707 pins = "gpio23"; 4708 function = "qup05"; 4709 }; 4710 4711 qup_uart6_cts: qup-uart6-cts { 4712 pins = "gpio24"; 4713 function = "qup06"; 4714 }; 4715 4716 qup_uart6_rts: qup-uart6-rts { 4717 pins = "gpio25"; 4718 function = "qup06"; 4719 }; 4720 4721 qup_uart6_tx: qup-uart6-tx { 4722 pins = "gpio26"; 4723 function = "qup06"; 4724 }; 4725 4726 qup_uart6_rx: qup-uart6-rx { 4727 pins = "gpio27"; 4728 function = "qup06"; 4729 }; 4730 4731 qup_uart7_cts: qup-uart7-cts { 4732 pins = "gpio28"; 4733 function = "qup07"; 4734 }; 4735 4736 qup_uart7_rts: qup-uart7-rts { 4737 pins = "gpio29"; 4738 function = "qup07"; 4739 }; 4740 4741 qup_uart7_tx: qup-uart7-tx { 4742 pins = "gpio30"; 4743 function = "qup07"; 4744 }; 4745 4746 qup_uart7_rx: qup-uart7-rx { 4747 pins = "gpio31"; 4748 function = "qup07"; 4749 }; 4750 4751 qup_uart8_cts: qup-uart8-cts { 4752 pins = "gpio32"; 4753 function = "qup10"; 4754 }; 4755 4756 qup_uart8_rts: qup-uart8-rts { 4757 pins = "gpio33"; 4758 function = "qup10"; 4759 }; 4760 4761 qup_uart8_tx: qup-uart8-tx { 4762 pins = "gpio34"; 4763 function = "qup10"; 4764 }; 4765 4766 qup_uart8_rx: qup-uart8-rx { 4767 pins = "gpio35"; 4768 function = "qup10"; 4769 }; 4770 4771 qup_uart9_cts: qup-uart9-cts { 4772 pins = "gpio36"; 4773 function = "qup11"; 4774 }; 4775 4776 qup_uart9_rts: qup-uart9-rts { 4777 pins = "gpio37"; 4778 function = "qup11"; 4779 }; 4780 4781 qup_uart9_tx: qup-uart9-tx { 4782 pins = "gpio38"; 4783 function = "qup11"; 4784 }; 4785 4786 qup_uart9_rx: qup-uart9-rx { 4787 pins = "gpio39"; 4788 function = "qup11"; 4789 }; 4790 4791 qup_uart10_cts: qup-uart10-cts { 4792 pins = "gpio40"; 4793 function = "qup12"; 4794 }; 4795 4796 qup_uart10_rts: qup-uart10-rts { 4797 pins = "gpio41"; 4798 function = "qup12"; 4799 }; 4800 4801 qup_uart10_tx: qup-uart10-tx { 4802 pins = "gpio42"; 4803 function = "qup12"; 4804 }; 4805 4806 qup_uart10_rx: qup-uart10-rx { 4807 pins = "gpio43"; 4808 function = "qup12"; 4809 }; 4810 4811 qup_uart11_cts: qup-uart11-cts { 4812 pins = "gpio44"; 4813 function = "qup13"; 4814 }; 4815 4816 qup_uart11_rts: qup-uart11-rts { 4817 pins = "gpio45"; 4818 function = "qup13"; 4819 }; 4820 4821 qup_uart11_tx: qup-uart11-tx { 4822 pins = "gpio46"; 4823 function = "qup13"; 4824 }; 4825 4826 qup_uart11_rx: qup-uart11-rx { 4827 pins = "gpio47"; 4828 function = "qup13"; 4829 }; 4830 4831 qup_uart12_cts: qup-uart12-cts { 4832 pins = "gpio48"; 4833 function = "qup14"; 4834 }; 4835 4836 qup_uart12_rts: qup-uart12-rts { 4837 pins = "gpio49"; 4838 function = "qup14"; 4839 }; 4840 4841 qup_uart12_tx: qup-uart12-tx { 4842 pins = "gpio50"; 4843 function = "qup14"; 4844 }; 4845 4846 qup_uart12_rx: qup-uart12-rx { 4847 pins = "gpio51"; 4848 function = "qup14"; 4849 }; 4850 4851 qup_uart13_cts: qup-uart13-cts { 4852 pins = "gpio52"; 4853 function = "qup15"; 4854 }; 4855 4856 qup_uart13_rts: qup-uart13-rts { 4857 pins = "gpio53"; 4858 function = "qup15"; 4859 }; 4860 4861 qup_uart13_tx: qup-uart13-tx { 4862 pins = "gpio54"; 4863 function = "qup15"; 4864 }; 4865 4866 qup_uart13_rx: qup-uart13-rx { 4867 pins = "gpio55"; 4868 function = "qup15"; 4869 }; 4870 4871 qup_uart14_cts: qup-uart14-cts { 4872 pins = "gpio56"; 4873 function = "qup16"; 4874 }; 4875 4876 qup_uart14_rts: qup-uart14-rts { 4877 pins = "gpio57"; 4878 function = "qup16"; 4879 }; 4880 4881 qup_uart14_tx: qup-uart14-tx { 4882 pins = "gpio58"; 4883 function = "qup16"; 4884 }; 4885 4886 qup_uart14_rx: qup-uart14-rx { 4887 pins = "gpio59"; 4888 function = "qup16"; 4889 }; 4890 4891 qup_uart15_cts: qup-uart15-cts { 4892 pins = "gpio60"; 4893 function = "qup17"; 4894 }; 4895 4896 qup_uart15_rts: qup-uart15-rts { 4897 pins = "gpio61"; 4898 function = "qup17"; 4899 }; 4900 4901 qup_uart15_tx: qup-uart15-tx { 4902 pins = "gpio62"; 4903 function = "qup17"; 4904 }; 4905 4906 qup_uart15_rx: qup-uart15-rx { 4907 pins = "gpio63"; 4908 function = "qup17"; 4909 }; 4910 4911 sdc1_clk: sdc1-clk { 4912 pins = "sdc1_clk"; 4913 }; 4914 4915 sdc1_cmd: sdc1-cmd { 4916 pins = "sdc1_cmd"; 4917 }; 4918 4919 sdc1_data: sdc1-data { 4920 pins = "sdc1_data"; 4921 }; 4922 4923 sdc1_rclk: sdc1-rclk { 4924 pins = "sdc1_rclk"; 4925 }; 4926 4927 sdc1_clk_sleep: sdc1-clk-sleep { 4928 pins = "sdc1_clk"; 4929 drive-strength = <2>; 4930 bias-bus-hold; 4931 }; 4932 4933 sdc1_cmd_sleep: sdc1-cmd-sleep { 4934 pins = "sdc1_cmd"; 4935 drive-strength = <2>; 4936 bias-bus-hold; 4937 }; 4938 4939 sdc1_data_sleep: sdc1-data-sleep { 4940 pins = "sdc1_data"; 4941 drive-strength = <2>; 4942 bias-bus-hold; 4943 }; 4944 4945 sdc1_rclk_sleep: sdc1-rclk-sleep { 4946 pins = "sdc1_rclk"; 4947 drive-strength = <2>; 4948 bias-bus-hold; 4949 }; 4950 4951 sdc2_clk: sdc2-clk { 4952 pins = "sdc2_clk"; 4953 }; 4954 4955 sdc2_cmd: sdc2-cmd { 4956 pins = "sdc2_cmd"; 4957 }; 4958 4959 sdc2_data: sdc2-data { 4960 pins = "sdc2_data"; 4961 }; 4962 4963 sdc2_clk_sleep: sdc2-clk-sleep { 4964 pins = "sdc2_clk"; 4965 drive-strength = <2>; 4966 bias-bus-hold; 4967 }; 4968 4969 sdc2_cmd_sleep: sdc2-cmd-sleep { 4970 pins = "sdc2_cmd"; 4971 drive-strength = <2>; 4972 bias-bus-hold; 4973 }; 4974 4975 sdc2_data_sleep: sdc2-data-sleep { 4976 pins = "sdc2_data"; 4977 drive-strength = <2>; 4978 bias-bus-hold; 4979 }; 4980 }; 4981 4982 sram@146a5000 { 4983 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 4984 reg = <0 0x146a5000 0 0x6000>; 4985 4986 #address-cells = <1>; 4987 #size-cells = <1>; 4988 4989 ranges = <0 0 0x146a5000 0x6000>; 4990 4991 pil-reloc@594c { 4992 compatible = "qcom,pil-reloc-info"; 4993 reg = <0x594c 0xc8>; 4994 }; 4995 }; 4996 4997 apps_smmu: iommu@15000000 { 4998 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 4999 reg = <0 0x15000000 0 0x100000>; 5000 #iommu-cells = <2>; 5001 #global-interrupts = <1>; 5002 dma-coherent; 5003 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5004 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5005 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5006 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5007 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5008 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5009 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5010 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5011 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5012 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5013 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5014 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5015 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5016 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5017 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5018 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5019 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5020 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5021 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5022 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5023 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5024 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5025 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5026 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5027 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5028 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5029 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5030 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5031 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5032 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5033 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5034 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5035 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5036 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5037 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5038 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5039 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5040 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5041 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5042 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5043 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5044 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5045 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5046 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5047 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5048 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5049 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5050 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5051 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5052 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5053 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5054 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5055 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5056 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5057 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5058 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5059 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5060 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5061 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5062 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5063 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5064 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5065 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5066 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5067 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5068 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5069 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5070 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5071 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5072 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5073 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5074 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5075 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5076 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5077 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5078 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5079 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5080 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5081 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5082 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5083 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5084 }; 5085 5086 intc: interrupt-controller@17a00000 { 5087 compatible = "arm,gic-v3"; 5088 #address-cells = <2>; 5089 #size-cells = <2>; 5090 ranges; 5091 #interrupt-cells = <3>; 5092 interrupt-controller; 5093 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5094 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5095 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5096 5097 gic-its@17a40000 { 5098 compatible = "arm,gic-v3-its"; 5099 msi-controller; 5100 #msi-cells = <1>; 5101 reg = <0 0x17a40000 0 0x20000>; 5102 status = "disabled"; 5103 }; 5104 }; 5105 5106 watchdog@17c10000 { 5107 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5108 reg = <0 0x17c10000 0 0x1000>; 5109 clocks = <&sleep_clk>; 5110 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5111 }; 5112 5113 timer@17c20000 { 5114 #address-cells = <1>; 5115 #size-cells = <1>; 5116 ranges = <0 0 0 0x20000000>; 5117 compatible = "arm,armv7-timer-mem"; 5118 reg = <0 0x17c20000 0 0x1000>; 5119 5120 frame@17c21000 { 5121 frame-number = <0>; 5122 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5124 reg = <0x17c21000 0x1000>, 5125 <0x17c22000 0x1000>; 5126 }; 5127 5128 frame@17c23000 { 5129 frame-number = <1>; 5130 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5131 reg = <0x17c23000 0x1000>; 5132 status = "disabled"; 5133 }; 5134 5135 frame@17c25000 { 5136 frame-number = <2>; 5137 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5138 reg = <0x17c25000 0x1000>; 5139 status = "disabled"; 5140 }; 5141 5142 frame@17c27000 { 5143 frame-number = <3>; 5144 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5145 reg = <0x17c27000 0x1000>; 5146 status = "disabled"; 5147 }; 5148 5149 frame@17c29000 { 5150 frame-number = <4>; 5151 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5152 reg = <0x17c29000 0x1000>; 5153 status = "disabled"; 5154 }; 5155 5156 frame@17c2b000 { 5157 frame-number = <5>; 5158 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5159 reg = <0x17c2b000 0x1000>; 5160 status = "disabled"; 5161 }; 5162 5163 frame@17c2d000 { 5164 frame-number = <6>; 5165 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5166 reg = <0x17c2d000 0x1000>; 5167 status = "disabled"; 5168 }; 5169 }; 5170 5171 apps_rsc: rsc@18200000 { 5172 compatible = "qcom,rpmh-rsc"; 5173 reg = <0 0x18200000 0 0x10000>, 5174 <0 0x18210000 0 0x10000>, 5175 <0 0x18220000 0 0x10000>; 5176 reg-names = "drv-0", "drv-1", "drv-2"; 5177 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5178 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5179 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5180 qcom,tcs-offset = <0xd00>; 5181 qcom,drv-id = <2>; 5182 qcom,tcs-config = <ACTIVE_TCS 2>, 5183 <SLEEP_TCS 3>, 5184 <WAKE_TCS 3>, 5185 <CONTROL_TCS 1>; 5186 5187 apps_bcm_voter: bcm-voter { 5188 compatible = "qcom,bcm-voter"; 5189 }; 5190 5191 rpmhpd: power-controller { 5192 compatible = "qcom,sc7280-rpmhpd"; 5193 #power-domain-cells = <1>; 5194 operating-points-v2 = <&rpmhpd_opp_table>; 5195 5196 rpmhpd_opp_table: opp-table { 5197 compatible = "operating-points-v2"; 5198 5199 rpmhpd_opp_ret: opp1 { 5200 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5201 }; 5202 5203 rpmhpd_opp_low_svs: opp2 { 5204 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5205 }; 5206 5207 rpmhpd_opp_svs: opp3 { 5208 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5209 }; 5210 5211 rpmhpd_opp_svs_l1: opp4 { 5212 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5213 }; 5214 5215 rpmhpd_opp_svs_l2: opp5 { 5216 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5217 }; 5218 5219 rpmhpd_opp_nom: opp6 { 5220 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5221 }; 5222 5223 rpmhpd_opp_nom_l1: opp7 { 5224 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5225 }; 5226 5227 rpmhpd_opp_turbo: opp8 { 5228 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5229 }; 5230 5231 rpmhpd_opp_turbo_l1: opp9 { 5232 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5233 }; 5234 }; 5235 }; 5236 5237 rpmhcc: clock-controller { 5238 compatible = "qcom,sc7280-rpmh-clk"; 5239 clocks = <&xo_board>; 5240 clock-names = "xo"; 5241 #clock-cells = <1>; 5242 }; 5243 }; 5244 5245 epss_l3: interconnect@18590000 { 5246 compatible = "qcom,sc7280-epss-l3"; 5247 reg = <0 0x18590000 0 0x1000>; 5248 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5249 clock-names = "xo", "alternate"; 5250 #interconnect-cells = <1>; 5251 }; 5252 5253 cpufreq_hw: cpufreq@18591000 { 5254 compatible = "qcom,cpufreq-epss"; 5255 reg = <0 0x18591000 0 0x1000>, 5256 <0 0x18592000 0 0x1000>, 5257 <0 0x18593000 0 0x1000>; 5258 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5259 clock-names = "xo", "alternate"; 5260 #freq-domain-cells = <1>; 5261 }; 5262 }; 5263 5264 thermal_zones: thermal-zones { 5265 cpu0-thermal { 5266 polling-delay-passive = <250>; 5267 polling-delay = <0>; 5268 5269 thermal-sensors = <&tsens0 1>; 5270 5271 trips { 5272 cpu0_alert0: trip-point0 { 5273 temperature = <90000>; 5274 hysteresis = <2000>; 5275 type = "passive"; 5276 }; 5277 5278 cpu0_alert1: trip-point1 { 5279 temperature = <95000>; 5280 hysteresis = <2000>; 5281 type = "passive"; 5282 }; 5283 5284 cpu0_crit: cpu-crit { 5285 temperature = <110000>; 5286 hysteresis = <0>; 5287 type = "critical"; 5288 }; 5289 }; 5290 5291 cooling-maps { 5292 map0 { 5293 trip = <&cpu0_alert0>; 5294 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5295 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5296 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5297 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5298 }; 5299 map1 { 5300 trip = <&cpu0_alert1>; 5301 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5302 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5303 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5304 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5305 }; 5306 }; 5307 }; 5308 5309 cpu1-thermal { 5310 polling-delay-passive = <250>; 5311 polling-delay = <0>; 5312 5313 thermal-sensors = <&tsens0 2>; 5314 5315 trips { 5316 cpu1_alert0: trip-point0 { 5317 temperature = <90000>; 5318 hysteresis = <2000>; 5319 type = "passive"; 5320 }; 5321 5322 cpu1_alert1: trip-point1 { 5323 temperature = <95000>; 5324 hysteresis = <2000>; 5325 type = "passive"; 5326 }; 5327 5328 cpu1_crit: cpu-crit { 5329 temperature = <110000>; 5330 hysteresis = <0>; 5331 type = "critical"; 5332 }; 5333 }; 5334 5335 cooling-maps { 5336 map0 { 5337 trip = <&cpu1_alert0>; 5338 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5339 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5340 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5341 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5342 }; 5343 map1 { 5344 trip = <&cpu1_alert1>; 5345 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5346 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5347 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5348 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5349 }; 5350 }; 5351 }; 5352 5353 cpu2-thermal { 5354 polling-delay-passive = <250>; 5355 polling-delay = <0>; 5356 5357 thermal-sensors = <&tsens0 3>; 5358 5359 trips { 5360 cpu2_alert0: trip-point0 { 5361 temperature = <90000>; 5362 hysteresis = <2000>; 5363 type = "passive"; 5364 }; 5365 5366 cpu2_alert1: trip-point1 { 5367 temperature = <95000>; 5368 hysteresis = <2000>; 5369 type = "passive"; 5370 }; 5371 5372 cpu2_crit: cpu-crit { 5373 temperature = <110000>; 5374 hysteresis = <0>; 5375 type = "critical"; 5376 }; 5377 }; 5378 5379 cooling-maps { 5380 map0 { 5381 trip = <&cpu2_alert0>; 5382 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5383 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5384 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5385 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5386 }; 5387 map1 { 5388 trip = <&cpu2_alert1>; 5389 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5390 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5391 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5392 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5393 }; 5394 }; 5395 }; 5396 5397 cpu3-thermal { 5398 polling-delay-passive = <250>; 5399 polling-delay = <0>; 5400 5401 thermal-sensors = <&tsens0 4>; 5402 5403 trips { 5404 cpu3_alert0: trip-point0 { 5405 temperature = <90000>; 5406 hysteresis = <2000>; 5407 type = "passive"; 5408 }; 5409 5410 cpu3_alert1: trip-point1 { 5411 temperature = <95000>; 5412 hysteresis = <2000>; 5413 type = "passive"; 5414 }; 5415 5416 cpu3_crit: cpu-crit { 5417 temperature = <110000>; 5418 hysteresis = <0>; 5419 type = "critical"; 5420 }; 5421 }; 5422 5423 cooling-maps { 5424 map0 { 5425 trip = <&cpu3_alert0>; 5426 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5427 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5428 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5429 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5430 }; 5431 map1 { 5432 trip = <&cpu3_alert1>; 5433 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5434 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5435 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5436 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5437 }; 5438 }; 5439 }; 5440 5441 cpu4-thermal { 5442 polling-delay-passive = <250>; 5443 polling-delay = <0>; 5444 5445 thermal-sensors = <&tsens0 7>; 5446 5447 trips { 5448 cpu4_alert0: trip-point0 { 5449 temperature = <90000>; 5450 hysteresis = <2000>; 5451 type = "passive"; 5452 }; 5453 5454 cpu4_alert1: trip-point1 { 5455 temperature = <95000>; 5456 hysteresis = <2000>; 5457 type = "passive"; 5458 }; 5459 5460 cpu4_crit: cpu-crit { 5461 temperature = <110000>; 5462 hysteresis = <0>; 5463 type = "critical"; 5464 }; 5465 }; 5466 5467 cooling-maps { 5468 map0 { 5469 trip = <&cpu4_alert0>; 5470 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5471 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5472 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5473 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5474 }; 5475 map1 { 5476 trip = <&cpu4_alert1>; 5477 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5478 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5479 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5480 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5481 }; 5482 }; 5483 }; 5484 5485 cpu5-thermal { 5486 polling-delay-passive = <250>; 5487 polling-delay = <0>; 5488 5489 thermal-sensors = <&tsens0 8>; 5490 5491 trips { 5492 cpu5_alert0: trip-point0 { 5493 temperature = <90000>; 5494 hysteresis = <2000>; 5495 type = "passive"; 5496 }; 5497 5498 cpu5_alert1: trip-point1 { 5499 temperature = <95000>; 5500 hysteresis = <2000>; 5501 type = "passive"; 5502 }; 5503 5504 cpu5_crit: cpu-crit { 5505 temperature = <110000>; 5506 hysteresis = <0>; 5507 type = "critical"; 5508 }; 5509 }; 5510 5511 cooling-maps { 5512 map0 { 5513 trip = <&cpu5_alert0>; 5514 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5515 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5516 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5517 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5518 }; 5519 map1 { 5520 trip = <&cpu5_alert1>; 5521 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5522 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5523 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5524 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5525 }; 5526 }; 5527 }; 5528 5529 cpu6-thermal { 5530 polling-delay-passive = <250>; 5531 polling-delay = <0>; 5532 5533 thermal-sensors = <&tsens0 9>; 5534 5535 trips { 5536 cpu6_alert0: trip-point0 { 5537 temperature = <90000>; 5538 hysteresis = <2000>; 5539 type = "passive"; 5540 }; 5541 5542 cpu6_alert1: trip-point1 { 5543 temperature = <95000>; 5544 hysteresis = <2000>; 5545 type = "passive"; 5546 }; 5547 5548 cpu6_crit: cpu-crit { 5549 temperature = <110000>; 5550 hysteresis = <0>; 5551 type = "critical"; 5552 }; 5553 }; 5554 5555 cooling-maps { 5556 map0 { 5557 trip = <&cpu6_alert0>; 5558 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5559 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5560 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5561 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5562 }; 5563 map1 { 5564 trip = <&cpu6_alert1>; 5565 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5566 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5567 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5568 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5569 }; 5570 }; 5571 }; 5572 5573 cpu7-thermal { 5574 polling-delay-passive = <250>; 5575 polling-delay = <0>; 5576 5577 thermal-sensors = <&tsens0 10>; 5578 5579 trips { 5580 cpu7_alert0: trip-point0 { 5581 temperature = <90000>; 5582 hysteresis = <2000>; 5583 type = "passive"; 5584 }; 5585 5586 cpu7_alert1: trip-point1 { 5587 temperature = <95000>; 5588 hysteresis = <2000>; 5589 type = "passive"; 5590 }; 5591 5592 cpu7_crit: cpu-crit { 5593 temperature = <110000>; 5594 hysteresis = <0>; 5595 type = "critical"; 5596 }; 5597 }; 5598 5599 cooling-maps { 5600 map0 { 5601 trip = <&cpu7_alert0>; 5602 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5603 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5604 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5605 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5606 }; 5607 map1 { 5608 trip = <&cpu7_alert1>; 5609 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5610 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5611 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5612 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5613 }; 5614 }; 5615 }; 5616 5617 cpu8-thermal { 5618 polling-delay-passive = <250>; 5619 polling-delay = <0>; 5620 5621 thermal-sensors = <&tsens0 11>; 5622 5623 trips { 5624 cpu8_alert0: trip-point0 { 5625 temperature = <90000>; 5626 hysteresis = <2000>; 5627 type = "passive"; 5628 }; 5629 5630 cpu8_alert1: trip-point1 { 5631 temperature = <95000>; 5632 hysteresis = <2000>; 5633 type = "passive"; 5634 }; 5635 5636 cpu8_crit: cpu-crit { 5637 temperature = <110000>; 5638 hysteresis = <0>; 5639 type = "critical"; 5640 }; 5641 }; 5642 5643 cooling-maps { 5644 map0 { 5645 trip = <&cpu8_alert0>; 5646 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5647 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5648 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5649 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5650 }; 5651 map1 { 5652 trip = <&cpu8_alert1>; 5653 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5654 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5655 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5656 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5657 }; 5658 }; 5659 }; 5660 5661 cpu9-thermal { 5662 polling-delay-passive = <250>; 5663 polling-delay = <0>; 5664 5665 thermal-sensors = <&tsens0 12>; 5666 5667 trips { 5668 cpu9_alert0: trip-point0 { 5669 temperature = <90000>; 5670 hysteresis = <2000>; 5671 type = "passive"; 5672 }; 5673 5674 cpu9_alert1: trip-point1 { 5675 temperature = <95000>; 5676 hysteresis = <2000>; 5677 type = "passive"; 5678 }; 5679 5680 cpu9_crit: cpu-crit { 5681 temperature = <110000>; 5682 hysteresis = <0>; 5683 type = "critical"; 5684 }; 5685 }; 5686 5687 cooling-maps { 5688 map0 { 5689 trip = <&cpu9_alert0>; 5690 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5691 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5692 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5693 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5694 }; 5695 map1 { 5696 trip = <&cpu9_alert1>; 5697 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5698 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5699 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5700 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5701 }; 5702 }; 5703 }; 5704 5705 cpu10-thermal { 5706 polling-delay-passive = <250>; 5707 polling-delay = <0>; 5708 5709 thermal-sensors = <&tsens0 13>; 5710 5711 trips { 5712 cpu10_alert0: trip-point0 { 5713 temperature = <90000>; 5714 hysteresis = <2000>; 5715 type = "passive"; 5716 }; 5717 5718 cpu10_alert1: trip-point1 { 5719 temperature = <95000>; 5720 hysteresis = <2000>; 5721 type = "passive"; 5722 }; 5723 5724 cpu10_crit: cpu-crit { 5725 temperature = <110000>; 5726 hysteresis = <0>; 5727 type = "critical"; 5728 }; 5729 }; 5730 5731 cooling-maps { 5732 map0 { 5733 trip = <&cpu10_alert0>; 5734 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5735 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5736 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5737 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5738 }; 5739 map1 { 5740 trip = <&cpu10_alert1>; 5741 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5742 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5743 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5744 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5745 }; 5746 }; 5747 }; 5748 5749 cpu11-thermal { 5750 polling-delay-passive = <250>; 5751 polling-delay = <0>; 5752 5753 thermal-sensors = <&tsens0 14>; 5754 5755 trips { 5756 cpu11_alert0: trip-point0 { 5757 temperature = <90000>; 5758 hysteresis = <2000>; 5759 type = "passive"; 5760 }; 5761 5762 cpu11_alert1: trip-point1 { 5763 temperature = <95000>; 5764 hysteresis = <2000>; 5765 type = "passive"; 5766 }; 5767 5768 cpu11_crit: cpu-crit { 5769 temperature = <110000>; 5770 hysteresis = <0>; 5771 type = "critical"; 5772 }; 5773 }; 5774 5775 cooling-maps { 5776 map0 { 5777 trip = <&cpu11_alert0>; 5778 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5779 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5780 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5781 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5782 }; 5783 map1 { 5784 trip = <&cpu11_alert1>; 5785 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5786 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5787 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5788 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5789 }; 5790 }; 5791 }; 5792 5793 aoss0-thermal { 5794 polling-delay-passive = <0>; 5795 polling-delay = <0>; 5796 5797 thermal-sensors = <&tsens0 0>; 5798 5799 trips { 5800 aoss0_alert0: trip-point0 { 5801 temperature = <90000>; 5802 hysteresis = <2000>; 5803 type = "hot"; 5804 }; 5805 5806 aoss0_crit: aoss0-crit { 5807 temperature = <110000>; 5808 hysteresis = <0>; 5809 type = "critical"; 5810 }; 5811 }; 5812 }; 5813 5814 aoss1-thermal { 5815 polling-delay-passive = <0>; 5816 polling-delay = <0>; 5817 5818 thermal-sensors = <&tsens1 0>; 5819 5820 trips { 5821 aoss1_alert0: trip-point0 { 5822 temperature = <90000>; 5823 hysteresis = <2000>; 5824 type = "hot"; 5825 }; 5826 5827 aoss1_crit: aoss1-crit { 5828 temperature = <110000>; 5829 hysteresis = <0>; 5830 type = "critical"; 5831 }; 5832 }; 5833 }; 5834 5835 cpuss0-thermal { 5836 polling-delay-passive = <0>; 5837 polling-delay = <0>; 5838 5839 thermal-sensors = <&tsens0 5>; 5840 5841 trips { 5842 cpuss0_alert0: trip-point0 { 5843 temperature = <90000>; 5844 hysteresis = <2000>; 5845 type = "hot"; 5846 }; 5847 cpuss0_crit: cluster0-crit { 5848 temperature = <110000>; 5849 hysteresis = <0>; 5850 type = "critical"; 5851 }; 5852 }; 5853 }; 5854 5855 cpuss1-thermal { 5856 polling-delay-passive = <0>; 5857 polling-delay = <0>; 5858 5859 thermal-sensors = <&tsens0 6>; 5860 5861 trips { 5862 cpuss1_alert0: trip-point0 { 5863 temperature = <90000>; 5864 hysteresis = <2000>; 5865 type = "hot"; 5866 }; 5867 cpuss1_crit: cluster0-crit { 5868 temperature = <110000>; 5869 hysteresis = <0>; 5870 type = "critical"; 5871 }; 5872 }; 5873 }; 5874 5875 gpuss0-thermal { 5876 polling-delay-passive = <100>; 5877 polling-delay = <0>; 5878 5879 thermal-sensors = <&tsens1 1>; 5880 5881 trips { 5882 gpuss0_alert0: trip-point0 { 5883 temperature = <95000>; 5884 hysteresis = <2000>; 5885 type = "passive"; 5886 }; 5887 5888 gpuss0_crit: gpuss0-crit { 5889 temperature = <110000>; 5890 hysteresis = <0>; 5891 type = "critical"; 5892 }; 5893 }; 5894 5895 cooling-maps { 5896 map0 { 5897 trip = <&gpuss0_alert0>; 5898 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5899 }; 5900 }; 5901 }; 5902 5903 gpuss1-thermal { 5904 polling-delay-passive = <100>; 5905 polling-delay = <0>; 5906 5907 thermal-sensors = <&tsens1 2>; 5908 5909 trips { 5910 gpuss1_alert0: trip-point0 { 5911 temperature = <95000>; 5912 hysteresis = <2000>; 5913 type = "passive"; 5914 }; 5915 5916 gpuss1_crit: gpuss1-crit { 5917 temperature = <110000>; 5918 hysteresis = <0>; 5919 type = "critical"; 5920 }; 5921 }; 5922 5923 cooling-maps { 5924 map0 { 5925 trip = <&gpuss1_alert0>; 5926 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5927 }; 5928 }; 5929 }; 5930 5931 nspss0-thermal { 5932 polling-delay-passive = <0>; 5933 polling-delay = <0>; 5934 5935 thermal-sensors = <&tsens1 3>; 5936 5937 trips { 5938 nspss0_alert0: trip-point0 { 5939 temperature = <90000>; 5940 hysteresis = <2000>; 5941 type = "hot"; 5942 }; 5943 5944 nspss0_crit: nspss0-crit { 5945 temperature = <110000>; 5946 hysteresis = <0>; 5947 type = "critical"; 5948 }; 5949 }; 5950 }; 5951 5952 nspss1-thermal { 5953 polling-delay-passive = <0>; 5954 polling-delay = <0>; 5955 5956 thermal-sensors = <&tsens1 4>; 5957 5958 trips { 5959 nspss1_alert0: trip-point0 { 5960 temperature = <90000>; 5961 hysteresis = <2000>; 5962 type = "hot"; 5963 }; 5964 5965 nspss1_crit: nspss1-crit { 5966 temperature = <110000>; 5967 hysteresis = <0>; 5968 type = "critical"; 5969 }; 5970 }; 5971 }; 5972 5973 video-thermal { 5974 polling-delay-passive = <0>; 5975 polling-delay = <0>; 5976 5977 thermal-sensors = <&tsens1 5>; 5978 5979 trips { 5980 video_alert0: trip-point0 { 5981 temperature = <90000>; 5982 hysteresis = <2000>; 5983 type = "hot"; 5984 }; 5985 5986 video_crit: video-crit { 5987 temperature = <110000>; 5988 hysteresis = <0>; 5989 type = "critical"; 5990 }; 5991 }; 5992 }; 5993 5994 ddr-thermal { 5995 polling-delay-passive = <0>; 5996 polling-delay = <0>; 5997 5998 thermal-sensors = <&tsens1 6>; 5999 6000 trips { 6001 ddr_alert0: trip-point0 { 6002 temperature = <90000>; 6003 hysteresis = <2000>; 6004 type = "hot"; 6005 }; 6006 6007 ddr_crit: ddr-crit { 6008 temperature = <110000>; 6009 hysteresis = <0>; 6010 type = "critical"; 6011 }; 6012 }; 6013 }; 6014 6015 mdmss0-thermal { 6016 polling-delay-passive = <0>; 6017 polling-delay = <0>; 6018 6019 thermal-sensors = <&tsens1 7>; 6020 6021 trips { 6022 mdmss0_alert0: trip-point0 { 6023 temperature = <90000>; 6024 hysteresis = <2000>; 6025 type = "hot"; 6026 }; 6027 6028 mdmss0_crit: mdmss0-crit { 6029 temperature = <110000>; 6030 hysteresis = <0>; 6031 type = "critical"; 6032 }; 6033 }; 6034 }; 6035 6036 mdmss1-thermal { 6037 polling-delay-passive = <0>; 6038 polling-delay = <0>; 6039 6040 thermal-sensors = <&tsens1 8>; 6041 6042 trips { 6043 mdmss1_alert0: trip-point0 { 6044 temperature = <90000>; 6045 hysteresis = <2000>; 6046 type = "hot"; 6047 }; 6048 6049 mdmss1_crit: mdmss1-crit { 6050 temperature = <110000>; 6051 hysteresis = <0>; 6052 type = "critical"; 6053 }; 6054 }; 6055 }; 6056 6057 mdmss2-thermal { 6058 polling-delay-passive = <0>; 6059 polling-delay = <0>; 6060 6061 thermal-sensors = <&tsens1 9>; 6062 6063 trips { 6064 mdmss2_alert0: trip-point0 { 6065 temperature = <90000>; 6066 hysteresis = <2000>; 6067 type = "hot"; 6068 }; 6069 6070 mdmss2_crit: mdmss2-crit { 6071 temperature = <110000>; 6072 hysteresis = <0>; 6073 type = "critical"; 6074 }; 6075 }; 6076 }; 6077 6078 mdmss3-thermal { 6079 polling-delay-passive = <0>; 6080 polling-delay = <0>; 6081 6082 thermal-sensors = <&tsens1 10>; 6083 6084 trips { 6085 mdmss3_alert0: trip-point0 { 6086 temperature = <90000>; 6087 hysteresis = <2000>; 6088 type = "hot"; 6089 }; 6090 6091 mdmss3_crit: mdmss3-crit { 6092 temperature = <110000>; 6093 hysteresis = <0>; 6094 type = "critical"; 6095 }; 6096 }; 6097 }; 6098 6099 camera0-thermal { 6100 polling-delay-passive = <0>; 6101 polling-delay = <0>; 6102 6103 thermal-sensors = <&tsens1 11>; 6104 6105 trips { 6106 camera0_alert0: trip-point0 { 6107 temperature = <90000>; 6108 hysteresis = <2000>; 6109 type = "hot"; 6110 }; 6111 6112 camera0_crit: camera0-crit { 6113 temperature = <110000>; 6114 hysteresis = <0>; 6115 type = "critical"; 6116 }; 6117 }; 6118 }; 6119 }; 6120 6121 timer { 6122 compatible = "arm,armv8-timer"; 6123 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6124 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6125 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6126 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6127 }; 6128}; 6129