1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,lpass.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 mmc1 = &sdhc_1; 54 mmc2 = &sdhc_2; 55 spi0 = &spi0; 56 spi1 = &spi1; 57 spi2 = &spi2; 58 spi3 = &spi3; 59 spi4 = &spi4; 60 spi5 = &spi5; 61 spi6 = &spi6; 62 spi7 = &spi7; 63 spi8 = &spi8; 64 spi9 = &spi9; 65 spi10 = &spi10; 66 spi11 = &spi11; 67 spi12 = &spi12; 68 spi13 = &spi13; 69 spi14 = &spi14; 70 spi15 = &spi15; 71 }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 clock-frequency = <76800000>; 77 #clock-cells = <0>; 78 }; 79 80 sleep_clk: sleep-clk { 81 compatible = "fixed-clock"; 82 clock-frequency = <32000>; 83 #clock-cells = <0>; 84 }; 85 }; 86 87 reserved-memory { 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges; 91 92 wlan_ce_mem: memory@4cd000 { 93 no-map; 94 reg = <0x0 0x004cd000 0x0 0x1000>; 95 }; 96 97 hyp_mem: memory@80000000 { 98 reg = <0x0 0x80000000 0x0 0x600000>; 99 no-map; 100 }; 101 102 xbl_mem: memory@80600000 { 103 reg = <0x0 0x80600000 0x0 0x200000>; 104 no-map; 105 }; 106 107 aop_mem: memory@80800000 { 108 reg = <0x0 0x80800000 0x0 0x60000>; 109 no-map; 110 }; 111 112 aop_cmd_db_mem: memory@80860000 { 113 reg = <0x0 0x80860000 0x0 0x20000>; 114 compatible = "qcom,cmd-db"; 115 no-map; 116 }; 117 118 reserved_xbl_uefi_log: memory@80880000 { 119 reg = <0x0 0x80884000 0x0 0x10000>; 120 no-map; 121 }; 122 123 sec_apps_mem: memory@808ff000 { 124 reg = <0x0 0x808ff000 0x0 0x1000>; 125 no-map; 126 }; 127 128 smem_mem: memory@80900000 { 129 reg = <0x0 0x80900000 0x0 0x200000>; 130 no-map; 131 }; 132 133 cpucp_mem: memory@80b00000 { 134 no-map; 135 reg = <0x0 0x80b00000 0x0 0x100000>; 136 }; 137 138 wlan_fw_mem: memory@80c00000 { 139 reg = <0x0 0x80c00000 0x0 0xc00000>; 140 no-map; 141 }; 142 143 video_mem: memory@8b200000 { 144 reg = <0x0 0x8b200000 0x0 0x500000>; 145 no-map; 146 }; 147 148 ipa_fw_mem: memory@8b700000 { 149 reg = <0 0x8b700000 0 0x10000>; 150 no-map; 151 }; 152 153 rmtfs_mem: memory@9c900000 { 154 compatible = "qcom,rmtfs-mem"; 155 reg = <0x0 0x9c900000 0x0 0x280000>; 156 no-map; 157 158 qcom,client-id = <1>; 159 qcom,vmid = <15>; 160 }; 161 }; 162 163 cpus { 164 #address-cells = <2>; 165 #size-cells = <0>; 166 167 CPU0: cpu@0 { 168 device_type = "cpu"; 169 compatible = "qcom,kryo"; 170 reg = <0x0 0x0>; 171 clocks = <&cpufreq_hw 0>; 172 enable-method = "psci"; 173 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 174 &LITTLE_CPU_SLEEP_1 175 &CLUSTER_SLEEP_0>; 176 next-level-cache = <&L2_0>; 177 operating-points-v2 = <&cpu0_opp_table>; 178 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 179 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 180 qcom,freq-domain = <&cpufreq_hw 0>; 181 #cooling-cells = <2>; 182 L2_0: l2-cache { 183 compatible = "cache"; 184 cache-level = <2>; 185 next-level-cache = <&L3_0>; 186 L3_0: l3-cache { 187 compatible = "cache"; 188 cache-level = <3>; 189 }; 190 }; 191 }; 192 193 CPU1: cpu@100 { 194 device_type = "cpu"; 195 compatible = "qcom,kryo"; 196 reg = <0x0 0x100>; 197 clocks = <&cpufreq_hw 0>; 198 enable-method = "psci"; 199 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 200 &LITTLE_CPU_SLEEP_1 201 &CLUSTER_SLEEP_0>; 202 next-level-cache = <&L2_100>; 203 operating-points-v2 = <&cpu0_opp_table>; 204 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 205 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 206 qcom,freq-domain = <&cpufreq_hw 0>; 207 #cooling-cells = <2>; 208 L2_100: l2-cache { 209 compatible = "cache"; 210 cache-level = <2>; 211 next-level-cache = <&L3_0>; 212 }; 213 }; 214 215 CPU2: cpu@200 { 216 device_type = "cpu"; 217 compatible = "qcom,kryo"; 218 reg = <0x0 0x200>; 219 clocks = <&cpufreq_hw 0>; 220 enable-method = "psci"; 221 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 222 &LITTLE_CPU_SLEEP_1 223 &CLUSTER_SLEEP_0>; 224 next-level-cache = <&L2_200>; 225 operating-points-v2 = <&cpu0_opp_table>; 226 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 227 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 228 qcom,freq-domain = <&cpufreq_hw 0>; 229 #cooling-cells = <2>; 230 L2_200: l2-cache { 231 compatible = "cache"; 232 cache-level = <2>; 233 next-level-cache = <&L3_0>; 234 }; 235 }; 236 237 CPU3: cpu@300 { 238 device_type = "cpu"; 239 compatible = "qcom,kryo"; 240 reg = <0x0 0x300>; 241 clocks = <&cpufreq_hw 0>; 242 enable-method = "psci"; 243 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 244 &LITTLE_CPU_SLEEP_1 245 &CLUSTER_SLEEP_0>; 246 next-level-cache = <&L2_300>; 247 operating-points-v2 = <&cpu0_opp_table>; 248 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 249 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 250 qcom,freq-domain = <&cpufreq_hw 0>; 251 #cooling-cells = <2>; 252 L2_300: l2-cache { 253 compatible = "cache"; 254 cache-level = <2>; 255 next-level-cache = <&L3_0>; 256 }; 257 }; 258 259 CPU4: cpu@400 { 260 device_type = "cpu"; 261 compatible = "qcom,kryo"; 262 reg = <0x0 0x400>; 263 clocks = <&cpufreq_hw 1>; 264 enable-method = "psci"; 265 cpu-idle-states = <&BIG_CPU_SLEEP_0 266 &BIG_CPU_SLEEP_1 267 &CLUSTER_SLEEP_0>; 268 next-level-cache = <&L2_400>; 269 operating-points-v2 = <&cpu4_opp_table>; 270 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 271 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 272 qcom,freq-domain = <&cpufreq_hw 1>; 273 #cooling-cells = <2>; 274 L2_400: l2-cache { 275 compatible = "cache"; 276 cache-level = <2>; 277 next-level-cache = <&L3_0>; 278 }; 279 }; 280 281 CPU5: cpu@500 { 282 device_type = "cpu"; 283 compatible = "qcom,kryo"; 284 reg = <0x0 0x500>; 285 clocks = <&cpufreq_hw 1>; 286 enable-method = "psci"; 287 cpu-idle-states = <&BIG_CPU_SLEEP_0 288 &BIG_CPU_SLEEP_1 289 &CLUSTER_SLEEP_0>; 290 next-level-cache = <&L2_500>; 291 operating-points-v2 = <&cpu4_opp_table>; 292 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 293 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 294 qcom,freq-domain = <&cpufreq_hw 1>; 295 #cooling-cells = <2>; 296 L2_500: l2-cache { 297 compatible = "cache"; 298 cache-level = <2>; 299 next-level-cache = <&L3_0>; 300 }; 301 }; 302 303 CPU6: cpu@600 { 304 device_type = "cpu"; 305 compatible = "qcom,kryo"; 306 reg = <0x0 0x600>; 307 clocks = <&cpufreq_hw 1>; 308 enable-method = "psci"; 309 cpu-idle-states = <&BIG_CPU_SLEEP_0 310 &BIG_CPU_SLEEP_1 311 &CLUSTER_SLEEP_0>; 312 next-level-cache = <&L2_600>; 313 operating-points-v2 = <&cpu4_opp_table>; 314 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 315 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 316 qcom,freq-domain = <&cpufreq_hw 1>; 317 #cooling-cells = <2>; 318 L2_600: l2-cache { 319 compatible = "cache"; 320 cache-level = <2>; 321 next-level-cache = <&L3_0>; 322 }; 323 }; 324 325 CPU7: cpu@700 { 326 device_type = "cpu"; 327 compatible = "qcom,kryo"; 328 reg = <0x0 0x700>; 329 clocks = <&cpufreq_hw 2>; 330 enable-method = "psci"; 331 cpu-idle-states = <&BIG_CPU_SLEEP_0 332 &BIG_CPU_SLEEP_1 333 &CLUSTER_SLEEP_0>; 334 next-level-cache = <&L2_700>; 335 operating-points-v2 = <&cpu7_opp_table>; 336 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 337 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 338 qcom,freq-domain = <&cpufreq_hw 2>; 339 #cooling-cells = <2>; 340 L2_700: l2-cache { 341 compatible = "cache"; 342 cache-level = <2>; 343 next-level-cache = <&L3_0>; 344 }; 345 }; 346 347 cpu-map { 348 cluster0 { 349 core0 { 350 cpu = <&CPU0>; 351 }; 352 353 core1 { 354 cpu = <&CPU1>; 355 }; 356 357 core2 { 358 cpu = <&CPU2>; 359 }; 360 361 core3 { 362 cpu = <&CPU3>; 363 }; 364 365 core4 { 366 cpu = <&CPU4>; 367 }; 368 369 core5 { 370 cpu = <&CPU5>; 371 }; 372 373 core6 { 374 cpu = <&CPU6>; 375 }; 376 377 core7 { 378 cpu = <&CPU7>; 379 }; 380 }; 381 }; 382 383 idle-states { 384 entry-method = "psci"; 385 386 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 387 compatible = "arm,idle-state"; 388 idle-state-name = "little-power-down"; 389 arm,psci-suspend-param = <0x40000003>; 390 entry-latency-us = <549>; 391 exit-latency-us = <901>; 392 min-residency-us = <1774>; 393 local-timer-stop; 394 }; 395 396 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 397 compatible = "arm,idle-state"; 398 idle-state-name = "little-rail-power-down"; 399 arm,psci-suspend-param = <0x40000004>; 400 entry-latency-us = <702>; 401 exit-latency-us = <915>; 402 min-residency-us = <4001>; 403 local-timer-stop; 404 }; 405 406 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 407 compatible = "arm,idle-state"; 408 idle-state-name = "big-power-down"; 409 arm,psci-suspend-param = <0x40000003>; 410 entry-latency-us = <523>; 411 exit-latency-us = <1244>; 412 min-residency-us = <2207>; 413 local-timer-stop; 414 }; 415 416 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 417 compatible = "arm,idle-state"; 418 idle-state-name = "big-rail-power-down"; 419 arm,psci-suspend-param = <0x40000004>; 420 entry-latency-us = <526>; 421 exit-latency-us = <1854>; 422 min-residency-us = <5555>; 423 local-timer-stop; 424 }; 425 426 CLUSTER_SLEEP_0: cluster-sleep-0 { 427 compatible = "arm,idle-state"; 428 idle-state-name = "cluster-power-down"; 429 arm,psci-suspend-param = <0x40003444>; 430 entry-latency-us = <3263>; 431 exit-latency-us = <6562>; 432 min-residency-us = <9926>; 433 local-timer-stop; 434 }; 435 }; 436 }; 437 438 cpu0_opp_table: opp-table-cpu0 { 439 compatible = "operating-points-v2"; 440 opp-shared; 441 442 cpu0_opp_300mhz: opp-300000000 { 443 opp-hz = /bits/ 64 <300000000>; 444 opp-peak-kBps = <800000 9600000>; 445 }; 446 447 cpu0_opp_691mhz: opp-691200000 { 448 opp-hz = /bits/ 64 <691200000>; 449 opp-peak-kBps = <800000 17817600>; 450 }; 451 452 cpu0_opp_806mhz: opp-806400000 { 453 opp-hz = /bits/ 64 <806400000>; 454 opp-peak-kBps = <800000 20889600>; 455 }; 456 457 cpu0_opp_941mhz: opp-940800000 { 458 opp-hz = /bits/ 64 <940800000>; 459 opp-peak-kBps = <1804000 24576000>; 460 }; 461 462 cpu0_opp_1152mhz: opp-1152000000 { 463 opp-hz = /bits/ 64 <1152000000>; 464 opp-peak-kBps = <2188000 27033600>; 465 }; 466 467 cpu0_opp_1325mhz: opp-1324800000 { 468 opp-hz = /bits/ 64 <1324800000>; 469 opp-peak-kBps = <2188000 33792000>; 470 }; 471 472 cpu0_opp_1517mhz: opp-1516800000 { 473 opp-hz = /bits/ 64 <1516800000>; 474 opp-peak-kBps = <3072000 38092800>; 475 }; 476 477 cpu0_opp_1651mhz: opp-1651200000 { 478 opp-hz = /bits/ 64 <1651200000>; 479 opp-peak-kBps = <3072000 41779200>; 480 }; 481 482 cpu0_opp_1805mhz: opp-1804800000 { 483 opp-hz = /bits/ 64 <1804800000>; 484 opp-peak-kBps = <4068000 48537600>; 485 }; 486 487 cpu0_opp_1958mhz: opp-1958400000 { 488 opp-hz = /bits/ 64 <1958400000>; 489 opp-peak-kBps = <4068000 48537600>; 490 }; 491 492 cpu0_opp_2016mhz: opp-2016000000 { 493 opp-hz = /bits/ 64 <2016000000>; 494 opp-peak-kBps = <6220000 48537600>; 495 }; 496 }; 497 498 cpu4_opp_table: opp-table-cpu4 { 499 compatible = "operating-points-v2"; 500 opp-shared; 501 502 cpu4_opp_691mhz: opp-691200000 { 503 opp-hz = /bits/ 64 <691200000>; 504 opp-peak-kBps = <1804000 9600000>; 505 }; 506 507 cpu4_opp_941mhz: opp-940800000 { 508 opp-hz = /bits/ 64 <940800000>; 509 opp-peak-kBps = <2188000 17817600>; 510 }; 511 512 cpu4_opp_1229mhz: opp-1228800000 { 513 opp-hz = /bits/ 64 <1228800000>; 514 opp-peak-kBps = <4068000 24576000>; 515 }; 516 517 cpu4_opp_1344mhz: opp-1344000000 { 518 opp-hz = /bits/ 64 <1344000000>; 519 opp-peak-kBps = <4068000 24576000>; 520 }; 521 522 cpu4_opp_1517mhz: opp-1516800000 { 523 opp-hz = /bits/ 64 <1516800000>; 524 opp-peak-kBps = <4068000 24576000>; 525 }; 526 527 cpu4_opp_1651mhz: opp-1651200000 { 528 opp-hz = /bits/ 64 <1651200000>; 529 opp-peak-kBps = <6220000 38092800>; 530 }; 531 532 cpu4_opp_1901mhz: opp-1900800000 { 533 opp-hz = /bits/ 64 <1900800000>; 534 opp-peak-kBps = <6220000 44851200>; 535 }; 536 537 cpu4_opp_2054mhz: opp-2054400000 { 538 opp-hz = /bits/ 64 <2054400000>; 539 opp-peak-kBps = <6220000 44851200>; 540 }; 541 542 cpu4_opp_2112mhz: opp-2112000000 { 543 opp-hz = /bits/ 64 <2112000000>; 544 opp-peak-kBps = <6220000 44851200>; 545 }; 546 547 cpu4_opp_2131mhz: opp-2131200000 { 548 opp-hz = /bits/ 64 <2131200000>; 549 opp-peak-kBps = <6220000 44851200>; 550 }; 551 552 cpu4_opp_2208mhz: opp-2208000000 { 553 opp-hz = /bits/ 64 <2208000000>; 554 opp-peak-kBps = <6220000 44851200>; 555 }; 556 557 cpu4_opp_2400mhz: opp-2400000000 { 558 opp-hz = /bits/ 64 <2400000000>; 559 opp-peak-kBps = <8532000 48537600>; 560 }; 561 562 cpu4_opp_2611mhz: opp-2611200000 { 563 opp-hz = /bits/ 64 <2611200000>; 564 opp-peak-kBps = <8532000 48537600>; 565 }; 566 }; 567 568 cpu7_opp_table: opp-table-cpu7 { 569 compatible = "operating-points-v2"; 570 opp-shared; 571 572 cpu7_opp_806mhz: opp-806400000 { 573 opp-hz = /bits/ 64 <806400000>; 574 opp-peak-kBps = <1804000 9600000>; 575 }; 576 577 cpu7_opp_1056mhz: opp-1056000000 { 578 opp-hz = /bits/ 64 <1056000000>; 579 opp-peak-kBps = <2188000 17817600>; 580 }; 581 582 cpu7_opp_1325mhz: opp-1324800000 { 583 opp-hz = /bits/ 64 <1324800000>; 584 opp-peak-kBps = <4068000 24576000>; 585 }; 586 587 cpu7_opp_1517mhz: opp-1516800000 { 588 opp-hz = /bits/ 64 <1516800000>; 589 opp-peak-kBps = <4068000 24576000>; 590 }; 591 592 cpu7_opp_1766mhz: opp-1766400000 { 593 opp-hz = /bits/ 64 <1766400000>; 594 opp-peak-kBps = <6220000 38092800>; 595 }; 596 597 cpu7_opp_1862mhz: opp-1862400000 { 598 opp-hz = /bits/ 64 <1862400000>; 599 opp-peak-kBps = <6220000 38092800>; 600 }; 601 602 cpu7_opp_2035mhz: opp-2035200000 { 603 opp-hz = /bits/ 64 <2035200000>; 604 opp-peak-kBps = <6220000 38092800>; 605 }; 606 607 cpu7_opp_2112mhz: opp-2112000000 { 608 opp-hz = /bits/ 64 <2112000000>; 609 opp-peak-kBps = <6220000 44851200>; 610 }; 611 612 cpu7_opp_2208mhz: opp-2208000000 { 613 opp-hz = /bits/ 64 <2208000000>; 614 opp-peak-kBps = <6220000 44851200>; 615 }; 616 617 cpu7_opp_2381mhz: opp-2380800000 { 618 opp-hz = /bits/ 64 <2380800000>; 619 opp-peak-kBps = <6832000 44851200>; 620 }; 621 622 cpu7_opp_2400mhz: opp-2400000000 { 623 opp-hz = /bits/ 64 <2400000000>; 624 opp-peak-kBps = <8532000 48537600>; 625 }; 626 627 cpu7_opp_2515mhz: opp-2515200000 { 628 opp-hz = /bits/ 64 <2515200000>; 629 opp-peak-kBps = <8532000 48537600>; 630 }; 631 632 cpu7_opp_2707mhz: opp-2707200000 { 633 opp-hz = /bits/ 64 <2707200000>; 634 opp-peak-kBps = <8532000 48537600>; 635 }; 636 637 cpu7_opp_3014mhz: opp-3014400000 { 638 opp-hz = /bits/ 64 <3014400000>; 639 opp-peak-kBps = <8532000 48537600>; 640 }; 641 }; 642 643 eud_typec: connector { 644 compatible = "usb-c-connector"; 645 646 ports { 647 port@0 { 648 con_eud: endpoint { 649 remote-endpoint = <&eud_con>; 650 }; 651 }; 652 }; 653 }; 654 655 memory@80000000 { 656 device_type = "memory"; 657 /* We expect the bootloader to fill in the size */ 658 reg = <0 0x80000000 0 0>; 659 }; 660 661 firmware { 662 scm { 663 compatible = "qcom,scm-sc7280", "qcom,scm"; 664 }; 665 }; 666 667 clk_virt: interconnect { 668 compatible = "qcom,sc7280-clk-virt"; 669 #interconnect-cells = <2>; 670 qcom,bcm-voters = <&apps_bcm_voter>; 671 }; 672 673 smem { 674 compatible = "qcom,smem"; 675 memory-region = <&smem_mem>; 676 hwlocks = <&tcsr_mutex 3>; 677 }; 678 679 smp2p-adsp { 680 compatible = "qcom,smp2p"; 681 qcom,smem = <443>, <429>; 682 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 683 IPCC_MPROC_SIGNAL_SMP2P 684 IRQ_TYPE_EDGE_RISING>; 685 mboxes = <&ipcc IPCC_CLIENT_LPASS 686 IPCC_MPROC_SIGNAL_SMP2P>; 687 688 qcom,local-pid = <0>; 689 qcom,remote-pid = <2>; 690 691 adsp_smp2p_out: master-kernel { 692 qcom,entry-name = "master-kernel"; 693 #qcom,smem-state-cells = <1>; 694 }; 695 696 adsp_smp2p_in: slave-kernel { 697 qcom,entry-name = "slave-kernel"; 698 interrupt-controller; 699 #interrupt-cells = <2>; 700 }; 701 }; 702 703 smp2p-cdsp { 704 compatible = "qcom,smp2p"; 705 qcom,smem = <94>, <432>; 706 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 707 IPCC_MPROC_SIGNAL_SMP2P 708 IRQ_TYPE_EDGE_RISING>; 709 mboxes = <&ipcc IPCC_CLIENT_CDSP 710 IPCC_MPROC_SIGNAL_SMP2P>; 711 712 qcom,local-pid = <0>; 713 qcom,remote-pid = <5>; 714 715 cdsp_smp2p_out: master-kernel { 716 qcom,entry-name = "master-kernel"; 717 #qcom,smem-state-cells = <1>; 718 }; 719 720 cdsp_smp2p_in: slave-kernel { 721 qcom,entry-name = "slave-kernel"; 722 interrupt-controller; 723 #interrupt-cells = <2>; 724 }; 725 }; 726 727 smp2p-mpss { 728 compatible = "qcom,smp2p"; 729 qcom,smem = <435>, <428>; 730 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 731 IPCC_MPROC_SIGNAL_SMP2P 732 IRQ_TYPE_EDGE_RISING>; 733 mboxes = <&ipcc IPCC_CLIENT_MPSS 734 IPCC_MPROC_SIGNAL_SMP2P>; 735 736 qcom,local-pid = <0>; 737 qcom,remote-pid = <1>; 738 739 modem_smp2p_out: master-kernel { 740 qcom,entry-name = "master-kernel"; 741 #qcom,smem-state-cells = <1>; 742 }; 743 744 modem_smp2p_in: slave-kernel { 745 qcom,entry-name = "slave-kernel"; 746 interrupt-controller; 747 #interrupt-cells = <2>; 748 }; 749 750 ipa_smp2p_out: ipa-ap-to-modem { 751 qcom,entry-name = "ipa"; 752 #qcom,smem-state-cells = <1>; 753 }; 754 755 ipa_smp2p_in: ipa-modem-to-ap { 756 qcom,entry-name = "ipa"; 757 interrupt-controller; 758 #interrupt-cells = <2>; 759 }; 760 }; 761 762 smp2p-wpss { 763 compatible = "qcom,smp2p"; 764 qcom,smem = <617>, <616>; 765 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 766 IPCC_MPROC_SIGNAL_SMP2P 767 IRQ_TYPE_EDGE_RISING>; 768 mboxes = <&ipcc IPCC_CLIENT_WPSS 769 IPCC_MPROC_SIGNAL_SMP2P>; 770 771 qcom,local-pid = <0>; 772 qcom,remote-pid = <13>; 773 774 wpss_smp2p_out: master-kernel { 775 qcom,entry-name = "master-kernel"; 776 #qcom,smem-state-cells = <1>; 777 }; 778 779 wpss_smp2p_in: slave-kernel { 780 qcom,entry-name = "slave-kernel"; 781 interrupt-controller; 782 #interrupt-cells = <2>; 783 }; 784 785 wlan_smp2p_out: wlan-ap-to-wpss { 786 qcom,entry-name = "wlan"; 787 #qcom,smem-state-cells = <1>; 788 }; 789 790 wlan_smp2p_in: wlan-wpss-to-ap { 791 qcom,entry-name = "wlan"; 792 interrupt-controller; 793 #interrupt-cells = <2>; 794 }; 795 }; 796 797 pmu { 798 compatible = "arm,armv8-pmuv3"; 799 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 800 }; 801 802 psci { 803 compatible = "arm,psci-1.0"; 804 method = "smc"; 805 }; 806 807 qspi_opp_table: opp-table-qspi { 808 compatible = "operating-points-v2"; 809 810 opp-75000000 { 811 opp-hz = /bits/ 64 <75000000>; 812 required-opps = <&rpmhpd_opp_low_svs>; 813 }; 814 815 opp-150000000 { 816 opp-hz = /bits/ 64 <150000000>; 817 required-opps = <&rpmhpd_opp_svs>; 818 }; 819 820 opp-200000000 { 821 opp-hz = /bits/ 64 <200000000>; 822 required-opps = <&rpmhpd_opp_svs_l1>; 823 }; 824 825 opp-300000000 { 826 opp-hz = /bits/ 64 <300000000>; 827 required-opps = <&rpmhpd_opp_nom>; 828 }; 829 }; 830 831 qup_opp_table: opp-table-qup { 832 compatible = "operating-points-v2"; 833 834 opp-75000000 { 835 opp-hz = /bits/ 64 <75000000>; 836 required-opps = <&rpmhpd_opp_low_svs>; 837 }; 838 839 opp-100000000 { 840 opp-hz = /bits/ 64 <100000000>; 841 required-opps = <&rpmhpd_opp_svs>; 842 }; 843 844 opp-128000000 { 845 opp-hz = /bits/ 64 <128000000>; 846 required-opps = <&rpmhpd_opp_nom>; 847 }; 848 }; 849 850 soc: soc@0 { 851 #address-cells = <2>; 852 #size-cells = <2>; 853 ranges = <0 0 0 0 0x10 0>; 854 dma-ranges = <0 0 0 0 0x10 0>; 855 compatible = "simple-bus"; 856 857 gcc: clock-controller@100000 { 858 compatible = "qcom,gcc-sc7280"; 859 reg = <0 0x00100000 0 0x1f0000>; 860 clocks = <&rpmhcc RPMH_CXO_CLK>, 861 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 862 <0>, <&pcie1_lane>, 863 <0>, <0>, <0>, <0>; 864 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 865 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 866 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 867 "ufs_phy_tx_symbol_0_clk", 868 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 869 #clock-cells = <1>; 870 #reset-cells = <1>; 871 #power-domain-cells = <1>; 872 power-domains = <&rpmhpd SC7280_CX>; 873 }; 874 875 ipcc: mailbox@408000 { 876 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 877 reg = <0 0x00408000 0 0x1000>; 878 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 879 interrupt-controller; 880 #interrupt-cells = <3>; 881 #mbox-cells = <2>; 882 }; 883 884 qfprom: efuse@784000 { 885 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 886 reg = <0 0x00784000 0 0xa20>, 887 <0 0x00780000 0 0xa20>, 888 <0 0x00782000 0 0x120>, 889 <0 0x00786000 0 0x1fff>; 890 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 891 clock-names = "core"; 892 power-domains = <&rpmhpd SC7280_MX>; 893 #address-cells = <1>; 894 #size-cells = <1>; 895 896 gpu_speed_bin: gpu_speed_bin@1e9 { 897 reg = <0x1e9 0x2>; 898 bits = <5 8>; 899 }; 900 }; 901 902 sdhc_1: mmc@7c4000 { 903 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 904 pinctrl-names = "default", "sleep"; 905 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 906 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 907 status = "disabled"; 908 909 reg = <0 0x007c4000 0 0x1000>, 910 <0 0x007c5000 0 0x1000>; 911 reg-names = "hc", "cqhci"; 912 913 iommus = <&apps_smmu 0xc0 0x0>; 914 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 916 interrupt-names = "hc_irq", "pwr_irq"; 917 918 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 919 <&gcc GCC_SDCC1_APPS_CLK>, 920 <&rpmhcc RPMH_CXO_CLK>; 921 clock-names = "iface", "core", "xo"; 922 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 923 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 924 interconnect-names = "sdhc-ddr","cpu-sdhc"; 925 power-domains = <&rpmhpd SC7280_CX>; 926 operating-points-v2 = <&sdhc1_opp_table>; 927 928 bus-width = <8>; 929 supports-cqe; 930 931 qcom,dll-config = <0x0007642c>; 932 qcom,ddr-config = <0x80040868>; 933 934 mmc-ddr-1_8v; 935 mmc-hs200-1_8v; 936 mmc-hs400-1_8v; 937 mmc-hs400-enhanced-strobe; 938 939 resets = <&gcc GCC_SDCC1_BCR>; 940 941 sdhc1_opp_table: opp-table { 942 compatible = "operating-points-v2"; 943 944 opp-100000000 { 945 opp-hz = /bits/ 64 <100000000>; 946 required-opps = <&rpmhpd_opp_low_svs>; 947 opp-peak-kBps = <1800000 400000>; 948 opp-avg-kBps = <100000 0>; 949 }; 950 951 opp-384000000 { 952 opp-hz = /bits/ 64 <384000000>; 953 required-opps = <&rpmhpd_opp_nom>; 954 opp-peak-kBps = <5400000 1600000>; 955 opp-avg-kBps = <390000 0>; 956 }; 957 }; 958 }; 959 960 gpi_dma0: dma-controller@900000 { 961 #dma-cells = <3>; 962 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 963 reg = <0 0x00900000 0 0x60000>; 964 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 976 dma-channels = <12>; 977 dma-channel-mask = <0x7f>; 978 iommus = <&apps_smmu 0x0136 0x0>; 979 status = "disabled"; 980 }; 981 982 qupv3_id_0: geniqup@9c0000 { 983 compatible = "qcom,geni-se-qup"; 984 reg = <0 0x009c0000 0 0x2000>; 985 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 986 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 987 clock-names = "m-ahb", "s-ahb"; 988 #address-cells = <2>; 989 #size-cells = <2>; 990 ranges; 991 iommus = <&apps_smmu 0x123 0x0>; 992 status = "disabled"; 993 994 i2c0: i2c@980000 { 995 compatible = "qcom,geni-i2c"; 996 reg = <0 0x00980000 0 0x4000>; 997 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 998 clock-names = "se"; 999 pinctrl-names = "default"; 1000 pinctrl-0 = <&qup_i2c0_data_clk>; 1001 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1005 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1006 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1007 interconnect-names = "qup-core", "qup-config", 1008 "qup-memory"; 1009 power-domains = <&rpmhpd SC7280_CX>; 1010 required-opps = <&rpmhpd_opp_low_svs>; 1011 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1012 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1013 dma-names = "tx", "rx"; 1014 status = "disabled"; 1015 }; 1016 1017 spi0: spi@980000 { 1018 compatible = "qcom,geni-spi"; 1019 reg = <0 0x00980000 0 0x4000>; 1020 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1021 clock-names = "se"; 1022 pinctrl-names = "default"; 1023 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1024 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 power-domains = <&rpmhpd SC7280_CX>; 1028 operating-points-v2 = <&qup_opp_table>; 1029 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1030 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1031 interconnect-names = "qup-core", "qup-config"; 1032 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1033 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1034 dma-names = "tx", "rx"; 1035 status = "disabled"; 1036 }; 1037 1038 uart0: serial@980000 { 1039 compatible = "qcom,geni-uart"; 1040 reg = <0 0x00980000 0 0x4000>; 1041 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1042 clock-names = "se"; 1043 pinctrl-names = "default"; 1044 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1045 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1046 power-domains = <&rpmhpd SC7280_CX>; 1047 operating-points-v2 = <&qup_opp_table>; 1048 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1049 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1050 interconnect-names = "qup-core", "qup-config"; 1051 status = "disabled"; 1052 }; 1053 1054 i2c1: i2c@984000 { 1055 compatible = "qcom,geni-i2c"; 1056 reg = <0 0x00984000 0 0x4000>; 1057 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1058 clock-names = "se"; 1059 pinctrl-names = "default"; 1060 pinctrl-0 = <&qup_i2c1_data_clk>; 1061 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1065 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1066 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1067 interconnect-names = "qup-core", "qup-config", 1068 "qup-memory"; 1069 power-domains = <&rpmhpd SC7280_CX>; 1070 required-opps = <&rpmhpd_opp_low_svs>; 1071 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1072 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1073 dma-names = "tx", "rx"; 1074 status = "disabled"; 1075 }; 1076 1077 spi1: spi@984000 { 1078 compatible = "qcom,geni-spi"; 1079 reg = <0 0x00984000 0 0x4000>; 1080 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1081 clock-names = "se"; 1082 pinctrl-names = "default"; 1083 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1084 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 power-domains = <&rpmhpd SC7280_CX>; 1088 operating-points-v2 = <&qup_opp_table>; 1089 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1090 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1091 interconnect-names = "qup-core", "qup-config"; 1092 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1093 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1094 dma-names = "tx", "rx"; 1095 status = "disabled"; 1096 }; 1097 1098 uart1: serial@984000 { 1099 compatible = "qcom,geni-uart"; 1100 reg = <0 0x00984000 0 0x4000>; 1101 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1102 clock-names = "se"; 1103 pinctrl-names = "default"; 1104 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1105 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1106 power-domains = <&rpmhpd SC7280_CX>; 1107 operating-points-v2 = <&qup_opp_table>; 1108 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1109 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1110 interconnect-names = "qup-core", "qup-config"; 1111 status = "disabled"; 1112 }; 1113 1114 i2c2: i2c@988000 { 1115 compatible = "qcom,geni-i2c"; 1116 reg = <0 0x00988000 0 0x4000>; 1117 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1118 clock-names = "se"; 1119 pinctrl-names = "default"; 1120 pinctrl-0 = <&qup_i2c2_data_clk>; 1121 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1125 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1126 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1127 interconnect-names = "qup-core", "qup-config", 1128 "qup-memory"; 1129 power-domains = <&rpmhpd SC7280_CX>; 1130 required-opps = <&rpmhpd_opp_low_svs>; 1131 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1132 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1133 dma-names = "tx", "rx"; 1134 status = "disabled"; 1135 }; 1136 1137 spi2: spi@988000 { 1138 compatible = "qcom,geni-spi"; 1139 reg = <0 0x00988000 0 0x4000>; 1140 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1141 clock-names = "se"; 1142 pinctrl-names = "default"; 1143 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1144 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 power-domains = <&rpmhpd SC7280_CX>; 1148 operating-points-v2 = <&qup_opp_table>; 1149 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1150 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1151 interconnect-names = "qup-core", "qup-config"; 1152 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1153 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1154 dma-names = "tx", "rx"; 1155 status = "disabled"; 1156 }; 1157 1158 uart2: serial@988000 { 1159 compatible = "qcom,geni-uart"; 1160 reg = <0 0x00988000 0 0x4000>; 1161 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1162 clock-names = "se"; 1163 pinctrl-names = "default"; 1164 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1165 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1166 power-domains = <&rpmhpd SC7280_CX>; 1167 operating-points-v2 = <&qup_opp_table>; 1168 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1169 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1170 interconnect-names = "qup-core", "qup-config"; 1171 status = "disabled"; 1172 }; 1173 1174 i2c3: i2c@98c000 { 1175 compatible = "qcom,geni-i2c"; 1176 reg = <0 0x0098c000 0 0x4000>; 1177 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1178 clock-names = "se"; 1179 pinctrl-names = "default"; 1180 pinctrl-0 = <&qup_i2c3_data_clk>; 1181 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1185 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1186 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1187 interconnect-names = "qup-core", "qup-config", 1188 "qup-memory"; 1189 power-domains = <&rpmhpd SC7280_CX>; 1190 required-opps = <&rpmhpd_opp_low_svs>; 1191 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1192 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1193 dma-names = "tx", "rx"; 1194 status = "disabled"; 1195 }; 1196 1197 spi3: spi@98c000 { 1198 compatible = "qcom,geni-spi"; 1199 reg = <0 0x0098c000 0 0x4000>; 1200 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1201 clock-names = "se"; 1202 pinctrl-names = "default"; 1203 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1204 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1205 #address-cells = <1>; 1206 #size-cells = <0>; 1207 power-domains = <&rpmhpd SC7280_CX>; 1208 operating-points-v2 = <&qup_opp_table>; 1209 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1210 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1211 interconnect-names = "qup-core", "qup-config"; 1212 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1213 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1214 dma-names = "tx", "rx"; 1215 status = "disabled"; 1216 }; 1217 1218 uart3: serial@98c000 { 1219 compatible = "qcom,geni-uart"; 1220 reg = <0 0x0098c000 0 0x4000>; 1221 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1222 clock-names = "se"; 1223 pinctrl-names = "default"; 1224 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1225 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1226 power-domains = <&rpmhpd SC7280_CX>; 1227 operating-points-v2 = <&qup_opp_table>; 1228 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1229 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1230 interconnect-names = "qup-core", "qup-config"; 1231 status = "disabled"; 1232 }; 1233 1234 i2c4: i2c@990000 { 1235 compatible = "qcom,geni-i2c"; 1236 reg = <0 0x00990000 0 0x4000>; 1237 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1238 clock-names = "se"; 1239 pinctrl-names = "default"; 1240 pinctrl-0 = <&qup_i2c4_data_clk>; 1241 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1242 #address-cells = <1>; 1243 #size-cells = <0>; 1244 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1245 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1246 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1247 interconnect-names = "qup-core", "qup-config", 1248 "qup-memory"; 1249 power-domains = <&rpmhpd SC7280_CX>; 1250 required-opps = <&rpmhpd_opp_low_svs>; 1251 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1252 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1253 dma-names = "tx", "rx"; 1254 status = "disabled"; 1255 }; 1256 1257 spi4: spi@990000 { 1258 compatible = "qcom,geni-spi"; 1259 reg = <0 0x00990000 0 0x4000>; 1260 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1261 clock-names = "se"; 1262 pinctrl-names = "default"; 1263 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1264 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1265 #address-cells = <1>; 1266 #size-cells = <0>; 1267 power-domains = <&rpmhpd SC7280_CX>; 1268 operating-points-v2 = <&qup_opp_table>; 1269 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1270 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1271 interconnect-names = "qup-core", "qup-config"; 1272 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1273 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1274 dma-names = "tx", "rx"; 1275 status = "disabled"; 1276 }; 1277 1278 uart4: serial@990000 { 1279 compatible = "qcom,geni-uart"; 1280 reg = <0 0x00990000 0 0x4000>; 1281 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1282 clock-names = "se"; 1283 pinctrl-names = "default"; 1284 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1285 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1286 power-domains = <&rpmhpd SC7280_CX>; 1287 operating-points-v2 = <&qup_opp_table>; 1288 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1289 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1290 interconnect-names = "qup-core", "qup-config"; 1291 status = "disabled"; 1292 }; 1293 1294 i2c5: i2c@994000 { 1295 compatible = "qcom,geni-i2c"; 1296 reg = <0 0x00994000 0 0x4000>; 1297 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1298 clock-names = "se"; 1299 pinctrl-names = "default"; 1300 pinctrl-0 = <&qup_i2c5_data_clk>; 1301 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1302 #address-cells = <1>; 1303 #size-cells = <0>; 1304 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1305 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1306 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1307 interconnect-names = "qup-core", "qup-config", 1308 "qup-memory"; 1309 power-domains = <&rpmhpd SC7280_CX>; 1310 required-opps = <&rpmhpd_opp_low_svs>; 1311 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1312 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1313 dma-names = "tx", "rx"; 1314 status = "disabled"; 1315 }; 1316 1317 spi5: spi@994000 { 1318 compatible = "qcom,geni-spi"; 1319 reg = <0 0x00994000 0 0x4000>; 1320 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1321 clock-names = "se"; 1322 pinctrl-names = "default"; 1323 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1324 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 power-domains = <&rpmhpd SC7280_CX>; 1328 operating-points-v2 = <&qup_opp_table>; 1329 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1330 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1331 interconnect-names = "qup-core", "qup-config"; 1332 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1333 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1334 dma-names = "tx", "rx"; 1335 status = "disabled"; 1336 }; 1337 1338 uart5: serial@994000 { 1339 compatible = "qcom,geni-uart"; 1340 reg = <0 0x00994000 0 0x4000>; 1341 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1342 clock-names = "se"; 1343 pinctrl-names = "default"; 1344 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1345 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1346 power-domains = <&rpmhpd SC7280_CX>; 1347 operating-points-v2 = <&qup_opp_table>; 1348 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1349 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1350 interconnect-names = "qup-core", "qup-config"; 1351 status = "disabled"; 1352 }; 1353 1354 i2c6: i2c@998000 { 1355 compatible = "qcom,geni-i2c"; 1356 reg = <0 0x00998000 0 0x4000>; 1357 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1358 clock-names = "se"; 1359 pinctrl-names = "default"; 1360 pinctrl-0 = <&qup_i2c6_data_clk>; 1361 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1365 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1366 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1367 interconnect-names = "qup-core", "qup-config", 1368 "qup-memory"; 1369 power-domains = <&rpmhpd SC7280_CX>; 1370 required-opps = <&rpmhpd_opp_low_svs>; 1371 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1372 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1373 dma-names = "tx", "rx"; 1374 status = "disabled"; 1375 }; 1376 1377 spi6: spi@998000 { 1378 compatible = "qcom,geni-spi"; 1379 reg = <0 0x00998000 0 0x4000>; 1380 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1381 clock-names = "se"; 1382 pinctrl-names = "default"; 1383 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1384 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1385 #address-cells = <1>; 1386 #size-cells = <0>; 1387 power-domains = <&rpmhpd SC7280_CX>; 1388 operating-points-v2 = <&qup_opp_table>; 1389 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1390 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1391 interconnect-names = "qup-core", "qup-config"; 1392 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1393 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1394 dma-names = "tx", "rx"; 1395 status = "disabled"; 1396 }; 1397 1398 uart6: serial@998000 { 1399 compatible = "qcom,geni-uart"; 1400 reg = <0 0x00998000 0 0x4000>; 1401 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1402 clock-names = "se"; 1403 pinctrl-names = "default"; 1404 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1405 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1406 power-domains = <&rpmhpd SC7280_CX>; 1407 operating-points-v2 = <&qup_opp_table>; 1408 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1409 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1410 interconnect-names = "qup-core", "qup-config"; 1411 status = "disabled"; 1412 }; 1413 1414 i2c7: i2c@99c000 { 1415 compatible = "qcom,geni-i2c"; 1416 reg = <0 0x0099c000 0 0x4000>; 1417 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1418 clock-names = "se"; 1419 pinctrl-names = "default"; 1420 pinctrl-0 = <&qup_i2c7_data_clk>; 1421 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1422 #address-cells = <1>; 1423 #size-cells = <0>; 1424 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1425 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1426 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1427 interconnect-names = "qup-core", "qup-config", 1428 "qup-memory"; 1429 power-domains = <&rpmhpd SC7280_CX>; 1430 required-opps = <&rpmhpd_opp_low_svs>; 1431 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1432 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1433 dma-names = "tx", "rx"; 1434 status = "disabled"; 1435 }; 1436 1437 spi7: spi@99c000 { 1438 compatible = "qcom,geni-spi"; 1439 reg = <0 0x0099c000 0 0x4000>; 1440 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1441 clock-names = "se"; 1442 pinctrl-names = "default"; 1443 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1444 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1445 #address-cells = <1>; 1446 #size-cells = <0>; 1447 power-domains = <&rpmhpd SC7280_CX>; 1448 operating-points-v2 = <&qup_opp_table>; 1449 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1450 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1451 interconnect-names = "qup-core", "qup-config"; 1452 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1453 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1454 dma-names = "tx", "rx"; 1455 status = "disabled"; 1456 }; 1457 1458 uart7: serial@99c000 { 1459 compatible = "qcom,geni-uart"; 1460 reg = <0 0x0099c000 0 0x4000>; 1461 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1462 clock-names = "se"; 1463 pinctrl-names = "default"; 1464 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1465 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1466 power-domains = <&rpmhpd SC7280_CX>; 1467 operating-points-v2 = <&qup_opp_table>; 1468 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1469 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1470 interconnect-names = "qup-core", "qup-config"; 1471 status = "disabled"; 1472 }; 1473 }; 1474 1475 gpi_dma1: dma-controller@a00000 { 1476 #dma-cells = <3>; 1477 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1478 reg = <0 0x00a00000 0 0x60000>; 1479 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1491 dma-channels = <12>; 1492 dma-channel-mask = <0x1e>; 1493 iommus = <&apps_smmu 0x56 0x0>; 1494 status = "disabled"; 1495 }; 1496 1497 qupv3_id_1: geniqup@ac0000 { 1498 compatible = "qcom,geni-se-qup"; 1499 reg = <0 0x00ac0000 0 0x2000>; 1500 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1501 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1502 clock-names = "m-ahb", "s-ahb"; 1503 #address-cells = <2>; 1504 #size-cells = <2>; 1505 ranges; 1506 iommus = <&apps_smmu 0x43 0x0>; 1507 status = "disabled"; 1508 1509 i2c8: i2c@a80000 { 1510 compatible = "qcom,geni-i2c"; 1511 reg = <0 0x00a80000 0 0x4000>; 1512 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1513 clock-names = "se"; 1514 pinctrl-names = "default"; 1515 pinctrl-0 = <&qup_i2c8_data_clk>; 1516 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1517 #address-cells = <1>; 1518 #size-cells = <0>; 1519 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1520 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1521 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1522 interconnect-names = "qup-core", "qup-config", 1523 "qup-memory"; 1524 power-domains = <&rpmhpd SC7280_CX>; 1525 required-opps = <&rpmhpd_opp_low_svs>; 1526 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1527 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1528 dma-names = "tx", "rx"; 1529 status = "disabled"; 1530 }; 1531 1532 spi8: spi@a80000 { 1533 compatible = "qcom,geni-spi"; 1534 reg = <0 0x00a80000 0 0x4000>; 1535 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1536 clock-names = "se"; 1537 pinctrl-names = "default"; 1538 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1539 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1540 #address-cells = <1>; 1541 #size-cells = <0>; 1542 power-domains = <&rpmhpd SC7280_CX>; 1543 operating-points-v2 = <&qup_opp_table>; 1544 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1545 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1546 interconnect-names = "qup-core", "qup-config"; 1547 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1548 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1549 dma-names = "tx", "rx"; 1550 status = "disabled"; 1551 }; 1552 1553 uart8: serial@a80000 { 1554 compatible = "qcom,geni-uart"; 1555 reg = <0 0x00a80000 0 0x4000>; 1556 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1557 clock-names = "se"; 1558 pinctrl-names = "default"; 1559 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1560 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1561 power-domains = <&rpmhpd SC7280_CX>; 1562 operating-points-v2 = <&qup_opp_table>; 1563 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1564 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1565 interconnect-names = "qup-core", "qup-config"; 1566 status = "disabled"; 1567 }; 1568 1569 i2c9: i2c@a84000 { 1570 compatible = "qcom,geni-i2c"; 1571 reg = <0 0x00a84000 0 0x4000>; 1572 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1573 clock-names = "se"; 1574 pinctrl-names = "default"; 1575 pinctrl-0 = <&qup_i2c9_data_clk>; 1576 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1577 #address-cells = <1>; 1578 #size-cells = <0>; 1579 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1580 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1581 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1582 interconnect-names = "qup-core", "qup-config", 1583 "qup-memory"; 1584 power-domains = <&rpmhpd SC7280_CX>; 1585 required-opps = <&rpmhpd_opp_low_svs>; 1586 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1587 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1588 dma-names = "tx", "rx"; 1589 status = "disabled"; 1590 }; 1591 1592 spi9: spi@a84000 { 1593 compatible = "qcom,geni-spi"; 1594 reg = <0 0x00a84000 0 0x4000>; 1595 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1596 clock-names = "se"; 1597 pinctrl-names = "default"; 1598 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1599 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1600 #address-cells = <1>; 1601 #size-cells = <0>; 1602 power-domains = <&rpmhpd SC7280_CX>; 1603 operating-points-v2 = <&qup_opp_table>; 1604 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1605 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1606 interconnect-names = "qup-core", "qup-config"; 1607 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1608 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1609 dma-names = "tx", "rx"; 1610 status = "disabled"; 1611 }; 1612 1613 uart9: serial@a84000 { 1614 compatible = "qcom,geni-uart"; 1615 reg = <0 0x00a84000 0 0x4000>; 1616 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1617 clock-names = "se"; 1618 pinctrl-names = "default"; 1619 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1620 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1621 power-domains = <&rpmhpd SC7280_CX>; 1622 operating-points-v2 = <&qup_opp_table>; 1623 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1624 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1625 interconnect-names = "qup-core", "qup-config"; 1626 status = "disabled"; 1627 }; 1628 1629 i2c10: i2c@a88000 { 1630 compatible = "qcom,geni-i2c"; 1631 reg = <0 0x00a88000 0 0x4000>; 1632 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1633 clock-names = "se"; 1634 pinctrl-names = "default"; 1635 pinctrl-0 = <&qup_i2c10_data_clk>; 1636 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1637 #address-cells = <1>; 1638 #size-cells = <0>; 1639 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1640 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1641 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1642 interconnect-names = "qup-core", "qup-config", 1643 "qup-memory"; 1644 power-domains = <&rpmhpd SC7280_CX>; 1645 required-opps = <&rpmhpd_opp_low_svs>; 1646 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1647 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1648 dma-names = "tx", "rx"; 1649 status = "disabled"; 1650 }; 1651 1652 spi10: spi@a88000 { 1653 compatible = "qcom,geni-spi"; 1654 reg = <0 0x00a88000 0 0x4000>; 1655 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1656 clock-names = "se"; 1657 pinctrl-names = "default"; 1658 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1659 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1660 #address-cells = <1>; 1661 #size-cells = <0>; 1662 power-domains = <&rpmhpd SC7280_CX>; 1663 operating-points-v2 = <&qup_opp_table>; 1664 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1665 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1666 interconnect-names = "qup-core", "qup-config"; 1667 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1668 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1669 dma-names = "tx", "rx"; 1670 status = "disabled"; 1671 }; 1672 1673 uart10: serial@a88000 { 1674 compatible = "qcom,geni-uart"; 1675 reg = <0 0x00a88000 0 0x4000>; 1676 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1677 clock-names = "se"; 1678 pinctrl-names = "default"; 1679 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1680 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1681 power-domains = <&rpmhpd SC7280_CX>; 1682 operating-points-v2 = <&qup_opp_table>; 1683 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1684 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1685 interconnect-names = "qup-core", "qup-config"; 1686 status = "disabled"; 1687 }; 1688 1689 i2c11: i2c@a8c000 { 1690 compatible = "qcom,geni-i2c"; 1691 reg = <0 0x00a8c000 0 0x4000>; 1692 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1693 clock-names = "se"; 1694 pinctrl-names = "default"; 1695 pinctrl-0 = <&qup_i2c11_data_clk>; 1696 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1697 #address-cells = <1>; 1698 #size-cells = <0>; 1699 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1700 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1701 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1702 interconnect-names = "qup-core", "qup-config", 1703 "qup-memory"; 1704 power-domains = <&rpmhpd SC7280_CX>; 1705 required-opps = <&rpmhpd_opp_low_svs>; 1706 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1707 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1708 dma-names = "tx", "rx"; 1709 status = "disabled"; 1710 }; 1711 1712 spi11: spi@a8c000 { 1713 compatible = "qcom,geni-spi"; 1714 reg = <0 0x00a8c000 0 0x4000>; 1715 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1716 clock-names = "se"; 1717 pinctrl-names = "default"; 1718 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1719 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1720 #address-cells = <1>; 1721 #size-cells = <0>; 1722 power-domains = <&rpmhpd SC7280_CX>; 1723 operating-points-v2 = <&qup_opp_table>; 1724 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1725 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1726 interconnect-names = "qup-core", "qup-config"; 1727 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1728 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1729 dma-names = "tx", "rx"; 1730 status = "disabled"; 1731 }; 1732 1733 uart11: serial@a8c000 { 1734 compatible = "qcom,geni-uart"; 1735 reg = <0 0x00a8c000 0 0x4000>; 1736 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1737 clock-names = "se"; 1738 pinctrl-names = "default"; 1739 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1740 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1741 power-domains = <&rpmhpd SC7280_CX>; 1742 operating-points-v2 = <&qup_opp_table>; 1743 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1744 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1745 interconnect-names = "qup-core", "qup-config"; 1746 status = "disabled"; 1747 }; 1748 1749 i2c12: i2c@a90000 { 1750 compatible = "qcom,geni-i2c"; 1751 reg = <0 0x00a90000 0 0x4000>; 1752 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1753 clock-names = "se"; 1754 pinctrl-names = "default"; 1755 pinctrl-0 = <&qup_i2c12_data_clk>; 1756 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1757 #address-cells = <1>; 1758 #size-cells = <0>; 1759 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1760 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1761 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1762 interconnect-names = "qup-core", "qup-config", 1763 "qup-memory"; 1764 power-domains = <&rpmhpd SC7280_CX>; 1765 required-opps = <&rpmhpd_opp_low_svs>; 1766 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1767 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1768 dma-names = "tx", "rx"; 1769 status = "disabled"; 1770 }; 1771 1772 spi12: spi@a90000 { 1773 compatible = "qcom,geni-spi"; 1774 reg = <0 0x00a90000 0 0x4000>; 1775 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1776 clock-names = "se"; 1777 pinctrl-names = "default"; 1778 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1779 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1780 #address-cells = <1>; 1781 #size-cells = <0>; 1782 power-domains = <&rpmhpd SC7280_CX>; 1783 operating-points-v2 = <&qup_opp_table>; 1784 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1785 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1786 interconnect-names = "qup-core", "qup-config"; 1787 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1788 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1789 dma-names = "tx", "rx"; 1790 status = "disabled"; 1791 }; 1792 1793 uart12: serial@a90000 { 1794 compatible = "qcom,geni-uart"; 1795 reg = <0 0x00a90000 0 0x4000>; 1796 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1797 clock-names = "se"; 1798 pinctrl-names = "default"; 1799 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1800 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1801 power-domains = <&rpmhpd SC7280_CX>; 1802 operating-points-v2 = <&qup_opp_table>; 1803 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1804 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1805 interconnect-names = "qup-core", "qup-config"; 1806 status = "disabled"; 1807 }; 1808 1809 i2c13: i2c@a94000 { 1810 compatible = "qcom,geni-i2c"; 1811 reg = <0 0x00a94000 0 0x4000>; 1812 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1813 clock-names = "se"; 1814 pinctrl-names = "default"; 1815 pinctrl-0 = <&qup_i2c13_data_clk>; 1816 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1817 #address-cells = <1>; 1818 #size-cells = <0>; 1819 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1820 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1821 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1822 interconnect-names = "qup-core", "qup-config", 1823 "qup-memory"; 1824 power-domains = <&rpmhpd SC7280_CX>; 1825 required-opps = <&rpmhpd_opp_low_svs>; 1826 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1827 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1828 dma-names = "tx", "rx"; 1829 status = "disabled"; 1830 }; 1831 1832 spi13: spi@a94000 { 1833 compatible = "qcom,geni-spi"; 1834 reg = <0 0x00a94000 0 0x4000>; 1835 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1836 clock-names = "se"; 1837 pinctrl-names = "default"; 1838 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1839 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1840 #address-cells = <1>; 1841 #size-cells = <0>; 1842 power-domains = <&rpmhpd SC7280_CX>; 1843 operating-points-v2 = <&qup_opp_table>; 1844 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1845 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1846 interconnect-names = "qup-core", "qup-config"; 1847 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1848 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1849 dma-names = "tx", "rx"; 1850 status = "disabled"; 1851 }; 1852 1853 uart13: serial@a94000 { 1854 compatible = "qcom,geni-uart"; 1855 reg = <0 0x00a94000 0 0x4000>; 1856 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1857 clock-names = "se"; 1858 pinctrl-names = "default"; 1859 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1860 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1861 power-domains = <&rpmhpd SC7280_CX>; 1862 operating-points-v2 = <&qup_opp_table>; 1863 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1864 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1865 interconnect-names = "qup-core", "qup-config"; 1866 status = "disabled"; 1867 }; 1868 1869 i2c14: i2c@a98000 { 1870 compatible = "qcom,geni-i2c"; 1871 reg = <0 0x00a98000 0 0x4000>; 1872 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1873 clock-names = "se"; 1874 pinctrl-names = "default"; 1875 pinctrl-0 = <&qup_i2c14_data_clk>; 1876 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1877 #address-cells = <1>; 1878 #size-cells = <0>; 1879 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1880 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1881 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1882 interconnect-names = "qup-core", "qup-config", 1883 "qup-memory"; 1884 power-domains = <&rpmhpd SC7280_CX>; 1885 required-opps = <&rpmhpd_opp_low_svs>; 1886 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1887 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1888 dma-names = "tx", "rx"; 1889 status = "disabled"; 1890 }; 1891 1892 spi14: spi@a98000 { 1893 compatible = "qcom,geni-spi"; 1894 reg = <0 0x00a98000 0 0x4000>; 1895 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1896 clock-names = "se"; 1897 pinctrl-names = "default"; 1898 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1899 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1900 #address-cells = <1>; 1901 #size-cells = <0>; 1902 power-domains = <&rpmhpd SC7280_CX>; 1903 operating-points-v2 = <&qup_opp_table>; 1904 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1905 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1906 interconnect-names = "qup-core", "qup-config"; 1907 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1908 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1909 dma-names = "tx", "rx"; 1910 status = "disabled"; 1911 }; 1912 1913 uart14: serial@a98000 { 1914 compatible = "qcom,geni-uart"; 1915 reg = <0 0x00a98000 0 0x4000>; 1916 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1917 clock-names = "se"; 1918 pinctrl-names = "default"; 1919 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1920 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1921 power-domains = <&rpmhpd SC7280_CX>; 1922 operating-points-v2 = <&qup_opp_table>; 1923 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1924 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1925 interconnect-names = "qup-core", "qup-config"; 1926 status = "disabled"; 1927 }; 1928 1929 i2c15: i2c@a9c000 { 1930 compatible = "qcom,geni-i2c"; 1931 reg = <0 0x00a9c000 0 0x4000>; 1932 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1933 clock-names = "se"; 1934 pinctrl-names = "default"; 1935 pinctrl-0 = <&qup_i2c15_data_clk>; 1936 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1937 #address-cells = <1>; 1938 #size-cells = <0>; 1939 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1940 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1941 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1942 interconnect-names = "qup-core", "qup-config", 1943 "qup-memory"; 1944 power-domains = <&rpmhpd SC7280_CX>; 1945 required-opps = <&rpmhpd_opp_low_svs>; 1946 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1947 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1948 dma-names = "tx", "rx"; 1949 status = "disabled"; 1950 }; 1951 1952 spi15: spi@a9c000 { 1953 compatible = "qcom,geni-spi"; 1954 reg = <0 0x00a9c000 0 0x4000>; 1955 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1956 clock-names = "se"; 1957 pinctrl-names = "default"; 1958 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1959 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1960 #address-cells = <1>; 1961 #size-cells = <0>; 1962 power-domains = <&rpmhpd SC7280_CX>; 1963 operating-points-v2 = <&qup_opp_table>; 1964 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1965 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1966 interconnect-names = "qup-core", "qup-config"; 1967 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1968 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1969 dma-names = "tx", "rx"; 1970 status = "disabled"; 1971 }; 1972 1973 uart15: serial@a9c000 { 1974 compatible = "qcom,geni-uart"; 1975 reg = <0 0x00a9c000 0 0x4000>; 1976 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1977 clock-names = "se"; 1978 pinctrl-names = "default"; 1979 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1980 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1981 power-domains = <&rpmhpd SC7280_CX>; 1982 operating-points-v2 = <&qup_opp_table>; 1983 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1984 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1985 interconnect-names = "qup-core", "qup-config"; 1986 status = "disabled"; 1987 }; 1988 }; 1989 1990 cnoc2: interconnect@1500000 { 1991 reg = <0 0x01500000 0 0x1000>; 1992 compatible = "qcom,sc7280-cnoc2"; 1993 #interconnect-cells = <2>; 1994 qcom,bcm-voters = <&apps_bcm_voter>; 1995 }; 1996 1997 cnoc3: interconnect@1502000 { 1998 reg = <0 0x01502000 0 0x1000>; 1999 compatible = "qcom,sc7280-cnoc3"; 2000 #interconnect-cells = <2>; 2001 qcom,bcm-voters = <&apps_bcm_voter>; 2002 }; 2003 2004 mc_virt: interconnect@1580000 { 2005 reg = <0 0x01580000 0 0x4>; 2006 compatible = "qcom,sc7280-mc-virt"; 2007 #interconnect-cells = <2>; 2008 qcom,bcm-voters = <&apps_bcm_voter>; 2009 }; 2010 2011 system_noc: interconnect@1680000 { 2012 reg = <0 0x01680000 0 0x15480>; 2013 compatible = "qcom,sc7280-system-noc"; 2014 #interconnect-cells = <2>; 2015 qcom,bcm-voters = <&apps_bcm_voter>; 2016 }; 2017 2018 aggre1_noc: interconnect@16e0000 { 2019 compatible = "qcom,sc7280-aggre1-noc"; 2020 reg = <0 0x016e0000 0 0x1c080>; 2021 #interconnect-cells = <2>; 2022 qcom,bcm-voters = <&apps_bcm_voter>; 2023 }; 2024 2025 aggre2_noc: interconnect@1700000 { 2026 reg = <0 0x01700000 0 0x2b080>; 2027 compatible = "qcom,sc7280-aggre2-noc"; 2028 #interconnect-cells = <2>; 2029 qcom,bcm-voters = <&apps_bcm_voter>; 2030 }; 2031 2032 mmss_noc: interconnect@1740000 { 2033 reg = <0 0x01740000 0 0x1e080>; 2034 compatible = "qcom,sc7280-mmss-noc"; 2035 #interconnect-cells = <2>; 2036 qcom,bcm-voters = <&apps_bcm_voter>; 2037 }; 2038 2039 wifi: wifi@17a10040 { 2040 compatible = "qcom,wcn6750-wifi"; 2041 reg = <0 0x17a10040 0 0x0>; 2042 iommus = <&apps_smmu 0x1c00 0x1>; 2043 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2044 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2045 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2046 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2047 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2048 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2049 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2050 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2051 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2052 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2053 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2054 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2055 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2056 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2057 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2058 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2059 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2060 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2061 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2062 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2063 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2064 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2065 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2066 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2067 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2068 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2069 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2070 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2071 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2072 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2073 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2074 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2075 qcom,rproc = <&remoteproc_wpss>; 2076 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2077 status = "disabled"; 2078 qcom,smem-states = <&wlan_smp2p_out 0>; 2079 qcom,smem-state-names = "wlan-smp2p-out"; 2080 }; 2081 2082 pcie1: pci@1c08000 { 2083 compatible = "qcom,pcie-sc7280"; 2084 reg = <0 0x01c08000 0 0x3000>, 2085 <0 0x40000000 0 0xf1d>, 2086 <0 0x40000f20 0 0xa8>, 2087 <0 0x40001000 0 0x1000>, 2088 <0 0x40100000 0 0x100000>; 2089 2090 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2091 device_type = "pci"; 2092 linux,pci-domain = <1>; 2093 bus-range = <0x00 0xff>; 2094 num-lanes = <2>; 2095 2096 #address-cells = <3>; 2097 #size-cells = <2>; 2098 2099 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2100 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2101 2102 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2103 interrupt-names = "msi"; 2104 #interrupt-cells = <1>; 2105 interrupt-map-mask = <0 0 0 0x7>; 2106 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2107 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2108 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2109 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2110 2111 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2112 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2113 <&pcie1_lane>, 2114 <&rpmhcc RPMH_CXO_CLK>, 2115 <&gcc GCC_PCIE_1_AUX_CLK>, 2116 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2117 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2118 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2119 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2120 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2121 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2122 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2123 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2124 2125 clock-names = "pipe", 2126 "pipe_mux", 2127 "phy_pipe", 2128 "ref", 2129 "aux", 2130 "cfg", 2131 "bus_master", 2132 "bus_slave", 2133 "slave_q2a", 2134 "tbu", 2135 "ddrss_sf_tbu", 2136 "aggre0", 2137 "aggre1"; 2138 2139 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2140 assigned-clock-rates = <19200000>; 2141 2142 resets = <&gcc GCC_PCIE_1_BCR>; 2143 reset-names = "pci"; 2144 2145 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2146 2147 phys = <&pcie1_lane>; 2148 phy-names = "pciephy"; 2149 2150 pinctrl-names = "default"; 2151 pinctrl-0 = <&pcie1_clkreq_n>; 2152 2153 dma-coherent; 2154 2155 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2156 <0x100 &apps_smmu 0x1c81 0x1>; 2157 2158 status = "disabled"; 2159 }; 2160 2161 pcie1_phy: phy@1c0e000 { 2162 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2163 reg = <0 0x01c0e000 0 0x1c0>; 2164 #address-cells = <2>; 2165 #size-cells = <2>; 2166 ranges; 2167 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2168 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2169 <&gcc GCC_PCIE_CLKREF_EN>, 2170 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2171 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2172 2173 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2174 reset-names = "phy"; 2175 2176 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2177 assigned-clock-rates = <100000000>; 2178 2179 status = "disabled"; 2180 2181 pcie1_lane: phy@1c0e200 { 2182 reg = <0 0x01c0e200 0 0x170>, 2183 <0 0x01c0e400 0 0x200>, 2184 <0 0x01c0ea00 0 0x1f0>, 2185 <0 0x01c0e600 0 0x170>, 2186 <0 0x01c0e800 0 0x200>, 2187 <0 0x01c0ee00 0 0xf4>; 2188 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2189 clock-names = "pipe0"; 2190 2191 #phy-cells = <0>; 2192 #clock-cells = <0>; 2193 clock-output-names = "pcie_1_pipe_clk"; 2194 }; 2195 }; 2196 2197 ipa: ipa@1e40000 { 2198 compatible = "qcom,sc7280-ipa"; 2199 2200 iommus = <&apps_smmu 0x480 0x0>, 2201 <&apps_smmu 0x482 0x0>; 2202 reg = <0 0x01e40000 0 0x8000>, 2203 <0 0x01e50000 0 0x4ad0>, 2204 <0 0x01e04000 0 0x23000>; 2205 reg-names = "ipa-reg", 2206 "ipa-shared", 2207 "gsi"; 2208 2209 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2210 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2211 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2212 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2213 interrupt-names = "ipa", 2214 "gsi", 2215 "ipa-clock-query", 2216 "ipa-setup-ready"; 2217 2218 clocks = <&rpmhcc RPMH_IPA_CLK>; 2219 clock-names = "core"; 2220 2221 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2222 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2223 interconnect-names = "memory", 2224 "config"; 2225 2226 qcom,qmp = <&aoss_qmp>; 2227 2228 qcom,smem-states = <&ipa_smp2p_out 0>, 2229 <&ipa_smp2p_out 1>; 2230 qcom,smem-state-names = "ipa-clock-enabled-valid", 2231 "ipa-clock-enabled"; 2232 2233 status = "disabled"; 2234 }; 2235 2236 tcsr_mutex: hwlock@1f40000 { 2237 compatible = "qcom,tcsr-mutex"; 2238 reg = <0 0x01f40000 0 0x20000>; 2239 #hwlock-cells = <1>; 2240 }; 2241 2242 tcsr_1: syscon@1f60000 { 2243 compatible = "qcom,sc7280-tcsr", "syscon"; 2244 reg = <0 0x01f60000 0 0x20000>; 2245 }; 2246 2247 tcsr_2: syscon@1fc0000 { 2248 compatible = "qcom,sc7280-tcsr", "syscon"; 2249 reg = <0 0x01fc0000 0 0x30000>; 2250 }; 2251 2252 lpasscc: lpasscc@3000000 { 2253 compatible = "qcom,sc7280-lpasscc"; 2254 reg = <0 0x03000000 0 0x40>, 2255 <0 0x03c04000 0 0x4>; 2256 reg-names = "qdsp6ss", "top_cc"; 2257 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2258 clock-names = "iface"; 2259 #clock-cells = <1>; 2260 }; 2261 2262 lpass_rx_macro: codec@3200000 { 2263 compatible = "qcom,sc7280-lpass-rx-macro"; 2264 reg = <0 0x03200000 0 0x1000>; 2265 2266 pinctrl-names = "default"; 2267 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2268 2269 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2270 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2271 <&lpass_va_macro>; 2272 clock-names = "mclk", "npl", "fsgen"; 2273 2274 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2275 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2276 power-domain-names = "macro", "dcodec"; 2277 2278 #clock-cells = <0>; 2279 #sound-dai-cells = <1>; 2280 2281 status = "disabled"; 2282 }; 2283 2284 swr0: soundwire@3210000 { 2285 compatible = "qcom,soundwire-v1.6.0"; 2286 reg = <0 0x03210000 0 0x2000>; 2287 2288 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2289 clocks = <&lpass_rx_macro>; 2290 clock-names = "iface"; 2291 2292 qcom,din-ports = <0>; 2293 qcom,dout-ports = <5>; 2294 2295 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2296 reset-names = "swr_audio_cgcr"; 2297 2298 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2299 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2300 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2301 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2302 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2303 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2304 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2305 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2306 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2307 2308 #sound-dai-cells = <1>; 2309 #address-cells = <2>; 2310 #size-cells = <0>; 2311 2312 status = "disabled"; 2313 }; 2314 2315 lpass_tx_macro: codec@3220000 { 2316 compatible = "qcom,sc7280-lpass-tx-macro"; 2317 reg = <0 0x03220000 0 0x1000>; 2318 2319 pinctrl-names = "default"; 2320 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2321 2322 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2323 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2324 <&lpass_va_macro>; 2325 clock-names = "mclk", "npl", "fsgen"; 2326 2327 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2328 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2329 power-domain-names = "macro", "dcodec"; 2330 2331 #clock-cells = <0>; 2332 #sound-dai-cells = <1>; 2333 2334 status = "disabled"; 2335 }; 2336 2337 swr1: soundwire@3230000 { 2338 compatible = "qcom,soundwire-v1.6.0"; 2339 reg = <0 0x03230000 0 0x2000>; 2340 2341 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2342 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2343 clocks = <&lpass_tx_macro>; 2344 clock-names = "iface"; 2345 2346 qcom,din-ports = <3>; 2347 qcom,dout-ports = <0>; 2348 2349 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2350 reset-names = "swr_audio_cgcr"; 2351 2352 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2353 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2354 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2355 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2356 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2357 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2358 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2359 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2360 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2361 2362 #sound-dai-cells = <1>; 2363 #address-cells = <2>; 2364 #size-cells = <0>; 2365 2366 status = "disabled"; 2367 }; 2368 2369 lpass_audiocc: clock-controller@3300000 { 2370 compatible = "qcom,sc7280-lpassaudiocc"; 2371 reg = <0 0x03300000 0 0x30000>, 2372 <0 0x032a9000 0 0x1000>; 2373 clocks = <&rpmhcc RPMH_CXO_CLK>, 2374 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2375 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2376 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2377 #clock-cells = <1>; 2378 #power-domain-cells = <1>; 2379 #reset-cells = <1>; 2380 }; 2381 2382 lpass_va_macro: codec@3370000 { 2383 compatible = "qcom,sc7280-lpass-va-macro"; 2384 reg = <0 0x03370000 0 0x1000>; 2385 2386 pinctrl-names = "default"; 2387 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2388 2389 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2390 clock-names = "mclk"; 2391 2392 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2393 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2394 power-domain-names = "macro", "dcodec"; 2395 2396 #clock-cells = <0>; 2397 #sound-dai-cells = <1>; 2398 2399 status = "disabled"; 2400 }; 2401 2402 lpass_aon: clock-controller@3380000 { 2403 compatible = "qcom,sc7280-lpassaoncc"; 2404 reg = <0 0x03380000 0 0x30000>; 2405 clocks = <&rpmhcc RPMH_CXO_CLK>, 2406 <&rpmhcc RPMH_CXO_CLK_A>, 2407 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2408 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2409 #clock-cells = <1>; 2410 #power-domain-cells = <1>; 2411 }; 2412 2413 lpass_core: clock-controller@3900000 { 2414 compatible = "qcom,sc7280-lpasscorecc"; 2415 reg = <0 0x03900000 0 0x50000>; 2416 clocks = <&rpmhcc RPMH_CXO_CLK>; 2417 clock-names = "bi_tcxo"; 2418 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2419 #clock-cells = <1>; 2420 #power-domain-cells = <1>; 2421 }; 2422 2423 lpass_cpu: audio@3987000 { 2424 compatible = "qcom,sc7280-lpass-cpu"; 2425 2426 reg = <0 0x03987000 0 0x68000>, 2427 <0 0x03b00000 0 0x29000>, 2428 <0 0x03260000 0 0xc000>, 2429 <0 0x03280000 0 0x29000>, 2430 <0 0x03340000 0 0x29000>, 2431 <0 0x0336c000 0 0x3000>; 2432 reg-names = "lpass-hdmiif", 2433 "lpass-lpaif", 2434 "lpass-rxtx-cdc-dma-lpm", 2435 "lpass-rxtx-lpaif", 2436 "lpass-va-lpaif", 2437 "lpass-va-cdc-dma-lpm"; 2438 2439 iommus = <&apps_smmu 0x1820 0>, 2440 <&apps_smmu 0x1821 0>, 2441 <&apps_smmu 0x1832 0>; 2442 2443 power-domains = <&rpmhpd SC7280_LCX>; 2444 power-domain-names = "lcx"; 2445 required-opps = <&rpmhpd_opp_nom>; 2446 2447 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2448 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2449 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2450 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2451 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2452 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2453 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2454 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2455 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2456 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2457 clock-names = "aon_cc_audio_hm_h", 2458 "audio_cc_ext_mclk0", 2459 "core_cc_sysnoc_mport_core", 2460 "core_cc_ext_if0_ibit", 2461 "core_cc_ext_if1_ibit", 2462 "audio_cc_codec_mem", 2463 "audio_cc_codec_mem0", 2464 "audio_cc_codec_mem1", 2465 "audio_cc_codec_mem2", 2466 "aon_cc_va_mem0"; 2467 2468 #sound-dai-cells = <1>; 2469 #address-cells = <1>; 2470 #size-cells = <0>; 2471 2472 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2473 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2474 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2475 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2476 interrupt-names = "lpass-irq-lpaif", 2477 "lpass-irq-hdmi", 2478 "lpass-irq-vaif", 2479 "lpass-irq-rxtxif"; 2480 2481 status = "disabled"; 2482 }; 2483 2484 lpass_hm: clock-controller@3c00000 { 2485 compatible = "qcom,sc7280-lpasshm"; 2486 reg = <0 0x03c00000 0 0x28>; 2487 clocks = <&rpmhcc RPMH_CXO_CLK>; 2488 clock-names = "bi_tcxo"; 2489 #clock-cells = <1>; 2490 #power-domain-cells = <1>; 2491 }; 2492 2493 lpass_ag_noc: interconnect@3c40000 { 2494 reg = <0 0x03c40000 0 0xf080>; 2495 compatible = "qcom,sc7280-lpass-ag-noc"; 2496 #interconnect-cells = <2>; 2497 qcom,bcm-voters = <&apps_bcm_voter>; 2498 }; 2499 2500 lpass_tlmm: pinctrl@33c0000 { 2501 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2502 reg = <0 0x033c0000 0x0 0x20000>, 2503 <0 0x03550000 0x0 0x10000>; 2504 qcom,adsp-bypass-mode; 2505 gpio-controller; 2506 #gpio-cells = <2>; 2507 gpio-ranges = <&lpass_tlmm 0 0 15>; 2508 2509 lpass_dmic01_clk: dmic01-clk-state { 2510 pins = "gpio6"; 2511 function = "dmic1_clk"; 2512 }; 2513 2514 lpass_dmic01_data: dmic01-data-state { 2515 pins = "gpio7"; 2516 function = "dmic1_data"; 2517 }; 2518 2519 lpass_dmic23_clk: dmic23-clk-state { 2520 pins = "gpio8"; 2521 function = "dmic2_clk"; 2522 }; 2523 2524 lpass_dmic23_data: dmic23-data-state { 2525 pins = "gpio9"; 2526 function = "dmic2_data"; 2527 }; 2528 2529 lpass_rx_swr_clk: rx-swr-clk-state { 2530 pins = "gpio3"; 2531 function = "swr_rx_clk"; 2532 }; 2533 2534 lpass_rx_swr_data: rx-swr-data-state { 2535 pins = "gpio4", "gpio5"; 2536 function = "swr_rx_data"; 2537 }; 2538 2539 lpass_tx_swr_clk: tx-swr-clk-state { 2540 pins = "gpio0"; 2541 function = "swr_tx_clk"; 2542 }; 2543 2544 lpass_tx_swr_data: tx-swr-data-state { 2545 pins = "gpio1", "gpio2", "gpio14"; 2546 function = "swr_tx_data"; 2547 }; 2548 }; 2549 2550 gpu: gpu@3d00000 { 2551 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2552 reg = <0 0x03d00000 0 0x40000>, 2553 <0 0x03d9e000 0 0x1000>, 2554 <0 0x03d61000 0 0x800>; 2555 reg-names = "kgsl_3d0_reg_memory", 2556 "cx_mem", 2557 "cx_dbgc"; 2558 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2559 iommus = <&adreno_smmu 0 0x401>; 2560 operating-points-v2 = <&gpu_opp_table>; 2561 qcom,gmu = <&gmu>; 2562 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2563 interconnect-names = "gfx-mem"; 2564 #cooling-cells = <2>; 2565 2566 nvmem-cells = <&gpu_speed_bin>; 2567 nvmem-cell-names = "speed_bin"; 2568 2569 gpu_opp_table: opp-table { 2570 compatible = "operating-points-v2"; 2571 2572 opp-315000000 { 2573 opp-hz = /bits/ 64 <315000000>; 2574 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2575 opp-peak-kBps = <1804000>; 2576 opp-supported-hw = <0x03>; 2577 }; 2578 2579 opp-450000000 { 2580 opp-hz = /bits/ 64 <450000000>; 2581 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2582 opp-peak-kBps = <4068000>; 2583 opp-supported-hw = <0x03>; 2584 }; 2585 2586 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2587 opp-550000000-0 { 2588 opp-hz = /bits/ 64 <550000000>; 2589 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2590 opp-peak-kBps = <8368000>; 2591 opp-supported-hw = <0x01>; 2592 }; 2593 2594 opp-550000000-1 { 2595 opp-hz = /bits/ 64 <550000000>; 2596 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2597 opp-peak-kBps = <6832000>; 2598 opp-supported-hw = <0x02>; 2599 }; 2600 2601 opp-608000000 { 2602 opp-hz = /bits/ 64 <608000000>; 2603 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2604 opp-peak-kBps = <8368000>; 2605 opp-supported-hw = <0x02>; 2606 }; 2607 2608 opp-700000000 { 2609 opp-hz = /bits/ 64 <700000000>; 2610 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2611 opp-peak-kBps = <8532000>; 2612 opp-supported-hw = <0x02>; 2613 }; 2614 2615 opp-812000000 { 2616 opp-hz = /bits/ 64 <812000000>; 2617 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2618 opp-peak-kBps = <8532000>; 2619 opp-supported-hw = <0x02>; 2620 }; 2621 2622 opp-840000000 { 2623 opp-hz = /bits/ 64 <840000000>; 2624 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2625 opp-peak-kBps = <8532000>; 2626 opp-supported-hw = <0x02>; 2627 }; 2628 2629 opp-900000000 { 2630 opp-hz = /bits/ 64 <900000000>; 2631 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2632 opp-peak-kBps = <8532000>; 2633 opp-supported-hw = <0x02>; 2634 }; 2635 }; 2636 }; 2637 2638 gmu: gmu@3d6a000 { 2639 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2640 reg = <0 0x03d6a000 0 0x34000>, 2641 <0 0x3de0000 0 0x10000>, 2642 <0 0x0b290000 0 0x10000>; 2643 reg-names = "gmu", "rscc", "gmu_pdc"; 2644 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2645 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2646 interrupt-names = "hfi", "gmu"; 2647 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2648 <&gpucc GPU_CC_CXO_CLK>, 2649 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2650 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2651 <&gpucc GPU_CC_AHB_CLK>, 2652 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2653 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2654 clock-names = "gmu", 2655 "cxo", 2656 "axi", 2657 "memnoc", 2658 "ahb", 2659 "hub", 2660 "smmu_vote"; 2661 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2662 <&gpucc GPU_CC_GX_GDSC>; 2663 power-domain-names = "cx", 2664 "gx"; 2665 iommus = <&adreno_smmu 5 0x400>; 2666 operating-points-v2 = <&gmu_opp_table>; 2667 2668 gmu_opp_table: opp-table { 2669 compatible = "operating-points-v2"; 2670 2671 opp-200000000 { 2672 opp-hz = /bits/ 64 <200000000>; 2673 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2674 }; 2675 }; 2676 }; 2677 2678 gpucc: clock-controller@3d90000 { 2679 compatible = "qcom,sc7280-gpucc"; 2680 reg = <0 0x03d90000 0 0x9000>; 2681 clocks = <&rpmhcc RPMH_CXO_CLK>, 2682 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2683 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2684 clock-names = "bi_tcxo", 2685 "gcc_gpu_gpll0_clk_src", 2686 "gcc_gpu_gpll0_div_clk_src"; 2687 #clock-cells = <1>; 2688 #reset-cells = <1>; 2689 #power-domain-cells = <1>; 2690 }; 2691 2692 dma@117f000 { 2693 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 2694 reg = <0x0 0x0117f000 0x0 0x1000>, 2695 <0x0 0x01112000 0x0 0x6000>; 2696 }; 2697 2698 adreno_smmu: iommu@3da0000 { 2699 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", 2700 "qcom,smmu-500", "arm,mmu-500"; 2701 reg = <0 0x03da0000 0 0x20000>; 2702 #iommu-cells = <2>; 2703 #global-interrupts = <2>; 2704 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2705 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2706 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2707 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2708 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2709 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2710 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2711 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2712 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2713 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2714 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2715 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2716 2717 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2718 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2719 <&gpucc GPU_CC_AHB_CLK>, 2720 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2721 <&gpucc GPU_CC_CX_GMU_CLK>, 2722 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2723 <&gpucc GPU_CC_HUB_AON_CLK>; 2724 clock-names = "gcc_gpu_memnoc_gfx_clk", 2725 "gcc_gpu_snoc_dvm_gfx_clk", 2726 "gpu_cc_ahb_clk", 2727 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2728 "gpu_cc_cx_gmu_clk", 2729 "gpu_cc_hub_cx_int_clk", 2730 "gpu_cc_hub_aon_clk"; 2731 2732 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2733 }; 2734 2735 remoteproc_mpss: remoteproc@4080000 { 2736 compatible = "qcom,sc7280-mpss-pas"; 2737 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2738 reg-names = "qdsp6", "rmb"; 2739 2740 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2741 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2742 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2743 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2744 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2745 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2746 interrupt-names = "wdog", "fatal", "ready", "handover", 2747 "stop-ack", "shutdown-ack"; 2748 2749 clocks = <&rpmhcc RPMH_CXO_CLK>; 2750 clock-names = "xo"; 2751 2752 power-domains = <&rpmhpd SC7280_CX>, 2753 <&rpmhpd SC7280_MSS>; 2754 power-domain-names = "cx", "mss"; 2755 2756 memory-region = <&mpss_mem>; 2757 2758 qcom,qmp = <&aoss_qmp>; 2759 2760 qcom,smem-states = <&modem_smp2p_out 0>; 2761 qcom,smem-state-names = "stop"; 2762 2763 status = "disabled"; 2764 2765 glink-edge { 2766 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2767 IPCC_MPROC_SIGNAL_GLINK_QMP 2768 IRQ_TYPE_EDGE_RISING>; 2769 mboxes = <&ipcc IPCC_CLIENT_MPSS 2770 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2771 label = "modem"; 2772 qcom,remote-pid = <1>; 2773 }; 2774 }; 2775 2776 stm@6002000 { 2777 compatible = "arm,coresight-stm", "arm,primecell"; 2778 reg = <0 0x06002000 0 0x1000>, 2779 <0 0x16280000 0 0x180000>; 2780 reg-names = "stm-base", "stm-stimulus-base"; 2781 2782 clocks = <&aoss_qmp>; 2783 clock-names = "apb_pclk"; 2784 2785 out-ports { 2786 port { 2787 stm_out: endpoint { 2788 remote-endpoint = <&funnel0_in7>; 2789 }; 2790 }; 2791 }; 2792 }; 2793 2794 funnel@6041000 { 2795 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2796 reg = <0 0x06041000 0 0x1000>; 2797 2798 clocks = <&aoss_qmp>; 2799 clock-names = "apb_pclk"; 2800 2801 out-ports { 2802 port { 2803 funnel0_out: endpoint { 2804 remote-endpoint = <&merge_funnel_in0>; 2805 }; 2806 }; 2807 }; 2808 2809 in-ports { 2810 #address-cells = <1>; 2811 #size-cells = <0>; 2812 2813 port@7 { 2814 reg = <7>; 2815 funnel0_in7: endpoint { 2816 remote-endpoint = <&stm_out>; 2817 }; 2818 }; 2819 }; 2820 }; 2821 2822 funnel@6042000 { 2823 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2824 reg = <0 0x06042000 0 0x1000>; 2825 2826 clocks = <&aoss_qmp>; 2827 clock-names = "apb_pclk"; 2828 2829 out-ports { 2830 port { 2831 funnel1_out: endpoint { 2832 remote-endpoint = <&merge_funnel_in1>; 2833 }; 2834 }; 2835 }; 2836 2837 in-ports { 2838 #address-cells = <1>; 2839 #size-cells = <0>; 2840 2841 port@4 { 2842 reg = <4>; 2843 funnel1_in4: endpoint { 2844 remote-endpoint = <&apss_merge_funnel_out>; 2845 }; 2846 }; 2847 }; 2848 }; 2849 2850 funnel@6045000 { 2851 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2852 reg = <0 0x06045000 0 0x1000>; 2853 2854 clocks = <&aoss_qmp>; 2855 clock-names = "apb_pclk"; 2856 2857 out-ports { 2858 port { 2859 merge_funnel_out: endpoint { 2860 remote-endpoint = <&swao_funnel_in>; 2861 }; 2862 }; 2863 }; 2864 2865 in-ports { 2866 #address-cells = <1>; 2867 #size-cells = <0>; 2868 2869 port@0 { 2870 reg = <0>; 2871 merge_funnel_in0: endpoint { 2872 remote-endpoint = <&funnel0_out>; 2873 }; 2874 }; 2875 2876 port@1 { 2877 reg = <1>; 2878 merge_funnel_in1: endpoint { 2879 remote-endpoint = <&funnel1_out>; 2880 }; 2881 }; 2882 }; 2883 }; 2884 2885 replicator@6046000 { 2886 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2887 reg = <0 0x06046000 0 0x1000>; 2888 2889 clocks = <&aoss_qmp>; 2890 clock-names = "apb_pclk"; 2891 2892 out-ports { 2893 port { 2894 replicator_out: endpoint { 2895 remote-endpoint = <&etr_in>; 2896 }; 2897 }; 2898 }; 2899 2900 in-ports { 2901 port { 2902 replicator_in: endpoint { 2903 remote-endpoint = <&swao_replicator_out>; 2904 }; 2905 }; 2906 }; 2907 }; 2908 2909 etr@6048000 { 2910 compatible = "arm,coresight-tmc", "arm,primecell"; 2911 reg = <0 0x06048000 0 0x1000>; 2912 iommus = <&apps_smmu 0x04c0 0>; 2913 2914 clocks = <&aoss_qmp>; 2915 clock-names = "apb_pclk"; 2916 arm,scatter-gather; 2917 2918 in-ports { 2919 port { 2920 etr_in: endpoint { 2921 remote-endpoint = <&replicator_out>; 2922 }; 2923 }; 2924 }; 2925 }; 2926 2927 funnel@6b04000 { 2928 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2929 reg = <0 0x06b04000 0 0x1000>; 2930 2931 clocks = <&aoss_qmp>; 2932 clock-names = "apb_pclk"; 2933 2934 out-ports { 2935 port { 2936 swao_funnel_out: endpoint { 2937 remote-endpoint = <&etf_in>; 2938 }; 2939 }; 2940 }; 2941 2942 in-ports { 2943 #address-cells = <1>; 2944 #size-cells = <0>; 2945 2946 port@7 { 2947 reg = <7>; 2948 swao_funnel_in: endpoint { 2949 remote-endpoint = <&merge_funnel_out>; 2950 }; 2951 }; 2952 }; 2953 }; 2954 2955 etf@6b05000 { 2956 compatible = "arm,coresight-tmc", "arm,primecell"; 2957 reg = <0 0x06b05000 0 0x1000>; 2958 2959 clocks = <&aoss_qmp>; 2960 clock-names = "apb_pclk"; 2961 2962 out-ports { 2963 port { 2964 etf_out: endpoint { 2965 remote-endpoint = <&swao_replicator_in>; 2966 }; 2967 }; 2968 }; 2969 2970 in-ports { 2971 port { 2972 etf_in: endpoint { 2973 remote-endpoint = <&swao_funnel_out>; 2974 }; 2975 }; 2976 }; 2977 }; 2978 2979 replicator@6b06000 { 2980 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2981 reg = <0 0x06b06000 0 0x1000>; 2982 2983 clocks = <&aoss_qmp>; 2984 clock-names = "apb_pclk"; 2985 qcom,replicator-loses-context; 2986 2987 out-ports { 2988 port { 2989 swao_replicator_out: endpoint { 2990 remote-endpoint = <&replicator_in>; 2991 }; 2992 }; 2993 }; 2994 2995 in-ports { 2996 port { 2997 swao_replicator_in: endpoint { 2998 remote-endpoint = <&etf_out>; 2999 }; 3000 }; 3001 }; 3002 }; 3003 3004 etm@7040000 { 3005 compatible = "arm,coresight-etm4x", "arm,primecell"; 3006 reg = <0 0x07040000 0 0x1000>; 3007 3008 cpu = <&CPU0>; 3009 3010 clocks = <&aoss_qmp>; 3011 clock-names = "apb_pclk"; 3012 arm,coresight-loses-context-with-cpu; 3013 qcom,skip-power-up; 3014 3015 out-ports { 3016 port { 3017 etm0_out: endpoint { 3018 remote-endpoint = <&apss_funnel_in0>; 3019 }; 3020 }; 3021 }; 3022 }; 3023 3024 etm@7140000 { 3025 compatible = "arm,coresight-etm4x", "arm,primecell"; 3026 reg = <0 0x07140000 0 0x1000>; 3027 3028 cpu = <&CPU1>; 3029 3030 clocks = <&aoss_qmp>; 3031 clock-names = "apb_pclk"; 3032 arm,coresight-loses-context-with-cpu; 3033 qcom,skip-power-up; 3034 3035 out-ports { 3036 port { 3037 etm1_out: endpoint { 3038 remote-endpoint = <&apss_funnel_in1>; 3039 }; 3040 }; 3041 }; 3042 }; 3043 3044 etm@7240000 { 3045 compatible = "arm,coresight-etm4x", "arm,primecell"; 3046 reg = <0 0x07240000 0 0x1000>; 3047 3048 cpu = <&CPU2>; 3049 3050 clocks = <&aoss_qmp>; 3051 clock-names = "apb_pclk"; 3052 arm,coresight-loses-context-with-cpu; 3053 qcom,skip-power-up; 3054 3055 out-ports { 3056 port { 3057 etm2_out: endpoint { 3058 remote-endpoint = <&apss_funnel_in2>; 3059 }; 3060 }; 3061 }; 3062 }; 3063 3064 etm@7340000 { 3065 compatible = "arm,coresight-etm4x", "arm,primecell"; 3066 reg = <0 0x07340000 0 0x1000>; 3067 3068 cpu = <&CPU3>; 3069 3070 clocks = <&aoss_qmp>; 3071 clock-names = "apb_pclk"; 3072 arm,coresight-loses-context-with-cpu; 3073 qcom,skip-power-up; 3074 3075 out-ports { 3076 port { 3077 etm3_out: endpoint { 3078 remote-endpoint = <&apss_funnel_in3>; 3079 }; 3080 }; 3081 }; 3082 }; 3083 3084 etm@7440000 { 3085 compatible = "arm,coresight-etm4x", "arm,primecell"; 3086 reg = <0 0x07440000 0 0x1000>; 3087 3088 cpu = <&CPU4>; 3089 3090 clocks = <&aoss_qmp>; 3091 clock-names = "apb_pclk"; 3092 arm,coresight-loses-context-with-cpu; 3093 qcom,skip-power-up; 3094 3095 out-ports { 3096 port { 3097 etm4_out: endpoint { 3098 remote-endpoint = <&apss_funnel_in4>; 3099 }; 3100 }; 3101 }; 3102 }; 3103 3104 etm@7540000 { 3105 compatible = "arm,coresight-etm4x", "arm,primecell"; 3106 reg = <0 0x07540000 0 0x1000>; 3107 3108 cpu = <&CPU5>; 3109 3110 clocks = <&aoss_qmp>; 3111 clock-names = "apb_pclk"; 3112 arm,coresight-loses-context-with-cpu; 3113 qcom,skip-power-up; 3114 3115 out-ports { 3116 port { 3117 etm5_out: endpoint { 3118 remote-endpoint = <&apss_funnel_in5>; 3119 }; 3120 }; 3121 }; 3122 }; 3123 3124 etm@7640000 { 3125 compatible = "arm,coresight-etm4x", "arm,primecell"; 3126 reg = <0 0x07640000 0 0x1000>; 3127 3128 cpu = <&CPU6>; 3129 3130 clocks = <&aoss_qmp>; 3131 clock-names = "apb_pclk"; 3132 arm,coresight-loses-context-with-cpu; 3133 qcom,skip-power-up; 3134 3135 out-ports { 3136 port { 3137 etm6_out: endpoint { 3138 remote-endpoint = <&apss_funnel_in6>; 3139 }; 3140 }; 3141 }; 3142 }; 3143 3144 etm@7740000 { 3145 compatible = "arm,coresight-etm4x", "arm,primecell"; 3146 reg = <0 0x07740000 0 0x1000>; 3147 3148 cpu = <&CPU7>; 3149 3150 clocks = <&aoss_qmp>; 3151 clock-names = "apb_pclk"; 3152 arm,coresight-loses-context-with-cpu; 3153 qcom,skip-power-up; 3154 3155 out-ports { 3156 port { 3157 etm7_out: endpoint { 3158 remote-endpoint = <&apss_funnel_in7>; 3159 }; 3160 }; 3161 }; 3162 }; 3163 3164 funnel@7800000 { /* APSS Funnel */ 3165 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3166 reg = <0 0x07800000 0 0x1000>; 3167 3168 clocks = <&aoss_qmp>; 3169 clock-names = "apb_pclk"; 3170 3171 out-ports { 3172 port { 3173 apss_funnel_out: endpoint { 3174 remote-endpoint = <&apss_merge_funnel_in>; 3175 }; 3176 }; 3177 }; 3178 3179 in-ports { 3180 #address-cells = <1>; 3181 #size-cells = <0>; 3182 3183 port@0 { 3184 reg = <0>; 3185 apss_funnel_in0: endpoint { 3186 remote-endpoint = <&etm0_out>; 3187 }; 3188 }; 3189 3190 port@1 { 3191 reg = <1>; 3192 apss_funnel_in1: endpoint { 3193 remote-endpoint = <&etm1_out>; 3194 }; 3195 }; 3196 3197 port@2 { 3198 reg = <2>; 3199 apss_funnel_in2: endpoint { 3200 remote-endpoint = <&etm2_out>; 3201 }; 3202 }; 3203 3204 port@3 { 3205 reg = <3>; 3206 apss_funnel_in3: endpoint { 3207 remote-endpoint = <&etm3_out>; 3208 }; 3209 }; 3210 3211 port@4 { 3212 reg = <4>; 3213 apss_funnel_in4: endpoint { 3214 remote-endpoint = <&etm4_out>; 3215 }; 3216 }; 3217 3218 port@5 { 3219 reg = <5>; 3220 apss_funnel_in5: endpoint { 3221 remote-endpoint = <&etm5_out>; 3222 }; 3223 }; 3224 3225 port@6 { 3226 reg = <6>; 3227 apss_funnel_in6: endpoint { 3228 remote-endpoint = <&etm6_out>; 3229 }; 3230 }; 3231 3232 port@7 { 3233 reg = <7>; 3234 apss_funnel_in7: endpoint { 3235 remote-endpoint = <&etm7_out>; 3236 }; 3237 }; 3238 }; 3239 }; 3240 3241 funnel@7810000 { 3242 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3243 reg = <0 0x07810000 0 0x1000>; 3244 3245 clocks = <&aoss_qmp>; 3246 clock-names = "apb_pclk"; 3247 3248 out-ports { 3249 port { 3250 apss_merge_funnel_out: endpoint { 3251 remote-endpoint = <&funnel1_in4>; 3252 }; 3253 }; 3254 }; 3255 3256 in-ports { 3257 port { 3258 apss_merge_funnel_in: endpoint { 3259 remote-endpoint = <&apss_funnel_out>; 3260 }; 3261 }; 3262 }; 3263 }; 3264 3265 sdhc_2: mmc@8804000 { 3266 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3267 pinctrl-names = "default", "sleep"; 3268 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3269 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3270 status = "disabled"; 3271 3272 reg = <0 0x08804000 0 0x1000>; 3273 3274 iommus = <&apps_smmu 0x100 0x0>; 3275 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3276 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3277 interrupt-names = "hc_irq", "pwr_irq"; 3278 3279 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3280 <&gcc GCC_SDCC2_APPS_CLK>, 3281 <&rpmhcc RPMH_CXO_CLK>; 3282 clock-names = "iface", "core", "xo"; 3283 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3284 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3285 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3286 power-domains = <&rpmhpd SC7280_CX>; 3287 operating-points-v2 = <&sdhc2_opp_table>; 3288 3289 bus-width = <4>; 3290 3291 qcom,dll-config = <0x0007642c>; 3292 3293 resets = <&gcc GCC_SDCC2_BCR>; 3294 3295 sdhc2_opp_table: opp-table { 3296 compatible = "operating-points-v2"; 3297 3298 opp-100000000 { 3299 opp-hz = /bits/ 64 <100000000>; 3300 required-opps = <&rpmhpd_opp_low_svs>; 3301 opp-peak-kBps = <1800000 400000>; 3302 opp-avg-kBps = <100000 0>; 3303 }; 3304 3305 opp-202000000 { 3306 opp-hz = /bits/ 64 <202000000>; 3307 required-opps = <&rpmhpd_opp_nom>; 3308 opp-peak-kBps = <5400000 1600000>; 3309 opp-avg-kBps = <200000 0>; 3310 }; 3311 }; 3312 }; 3313 3314 usb_1_hsphy: phy@88e3000 { 3315 compatible = "qcom,sc7280-usb-hs-phy", 3316 "qcom,usb-snps-hs-7nm-phy"; 3317 reg = <0 0x088e3000 0 0x400>; 3318 status = "disabled"; 3319 #phy-cells = <0>; 3320 3321 clocks = <&rpmhcc RPMH_CXO_CLK>; 3322 clock-names = "ref"; 3323 3324 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3325 }; 3326 3327 usb_2_hsphy: phy@88e4000 { 3328 compatible = "qcom,sc7280-usb-hs-phy", 3329 "qcom,usb-snps-hs-7nm-phy"; 3330 reg = <0 0x088e4000 0 0x400>; 3331 status = "disabled"; 3332 #phy-cells = <0>; 3333 3334 clocks = <&rpmhcc RPMH_CXO_CLK>; 3335 clock-names = "ref"; 3336 3337 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3338 }; 3339 3340 usb_1_qmpphy: phy-wrapper@88e9000 { 3341 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3342 "qcom,sm8250-qmp-usb3-dp-phy"; 3343 reg = <0 0x088e9000 0 0x200>, 3344 <0 0x088e8000 0 0x40>, 3345 <0 0x088ea000 0 0x200>; 3346 status = "disabled"; 3347 #address-cells = <2>; 3348 #size-cells = <2>; 3349 ranges; 3350 3351 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3352 <&rpmhcc RPMH_CXO_CLK>, 3353 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3354 clock-names = "aux", "ref_clk_src", "com_aux"; 3355 3356 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3357 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3358 reset-names = "phy", "common"; 3359 3360 usb_1_ssphy: usb3-phy@88e9200 { 3361 reg = <0 0x088e9200 0 0x200>, 3362 <0 0x088e9400 0 0x200>, 3363 <0 0x088e9c00 0 0x400>, 3364 <0 0x088e9600 0 0x200>, 3365 <0 0x088e9800 0 0x200>, 3366 <0 0x088e9a00 0 0x100>; 3367 #clock-cells = <0>; 3368 #phy-cells = <0>; 3369 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3370 clock-names = "pipe0"; 3371 clock-output-names = "usb3_phy_pipe_clk_src"; 3372 }; 3373 3374 dp_phy: dp-phy@88ea200 { 3375 reg = <0 0x088ea200 0 0x200>, 3376 <0 0x088ea400 0 0x200>, 3377 <0 0x088eaa00 0 0x200>, 3378 <0 0x088ea600 0 0x200>, 3379 <0 0x088ea800 0 0x200>; 3380 #phy-cells = <0>; 3381 #clock-cells = <1>; 3382 }; 3383 }; 3384 3385 usb_2: usb@8cf8800 { 3386 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3387 reg = <0 0x08cf8800 0 0x400>; 3388 status = "disabled"; 3389 #address-cells = <2>; 3390 #size-cells = <2>; 3391 ranges; 3392 dma-ranges; 3393 3394 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3395 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3396 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3397 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3398 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3399 clock-names = "cfg_noc", 3400 "core", 3401 "iface", 3402 "sleep", 3403 "mock_utmi"; 3404 3405 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3406 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3407 assigned-clock-rates = <19200000>, <200000000>; 3408 3409 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3410 <&pdc 12 IRQ_TYPE_EDGE_RISING>, 3411 <&pdc 13 IRQ_TYPE_EDGE_RISING>; 3412 interrupt-names = "hs_phy_irq", 3413 "dp_hs_phy_irq", 3414 "dm_hs_phy_irq"; 3415 3416 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3417 required-opps = <&rpmhpd_opp_nom>; 3418 3419 resets = <&gcc GCC_USB30_SEC_BCR>; 3420 3421 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3422 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3423 interconnect-names = "usb-ddr", "apps-usb"; 3424 3425 usb_2_dwc3: usb@8c00000 { 3426 compatible = "snps,dwc3"; 3427 reg = <0 0x08c00000 0 0xe000>; 3428 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3429 iommus = <&apps_smmu 0xa0 0x0>; 3430 snps,dis_u2_susphy_quirk; 3431 snps,dis_enblslpm_quirk; 3432 phys = <&usb_2_hsphy>; 3433 phy-names = "usb2-phy"; 3434 maximum-speed = "high-speed"; 3435 usb-role-switch; 3436 3437 port { 3438 usb2_role_switch: endpoint { 3439 remote-endpoint = <&eud_ep>; 3440 }; 3441 }; 3442 }; 3443 }; 3444 3445 qspi: spi@88dc000 { 3446 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3447 reg = <0 0x088dc000 0 0x1000>; 3448 iommus = <&apps_smmu 0x20 0x0>; 3449 #address-cells = <1>; 3450 #size-cells = <0>; 3451 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3452 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3453 <&gcc GCC_QSPI_CORE_CLK>; 3454 clock-names = "iface", "core"; 3455 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3456 &cnoc2 SLAVE_QSPI_0 0>; 3457 interconnect-names = "qspi-config"; 3458 power-domains = <&rpmhpd SC7280_CX>; 3459 operating-points-v2 = <&qspi_opp_table>; 3460 status = "disabled"; 3461 }; 3462 3463 remoteproc_wpss: remoteproc@8a00000 { 3464 compatible = "qcom,sc7280-wpss-pil"; 3465 reg = <0 0x08a00000 0 0x10000>; 3466 3467 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3468 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3469 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3470 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3471 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3472 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3473 interrupt-names = "wdog", "fatal", "ready", "handover", 3474 "stop-ack", "shutdown-ack"; 3475 3476 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3477 <&gcc GCC_WPSS_AHB_CLK>, 3478 <&gcc GCC_WPSS_RSCP_CLK>, 3479 <&rpmhcc RPMH_CXO_CLK>; 3480 clock-names = "ahb_bdg", "ahb", 3481 "rscp", "xo"; 3482 3483 power-domains = <&rpmhpd SC7280_CX>, 3484 <&rpmhpd SC7280_MX>; 3485 power-domain-names = "cx", "mx"; 3486 3487 memory-region = <&wpss_mem>; 3488 3489 qcom,qmp = <&aoss_qmp>; 3490 3491 qcom,smem-states = <&wpss_smp2p_out 0>; 3492 qcom,smem-state-names = "stop"; 3493 3494 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3495 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3496 reset-names = "restart", "pdc_sync"; 3497 3498 qcom,halt-regs = <&tcsr_1 0x17000>; 3499 3500 status = "disabled"; 3501 3502 glink-edge { 3503 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3504 IPCC_MPROC_SIGNAL_GLINK_QMP 3505 IRQ_TYPE_EDGE_RISING>; 3506 mboxes = <&ipcc IPCC_CLIENT_WPSS 3507 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3508 3509 label = "wpss"; 3510 qcom,remote-pid = <13>; 3511 }; 3512 }; 3513 3514 pmu@9091000 { 3515 compatible = "qcom,sc7280-llcc-bwmon"; 3516 reg = <0 0x09091000 0 0x1000>; 3517 3518 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3519 3520 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3521 3522 operating-points-v2 = <&llcc_bwmon_opp_table>; 3523 3524 llcc_bwmon_opp_table: opp-table { 3525 compatible = "operating-points-v2"; 3526 3527 opp-0 { 3528 opp-peak-kBps = <800000>; 3529 }; 3530 opp-1 { 3531 opp-peak-kBps = <1804000>; 3532 }; 3533 opp-2 { 3534 opp-peak-kBps = <2188000>; 3535 }; 3536 opp-3 { 3537 opp-peak-kBps = <3072000>; 3538 }; 3539 opp-4 { 3540 opp-peak-kBps = <4068000>; 3541 }; 3542 opp-5 { 3543 opp-peak-kBps = <6220000>; 3544 }; 3545 opp-6 { 3546 opp-peak-kBps = <6832000>; 3547 }; 3548 opp-7 { 3549 opp-peak-kBps = <8532000>; 3550 }; 3551 }; 3552 }; 3553 3554 pmu@90b6400 { 3555 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; 3556 reg = <0 0x090b6400 0 0x600>; 3557 3558 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3559 3560 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3561 operating-points-v2 = <&cpu_bwmon_opp_table>; 3562 3563 cpu_bwmon_opp_table: opp-table { 3564 compatible = "operating-points-v2"; 3565 3566 opp-0 { 3567 opp-peak-kBps = <2400000>; 3568 }; 3569 opp-1 { 3570 opp-peak-kBps = <4800000>; 3571 }; 3572 opp-2 { 3573 opp-peak-kBps = <7456000>; 3574 }; 3575 opp-3 { 3576 opp-peak-kBps = <9600000>; 3577 }; 3578 opp-4 { 3579 opp-peak-kBps = <12896000>; 3580 }; 3581 opp-5 { 3582 opp-peak-kBps = <14928000>; 3583 }; 3584 opp-6 { 3585 opp-peak-kBps = <17056000>; 3586 }; 3587 }; 3588 }; 3589 3590 dc_noc: interconnect@90e0000 { 3591 reg = <0 0x090e0000 0 0x5080>; 3592 compatible = "qcom,sc7280-dc-noc"; 3593 #interconnect-cells = <2>; 3594 qcom,bcm-voters = <&apps_bcm_voter>; 3595 }; 3596 3597 gem_noc: interconnect@9100000 { 3598 reg = <0 0x09100000 0 0xe2200>; 3599 compatible = "qcom,sc7280-gem-noc"; 3600 #interconnect-cells = <2>; 3601 qcom,bcm-voters = <&apps_bcm_voter>; 3602 }; 3603 3604 system-cache-controller@9200000 { 3605 compatible = "qcom,sc7280-llcc"; 3606 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3607 <0 0x09600000 0 0x58000>; 3608 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; 3609 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3610 }; 3611 3612 eud: eud@88e0000 { 3613 compatible = "qcom,sc7280-eud", "qcom,eud"; 3614 reg = <0 0x88e0000 0 0x2000>, 3615 <0 0x88e2000 0 0x1000>; 3616 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3617 3618 ports { 3619 #address-cells = <1>; 3620 #size-cells = <0>; 3621 3622 port@0 { 3623 reg = <0>; 3624 eud_ep: endpoint { 3625 remote-endpoint = <&usb2_role_switch>; 3626 }; 3627 }; 3628 3629 port@1 { 3630 reg = <1>; 3631 eud_con: endpoint { 3632 remote-endpoint = <&con_eud>; 3633 }; 3634 }; 3635 }; 3636 }; 3637 3638 nsp_noc: interconnect@a0c0000 { 3639 reg = <0 0x0a0c0000 0 0x10000>; 3640 compatible = "qcom,sc7280-nsp-noc"; 3641 #interconnect-cells = <2>; 3642 qcom,bcm-voters = <&apps_bcm_voter>; 3643 }; 3644 3645 usb_1: usb@a6f8800 { 3646 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3647 reg = <0 0x0a6f8800 0 0x400>; 3648 status = "disabled"; 3649 #address-cells = <2>; 3650 #size-cells = <2>; 3651 ranges; 3652 dma-ranges; 3653 3654 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3655 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3656 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3657 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3658 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3659 clock-names = "cfg_noc", 3660 "core", 3661 "iface", 3662 "sleep", 3663 "mock_utmi"; 3664 3665 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3666 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3667 assigned-clock-rates = <19200000>, <200000000>; 3668 3669 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3670 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3671 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3672 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3673 interrupt-names = "hs_phy_irq", 3674 "dp_hs_phy_irq", 3675 "dm_hs_phy_irq", 3676 "ss_phy_irq"; 3677 3678 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3679 required-opps = <&rpmhpd_opp_nom>; 3680 3681 resets = <&gcc GCC_USB30_PRIM_BCR>; 3682 3683 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3684 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3685 interconnect-names = "usb-ddr", "apps-usb"; 3686 3687 wakeup-source; 3688 3689 usb_1_dwc3: usb@a600000 { 3690 compatible = "snps,dwc3"; 3691 reg = <0 0x0a600000 0 0xe000>; 3692 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3693 iommus = <&apps_smmu 0xe0 0x0>; 3694 snps,dis_u2_susphy_quirk; 3695 snps,dis_enblslpm_quirk; 3696 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3697 phy-names = "usb2-phy", "usb3-phy"; 3698 maximum-speed = "super-speed"; 3699 }; 3700 }; 3701 3702 venus: video-codec@aa00000 { 3703 compatible = "qcom,sc7280-venus"; 3704 reg = <0 0x0aa00000 0 0xd0600>; 3705 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3706 3707 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3708 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3709 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3710 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3711 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3712 clock-names = "core", "bus", "iface", 3713 "vcodec_core", "vcodec_bus"; 3714 3715 power-domains = <&videocc MVSC_GDSC>, 3716 <&videocc MVS0_GDSC>, 3717 <&rpmhpd SC7280_CX>; 3718 power-domain-names = "venus", "vcodec0", "cx"; 3719 operating-points-v2 = <&venus_opp_table>; 3720 3721 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3722 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3723 interconnect-names = "cpu-cfg", "video-mem"; 3724 3725 iommus = <&apps_smmu 0x2180 0x20>, 3726 <&apps_smmu 0x2184 0x20>; 3727 memory-region = <&video_mem>; 3728 3729 video-decoder { 3730 compatible = "venus-decoder"; 3731 }; 3732 3733 video-encoder { 3734 compatible = "venus-encoder"; 3735 }; 3736 3737 video-firmware { 3738 iommus = <&apps_smmu 0x21a2 0x0>; 3739 }; 3740 3741 venus_opp_table: opp-table { 3742 compatible = "operating-points-v2"; 3743 3744 opp-133330000 { 3745 opp-hz = /bits/ 64 <133330000>; 3746 required-opps = <&rpmhpd_opp_low_svs>; 3747 }; 3748 3749 opp-240000000 { 3750 opp-hz = /bits/ 64 <240000000>; 3751 required-opps = <&rpmhpd_opp_svs>; 3752 }; 3753 3754 opp-335000000 { 3755 opp-hz = /bits/ 64 <335000000>; 3756 required-opps = <&rpmhpd_opp_svs_l1>; 3757 }; 3758 3759 opp-424000000 { 3760 opp-hz = /bits/ 64 <424000000>; 3761 required-opps = <&rpmhpd_opp_nom>; 3762 }; 3763 3764 opp-460000048 { 3765 opp-hz = /bits/ 64 <460000048>; 3766 required-opps = <&rpmhpd_opp_turbo>; 3767 }; 3768 }; 3769 }; 3770 3771 videocc: clock-controller@aaf0000 { 3772 compatible = "qcom,sc7280-videocc"; 3773 reg = <0 0x0aaf0000 0 0x10000>; 3774 clocks = <&rpmhcc RPMH_CXO_CLK>, 3775 <&rpmhcc RPMH_CXO_CLK_A>; 3776 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3777 #clock-cells = <1>; 3778 #reset-cells = <1>; 3779 #power-domain-cells = <1>; 3780 }; 3781 3782 camcc: clock-controller@ad00000 { 3783 compatible = "qcom,sc7280-camcc"; 3784 reg = <0 0x0ad00000 0 0x10000>; 3785 clocks = <&rpmhcc RPMH_CXO_CLK>, 3786 <&rpmhcc RPMH_CXO_CLK_A>, 3787 <&sleep_clk>; 3788 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3789 #clock-cells = <1>; 3790 #reset-cells = <1>; 3791 #power-domain-cells = <1>; 3792 }; 3793 3794 dispcc: clock-controller@af00000 { 3795 compatible = "qcom,sc7280-dispcc"; 3796 reg = <0 0x0af00000 0 0x20000>; 3797 clocks = <&rpmhcc RPMH_CXO_CLK>, 3798 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3799 <&mdss_dsi_phy 0>, 3800 <&mdss_dsi_phy 1>, 3801 <&dp_phy 0>, 3802 <&dp_phy 1>, 3803 <&mdss_edp_phy 0>, 3804 <&mdss_edp_phy 1>; 3805 clock-names = "bi_tcxo", 3806 "gcc_disp_gpll0_clk", 3807 "dsi0_phy_pll_out_byteclk", 3808 "dsi0_phy_pll_out_dsiclk", 3809 "dp_phy_pll_link_clk", 3810 "dp_phy_pll_vco_div_clk", 3811 "edp_phy_pll_link_clk", 3812 "edp_phy_pll_vco_div_clk"; 3813 #clock-cells = <1>; 3814 #reset-cells = <1>; 3815 #power-domain-cells = <1>; 3816 }; 3817 3818 mdss: display-subsystem@ae00000 { 3819 compatible = "qcom,sc7280-mdss"; 3820 reg = <0 0x0ae00000 0 0x1000>; 3821 reg-names = "mdss"; 3822 3823 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3824 3825 clocks = <&gcc GCC_DISP_AHB_CLK>, 3826 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3827 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3828 clock-names = "iface", 3829 "ahb", 3830 "core"; 3831 3832 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3833 interrupt-controller; 3834 #interrupt-cells = <1>; 3835 3836 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3837 interconnect-names = "mdp0-mem"; 3838 3839 iommus = <&apps_smmu 0x900 0x402>; 3840 3841 #address-cells = <2>; 3842 #size-cells = <2>; 3843 ranges; 3844 3845 status = "disabled"; 3846 3847 mdss_mdp: display-controller@ae01000 { 3848 compatible = "qcom,sc7280-dpu"; 3849 reg = <0 0x0ae01000 0 0x8f030>, 3850 <0 0x0aeb0000 0 0x2008>; 3851 reg-names = "mdp", "vbif"; 3852 3853 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3854 <&gcc GCC_DISP_SF_AXI_CLK>, 3855 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3856 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3857 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3858 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3859 clock-names = "bus", 3860 "nrt_bus", 3861 "iface", 3862 "lut", 3863 "core", 3864 "vsync"; 3865 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3866 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3867 assigned-clock-rates = <19200000>, 3868 <19200000>; 3869 operating-points-v2 = <&mdp_opp_table>; 3870 power-domains = <&rpmhpd SC7280_CX>; 3871 3872 interrupt-parent = <&mdss>; 3873 interrupts = <0>; 3874 3875 status = "disabled"; 3876 3877 ports { 3878 #address-cells = <1>; 3879 #size-cells = <0>; 3880 3881 port@0 { 3882 reg = <0>; 3883 dpu_intf1_out: endpoint { 3884 remote-endpoint = <&dsi0_in>; 3885 }; 3886 }; 3887 3888 port@1 { 3889 reg = <1>; 3890 dpu_intf5_out: endpoint { 3891 remote-endpoint = <&edp_in>; 3892 }; 3893 }; 3894 3895 port@2 { 3896 reg = <2>; 3897 dpu_intf0_out: endpoint { 3898 remote-endpoint = <&dp_in>; 3899 }; 3900 }; 3901 }; 3902 3903 mdp_opp_table: opp-table { 3904 compatible = "operating-points-v2"; 3905 3906 opp-200000000 { 3907 opp-hz = /bits/ 64 <200000000>; 3908 required-opps = <&rpmhpd_opp_low_svs>; 3909 }; 3910 3911 opp-300000000 { 3912 opp-hz = /bits/ 64 <300000000>; 3913 required-opps = <&rpmhpd_opp_svs>; 3914 }; 3915 3916 opp-380000000 { 3917 opp-hz = /bits/ 64 <380000000>; 3918 required-opps = <&rpmhpd_opp_svs_l1>; 3919 }; 3920 3921 opp-506666667 { 3922 opp-hz = /bits/ 64 <506666667>; 3923 required-opps = <&rpmhpd_opp_nom>; 3924 }; 3925 }; 3926 }; 3927 3928 mdss_dsi: dsi@ae94000 { 3929 compatible = "qcom,sc7280-dsi-ctrl", 3930 "qcom,mdss-dsi-ctrl"; 3931 reg = <0 0x0ae94000 0 0x400>; 3932 reg-names = "dsi_ctrl"; 3933 3934 interrupt-parent = <&mdss>; 3935 interrupts = <4>; 3936 3937 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3938 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3939 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3940 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3941 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3942 <&gcc GCC_DISP_HF_AXI_CLK>; 3943 clock-names = "byte", 3944 "byte_intf", 3945 "pixel", 3946 "core", 3947 "iface", 3948 "bus"; 3949 3950 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3951 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; 3952 3953 operating-points-v2 = <&dsi_opp_table>; 3954 power-domains = <&rpmhpd SC7280_CX>; 3955 3956 phys = <&mdss_dsi_phy>; 3957 3958 #address-cells = <1>; 3959 #size-cells = <0>; 3960 3961 status = "disabled"; 3962 3963 ports { 3964 #address-cells = <1>; 3965 #size-cells = <0>; 3966 3967 port@0 { 3968 reg = <0>; 3969 dsi0_in: endpoint { 3970 remote-endpoint = <&dpu_intf1_out>; 3971 }; 3972 }; 3973 3974 port@1 { 3975 reg = <1>; 3976 dsi0_out: endpoint { 3977 }; 3978 }; 3979 }; 3980 3981 dsi_opp_table: opp-table { 3982 compatible = "operating-points-v2"; 3983 3984 opp-187500000 { 3985 opp-hz = /bits/ 64 <187500000>; 3986 required-opps = <&rpmhpd_opp_low_svs>; 3987 }; 3988 3989 opp-300000000 { 3990 opp-hz = /bits/ 64 <300000000>; 3991 required-opps = <&rpmhpd_opp_svs>; 3992 }; 3993 3994 opp-358000000 { 3995 opp-hz = /bits/ 64 <358000000>; 3996 required-opps = <&rpmhpd_opp_svs_l1>; 3997 }; 3998 }; 3999 }; 4000 4001 mdss_dsi_phy: phy@ae94400 { 4002 compatible = "qcom,sc7280-dsi-phy-7nm"; 4003 reg = <0 0x0ae94400 0 0x200>, 4004 <0 0x0ae94600 0 0x280>, 4005 <0 0x0ae94900 0 0x280>; 4006 reg-names = "dsi_phy", 4007 "dsi_phy_lane", 4008 "dsi_pll"; 4009 4010 #clock-cells = <1>; 4011 #phy-cells = <0>; 4012 4013 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4014 <&rpmhcc RPMH_CXO_CLK>; 4015 clock-names = "iface", "ref"; 4016 4017 status = "disabled"; 4018 }; 4019 4020 mdss_edp: edp@aea0000 { 4021 compatible = "qcom,sc7280-edp"; 4022 pinctrl-names = "default"; 4023 pinctrl-0 = <&edp_hot_plug_det>; 4024 4025 reg = <0 0x0aea0000 0 0x200>, 4026 <0 0x0aea0200 0 0x200>, 4027 <0 0x0aea0400 0 0xc00>, 4028 <0 0x0aea1000 0 0x400>; 4029 4030 interrupt-parent = <&mdss>; 4031 interrupts = <14>; 4032 4033 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4034 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4035 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4036 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4037 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4038 clock-names = "core_iface", 4039 "core_aux", 4040 "ctrl_link", 4041 "ctrl_link_iface", 4042 "stream_pixel"; 4043 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4044 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4045 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4046 4047 phys = <&mdss_edp_phy>; 4048 phy-names = "dp"; 4049 4050 operating-points-v2 = <&edp_opp_table>; 4051 power-domains = <&rpmhpd SC7280_CX>; 4052 4053 status = "disabled"; 4054 4055 ports { 4056 #address-cells = <1>; 4057 #size-cells = <0>; 4058 4059 port@0 { 4060 reg = <0>; 4061 edp_in: endpoint { 4062 remote-endpoint = <&dpu_intf5_out>; 4063 }; 4064 }; 4065 4066 port@1 { 4067 reg = <1>; 4068 mdss_edp_out: endpoint { }; 4069 }; 4070 }; 4071 4072 edp_opp_table: opp-table { 4073 compatible = "operating-points-v2"; 4074 4075 opp-160000000 { 4076 opp-hz = /bits/ 64 <160000000>; 4077 required-opps = <&rpmhpd_opp_low_svs>; 4078 }; 4079 4080 opp-270000000 { 4081 opp-hz = /bits/ 64 <270000000>; 4082 required-opps = <&rpmhpd_opp_svs>; 4083 }; 4084 4085 opp-540000000 { 4086 opp-hz = /bits/ 64 <540000000>; 4087 required-opps = <&rpmhpd_opp_nom>; 4088 }; 4089 4090 opp-810000000 { 4091 opp-hz = /bits/ 64 <810000000>; 4092 required-opps = <&rpmhpd_opp_nom>; 4093 }; 4094 }; 4095 }; 4096 4097 mdss_edp_phy: phy@aec2a00 { 4098 compatible = "qcom,sc7280-edp-phy"; 4099 4100 reg = <0 0x0aec2a00 0 0x19c>, 4101 <0 0x0aec2200 0 0xa0>, 4102 <0 0x0aec2600 0 0xa0>, 4103 <0 0x0aec2000 0 0x1c0>; 4104 4105 clocks = <&rpmhcc RPMH_CXO_CLK>, 4106 <&gcc GCC_EDP_CLKREF_EN>; 4107 clock-names = "aux", 4108 "cfg_ahb"; 4109 4110 #clock-cells = <1>; 4111 #phy-cells = <0>; 4112 4113 status = "disabled"; 4114 }; 4115 4116 mdss_dp: displayport-controller@ae90000 { 4117 compatible = "qcom,sc7280-dp"; 4118 4119 reg = <0 0x0ae90000 0 0x200>, 4120 <0 0x0ae90200 0 0x200>, 4121 <0 0x0ae90400 0 0xc00>, 4122 <0 0x0ae91000 0 0x400>, 4123 <0 0x0ae91400 0 0x400>; 4124 4125 interrupt-parent = <&mdss>; 4126 interrupts = <12>; 4127 4128 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4129 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4130 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4131 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4132 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4133 clock-names = "core_iface", 4134 "core_aux", 4135 "ctrl_link", 4136 "ctrl_link_iface", 4137 "stream_pixel"; 4138 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4139 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4140 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4141 phys = <&dp_phy>; 4142 phy-names = "dp"; 4143 4144 operating-points-v2 = <&dp_opp_table>; 4145 power-domains = <&rpmhpd SC7280_CX>; 4146 4147 #sound-dai-cells = <0>; 4148 4149 status = "disabled"; 4150 4151 ports { 4152 #address-cells = <1>; 4153 #size-cells = <0>; 4154 4155 port@0 { 4156 reg = <0>; 4157 dp_in: endpoint { 4158 remote-endpoint = <&dpu_intf0_out>; 4159 }; 4160 }; 4161 4162 port@1 { 4163 reg = <1>; 4164 mdss_dp_out: endpoint { }; 4165 }; 4166 }; 4167 4168 dp_opp_table: opp-table { 4169 compatible = "operating-points-v2"; 4170 4171 opp-160000000 { 4172 opp-hz = /bits/ 64 <160000000>; 4173 required-opps = <&rpmhpd_opp_low_svs>; 4174 }; 4175 4176 opp-270000000 { 4177 opp-hz = /bits/ 64 <270000000>; 4178 required-opps = <&rpmhpd_opp_svs>; 4179 }; 4180 4181 opp-540000000 { 4182 opp-hz = /bits/ 64 <540000000>; 4183 required-opps = <&rpmhpd_opp_svs_l1>; 4184 }; 4185 4186 opp-810000000 { 4187 opp-hz = /bits/ 64 <810000000>; 4188 required-opps = <&rpmhpd_opp_nom>; 4189 }; 4190 }; 4191 }; 4192 }; 4193 4194 pdc: interrupt-controller@b220000 { 4195 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4196 reg = <0 0x0b220000 0 0x30000>; 4197 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4198 <55 306 4>, <59 312 3>, <62 374 2>, 4199 <64 434 2>, <66 438 3>, <69 86 1>, 4200 <70 520 54>, <124 609 31>, <155 63 1>, 4201 <156 716 12>; 4202 #interrupt-cells = <2>; 4203 interrupt-parent = <&intc>; 4204 interrupt-controller; 4205 }; 4206 4207 pdc_reset: reset-controller@b5e0000 { 4208 compatible = "qcom,sc7280-pdc-global"; 4209 reg = <0 0x0b5e0000 0 0x20000>; 4210 #reset-cells = <1>; 4211 }; 4212 4213 tsens0: thermal-sensor@c263000 { 4214 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4215 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4216 <0 0x0c222000 0 0x1ff>; /* SROT */ 4217 #qcom,sensors = <15>; 4218 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4219 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4220 interrupt-names = "uplow","critical"; 4221 #thermal-sensor-cells = <1>; 4222 }; 4223 4224 tsens1: thermal-sensor@c265000 { 4225 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4226 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4227 <0 0x0c223000 0 0x1ff>; /* SROT */ 4228 #qcom,sensors = <12>; 4229 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4230 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4231 interrupt-names = "uplow","critical"; 4232 #thermal-sensor-cells = <1>; 4233 }; 4234 4235 aoss_reset: reset-controller@c2a0000 { 4236 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4237 reg = <0 0x0c2a0000 0 0x31000>; 4238 #reset-cells = <1>; 4239 }; 4240 4241 aoss_qmp: power-management@c300000 { 4242 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4243 reg = <0 0x0c300000 0 0x400>; 4244 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4245 IPCC_MPROC_SIGNAL_GLINK_QMP 4246 IRQ_TYPE_EDGE_RISING>; 4247 mboxes = <&ipcc IPCC_CLIENT_AOP 4248 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4249 4250 #clock-cells = <0>; 4251 }; 4252 4253 sram@c3f0000 { 4254 compatible = "qcom,rpmh-stats"; 4255 reg = <0 0x0c3f0000 0 0x400>; 4256 }; 4257 4258 spmi_bus: spmi@c440000 { 4259 compatible = "qcom,spmi-pmic-arb"; 4260 reg = <0 0x0c440000 0 0x1100>, 4261 <0 0x0c600000 0 0x2000000>, 4262 <0 0x0e600000 0 0x100000>, 4263 <0 0x0e700000 0 0xa0000>, 4264 <0 0x0c40a000 0 0x26000>; 4265 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4266 interrupt-names = "periph_irq"; 4267 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4268 qcom,ee = <0>; 4269 qcom,channel = <0>; 4270 #address-cells = <2>; 4271 #size-cells = <0>; 4272 interrupt-controller; 4273 #interrupt-cells = <4>; 4274 }; 4275 4276 tlmm: pinctrl@f100000 { 4277 compatible = "qcom,sc7280-pinctrl"; 4278 reg = <0 0x0f100000 0 0x300000>; 4279 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4280 gpio-controller; 4281 #gpio-cells = <2>; 4282 interrupt-controller; 4283 #interrupt-cells = <2>; 4284 gpio-ranges = <&tlmm 0 0 175>; 4285 wakeup-parent = <&pdc>; 4286 4287 dp_hot_plug_det: dp-hot-plug-det-state { 4288 pins = "gpio47"; 4289 function = "dp_hot"; 4290 }; 4291 4292 edp_hot_plug_det: edp-hot-plug-det-state { 4293 pins = "gpio60"; 4294 function = "edp_hot"; 4295 }; 4296 4297 mi2s0_data0: mi2s0-data0-state { 4298 pins = "gpio98"; 4299 function = "mi2s0_data0"; 4300 }; 4301 4302 mi2s0_data1: mi2s0-data1-state { 4303 pins = "gpio99"; 4304 function = "mi2s0_data1"; 4305 }; 4306 4307 mi2s0_mclk: mi2s0-mclk-state { 4308 pins = "gpio96"; 4309 function = "pri_mi2s"; 4310 }; 4311 4312 mi2s0_sclk: mi2s0-sclk-state { 4313 pins = "gpio97"; 4314 function = "mi2s0_sck"; 4315 }; 4316 4317 mi2s0_ws: mi2s0-ws-state { 4318 pins = "gpio100"; 4319 function = "mi2s0_ws"; 4320 }; 4321 4322 mi2s1_data0: mi2s1-data0-state { 4323 pins = "gpio107"; 4324 function = "mi2s1_data0"; 4325 }; 4326 4327 mi2s1_sclk: mi2s1-sclk-state { 4328 pins = "gpio106"; 4329 function = "mi2s1_sck"; 4330 }; 4331 4332 mi2s1_ws: mi2s1-ws-state { 4333 pins = "gpio108"; 4334 function = "mi2s1_ws"; 4335 }; 4336 4337 pcie1_clkreq_n: pcie1-clkreq-n-state { 4338 pins = "gpio79"; 4339 function = "pcie1_clkreqn"; 4340 }; 4341 4342 qspi_clk: qspi-clk-state { 4343 pins = "gpio14"; 4344 function = "qspi_clk"; 4345 }; 4346 4347 qspi_cs0: qspi-cs0-state { 4348 pins = "gpio15"; 4349 function = "qspi_cs"; 4350 }; 4351 4352 qspi_cs1: qspi-cs1-state { 4353 pins = "gpio19"; 4354 function = "qspi_cs"; 4355 }; 4356 4357 qspi_data0: qspi-data0-state { 4358 pins = "gpio12"; 4359 function = "qspi_data"; 4360 }; 4361 4362 qspi_data1: qspi-data1-state { 4363 pins = "gpio13"; 4364 function = "qspi_data"; 4365 }; 4366 4367 qspi_data23: qspi-data23-state { 4368 pins = "gpio16", "gpio17"; 4369 function = "qspi_data"; 4370 }; 4371 4372 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4373 pins = "gpio0", "gpio1"; 4374 function = "qup00"; 4375 }; 4376 4377 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4378 pins = "gpio4", "gpio5"; 4379 function = "qup01"; 4380 }; 4381 4382 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4383 pins = "gpio8", "gpio9"; 4384 function = "qup02"; 4385 }; 4386 4387 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4388 pins = "gpio12", "gpio13"; 4389 function = "qup03"; 4390 }; 4391 4392 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4393 pins = "gpio16", "gpio17"; 4394 function = "qup04"; 4395 }; 4396 4397 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4398 pins = "gpio20", "gpio21"; 4399 function = "qup05"; 4400 }; 4401 4402 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4403 pins = "gpio24", "gpio25"; 4404 function = "qup06"; 4405 }; 4406 4407 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4408 pins = "gpio28", "gpio29"; 4409 function = "qup07"; 4410 }; 4411 4412 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4413 pins = "gpio32", "gpio33"; 4414 function = "qup10"; 4415 }; 4416 4417 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4418 pins = "gpio36", "gpio37"; 4419 function = "qup11"; 4420 }; 4421 4422 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4423 pins = "gpio40", "gpio41"; 4424 function = "qup12"; 4425 }; 4426 4427 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4428 pins = "gpio44", "gpio45"; 4429 function = "qup13"; 4430 }; 4431 4432 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4433 pins = "gpio48", "gpio49"; 4434 function = "qup14"; 4435 }; 4436 4437 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4438 pins = "gpio52", "gpio53"; 4439 function = "qup15"; 4440 }; 4441 4442 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4443 pins = "gpio56", "gpio57"; 4444 function = "qup16"; 4445 }; 4446 4447 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4448 pins = "gpio60", "gpio61"; 4449 function = "qup17"; 4450 }; 4451 4452 qup_spi0_data_clk: qup-spi0-data-clk-state { 4453 pins = "gpio0", "gpio1", "gpio2"; 4454 function = "qup00"; 4455 }; 4456 4457 qup_spi0_cs: qup-spi0-cs-state { 4458 pins = "gpio3"; 4459 function = "qup00"; 4460 }; 4461 4462 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4463 pins = "gpio3"; 4464 function = "gpio"; 4465 }; 4466 4467 qup_spi1_data_clk: qup-spi1-data-clk-state { 4468 pins = "gpio4", "gpio5", "gpio6"; 4469 function = "qup01"; 4470 }; 4471 4472 qup_spi1_cs: qup-spi1-cs-state { 4473 pins = "gpio7"; 4474 function = "qup01"; 4475 }; 4476 4477 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4478 pins = "gpio7"; 4479 function = "gpio"; 4480 }; 4481 4482 qup_spi2_data_clk: qup-spi2-data-clk-state { 4483 pins = "gpio8", "gpio9", "gpio10"; 4484 function = "qup02"; 4485 }; 4486 4487 qup_spi2_cs: qup-spi2-cs-state { 4488 pins = "gpio11"; 4489 function = "qup02"; 4490 }; 4491 4492 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4493 pins = "gpio11"; 4494 function = "gpio"; 4495 }; 4496 4497 qup_spi3_data_clk: qup-spi3-data-clk-state { 4498 pins = "gpio12", "gpio13", "gpio14"; 4499 function = "qup03"; 4500 }; 4501 4502 qup_spi3_cs: qup-spi3-cs-state { 4503 pins = "gpio15"; 4504 function = "qup03"; 4505 }; 4506 4507 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4508 pins = "gpio15"; 4509 function = "gpio"; 4510 }; 4511 4512 qup_spi4_data_clk: qup-spi4-data-clk-state { 4513 pins = "gpio16", "gpio17", "gpio18"; 4514 function = "qup04"; 4515 }; 4516 4517 qup_spi4_cs: qup-spi4-cs-state { 4518 pins = "gpio19"; 4519 function = "qup04"; 4520 }; 4521 4522 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4523 pins = "gpio19"; 4524 function = "gpio"; 4525 }; 4526 4527 qup_spi5_data_clk: qup-spi5-data-clk-state { 4528 pins = "gpio20", "gpio21", "gpio22"; 4529 function = "qup05"; 4530 }; 4531 4532 qup_spi5_cs: qup-spi5-cs-state { 4533 pins = "gpio23"; 4534 function = "qup05"; 4535 }; 4536 4537 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4538 pins = "gpio23"; 4539 function = "gpio"; 4540 }; 4541 4542 qup_spi6_data_clk: qup-spi6-data-clk-state { 4543 pins = "gpio24", "gpio25", "gpio26"; 4544 function = "qup06"; 4545 }; 4546 4547 qup_spi6_cs: qup-spi6-cs-state { 4548 pins = "gpio27"; 4549 function = "qup06"; 4550 }; 4551 4552 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4553 pins = "gpio27"; 4554 function = "gpio"; 4555 }; 4556 4557 qup_spi7_data_clk: qup-spi7-data-clk-state { 4558 pins = "gpio28", "gpio29", "gpio30"; 4559 function = "qup07"; 4560 }; 4561 4562 qup_spi7_cs: qup-spi7-cs-state { 4563 pins = "gpio31"; 4564 function = "qup07"; 4565 }; 4566 4567 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4568 pins = "gpio31"; 4569 function = "gpio"; 4570 }; 4571 4572 qup_spi8_data_clk: qup-spi8-data-clk-state { 4573 pins = "gpio32", "gpio33", "gpio34"; 4574 function = "qup10"; 4575 }; 4576 4577 qup_spi8_cs: qup-spi8-cs-state { 4578 pins = "gpio35"; 4579 function = "qup10"; 4580 }; 4581 4582 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4583 pins = "gpio35"; 4584 function = "gpio"; 4585 }; 4586 4587 qup_spi9_data_clk: qup-spi9-data-clk-state { 4588 pins = "gpio36", "gpio37", "gpio38"; 4589 function = "qup11"; 4590 }; 4591 4592 qup_spi9_cs: qup-spi9-cs-state { 4593 pins = "gpio39"; 4594 function = "qup11"; 4595 }; 4596 4597 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4598 pins = "gpio39"; 4599 function = "gpio"; 4600 }; 4601 4602 qup_spi10_data_clk: qup-spi10-data-clk-state { 4603 pins = "gpio40", "gpio41", "gpio42"; 4604 function = "qup12"; 4605 }; 4606 4607 qup_spi10_cs: qup-spi10-cs-state { 4608 pins = "gpio43"; 4609 function = "qup12"; 4610 }; 4611 4612 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4613 pins = "gpio43"; 4614 function = "gpio"; 4615 }; 4616 4617 qup_spi11_data_clk: qup-spi11-data-clk-state { 4618 pins = "gpio44", "gpio45", "gpio46"; 4619 function = "qup13"; 4620 }; 4621 4622 qup_spi11_cs: qup-spi11-cs-state { 4623 pins = "gpio47"; 4624 function = "qup13"; 4625 }; 4626 4627 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 4628 pins = "gpio47"; 4629 function = "gpio"; 4630 }; 4631 4632 qup_spi12_data_clk: qup-spi12-data-clk-state { 4633 pins = "gpio48", "gpio49", "gpio50"; 4634 function = "qup14"; 4635 }; 4636 4637 qup_spi12_cs: qup-spi12-cs-state { 4638 pins = "gpio51"; 4639 function = "qup14"; 4640 }; 4641 4642 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4643 pins = "gpio51"; 4644 function = "gpio"; 4645 }; 4646 4647 qup_spi13_data_clk: qup-spi13-data-clk-state { 4648 pins = "gpio52", "gpio53", "gpio54"; 4649 function = "qup15"; 4650 }; 4651 4652 qup_spi13_cs: qup-spi13-cs-state { 4653 pins = "gpio55"; 4654 function = "qup15"; 4655 }; 4656 4657 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 4658 pins = "gpio55"; 4659 function = "gpio"; 4660 }; 4661 4662 qup_spi14_data_clk: qup-spi14-data-clk-state { 4663 pins = "gpio56", "gpio57", "gpio58"; 4664 function = "qup16"; 4665 }; 4666 4667 qup_spi14_cs: qup-spi14-cs-state { 4668 pins = "gpio59"; 4669 function = "qup16"; 4670 }; 4671 4672 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 4673 pins = "gpio59"; 4674 function = "gpio"; 4675 }; 4676 4677 qup_spi15_data_clk: qup-spi15-data-clk-state { 4678 pins = "gpio60", "gpio61", "gpio62"; 4679 function = "qup17"; 4680 }; 4681 4682 qup_spi15_cs: qup-spi15-cs-state { 4683 pins = "gpio63"; 4684 function = "qup17"; 4685 }; 4686 4687 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 4688 pins = "gpio63"; 4689 function = "gpio"; 4690 }; 4691 4692 qup_uart0_cts: qup-uart0-cts-state { 4693 pins = "gpio0"; 4694 function = "qup00"; 4695 }; 4696 4697 qup_uart0_rts: qup-uart0-rts-state { 4698 pins = "gpio1"; 4699 function = "qup00"; 4700 }; 4701 4702 qup_uart0_tx: qup-uart0-tx-state { 4703 pins = "gpio2"; 4704 function = "qup00"; 4705 }; 4706 4707 qup_uart0_rx: qup-uart0-rx-state { 4708 pins = "gpio3"; 4709 function = "qup00"; 4710 }; 4711 4712 qup_uart1_cts: qup-uart1-cts-state { 4713 pins = "gpio4"; 4714 function = "qup01"; 4715 }; 4716 4717 qup_uart1_rts: qup-uart1-rts-state { 4718 pins = "gpio5"; 4719 function = "qup01"; 4720 }; 4721 4722 qup_uart1_tx: qup-uart1-tx-state { 4723 pins = "gpio6"; 4724 function = "qup01"; 4725 }; 4726 4727 qup_uart1_rx: qup-uart1-rx-state { 4728 pins = "gpio7"; 4729 function = "qup01"; 4730 }; 4731 4732 qup_uart2_cts: qup-uart2-cts-state { 4733 pins = "gpio8"; 4734 function = "qup02"; 4735 }; 4736 4737 qup_uart2_rts: qup-uart2-rts-state { 4738 pins = "gpio9"; 4739 function = "qup02"; 4740 }; 4741 4742 qup_uart2_tx: qup-uart2-tx-state { 4743 pins = "gpio10"; 4744 function = "qup02"; 4745 }; 4746 4747 qup_uart2_rx: qup-uart2-rx-state { 4748 pins = "gpio11"; 4749 function = "qup02"; 4750 }; 4751 4752 qup_uart3_cts: qup-uart3-cts-state { 4753 pins = "gpio12"; 4754 function = "qup03"; 4755 }; 4756 4757 qup_uart3_rts: qup-uart3-rts-state { 4758 pins = "gpio13"; 4759 function = "qup03"; 4760 }; 4761 4762 qup_uart3_tx: qup-uart3-tx-state { 4763 pins = "gpio14"; 4764 function = "qup03"; 4765 }; 4766 4767 qup_uart3_rx: qup-uart3-rx-state { 4768 pins = "gpio15"; 4769 function = "qup03"; 4770 }; 4771 4772 qup_uart4_cts: qup-uart4-cts-state { 4773 pins = "gpio16"; 4774 function = "qup04"; 4775 }; 4776 4777 qup_uart4_rts: qup-uart4-rts-state { 4778 pins = "gpio17"; 4779 function = "qup04"; 4780 }; 4781 4782 qup_uart4_tx: qup-uart4-tx-state { 4783 pins = "gpio18"; 4784 function = "qup04"; 4785 }; 4786 4787 qup_uart4_rx: qup-uart4-rx-state { 4788 pins = "gpio19"; 4789 function = "qup04"; 4790 }; 4791 4792 qup_uart5_cts: qup-uart5-cts-state { 4793 pins = "gpio20"; 4794 function = "qup05"; 4795 }; 4796 4797 qup_uart5_rts: qup-uart5-rts-state { 4798 pins = "gpio21"; 4799 function = "qup05"; 4800 }; 4801 4802 qup_uart5_tx: qup-uart5-tx-state { 4803 pins = "gpio22"; 4804 function = "qup05"; 4805 }; 4806 4807 qup_uart5_rx: qup-uart5-rx-state { 4808 pins = "gpio23"; 4809 function = "qup05"; 4810 }; 4811 4812 qup_uart6_cts: qup-uart6-cts-state { 4813 pins = "gpio24"; 4814 function = "qup06"; 4815 }; 4816 4817 qup_uart6_rts: qup-uart6-rts-state { 4818 pins = "gpio25"; 4819 function = "qup06"; 4820 }; 4821 4822 qup_uart6_tx: qup-uart6-tx-state { 4823 pins = "gpio26"; 4824 function = "qup06"; 4825 }; 4826 4827 qup_uart6_rx: qup-uart6-rx-state { 4828 pins = "gpio27"; 4829 function = "qup06"; 4830 }; 4831 4832 qup_uart7_cts: qup-uart7-cts-state { 4833 pins = "gpio28"; 4834 function = "qup07"; 4835 }; 4836 4837 qup_uart7_rts: qup-uart7-rts-state { 4838 pins = "gpio29"; 4839 function = "qup07"; 4840 }; 4841 4842 qup_uart7_tx: qup-uart7-tx-state { 4843 pins = "gpio30"; 4844 function = "qup07"; 4845 }; 4846 4847 qup_uart7_rx: qup-uart7-rx-state { 4848 pins = "gpio31"; 4849 function = "qup07"; 4850 }; 4851 4852 qup_uart8_cts: qup-uart8-cts-state { 4853 pins = "gpio32"; 4854 function = "qup10"; 4855 }; 4856 4857 qup_uart8_rts: qup-uart8-rts-state { 4858 pins = "gpio33"; 4859 function = "qup10"; 4860 }; 4861 4862 qup_uart8_tx: qup-uart8-tx-state { 4863 pins = "gpio34"; 4864 function = "qup10"; 4865 }; 4866 4867 qup_uart8_rx: qup-uart8-rx-state { 4868 pins = "gpio35"; 4869 function = "qup10"; 4870 }; 4871 4872 qup_uart9_cts: qup-uart9-cts-state { 4873 pins = "gpio36"; 4874 function = "qup11"; 4875 }; 4876 4877 qup_uart9_rts: qup-uart9-rts-state { 4878 pins = "gpio37"; 4879 function = "qup11"; 4880 }; 4881 4882 qup_uart9_tx: qup-uart9-tx-state { 4883 pins = "gpio38"; 4884 function = "qup11"; 4885 }; 4886 4887 qup_uart9_rx: qup-uart9-rx-state { 4888 pins = "gpio39"; 4889 function = "qup11"; 4890 }; 4891 4892 qup_uart10_cts: qup-uart10-cts-state { 4893 pins = "gpio40"; 4894 function = "qup12"; 4895 }; 4896 4897 qup_uart10_rts: qup-uart10-rts-state { 4898 pins = "gpio41"; 4899 function = "qup12"; 4900 }; 4901 4902 qup_uart10_tx: qup-uart10-tx-state { 4903 pins = "gpio42"; 4904 function = "qup12"; 4905 }; 4906 4907 qup_uart10_rx: qup-uart10-rx-state { 4908 pins = "gpio43"; 4909 function = "qup12"; 4910 }; 4911 4912 qup_uart11_cts: qup-uart11-cts-state { 4913 pins = "gpio44"; 4914 function = "qup13"; 4915 }; 4916 4917 qup_uart11_rts: qup-uart11-rts-state { 4918 pins = "gpio45"; 4919 function = "qup13"; 4920 }; 4921 4922 qup_uart11_tx: qup-uart11-tx-state { 4923 pins = "gpio46"; 4924 function = "qup13"; 4925 }; 4926 4927 qup_uart11_rx: qup-uart11-rx-state { 4928 pins = "gpio47"; 4929 function = "qup13"; 4930 }; 4931 4932 qup_uart12_cts: qup-uart12-cts-state { 4933 pins = "gpio48"; 4934 function = "qup14"; 4935 }; 4936 4937 qup_uart12_rts: qup-uart12-rts-state { 4938 pins = "gpio49"; 4939 function = "qup14"; 4940 }; 4941 4942 qup_uart12_tx: qup-uart12-tx-state { 4943 pins = "gpio50"; 4944 function = "qup14"; 4945 }; 4946 4947 qup_uart12_rx: qup-uart12-rx-state { 4948 pins = "gpio51"; 4949 function = "qup14"; 4950 }; 4951 4952 qup_uart13_cts: qup-uart13-cts-state { 4953 pins = "gpio52"; 4954 function = "qup15"; 4955 }; 4956 4957 qup_uart13_rts: qup-uart13-rts-state { 4958 pins = "gpio53"; 4959 function = "qup15"; 4960 }; 4961 4962 qup_uart13_tx: qup-uart13-tx-state { 4963 pins = "gpio54"; 4964 function = "qup15"; 4965 }; 4966 4967 qup_uart13_rx: qup-uart13-rx-state { 4968 pins = "gpio55"; 4969 function = "qup15"; 4970 }; 4971 4972 qup_uart14_cts: qup-uart14-cts-state { 4973 pins = "gpio56"; 4974 function = "qup16"; 4975 }; 4976 4977 qup_uart14_rts: qup-uart14-rts-state { 4978 pins = "gpio57"; 4979 function = "qup16"; 4980 }; 4981 4982 qup_uart14_tx: qup-uart14-tx-state { 4983 pins = "gpio58"; 4984 function = "qup16"; 4985 }; 4986 4987 qup_uart14_rx: qup-uart14-rx-state { 4988 pins = "gpio59"; 4989 function = "qup16"; 4990 }; 4991 4992 qup_uart15_cts: qup-uart15-cts-state { 4993 pins = "gpio60"; 4994 function = "qup17"; 4995 }; 4996 4997 qup_uart15_rts: qup-uart15-rts-state { 4998 pins = "gpio61"; 4999 function = "qup17"; 5000 }; 5001 5002 qup_uart15_tx: qup-uart15-tx-state { 5003 pins = "gpio62"; 5004 function = "qup17"; 5005 }; 5006 5007 qup_uart15_rx: qup-uart15-rx-state { 5008 pins = "gpio63"; 5009 function = "qup17"; 5010 }; 5011 5012 sdc1_clk: sdc1-clk-state { 5013 pins = "sdc1_clk"; 5014 }; 5015 5016 sdc1_cmd: sdc1-cmd-state { 5017 pins = "sdc1_cmd"; 5018 }; 5019 5020 sdc1_data: sdc1-data-state { 5021 pins = "sdc1_data"; 5022 }; 5023 5024 sdc1_rclk: sdc1-rclk-state { 5025 pins = "sdc1_rclk"; 5026 }; 5027 5028 sdc1_clk_sleep: sdc1-clk-sleep-state { 5029 pins = "sdc1_clk"; 5030 drive-strength = <2>; 5031 bias-bus-hold; 5032 }; 5033 5034 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5035 pins = "sdc1_cmd"; 5036 drive-strength = <2>; 5037 bias-bus-hold; 5038 }; 5039 5040 sdc1_data_sleep: sdc1-data-sleep-state { 5041 pins = "sdc1_data"; 5042 drive-strength = <2>; 5043 bias-bus-hold; 5044 }; 5045 5046 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5047 pins = "sdc1_rclk"; 5048 drive-strength = <2>; 5049 bias-bus-hold; 5050 }; 5051 5052 sdc2_clk: sdc2-clk-state { 5053 pins = "sdc2_clk"; 5054 }; 5055 5056 sdc2_cmd: sdc2-cmd-state { 5057 pins = "sdc2_cmd"; 5058 }; 5059 5060 sdc2_data: sdc2-data-state { 5061 pins = "sdc2_data"; 5062 }; 5063 5064 sdc2_clk_sleep: sdc2-clk-sleep-state { 5065 pins = "sdc2_clk"; 5066 drive-strength = <2>; 5067 bias-bus-hold; 5068 }; 5069 5070 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 5071 pins = "sdc2_cmd"; 5072 drive-strength = <2>; 5073 bias-bus-hold; 5074 }; 5075 5076 sdc2_data_sleep: sdc2-data-sleep-state { 5077 pins = "sdc2_data"; 5078 drive-strength = <2>; 5079 bias-bus-hold; 5080 }; 5081 }; 5082 5083 sram@146a5000 { 5084 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5085 reg = <0 0x146a5000 0 0x6000>; 5086 5087 #address-cells = <1>; 5088 #size-cells = <1>; 5089 5090 ranges = <0 0 0x146a5000 0x6000>; 5091 5092 pil-reloc@594c { 5093 compatible = "qcom,pil-reloc-info"; 5094 reg = <0x594c 0xc8>; 5095 }; 5096 }; 5097 5098 apps_smmu: iommu@15000000 { 5099 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5100 reg = <0 0x15000000 0 0x100000>; 5101 #iommu-cells = <2>; 5102 #global-interrupts = <1>; 5103 dma-coherent; 5104 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5169 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5170 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5171 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5172 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5173 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5174 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5175 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5176 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5177 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5178 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5179 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5180 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5181 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5182 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5183 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5184 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5185 }; 5186 5187 intc: interrupt-controller@17a00000 { 5188 compatible = "arm,gic-v3"; 5189 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5190 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5191 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5192 #interrupt-cells = <3>; 5193 interrupt-controller; 5194 #address-cells = <2>; 5195 #size-cells = <2>; 5196 ranges; 5197 5198 msi-controller@17a40000 { 5199 compatible = "arm,gic-v3-its"; 5200 reg = <0 0x17a40000 0 0x20000>; 5201 msi-controller; 5202 #msi-cells = <1>; 5203 status = "disabled"; 5204 }; 5205 }; 5206 5207 watchdog@17c10000 { 5208 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5209 reg = <0 0x17c10000 0 0x1000>; 5210 clocks = <&sleep_clk>; 5211 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5212 }; 5213 5214 timer@17c20000 { 5215 #address-cells = <1>; 5216 #size-cells = <1>; 5217 ranges = <0 0 0 0x20000000>; 5218 compatible = "arm,armv7-timer-mem"; 5219 reg = <0 0x17c20000 0 0x1000>; 5220 5221 frame@17c21000 { 5222 frame-number = <0>; 5223 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5224 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5225 reg = <0x17c21000 0x1000>, 5226 <0x17c22000 0x1000>; 5227 }; 5228 5229 frame@17c23000 { 5230 frame-number = <1>; 5231 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5232 reg = <0x17c23000 0x1000>; 5233 status = "disabled"; 5234 }; 5235 5236 frame@17c25000 { 5237 frame-number = <2>; 5238 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5239 reg = <0x17c25000 0x1000>; 5240 status = "disabled"; 5241 }; 5242 5243 frame@17c27000 { 5244 frame-number = <3>; 5245 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5246 reg = <0x17c27000 0x1000>; 5247 status = "disabled"; 5248 }; 5249 5250 frame@17c29000 { 5251 frame-number = <4>; 5252 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5253 reg = <0x17c29000 0x1000>; 5254 status = "disabled"; 5255 }; 5256 5257 frame@17c2b000 { 5258 frame-number = <5>; 5259 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5260 reg = <0x17c2b000 0x1000>; 5261 status = "disabled"; 5262 }; 5263 5264 frame@17c2d000 { 5265 frame-number = <6>; 5266 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5267 reg = <0x17c2d000 0x1000>; 5268 status = "disabled"; 5269 }; 5270 }; 5271 5272 apps_rsc: rsc@18200000 { 5273 compatible = "qcom,rpmh-rsc"; 5274 reg = <0 0x18200000 0 0x10000>, 5275 <0 0x18210000 0 0x10000>, 5276 <0 0x18220000 0 0x10000>; 5277 reg-names = "drv-0", "drv-1", "drv-2"; 5278 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5279 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5280 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5281 qcom,tcs-offset = <0xd00>; 5282 qcom,drv-id = <2>; 5283 qcom,tcs-config = <ACTIVE_TCS 2>, 5284 <SLEEP_TCS 3>, 5285 <WAKE_TCS 3>, 5286 <CONTROL_TCS 1>; 5287 5288 apps_bcm_voter: bcm-voter { 5289 compatible = "qcom,bcm-voter"; 5290 }; 5291 5292 rpmhpd: power-controller { 5293 compatible = "qcom,sc7280-rpmhpd"; 5294 #power-domain-cells = <1>; 5295 operating-points-v2 = <&rpmhpd_opp_table>; 5296 5297 rpmhpd_opp_table: opp-table { 5298 compatible = "operating-points-v2"; 5299 5300 rpmhpd_opp_ret: opp1 { 5301 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5302 }; 5303 5304 rpmhpd_opp_low_svs: opp2 { 5305 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5306 }; 5307 5308 rpmhpd_opp_svs: opp3 { 5309 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5310 }; 5311 5312 rpmhpd_opp_svs_l1: opp4 { 5313 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5314 }; 5315 5316 rpmhpd_opp_svs_l2: opp5 { 5317 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5318 }; 5319 5320 rpmhpd_opp_nom: opp6 { 5321 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5322 }; 5323 5324 rpmhpd_opp_nom_l1: opp7 { 5325 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5326 }; 5327 5328 rpmhpd_opp_turbo: opp8 { 5329 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5330 }; 5331 5332 rpmhpd_opp_turbo_l1: opp9 { 5333 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5334 }; 5335 }; 5336 }; 5337 5338 rpmhcc: clock-controller { 5339 compatible = "qcom,sc7280-rpmh-clk"; 5340 clocks = <&xo_board>; 5341 clock-names = "xo"; 5342 #clock-cells = <1>; 5343 }; 5344 }; 5345 5346 epss_l3: interconnect@18590000 { 5347 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 5348 reg = <0 0x18590000 0 0x1000>; 5349 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5350 clock-names = "xo", "alternate"; 5351 #interconnect-cells = <1>; 5352 }; 5353 5354 cpufreq_hw: cpufreq@18591000 { 5355 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 5356 reg = <0 0x18591000 0 0x1000>, 5357 <0 0x18592000 0 0x1000>, 5358 <0 0x18593000 0 0x1000>; 5359 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5360 clock-names = "xo", "alternate"; 5361 #freq-domain-cells = <1>; 5362 #clock-cells = <1>; 5363 }; 5364 }; 5365 5366 thermal_zones: thermal-zones { 5367 cpu0-thermal { 5368 polling-delay-passive = <250>; 5369 polling-delay = <0>; 5370 5371 thermal-sensors = <&tsens0 1>; 5372 5373 trips { 5374 cpu0_alert0: trip-point0 { 5375 temperature = <90000>; 5376 hysteresis = <2000>; 5377 type = "passive"; 5378 }; 5379 5380 cpu0_alert1: trip-point1 { 5381 temperature = <95000>; 5382 hysteresis = <2000>; 5383 type = "passive"; 5384 }; 5385 5386 cpu0_crit: cpu-crit { 5387 temperature = <110000>; 5388 hysteresis = <0>; 5389 type = "critical"; 5390 }; 5391 }; 5392 5393 cooling-maps { 5394 map0 { 5395 trip = <&cpu0_alert0>; 5396 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5397 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5398 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5399 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5400 }; 5401 map1 { 5402 trip = <&cpu0_alert1>; 5403 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5404 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5405 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5406 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5407 }; 5408 }; 5409 }; 5410 5411 cpu1-thermal { 5412 polling-delay-passive = <250>; 5413 polling-delay = <0>; 5414 5415 thermal-sensors = <&tsens0 2>; 5416 5417 trips { 5418 cpu1_alert0: trip-point0 { 5419 temperature = <90000>; 5420 hysteresis = <2000>; 5421 type = "passive"; 5422 }; 5423 5424 cpu1_alert1: trip-point1 { 5425 temperature = <95000>; 5426 hysteresis = <2000>; 5427 type = "passive"; 5428 }; 5429 5430 cpu1_crit: cpu-crit { 5431 temperature = <110000>; 5432 hysteresis = <0>; 5433 type = "critical"; 5434 }; 5435 }; 5436 5437 cooling-maps { 5438 map0 { 5439 trip = <&cpu1_alert0>; 5440 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5441 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5442 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5443 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5444 }; 5445 map1 { 5446 trip = <&cpu1_alert1>; 5447 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5448 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5449 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5450 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5451 }; 5452 }; 5453 }; 5454 5455 cpu2-thermal { 5456 polling-delay-passive = <250>; 5457 polling-delay = <0>; 5458 5459 thermal-sensors = <&tsens0 3>; 5460 5461 trips { 5462 cpu2_alert0: trip-point0 { 5463 temperature = <90000>; 5464 hysteresis = <2000>; 5465 type = "passive"; 5466 }; 5467 5468 cpu2_alert1: trip-point1 { 5469 temperature = <95000>; 5470 hysteresis = <2000>; 5471 type = "passive"; 5472 }; 5473 5474 cpu2_crit: cpu-crit { 5475 temperature = <110000>; 5476 hysteresis = <0>; 5477 type = "critical"; 5478 }; 5479 }; 5480 5481 cooling-maps { 5482 map0 { 5483 trip = <&cpu2_alert0>; 5484 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5485 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5486 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5487 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5488 }; 5489 map1 { 5490 trip = <&cpu2_alert1>; 5491 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5492 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5493 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5494 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5495 }; 5496 }; 5497 }; 5498 5499 cpu3-thermal { 5500 polling-delay-passive = <250>; 5501 polling-delay = <0>; 5502 5503 thermal-sensors = <&tsens0 4>; 5504 5505 trips { 5506 cpu3_alert0: trip-point0 { 5507 temperature = <90000>; 5508 hysteresis = <2000>; 5509 type = "passive"; 5510 }; 5511 5512 cpu3_alert1: trip-point1 { 5513 temperature = <95000>; 5514 hysteresis = <2000>; 5515 type = "passive"; 5516 }; 5517 5518 cpu3_crit: cpu-crit { 5519 temperature = <110000>; 5520 hysteresis = <0>; 5521 type = "critical"; 5522 }; 5523 }; 5524 5525 cooling-maps { 5526 map0 { 5527 trip = <&cpu3_alert0>; 5528 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5529 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5530 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5531 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5532 }; 5533 map1 { 5534 trip = <&cpu3_alert1>; 5535 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5536 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5537 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5538 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5539 }; 5540 }; 5541 }; 5542 5543 cpu4-thermal { 5544 polling-delay-passive = <250>; 5545 polling-delay = <0>; 5546 5547 thermal-sensors = <&tsens0 7>; 5548 5549 trips { 5550 cpu4_alert0: trip-point0 { 5551 temperature = <90000>; 5552 hysteresis = <2000>; 5553 type = "passive"; 5554 }; 5555 5556 cpu4_alert1: trip-point1 { 5557 temperature = <95000>; 5558 hysteresis = <2000>; 5559 type = "passive"; 5560 }; 5561 5562 cpu4_crit: cpu-crit { 5563 temperature = <110000>; 5564 hysteresis = <0>; 5565 type = "critical"; 5566 }; 5567 }; 5568 5569 cooling-maps { 5570 map0 { 5571 trip = <&cpu4_alert0>; 5572 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5573 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5574 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5575 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5576 }; 5577 map1 { 5578 trip = <&cpu4_alert1>; 5579 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5580 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5581 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5582 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5583 }; 5584 }; 5585 }; 5586 5587 cpu5-thermal { 5588 polling-delay-passive = <250>; 5589 polling-delay = <0>; 5590 5591 thermal-sensors = <&tsens0 8>; 5592 5593 trips { 5594 cpu5_alert0: trip-point0 { 5595 temperature = <90000>; 5596 hysteresis = <2000>; 5597 type = "passive"; 5598 }; 5599 5600 cpu5_alert1: trip-point1 { 5601 temperature = <95000>; 5602 hysteresis = <2000>; 5603 type = "passive"; 5604 }; 5605 5606 cpu5_crit: cpu-crit { 5607 temperature = <110000>; 5608 hysteresis = <0>; 5609 type = "critical"; 5610 }; 5611 }; 5612 5613 cooling-maps { 5614 map0 { 5615 trip = <&cpu5_alert0>; 5616 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5617 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5618 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5619 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5620 }; 5621 map1 { 5622 trip = <&cpu5_alert1>; 5623 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5624 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5625 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5626 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5627 }; 5628 }; 5629 }; 5630 5631 cpu6-thermal { 5632 polling-delay-passive = <250>; 5633 polling-delay = <0>; 5634 5635 thermal-sensors = <&tsens0 9>; 5636 5637 trips { 5638 cpu6_alert0: trip-point0 { 5639 temperature = <90000>; 5640 hysteresis = <2000>; 5641 type = "passive"; 5642 }; 5643 5644 cpu6_alert1: trip-point1 { 5645 temperature = <95000>; 5646 hysteresis = <2000>; 5647 type = "passive"; 5648 }; 5649 5650 cpu6_crit: cpu-crit { 5651 temperature = <110000>; 5652 hysteresis = <0>; 5653 type = "critical"; 5654 }; 5655 }; 5656 5657 cooling-maps { 5658 map0 { 5659 trip = <&cpu6_alert0>; 5660 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5661 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5662 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5663 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5664 }; 5665 map1 { 5666 trip = <&cpu6_alert1>; 5667 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5668 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5669 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5670 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5671 }; 5672 }; 5673 }; 5674 5675 cpu7-thermal { 5676 polling-delay-passive = <250>; 5677 polling-delay = <0>; 5678 5679 thermal-sensors = <&tsens0 10>; 5680 5681 trips { 5682 cpu7_alert0: trip-point0 { 5683 temperature = <90000>; 5684 hysteresis = <2000>; 5685 type = "passive"; 5686 }; 5687 5688 cpu7_alert1: trip-point1 { 5689 temperature = <95000>; 5690 hysteresis = <2000>; 5691 type = "passive"; 5692 }; 5693 5694 cpu7_crit: cpu-crit { 5695 temperature = <110000>; 5696 hysteresis = <0>; 5697 type = "critical"; 5698 }; 5699 }; 5700 5701 cooling-maps { 5702 map0 { 5703 trip = <&cpu7_alert0>; 5704 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5705 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5706 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5707 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5708 }; 5709 map1 { 5710 trip = <&cpu7_alert1>; 5711 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5712 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5713 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5714 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5715 }; 5716 }; 5717 }; 5718 5719 cpu8-thermal { 5720 polling-delay-passive = <250>; 5721 polling-delay = <0>; 5722 5723 thermal-sensors = <&tsens0 11>; 5724 5725 trips { 5726 cpu8_alert0: trip-point0 { 5727 temperature = <90000>; 5728 hysteresis = <2000>; 5729 type = "passive"; 5730 }; 5731 5732 cpu8_alert1: trip-point1 { 5733 temperature = <95000>; 5734 hysteresis = <2000>; 5735 type = "passive"; 5736 }; 5737 5738 cpu8_crit: cpu-crit { 5739 temperature = <110000>; 5740 hysteresis = <0>; 5741 type = "critical"; 5742 }; 5743 }; 5744 5745 cooling-maps { 5746 map0 { 5747 trip = <&cpu8_alert0>; 5748 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5749 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5750 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5751 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5752 }; 5753 map1 { 5754 trip = <&cpu8_alert1>; 5755 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5756 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5757 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5758 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5759 }; 5760 }; 5761 }; 5762 5763 cpu9-thermal { 5764 polling-delay-passive = <250>; 5765 polling-delay = <0>; 5766 5767 thermal-sensors = <&tsens0 12>; 5768 5769 trips { 5770 cpu9_alert0: trip-point0 { 5771 temperature = <90000>; 5772 hysteresis = <2000>; 5773 type = "passive"; 5774 }; 5775 5776 cpu9_alert1: trip-point1 { 5777 temperature = <95000>; 5778 hysteresis = <2000>; 5779 type = "passive"; 5780 }; 5781 5782 cpu9_crit: cpu-crit { 5783 temperature = <110000>; 5784 hysteresis = <0>; 5785 type = "critical"; 5786 }; 5787 }; 5788 5789 cooling-maps { 5790 map0 { 5791 trip = <&cpu9_alert0>; 5792 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5793 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5794 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5795 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5796 }; 5797 map1 { 5798 trip = <&cpu9_alert1>; 5799 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5800 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5801 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5802 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5803 }; 5804 }; 5805 }; 5806 5807 cpu10-thermal { 5808 polling-delay-passive = <250>; 5809 polling-delay = <0>; 5810 5811 thermal-sensors = <&tsens0 13>; 5812 5813 trips { 5814 cpu10_alert0: trip-point0 { 5815 temperature = <90000>; 5816 hysteresis = <2000>; 5817 type = "passive"; 5818 }; 5819 5820 cpu10_alert1: trip-point1 { 5821 temperature = <95000>; 5822 hysteresis = <2000>; 5823 type = "passive"; 5824 }; 5825 5826 cpu10_crit: cpu-crit { 5827 temperature = <110000>; 5828 hysteresis = <0>; 5829 type = "critical"; 5830 }; 5831 }; 5832 5833 cooling-maps { 5834 map0 { 5835 trip = <&cpu10_alert0>; 5836 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5837 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5838 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5839 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5840 }; 5841 map1 { 5842 trip = <&cpu10_alert1>; 5843 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5844 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5845 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5846 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5847 }; 5848 }; 5849 }; 5850 5851 cpu11-thermal { 5852 polling-delay-passive = <250>; 5853 polling-delay = <0>; 5854 5855 thermal-sensors = <&tsens0 14>; 5856 5857 trips { 5858 cpu11_alert0: trip-point0 { 5859 temperature = <90000>; 5860 hysteresis = <2000>; 5861 type = "passive"; 5862 }; 5863 5864 cpu11_alert1: trip-point1 { 5865 temperature = <95000>; 5866 hysteresis = <2000>; 5867 type = "passive"; 5868 }; 5869 5870 cpu11_crit: cpu-crit { 5871 temperature = <110000>; 5872 hysteresis = <0>; 5873 type = "critical"; 5874 }; 5875 }; 5876 5877 cooling-maps { 5878 map0 { 5879 trip = <&cpu11_alert0>; 5880 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5881 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5882 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5883 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5884 }; 5885 map1 { 5886 trip = <&cpu11_alert1>; 5887 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5888 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5889 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5890 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5891 }; 5892 }; 5893 }; 5894 5895 aoss0-thermal { 5896 polling-delay-passive = <0>; 5897 polling-delay = <0>; 5898 5899 thermal-sensors = <&tsens0 0>; 5900 5901 trips { 5902 aoss0_alert0: trip-point0 { 5903 temperature = <90000>; 5904 hysteresis = <2000>; 5905 type = "hot"; 5906 }; 5907 5908 aoss0_crit: aoss0-crit { 5909 temperature = <110000>; 5910 hysteresis = <0>; 5911 type = "critical"; 5912 }; 5913 }; 5914 }; 5915 5916 aoss1-thermal { 5917 polling-delay-passive = <0>; 5918 polling-delay = <0>; 5919 5920 thermal-sensors = <&tsens1 0>; 5921 5922 trips { 5923 aoss1_alert0: trip-point0 { 5924 temperature = <90000>; 5925 hysteresis = <2000>; 5926 type = "hot"; 5927 }; 5928 5929 aoss1_crit: aoss1-crit { 5930 temperature = <110000>; 5931 hysteresis = <0>; 5932 type = "critical"; 5933 }; 5934 }; 5935 }; 5936 5937 cpuss0-thermal { 5938 polling-delay-passive = <0>; 5939 polling-delay = <0>; 5940 5941 thermal-sensors = <&tsens0 5>; 5942 5943 trips { 5944 cpuss0_alert0: trip-point0 { 5945 temperature = <90000>; 5946 hysteresis = <2000>; 5947 type = "hot"; 5948 }; 5949 cpuss0_crit: cluster0-crit { 5950 temperature = <110000>; 5951 hysteresis = <0>; 5952 type = "critical"; 5953 }; 5954 }; 5955 }; 5956 5957 cpuss1-thermal { 5958 polling-delay-passive = <0>; 5959 polling-delay = <0>; 5960 5961 thermal-sensors = <&tsens0 6>; 5962 5963 trips { 5964 cpuss1_alert0: trip-point0 { 5965 temperature = <90000>; 5966 hysteresis = <2000>; 5967 type = "hot"; 5968 }; 5969 cpuss1_crit: cluster0-crit { 5970 temperature = <110000>; 5971 hysteresis = <0>; 5972 type = "critical"; 5973 }; 5974 }; 5975 }; 5976 5977 gpuss0-thermal { 5978 polling-delay-passive = <100>; 5979 polling-delay = <0>; 5980 5981 thermal-sensors = <&tsens1 1>; 5982 5983 trips { 5984 gpuss0_alert0: trip-point0 { 5985 temperature = <95000>; 5986 hysteresis = <2000>; 5987 type = "passive"; 5988 }; 5989 5990 gpuss0_crit: gpuss0-crit { 5991 temperature = <110000>; 5992 hysteresis = <0>; 5993 type = "critical"; 5994 }; 5995 }; 5996 5997 cooling-maps { 5998 map0 { 5999 trip = <&gpuss0_alert0>; 6000 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6001 }; 6002 }; 6003 }; 6004 6005 gpuss1-thermal { 6006 polling-delay-passive = <100>; 6007 polling-delay = <0>; 6008 6009 thermal-sensors = <&tsens1 2>; 6010 6011 trips { 6012 gpuss1_alert0: trip-point0 { 6013 temperature = <95000>; 6014 hysteresis = <2000>; 6015 type = "passive"; 6016 }; 6017 6018 gpuss1_crit: gpuss1-crit { 6019 temperature = <110000>; 6020 hysteresis = <0>; 6021 type = "critical"; 6022 }; 6023 }; 6024 6025 cooling-maps { 6026 map0 { 6027 trip = <&gpuss1_alert0>; 6028 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6029 }; 6030 }; 6031 }; 6032 6033 nspss0-thermal { 6034 polling-delay-passive = <0>; 6035 polling-delay = <0>; 6036 6037 thermal-sensors = <&tsens1 3>; 6038 6039 trips { 6040 nspss0_alert0: trip-point0 { 6041 temperature = <90000>; 6042 hysteresis = <2000>; 6043 type = "hot"; 6044 }; 6045 6046 nspss0_crit: nspss0-crit { 6047 temperature = <110000>; 6048 hysteresis = <0>; 6049 type = "critical"; 6050 }; 6051 }; 6052 }; 6053 6054 nspss1-thermal { 6055 polling-delay-passive = <0>; 6056 polling-delay = <0>; 6057 6058 thermal-sensors = <&tsens1 4>; 6059 6060 trips { 6061 nspss1_alert0: trip-point0 { 6062 temperature = <90000>; 6063 hysteresis = <2000>; 6064 type = "hot"; 6065 }; 6066 6067 nspss1_crit: nspss1-crit { 6068 temperature = <110000>; 6069 hysteresis = <0>; 6070 type = "critical"; 6071 }; 6072 }; 6073 }; 6074 6075 video-thermal { 6076 polling-delay-passive = <0>; 6077 polling-delay = <0>; 6078 6079 thermal-sensors = <&tsens1 5>; 6080 6081 trips { 6082 video_alert0: trip-point0 { 6083 temperature = <90000>; 6084 hysteresis = <2000>; 6085 type = "hot"; 6086 }; 6087 6088 video_crit: video-crit { 6089 temperature = <110000>; 6090 hysteresis = <0>; 6091 type = "critical"; 6092 }; 6093 }; 6094 }; 6095 6096 ddr-thermal { 6097 polling-delay-passive = <0>; 6098 polling-delay = <0>; 6099 6100 thermal-sensors = <&tsens1 6>; 6101 6102 trips { 6103 ddr_alert0: trip-point0 { 6104 temperature = <90000>; 6105 hysteresis = <2000>; 6106 type = "hot"; 6107 }; 6108 6109 ddr_crit: ddr-crit { 6110 temperature = <110000>; 6111 hysteresis = <0>; 6112 type = "critical"; 6113 }; 6114 }; 6115 }; 6116 6117 mdmss0-thermal { 6118 polling-delay-passive = <0>; 6119 polling-delay = <0>; 6120 6121 thermal-sensors = <&tsens1 7>; 6122 6123 trips { 6124 mdmss0_alert0: trip-point0 { 6125 temperature = <90000>; 6126 hysteresis = <2000>; 6127 type = "hot"; 6128 }; 6129 6130 mdmss0_crit: mdmss0-crit { 6131 temperature = <110000>; 6132 hysteresis = <0>; 6133 type = "critical"; 6134 }; 6135 }; 6136 }; 6137 6138 mdmss1-thermal { 6139 polling-delay-passive = <0>; 6140 polling-delay = <0>; 6141 6142 thermal-sensors = <&tsens1 8>; 6143 6144 trips { 6145 mdmss1_alert0: trip-point0 { 6146 temperature = <90000>; 6147 hysteresis = <2000>; 6148 type = "hot"; 6149 }; 6150 6151 mdmss1_crit: mdmss1-crit { 6152 temperature = <110000>; 6153 hysteresis = <0>; 6154 type = "critical"; 6155 }; 6156 }; 6157 }; 6158 6159 mdmss2-thermal { 6160 polling-delay-passive = <0>; 6161 polling-delay = <0>; 6162 6163 thermal-sensors = <&tsens1 9>; 6164 6165 trips { 6166 mdmss2_alert0: trip-point0 { 6167 temperature = <90000>; 6168 hysteresis = <2000>; 6169 type = "hot"; 6170 }; 6171 6172 mdmss2_crit: mdmss2-crit { 6173 temperature = <110000>; 6174 hysteresis = <0>; 6175 type = "critical"; 6176 }; 6177 }; 6178 }; 6179 6180 mdmss3-thermal { 6181 polling-delay-passive = <0>; 6182 polling-delay = <0>; 6183 6184 thermal-sensors = <&tsens1 10>; 6185 6186 trips { 6187 mdmss3_alert0: trip-point0 { 6188 temperature = <90000>; 6189 hysteresis = <2000>; 6190 type = "hot"; 6191 }; 6192 6193 mdmss3_crit: mdmss3-crit { 6194 temperature = <110000>; 6195 hysteresis = <0>; 6196 type = "critical"; 6197 }; 6198 }; 6199 }; 6200 6201 camera0-thermal { 6202 polling-delay-passive = <0>; 6203 polling-delay = <0>; 6204 6205 thermal-sensors = <&tsens1 11>; 6206 6207 trips { 6208 camera0_alert0: trip-point0 { 6209 temperature = <90000>; 6210 hysteresis = <2000>; 6211 type = "hot"; 6212 }; 6213 6214 camera0_crit: camera0-crit { 6215 temperature = <110000>; 6216 hysteresis = <0>; 6217 type = "critical"; 6218 }; 6219 }; 6220 }; 6221 }; 6222 6223 timer { 6224 compatible = "arm,armv8-timer"; 6225 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6226 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6227 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6228 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6229 }; 6230}; 6231