1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-sc7280.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/interconnect/qcom,sc7280.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/mailbox/qcom-ipcc.h> 13#include <dt-bindings/power/qcom-aoss-qmp.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/reset/qcom,sdm845-aoss.h> 16#include <dt-bindings/reset/qcom,sdm845-pdc.h> 17#include <dt-bindings/soc/qcom,rpmh-rsc.h> 18#include <dt-bindings/thermal/thermal.h> 19 20/ { 21 interrupt-parent = <&intc>; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 chosen { }; 27 28 aliases { 29 mmc1 = &sdhc_1; 30 mmc2 = &sdhc_2; 31 }; 32 33 clocks { 34 xo_board: xo-board { 35 compatible = "fixed-clock"; 36 clock-frequency = <76800000>; 37 #clock-cells = <0>; 38 }; 39 40 sleep_clk: sleep-clk { 41 compatible = "fixed-clock"; 42 clock-frequency = <32000>; 43 #clock-cells = <0>; 44 }; 45 }; 46 47 reserved-memory { 48 #address-cells = <2>; 49 #size-cells = <2>; 50 ranges; 51 52 aop_mem: memory@80800000 { 53 reg = <0x0 0x80800000 0x0 0x60000>; 54 no-map; 55 }; 56 57 aop_cmd_db_mem: memory@80860000 { 58 reg = <0x0 0x80860000 0x0 0x20000>; 59 compatible = "qcom,cmd-db"; 60 no-map; 61 }; 62 63 smem_mem: memory@80900000 { 64 reg = <0x0 0x80900000 0x0 0x200000>; 65 no-map; 66 }; 67 68 cpucp_mem: memory@80b00000 { 69 no-map; 70 reg = <0x0 0x80b00000 0x0 0x100000>; 71 }; 72 }; 73 74 cpus { 75 #address-cells = <2>; 76 #size-cells = <0>; 77 78 CPU0: cpu@0 { 79 device_type = "cpu"; 80 compatible = "arm,kryo"; 81 reg = <0x0 0x0>; 82 enable-method = "psci"; 83 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 84 &LITTLE_CPU_SLEEP_1 85 &CLUSTER_SLEEP_0>; 86 next-level-cache = <&L2_0>; 87 qcom,freq-domain = <&cpufreq_hw 0>; 88 #cooling-cells = <2>; 89 L2_0: l2-cache { 90 compatible = "cache"; 91 next-level-cache = <&L3_0>; 92 L3_0: l3-cache { 93 compatible = "cache"; 94 }; 95 }; 96 }; 97 98 CPU1: cpu@100 { 99 device_type = "cpu"; 100 compatible = "arm,kryo"; 101 reg = <0x0 0x100>; 102 enable-method = "psci"; 103 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 104 &LITTLE_CPU_SLEEP_1 105 &CLUSTER_SLEEP_0>; 106 next-level-cache = <&L2_100>; 107 qcom,freq-domain = <&cpufreq_hw 0>; 108 #cooling-cells = <2>; 109 L2_100: l2-cache { 110 compatible = "cache"; 111 next-level-cache = <&L3_0>; 112 }; 113 }; 114 115 CPU2: cpu@200 { 116 device_type = "cpu"; 117 compatible = "arm,kryo"; 118 reg = <0x0 0x200>; 119 enable-method = "psci"; 120 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 121 &LITTLE_CPU_SLEEP_1 122 &CLUSTER_SLEEP_0>; 123 next-level-cache = <&L2_200>; 124 qcom,freq-domain = <&cpufreq_hw 0>; 125 #cooling-cells = <2>; 126 L2_200: l2-cache { 127 compatible = "cache"; 128 next-level-cache = <&L3_0>; 129 }; 130 }; 131 132 CPU3: cpu@300 { 133 device_type = "cpu"; 134 compatible = "arm,kryo"; 135 reg = <0x0 0x300>; 136 enable-method = "psci"; 137 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 138 &LITTLE_CPU_SLEEP_1 139 &CLUSTER_SLEEP_0>; 140 next-level-cache = <&L2_300>; 141 qcom,freq-domain = <&cpufreq_hw 0>; 142 #cooling-cells = <2>; 143 L2_300: l2-cache { 144 compatible = "cache"; 145 next-level-cache = <&L3_0>; 146 }; 147 }; 148 149 CPU4: cpu@400 { 150 device_type = "cpu"; 151 compatible = "arm,kryo"; 152 reg = <0x0 0x400>; 153 enable-method = "psci"; 154 cpu-idle-states = <&BIG_CPU_SLEEP_0 155 &BIG_CPU_SLEEP_1 156 &CLUSTER_SLEEP_0>; 157 next-level-cache = <&L2_400>; 158 qcom,freq-domain = <&cpufreq_hw 1>; 159 #cooling-cells = <2>; 160 L2_400: l2-cache { 161 compatible = "cache"; 162 next-level-cache = <&L3_0>; 163 }; 164 }; 165 166 CPU5: cpu@500 { 167 device_type = "cpu"; 168 compatible = "arm,kryo"; 169 reg = <0x0 0x500>; 170 enable-method = "psci"; 171 cpu-idle-states = <&BIG_CPU_SLEEP_0 172 &BIG_CPU_SLEEP_1 173 &CLUSTER_SLEEP_0>; 174 next-level-cache = <&L2_500>; 175 qcom,freq-domain = <&cpufreq_hw 1>; 176 #cooling-cells = <2>; 177 L2_500: l2-cache { 178 compatible = "cache"; 179 next-level-cache = <&L3_0>; 180 }; 181 }; 182 183 CPU6: cpu@600 { 184 device_type = "cpu"; 185 compatible = "arm,kryo"; 186 reg = <0x0 0x600>; 187 enable-method = "psci"; 188 cpu-idle-states = <&BIG_CPU_SLEEP_0 189 &BIG_CPU_SLEEP_1 190 &CLUSTER_SLEEP_0>; 191 next-level-cache = <&L2_600>; 192 qcom,freq-domain = <&cpufreq_hw 1>; 193 #cooling-cells = <2>; 194 L2_600: l2-cache { 195 compatible = "cache"; 196 next-level-cache = <&L3_0>; 197 }; 198 }; 199 200 CPU7: cpu@700 { 201 device_type = "cpu"; 202 compatible = "arm,kryo"; 203 reg = <0x0 0x700>; 204 enable-method = "psci"; 205 cpu-idle-states = <&BIG_CPU_SLEEP_0 206 &BIG_CPU_SLEEP_1 207 &CLUSTER_SLEEP_0>; 208 next-level-cache = <&L2_700>; 209 qcom,freq-domain = <&cpufreq_hw 1>; 210 #cooling-cells = <2>; 211 L2_700: l2-cache { 212 compatible = "cache"; 213 next-level-cache = <&L3_0>; 214 }; 215 }; 216 217 idle-states { 218 entry-method = "psci"; 219 220 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 221 compatible = "arm,idle-state"; 222 idle-state-name = "little-power-down"; 223 arm,psci-suspend-param = <0x40000003>; 224 entry-latency-us = <549>; 225 exit-latency-us = <901>; 226 min-residency-us = <1774>; 227 local-timer-stop; 228 }; 229 230 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 231 compatible = "arm,idle-state"; 232 idle-state-name = "little-rail-power-down"; 233 arm,psci-suspend-param = <0x40000004>; 234 entry-latency-us = <702>; 235 exit-latency-us = <915>; 236 min-residency-us = <4001>; 237 local-timer-stop; 238 }; 239 240 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 241 compatible = "arm,idle-state"; 242 idle-state-name = "big-power-down"; 243 arm,psci-suspend-param = <0x40000003>; 244 entry-latency-us = <523>; 245 exit-latency-us = <1244>; 246 min-residency-us = <2207>; 247 local-timer-stop; 248 }; 249 250 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 251 compatible = "arm,idle-state"; 252 idle-state-name = "big-rail-power-down"; 253 arm,psci-suspend-param = <0x40000004>; 254 entry-latency-us = <526>; 255 exit-latency-us = <1854>; 256 min-residency-us = <5555>; 257 local-timer-stop; 258 }; 259 260 CLUSTER_SLEEP_0: cluster-sleep-0 { 261 compatible = "arm,idle-state"; 262 idle-state-name = "cluster-power-down"; 263 arm,psci-suspend-param = <0x40003444>; 264 entry-latency-us = <3263>; 265 exit-latency-us = <6562>; 266 min-residency-us = <9926>; 267 local-timer-stop; 268 }; 269 }; 270 }; 271 272 memory@80000000 { 273 device_type = "memory"; 274 /* We expect the bootloader to fill in the size */ 275 reg = <0 0x80000000 0 0>; 276 }; 277 278 firmware { 279 scm { 280 compatible = "qcom,scm-sc7280", "qcom,scm"; 281 }; 282 }; 283 284 clk_virt: interconnect { 285 compatible = "qcom,sc7280-clk-virt"; 286 #interconnect-cells = <2>; 287 qcom,bcm-voters = <&apps_bcm_voter>; 288 }; 289 290 smem { 291 compatible = "qcom,smem"; 292 memory-region = <&smem_mem>; 293 hwlocks = <&tcsr_mutex 3>; 294 }; 295 296 smp2p-adsp { 297 compatible = "qcom,smp2p"; 298 qcom,smem = <443>, <429>; 299 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 300 IPCC_MPROC_SIGNAL_SMP2P 301 IRQ_TYPE_EDGE_RISING>; 302 mboxes = <&ipcc IPCC_CLIENT_LPASS 303 IPCC_MPROC_SIGNAL_SMP2P>; 304 305 qcom,local-pid = <0>; 306 qcom,remote-pid = <2>; 307 308 adsp_smp2p_out: master-kernel { 309 qcom,entry-name = "master-kernel"; 310 #qcom,smem-state-cells = <1>; 311 }; 312 313 adsp_smp2p_in: slave-kernel { 314 qcom,entry-name = "slave-kernel"; 315 interrupt-controller; 316 #interrupt-cells = <2>; 317 }; 318 }; 319 320 smp2p-cdsp { 321 compatible = "qcom,smp2p"; 322 qcom,smem = <94>, <432>; 323 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 324 IPCC_MPROC_SIGNAL_SMP2P 325 IRQ_TYPE_EDGE_RISING>; 326 mboxes = <&ipcc IPCC_CLIENT_CDSP 327 IPCC_MPROC_SIGNAL_SMP2P>; 328 329 qcom,local-pid = <0>; 330 qcom,remote-pid = <5>; 331 332 cdsp_smp2p_out: master-kernel { 333 qcom,entry-name = "master-kernel"; 334 #qcom,smem-state-cells = <1>; 335 }; 336 337 cdsp_smp2p_in: slave-kernel { 338 qcom,entry-name = "slave-kernel"; 339 interrupt-controller; 340 #interrupt-cells = <2>; 341 }; 342 }; 343 344 smp2p-mpss { 345 compatible = "qcom,smp2p"; 346 qcom,smem = <435>, <428>; 347 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 348 IPCC_MPROC_SIGNAL_SMP2P 349 IRQ_TYPE_EDGE_RISING>; 350 mboxes = <&ipcc IPCC_CLIENT_MPSS 351 IPCC_MPROC_SIGNAL_SMP2P>; 352 353 qcom,local-pid = <0>; 354 qcom,remote-pid = <1>; 355 356 modem_smp2p_out: master-kernel { 357 qcom,entry-name = "master-kernel"; 358 #qcom,smem-state-cells = <1>; 359 }; 360 361 modem_smp2p_in: slave-kernel { 362 qcom,entry-name = "slave-kernel"; 363 interrupt-controller; 364 #interrupt-cells = <2>; 365 }; 366 367 ipa_smp2p_out: ipa-ap-to-modem { 368 qcom,entry-name = "ipa"; 369 #qcom,smem-state-cells = <1>; 370 }; 371 372 ipa_smp2p_in: ipa-modem-to-ap { 373 qcom,entry-name = "ipa"; 374 interrupt-controller; 375 #interrupt-cells = <2>; 376 }; 377 }; 378 379 smp2p-wpss { 380 compatible = "qcom,smp2p"; 381 qcom,smem = <617>, <616>; 382 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 383 IPCC_MPROC_SIGNAL_SMP2P 384 IRQ_TYPE_EDGE_RISING>; 385 mboxes = <&ipcc IPCC_CLIENT_WPSS 386 IPCC_MPROC_SIGNAL_SMP2P>; 387 388 qcom,local-pid = <0>; 389 qcom,remote-pid = <13>; 390 391 wpss_smp2p_out: master-kernel { 392 qcom,entry-name = "master-kernel"; 393 #qcom,smem-state-cells = <1>; 394 }; 395 396 wpss_smp2p_in: slave-kernel { 397 qcom,entry-name = "slave-kernel"; 398 interrupt-controller; 399 #interrupt-cells = <2>; 400 }; 401 }; 402 403 pmu { 404 compatible = "arm,armv8-pmuv3"; 405 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 406 }; 407 408 psci { 409 compatible = "arm,psci-1.0"; 410 method = "smc"; 411 }; 412 413 soc: soc@0 { 414 #address-cells = <2>; 415 #size-cells = <2>; 416 ranges = <0 0 0 0 0x10 0>; 417 dma-ranges = <0 0 0 0 0x10 0>; 418 compatible = "simple-bus"; 419 420 gcc: clock-controller@100000 { 421 compatible = "qcom,gcc-sc7280"; 422 reg = <0 0x00100000 0 0x1f0000>; 423 clocks = <&rpmhcc RPMH_CXO_CLK>, 424 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 425 <0>, <0>, <0>, <0>, <0>, <0>; 426 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 427 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 428 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 429 "ufs_phy_tx_symbol_0_clk", 430 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 431 #clock-cells = <1>; 432 #reset-cells = <1>; 433 #power-domain-cells = <1>; 434 }; 435 436 ipcc: mailbox@408000 { 437 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 438 reg = <0 0x00408000 0 0x1000>; 439 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 440 interrupt-controller; 441 #interrupt-cells = <3>; 442 #mbox-cells = <2>; 443 }; 444 445 sdhc_1: sdhci@7c4000 { 446 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 447 status = "disabled"; 448 449 reg = <0 0x007c4000 0 0x1000>, 450 <0 0x007c5000 0 0x1000>; 451 reg-names = "hc", "cqhci"; 452 453 iommus = <&apps_smmu 0xc0 0x0>; 454 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 456 interrupt-names = "hc_irq", "pwr_irq"; 457 458 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 459 <&gcc GCC_SDCC1_AHB_CLK>, 460 <&rpmhcc RPMH_CXO_CLK>; 461 clock-names = "core", "iface", "xo"; 462 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 463 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 464 interconnect-names = "sdhc-ddr","cpu-sdhc"; 465 power-domains = <&rpmhpd SC7280_CX>; 466 operating-points-v2 = <&sdhc1_opp_table>; 467 468 bus-width = <8>; 469 supports-cqe; 470 471 qcom,dll-config = <0x0007642c>; 472 qcom,ddr-config = <0x80040868>; 473 474 mmc-ddr-1_8v; 475 mmc-hs200-1_8v; 476 mmc-hs400-1_8v; 477 mmc-hs400-enhanced-strobe; 478 479 sdhc1_opp_table: opp-table { 480 compatible = "operating-points-v2"; 481 482 opp-100000000 { 483 opp-hz = /bits/ 64 <100000000>; 484 required-opps = <&rpmhpd_opp_low_svs>; 485 opp-peak-kBps = <1800000 400000>; 486 opp-avg-kBps = <100000 0>; 487 }; 488 489 opp-384000000 { 490 opp-hz = /bits/ 64 <384000000>; 491 required-opps = <&rpmhpd_opp_nom>; 492 opp-peak-kBps = <5400000 1600000>; 493 opp-avg-kBps = <390000 0>; 494 }; 495 }; 496 497 }; 498 499 qupv3_id_0: geniqup@9c0000 { 500 compatible = "qcom,geni-se-qup"; 501 reg = <0 0x009c0000 0 0x2000>; 502 clock-names = "m-ahb", "s-ahb"; 503 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 504 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 505 #address-cells = <2>; 506 #size-cells = <2>; 507 ranges; 508 status = "disabled"; 509 510 uart5: serial@994000 { 511 compatible = "qcom,geni-debug-uart"; 512 reg = <0 0x00994000 0 0x4000>; 513 clock-names = "se"; 514 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 515 pinctrl-names = "default"; 516 pinctrl-0 = <&qup_uart5_default>; 517 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 518 status = "disabled"; 519 }; 520 }; 521 522 cnoc2: interconnect@1500000 { 523 reg = <0 0x01500000 0 0x1000>; 524 compatible = "qcom,sc7280-cnoc2"; 525 #interconnect-cells = <2>; 526 qcom,bcm-voters = <&apps_bcm_voter>; 527 }; 528 529 cnoc3: interconnect@1502000 { 530 reg = <0 0x01502000 0 0x1000>; 531 compatible = "qcom,sc7280-cnoc3"; 532 #interconnect-cells = <2>; 533 qcom,bcm-voters = <&apps_bcm_voter>; 534 }; 535 536 mc_virt: interconnect@1580000 { 537 reg = <0 0x01580000 0 0x4>; 538 compatible = "qcom,sc7280-mc-virt"; 539 #interconnect-cells = <2>; 540 qcom,bcm-voters = <&apps_bcm_voter>; 541 }; 542 543 system_noc: interconnect@1680000 { 544 reg = <0 0x01680000 0 0x15480>; 545 compatible = "qcom,sc7280-system-noc"; 546 #interconnect-cells = <2>; 547 qcom,bcm-voters = <&apps_bcm_voter>; 548 }; 549 550 aggre1_noc: interconnect@16e0000 { 551 compatible = "qcom,sc7280-aggre1-noc"; 552 reg = <0 0x016e0000 0 0x1c080>; 553 #interconnect-cells = <2>; 554 qcom,bcm-voters = <&apps_bcm_voter>; 555 }; 556 557 aggre2_noc: interconnect@1700000 { 558 reg = <0 0x01700000 0 0x2b080>; 559 compatible = "qcom,sc7280-aggre2-noc"; 560 #interconnect-cells = <2>; 561 qcom,bcm-voters = <&apps_bcm_voter>; 562 }; 563 564 mmss_noc: interconnect@1740000 { 565 reg = <0 0x01740000 0 0x1e080>; 566 compatible = "qcom,sc7280-mmss-noc"; 567 #interconnect-cells = <2>; 568 qcom,bcm-voters = <&apps_bcm_voter>; 569 }; 570 571 tcsr_mutex: hwlock@1f40000 { 572 compatible = "qcom,tcsr-mutex", "syscon"; 573 reg = <0 0x01f40000 0 0x40000>; 574 #hwlock-cells = <1>; 575 }; 576 577 lpasscc: lpasscc@3000000 { 578 compatible = "qcom,sc7280-lpasscc"; 579 reg = <0 0x03000000 0 0x40>, 580 <0 0x03c04000 0 0x4>, 581 <0 0x03389000 0 0x24>; 582 reg-names = "qdsp6ss", "top_cc", "cc"; 583 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 584 clock-names = "iface"; 585 #clock-cells = <1>; 586 }; 587 588 lpass_ag_noc: interconnect@3c40000 { 589 reg = <0 0x03c40000 0 0xf080>; 590 compatible = "qcom,sc7280-lpass-ag-noc"; 591 #interconnect-cells = <2>; 592 qcom,bcm-voters = <&apps_bcm_voter>; 593 }; 594 595 gpucc: clock-controller@3d90000 { 596 compatible = "qcom,sc7280-gpucc"; 597 reg = <0 0x03d90000 0 0x9000>; 598 clocks = <&rpmhcc RPMH_CXO_CLK>, 599 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 600 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 601 clock-names = "bi_tcxo", 602 "gcc_gpu_gpll0_clk_src", 603 "gcc_gpu_gpll0_div_clk_src"; 604 #clock-cells = <1>; 605 #reset-cells = <1>; 606 #power-domain-cells = <1>; 607 }; 608 609 stm@6002000 { 610 compatible = "arm,coresight-stm", "arm,primecell"; 611 reg = <0 0x06002000 0 0x1000>, 612 <0 0x16280000 0 0x180000>; 613 reg-names = "stm-base", "stm-stimulus-base"; 614 615 clocks = <&aoss_qmp>; 616 clock-names = "apb_pclk"; 617 618 out-ports { 619 port { 620 stm_out: endpoint { 621 remote-endpoint = <&funnel0_in7>; 622 }; 623 }; 624 }; 625 }; 626 627 funnel@6041000 { 628 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 629 reg = <0 0x06041000 0 0x1000>; 630 631 clocks = <&aoss_qmp>; 632 clock-names = "apb_pclk"; 633 634 out-ports { 635 port { 636 funnel0_out: endpoint { 637 remote-endpoint = <&merge_funnel_in0>; 638 }; 639 }; 640 }; 641 642 in-ports { 643 #address-cells = <1>; 644 #size-cells = <0>; 645 646 port@7 { 647 reg = <7>; 648 funnel0_in7: endpoint { 649 remote-endpoint = <&stm_out>; 650 }; 651 }; 652 }; 653 }; 654 655 funnel@6042000 { 656 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 657 reg = <0 0x06042000 0 0x1000>; 658 659 clocks = <&aoss_qmp>; 660 clock-names = "apb_pclk"; 661 662 out-ports { 663 port { 664 funnel1_out: endpoint { 665 remote-endpoint = <&merge_funnel_in1>; 666 }; 667 }; 668 }; 669 670 in-ports { 671 #address-cells = <1>; 672 #size-cells = <0>; 673 674 port@4 { 675 reg = <4>; 676 funnel1_in4: endpoint { 677 remote-endpoint = <&apss_merge_funnel_out>; 678 }; 679 }; 680 }; 681 }; 682 683 funnel@6045000 { 684 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 685 reg = <0 0x06045000 0 0x1000>; 686 687 clocks = <&aoss_qmp>; 688 clock-names = "apb_pclk"; 689 690 out-ports { 691 port { 692 merge_funnel_out: endpoint { 693 remote-endpoint = <&swao_funnel_in>; 694 }; 695 }; 696 }; 697 698 in-ports { 699 #address-cells = <1>; 700 #size-cells = <0>; 701 702 port@0 { 703 reg = <0>; 704 merge_funnel_in0: endpoint { 705 remote-endpoint = <&funnel0_out>; 706 }; 707 }; 708 709 port@1 { 710 reg = <1>; 711 merge_funnel_in1: endpoint { 712 remote-endpoint = <&funnel1_out>; 713 }; 714 }; 715 }; 716 }; 717 718 replicator@6046000 { 719 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 720 reg = <0 0x06046000 0 0x1000>; 721 722 clocks = <&aoss_qmp>; 723 clock-names = "apb_pclk"; 724 725 out-ports { 726 port { 727 replicator_out: endpoint { 728 remote-endpoint = <&etr_in>; 729 }; 730 }; 731 }; 732 733 in-ports { 734 port { 735 replicator_in: endpoint { 736 remote-endpoint = <&swao_replicator_out>; 737 }; 738 }; 739 }; 740 }; 741 742 etr@6048000 { 743 compatible = "arm,coresight-tmc", "arm,primecell"; 744 reg = <0 0x06048000 0 0x1000>; 745 iommus = <&apps_smmu 0x04c0 0>; 746 747 clocks = <&aoss_qmp>; 748 clock-names = "apb_pclk"; 749 arm,scatter-gather; 750 751 in-ports { 752 port { 753 etr_in: endpoint { 754 remote-endpoint = <&replicator_out>; 755 }; 756 }; 757 }; 758 }; 759 760 funnel@6b04000 { 761 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 762 reg = <0 0x06b04000 0 0x1000>; 763 764 clocks = <&aoss_qmp>; 765 clock-names = "apb_pclk"; 766 767 out-ports { 768 port { 769 swao_funnel_out: endpoint { 770 remote-endpoint = <&etf_in>; 771 }; 772 }; 773 }; 774 775 in-ports { 776 #address-cells = <1>; 777 #size-cells = <0>; 778 779 port@7 { 780 reg = <7>; 781 swao_funnel_in: endpoint { 782 remote-endpoint = <&merge_funnel_out>; 783 }; 784 }; 785 }; 786 }; 787 788 etf@6b05000 { 789 compatible = "arm,coresight-tmc", "arm,primecell"; 790 reg = <0 0x06b05000 0 0x1000>; 791 792 clocks = <&aoss_qmp>; 793 clock-names = "apb_pclk"; 794 795 out-ports { 796 port { 797 etf_out: endpoint { 798 remote-endpoint = <&swao_replicator_in>; 799 }; 800 }; 801 }; 802 803 in-ports { 804 port { 805 etf_in: endpoint { 806 remote-endpoint = <&swao_funnel_out>; 807 }; 808 }; 809 }; 810 }; 811 812 replicator@6b06000 { 813 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 814 reg = <0 0x06b06000 0 0x1000>; 815 816 clocks = <&aoss_qmp>; 817 clock-names = "apb_pclk"; 818 qcom,replicator-loses-context; 819 820 out-ports { 821 port { 822 swao_replicator_out: endpoint { 823 remote-endpoint = <&replicator_in>; 824 }; 825 }; 826 }; 827 828 in-ports { 829 port { 830 swao_replicator_in: endpoint { 831 remote-endpoint = <&etf_out>; 832 }; 833 }; 834 }; 835 }; 836 837 etm@7040000 { 838 compatible = "arm,coresight-etm4x", "arm,primecell"; 839 reg = <0 0x07040000 0 0x1000>; 840 841 cpu = <&CPU0>; 842 843 clocks = <&aoss_qmp>; 844 clock-names = "apb_pclk"; 845 arm,coresight-loses-context-with-cpu; 846 qcom,skip-power-up; 847 848 out-ports { 849 port { 850 etm0_out: endpoint { 851 remote-endpoint = <&apss_funnel_in0>; 852 }; 853 }; 854 }; 855 }; 856 857 etm@7140000 { 858 compatible = "arm,coresight-etm4x", "arm,primecell"; 859 reg = <0 0x07140000 0 0x1000>; 860 861 cpu = <&CPU1>; 862 863 clocks = <&aoss_qmp>; 864 clock-names = "apb_pclk"; 865 arm,coresight-loses-context-with-cpu; 866 qcom,skip-power-up; 867 868 out-ports { 869 port { 870 etm1_out: endpoint { 871 remote-endpoint = <&apss_funnel_in1>; 872 }; 873 }; 874 }; 875 }; 876 877 etm@7240000 { 878 compatible = "arm,coresight-etm4x", "arm,primecell"; 879 reg = <0 0x07240000 0 0x1000>; 880 881 cpu = <&CPU2>; 882 883 clocks = <&aoss_qmp>; 884 clock-names = "apb_pclk"; 885 arm,coresight-loses-context-with-cpu; 886 qcom,skip-power-up; 887 888 out-ports { 889 port { 890 etm2_out: endpoint { 891 remote-endpoint = <&apss_funnel_in2>; 892 }; 893 }; 894 }; 895 }; 896 897 etm@7340000 { 898 compatible = "arm,coresight-etm4x", "arm,primecell"; 899 reg = <0 0x07340000 0 0x1000>; 900 901 cpu = <&CPU3>; 902 903 clocks = <&aoss_qmp>; 904 clock-names = "apb_pclk"; 905 arm,coresight-loses-context-with-cpu; 906 qcom,skip-power-up; 907 908 out-ports { 909 port { 910 etm3_out: endpoint { 911 remote-endpoint = <&apss_funnel_in3>; 912 }; 913 }; 914 }; 915 }; 916 917 etm@7440000 { 918 compatible = "arm,coresight-etm4x", "arm,primecell"; 919 reg = <0 0x07440000 0 0x1000>; 920 921 cpu = <&CPU4>; 922 923 clocks = <&aoss_qmp>; 924 clock-names = "apb_pclk"; 925 arm,coresight-loses-context-with-cpu; 926 qcom,skip-power-up; 927 928 out-ports { 929 port { 930 etm4_out: endpoint { 931 remote-endpoint = <&apss_funnel_in4>; 932 }; 933 }; 934 }; 935 }; 936 937 etm@7540000 { 938 compatible = "arm,coresight-etm4x", "arm,primecell"; 939 reg = <0 0x07540000 0 0x1000>; 940 941 cpu = <&CPU5>; 942 943 clocks = <&aoss_qmp>; 944 clock-names = "apb_pclk"; 945 arm,coresight-loses-context-with-cpu; 946 qcom,skip-power-up; 947 948 out-ports { 949 port { 950 etm5_out: endpoint { 951 remote-endpoint = <&apss_funnel_in5>; 952 }; 953 }; 954 }; 955 }; 956 957 etm@7640000 { 958 compatible = "arm,coresight-etm4x", "arm,primecell"; 959 reg = <0 0x07640000 0 0x1000>; 960 961 cpu = <&CPU6>; 962 963 clocks = <&aoss_qmp>; 964 clock-names = "apb_pclk"; 965 arm,coresight-loses-context-with-cpu; 966 qcom,skip-power-up; 967 968 out-ports { 969 port { 970 etm6_out: endpoint { 971 remote-endpoint = <&apss_funnel_in6>; 972 }; 973 }; 974 }; 975 }; 976 977 etm@7740000 { 978 compatible = "arm,coresight-etm4x", "arm,primecell"; 979 reg = <0 0x07740000 0 0x1000>; 980 981 cpu = <&CPU7>; 982 983 clocks = <&aoss_qmp>; 984 clock-names = "apb_pclk"; 985 arm,coresight-loses-context-with-cpu; 986 qcom,skip-power-up; 987 988 out-ports { 989 port { 990 etm7_out: endpoint { 991 remote-endpoint = <&apss_funnel_in7>; 992 }; 993 }; 994 }; 995 }; 996 997 funnel@7800000 { /* APSS Funnel */ 998 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 999 reg = <0 0x07800000 0 0x1000>; 1000 1001 clocks = <&aoss_qmp>; 1002 clock-names = "apb_pclk"; 1003 1004 out-ports { 1005 port { 1006 apss_funnel_out: endpoint { 1007 remote-endpoint = <&apss_merge_funnel_in>; 1008 }; 1009 }; 1010 }; 1011 1012 in-ports { 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 1016 port@0 { 1017 reg = <0>; 1018 apss_funnel_in0: endpoint { 1019 remote-endpoint = <&etm0_out>; 1020 }; 1021 }; 1022 1023 port@1 { 1024 reg = <1>; 1025 apss_funnel_in1: endpoint { 1026 remote-endpoint = <&etm1_out>; 1027 }; 1028 }; 1029 1030 port@2 { 1031 reg = <2>; 1032 apss_funnel_in2: endpoint { 1033 remote-endpoint = <&etm2_out>; 1034 }; 1035 }; 1036 1037 port@3 { 1038 reg = <3>; 1039 apss_funnel_in3: endpoint { 1040 remote-endpoint = <&etm3_out>; 1041 }; 1042 }; 1043 1044 port@4 { 1045 reg = <4>; 1046 apss_funnel_in4: endpoint { 1047 remote-endpoint = <&etm4_out>; 1048 }; 1049 }; 1050 1051 port@5 { 1052 reg = <5>; 1053 apss_funnel_in5: endpoint { 1054 remote-endpoint = <&etm5_out>; 1055 }; 1056 }; 1057 1058 port@6 { 1059 reg = <6>; 1060 apss_funnel_in6: endpoint { 1061 remote-endpoint = <&etm6_out>; 1062 }; 1063 }; 1064 1065 port@7 { 1066 reg = <7>; 1067 apss_funnel_in7: endpoint { 1068 remote-endpoint = <&etm7_out>; 1069 }; 1070 }; 1071 }; 1072 }; 1073 1074 funnel@7810000 { 1075 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1076 reg = <0 0x07810000 0 0x1000>; 1077 1078 clocks = <&aoss_qmp>; 1079 clock-names = "apb_pclk"; 1080 1081 out-ports { 1082 port { 1083 apss_merge_funnel_out: endpoint { 1084 remote-endpoint = <&funnel1_in4>; 1085 }; 1086 }; 1087 }; 1088 1089 in-ports { 1090 port { 1091 apss_merge_funnel_in: endpoint { 1092 remote-endpoint = <&apss_funnel_out>; 1093 }; 1094 }; 1095 }; 1096 }; 1097 1098 sdhc_2: sdhci@8804000 { 1099 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 1100 status = "disabled"; 1101 1102 reg = <0 0x08804000 0 0x1000>; 1103 1104 iommus = <&apps_smmu 0x100 0x0>; 1105 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1107 interrupt-names = "hc_irq", "pwr_irq"; 1108 1109 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 1110 <&gcc GCC_SDCC2_AHB_CLK>, 1111 <&rpmhcc RPMH_CXO_CLK>; 1112 clock-names = "core", "iface", "xo"; 1113 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 1114 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 1115 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1116 power-domains = <&rpmhpd SC7280_CX>; 1117 operating-points-v2 = <&sdhc2_opp_table>; 1118 1119 bus-width = <4>; 1120 1121 qcom,dll-config = <0x0007642c>; 1122 1123 sdhc2_opp_table: opp-table { 1124 compatible = "operating-points-v2"; 1125 1126 opp-100000000 { 1127 opp-hz = /bits/ 64 <100000000>; 1128 required-opps = <&rpmhpd_opp_low_svs>; 1129 opp-peak-kBps = <1800000 400000>; 1130 opp-avg-kBps = <100000 0>; 1131 }; 1132 1133 opp-202000000 { 1134 opp-hz = /bits/ 64 <202000000>; 1135 required-opps = <&rpmhpd_opp_nom>; 1136 opp-peak-kBps = <5400000 1600000>; 1137 opp-avg-kBps = <200000 0>; 1138 }; 1139 }; 1140 1141 }; 1142 1143 usb_1_hsphy: phy@88e3000 { 1144 compatible = "qcom,sc7280-usb-hs-phy", 1145 "qcom,usb-snps-hs-7nm-phy"; 1146 reg = <0 0x088e3000 0 0x400>; 1147 status = "disabled"; 1148 #phy-cells = <0>; 1149 1150 clocks = <&rpmhcc RPMH_CXO_CLK>; 1151 clock-names = "ref"; 1152 1153 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1154 }; 1155 1156 usb_2_hsphy: phy@88e4000 { 1157 compatible = "qcom,sc7280-usb-hs-phy", 1158 "qcom,usb-snps-hs-7nm-phy"; 1159 reg = <0 0x088e4000 0 0x400>; 1160 status = "disabled"; 1161 #phy-cells = <0>; 1162 1163 clocks = <&rpmhcc RPMH_CXO_CLK>; 1164 clock-names = "ref"; 1165 1166 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1167 }; 1168 1169 usb_1_qmpphy: phy-wrapper@88e9000 { 1170 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 1171 "qcom,sm8250-qmp-usb3-dp-phy"; 1172 reg = <0 0x088e9000 0 0x200>, 1173 <0 0x088e8000 0 0x40>, 1174 <0 0x088ea000 0 0x200>; 1175 status = "disabled"; 1176 #address-cells = <2>; 1177 #size-cells = <2>; 1178 ranges; 1179 1180 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1181 <&rpmhcc RPMH_CXO_CLK>, 1182 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1183 clock-names = "aux", "ref_clk_src", "com_aux"; 1184 1185 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 1186 <&gcc GCC_USB3_PHY_PRIM_BCR>; 1187 reset-names = "phy", "common"; 1188 1189 usb_1_ssphy: usb3-phy@88e9200 { 1190 reg = <0 0x088e9200 0 0x200>, 1191 <0 0x088e9400 0 0x200>, 1192 <0 0x088e9c00 0 0x400>, 1193 <0 0x088e9600 0 0x200>, 1194 <0 0x088e9800 0 0x200>, 1195 <0 0x088e9a00 0 0x100>; 1196 #clock-cells = <0>; 1197 #phy-cells = <0>; 1198 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1199 clock-names = "pipe0"; 1200 clock-output-names = "usb3_phy_pipe_clk_src"; 1201 }; 1202 1203 dp_phy: dp-phy@88ea200 { 1204 reg = <0 0x088ea200 0 0x200>, 1205 <0 0x088ea400 0 0x200>, 1206 <0 0x088eac00 0 0x400>, 1207 <0 0x088ea600 0 0x200>, 1208 <0 0x088ea800 0 0x200>, 1209 <0 0x088eaa00 0 0x100>; 1210 #phy-cells = <0>; 1211 #clock-cells = <1>; 1212 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1213 clock-names = "pipe0"; 1214 clock-output-names = "usb3_phy_pipe_clk_src"; 1215 }; 1216 }; 1217 1218 usb_2: usb@8cf8800 { 1219 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 1220 reg = <0 0x08cf8800 0 0x400>; 1221 status = "disabled"; 1222 #address-cells = <2>; 1223 #size-cells = <2>; 1224 ranges; 1225 dma-ranges; 1226 1227 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 1228 <&gcc GCC_USB30_SEC_MASTER_CLK>, 1229 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 1230 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1231 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 1232 clock-names = "cfg_noc", "core", "iface","mock_utmi", 1233 "sleep"; 1234 1235 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1236 <&gcc GCC_USB30_SEC_MASTER_CLK>; 1237 assigned-clock-rates = <19200000>, <200000000>; 1238 1239 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1240 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 1241 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 1242 interrupt-names = "hs_phy_irq", 1243 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1244 1245 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 1246 1247 resets = <&gcc GCC_USB30_SEC_BCR>; 1248 1249 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 1250 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 1251 interconnect-names = "usb-ddr", "apps-usb"; 1252 1253 usb_2_dwc3: usb@8c00000 { 1254 compatible = "snps,dwc3"; 1255 reg = <0 0x08c00000 0 0xe000>; 1256 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1257 iommus = <&apps_smmu 0xa0 0x0>; 1258 snps,dis_u2_susphy_quirk; 1259 snps,dis_enblslpm_quirk; 1260 phys = <&usb_2_hsphy>; 1261 phy-names = "usb2-phy"; 1262 maximum-speed = "high-speed"; 1263 }; 1264 }; 1265 1266 dc_noc: interconnect@90e0000 { 1267 reg = <0 0x090e0000 0 0x5080>; 1268 compatible = "qcom,sc7280-dc-noc"; 1269 #interconnect-cells = <2>; 1270 qcom,bcm-voters = <&apps_bcm_voter>; 1271 }; 1272 1273 gem_noc: interconnect@9100000 { 1274 reg = <0 0x9100000 0 0xe2200>; 1275 compatible = "qcom,sc7280-gem-noc"; 1276 #interconnect-cells = <2>; 1277 qcom,bcm-voters = <&apps_bcm_voter>; 1278 }; 1279 1280 system-cache-controller@9200000 { 1281 compatible = "qcom,sc7280-llcc"; 1282 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 1283 reg-names = "llcc_base", "llcc_broadcast_base"; 1284 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1285 }; 1286 1287 nsp_noc: interconnect@a0c0000 { 1288 reg = <0 0x0a0c0000 0 0x10000>; 1289 compatible = "qcom,sc7280-nsp-noc"; 1290 #interconnect-cells = <2>; 1291 qcom,bcm-voters = <&apps_bcm_voter>; 1292 }; 1293 1294 usb_1: usb@a6f8800 { 1295 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 1296 reg = <0 0x0a6f8800 0 0x400>; 1297 status = "disabled"; 1298 #address-cells = <2>; 1299 #size-cells = <2>; 1300 ranges; 1301 dma-ranges; 1302 1303 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1304 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1305 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1306 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1307 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 1308 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1309 "sleep"; 1310 1311 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1312 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1313 assigned-clock-rates = <19200000>, <200000000>; 1314 1315 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1316 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1317 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1318 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 1319 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 1320 "dm_hs_phy_irq", "ss_phy_irq"; 1321 1322 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1323 1324 resets = <&gcc GCC_USB30_PRIM_BCR>; 1325 1326 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 1327 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 1328 interconnect-names = "usb-ddr", "apps-usb"; 1329 1330 usb_1_dwc3: usb@a600000 { 1331 compatible = "snps,dwc3"; 1332 reg = <0 0x0a600000 0 0xe000>; 1333 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1334 iommus = <&apps_smmu 0xe0 0x0>; 1335 snps,dis_u2_susphy_quirk; 1336 snps,dis_enblslpm_quirk; 1337 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1338 phy-names = "usb2-phy", "usb3-phy"; 1339 maximum-speed = "super-speed"; 1340 }; 1341 }; 1342 1343 videocc: clock-controller@aaf0000 { 1344 compatible = "qcom,sc7280-videocc"; 1345 reg = <0 0xaaf0000 0 0x10000>; 1346 clocks = <&rpmhcc RPMH_CXO_CLK>, 1347 <&rpmhcc RPMH_CXO_CLK_A>; 1348 clock-names = "bi_tcxo", "bi_tcxo_ao"; 1349 #clock-cells = <1>; 1350 #reset-cells = <1>; 1351 #power-domain-cells = <1>; 1352 }; 1353 1354 dispcc: clock-controller@af00000 { 1355 compatible = "qcom,sc7280-dispcc"; 1356 reg = <0 0xaf00000 0 0x20000>; 1357 clocks = <&rpmhcc RPMH_CXO_CLK>, 1358 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 1359 <0>, <0>, <0>, <0>, <0>, <0>; 1360 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 1361 "dsi0_phy_pll_out_byteclk", 1362 "dsi0_phy_pll_out_dsiclk", 1363 "dp_phy_pll_link_clk", 1364 "dp_phy_pll_vco_div_clk", 1365 "edp_phy_pll_link_clk", 1366 "edp_phy_pll_vco_div_clk"; 1367 #clock-cells = <1>; 1368 #reset-cells = <1>; 1369 #power-domain-cells = <1>; 1370 }; 1371 1372 pdc: interrupt-controller@b220000 { 1373 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 1374 reg = <0 0x0b220000 0 0x30000>; 1375 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 1376 <55 306 4>, <59 312 3>, <62 374 2>, 1377 <64 434 2>, <66 438 3>, <69 86 1>, 1378 <70 520 54>, <124 609 31>, <155 63 1>, 1379 <156 716 12>; 1380 #interrupt-cells = <2>; 1381 interrupt-parent = <&intc>; 1382 interrupt-controller; 1383 }; 1384 1385 pdc_reset: reset-controller@b5e0000 { 1386 compatible = "qcom,sc7280-pdc-global"; 1387 reg = <0 0x0b5e0000 0 0x20000>; 1388 #reset-cells = <1>; 1389 }; 1390 1391 tsens0: thermal-sensor@c263000 { 1392 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 1393 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1394 <0 0x0c222000 0 0x1ff>; /* SROT */ 1395 #qcom,sensors = <15>; 1396 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1398 interrupt-names = "uplow","critical"; 1399 #thermal-sensor-cells = <1>; 1400 }; 1401 1402 tsens1: thermal-sensor@c265000 { 1403 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 1404 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1405 <0 0x0c223000 0 0x1ff>; /* SROT */ 1406 #qcom,sensors = <12>; 1407 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1409 interrupt-names = "uplow","critical"; 1410 #thermal-sensor-cells = <1>; 1411 }; 1412 1413 aoss_reset: reset-controller@c2a0000 { 1414 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 1415 reg = <0 0x0c2a0000 0 0x31000>; 1416 #reset-cells = <1>; 1417 }; 1418 1419 aoss_qmp: power-controller@c300000 { 1420 compatible = "qcom,sc7280-aoss-qmp"; 1421 reg = <0 0x0c300000 0 0x100000>; 1422 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 1423 IPCC_MPROC_SIGNAL_GLINK_QMP 1424 IRQ_TYPE_EDGE_RISING>; 1425 mboxes = <&ipcc IPCC_CLIENT_AOP 1426 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1427 1428 #clock-cells = <0>; 1429 #power-domain-cells = <1>; 1430 }; 1431 1432 spmi_bus: spmi@c440000 { 1433 compatible = "qcom,spmi-pmic-arb"; 1434 reg = <0 0x0c440000 0 0x1100>, 1435 <0 0x0c600000 0 0x2000000>, 1436 <0 0x0e600000 0 0x100000>, 1437 <0 0x0e700000 0 0xa0000>, 1438 <0 0x0c40a000 0 0x26000>; 1439 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1440 interrupt-names = "periph_irq"; 1441 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1442 qcom,ee = <0>; 1443 qcom,channel = <0>; 1444 #address-cells = <1>; 1445 #size-cells = <1>; 1446 interrupt-controller; 1447 #interrupt-cells = <4>; 1448 }; 1449 1450 tlmm: pinctrl@f100000 { 1451 compatible = "qcom,sc7280-pinctrl"; 1452 reg = <0 0x0f100000 0 0x300000>; 1453 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1454 gpio-controller; 1455 #gpio-cells = <2>; 1456 interrupt-controller; 1457 #interrupt-cells = <2>; 1458 gpio-ranges = <&tlmm 0 0 175>; 1459 wakeup-parent = <&pdc>; 1460 1461 qup_uart5_default: qup-uart5-default { 1462 pins = "gpio46", "gpio47"; 1463 function = "qup13"; 1464 }; 1465 1466 sdc1_on: sdc1-on { 1467 clk { 1468 pins = "sdc1_clk"; 1469 }; 1470 1471 cmd { 1472 pins = "sdc1_cmd"; 1473 }; 1474 1475 data { 1476 pins = "sdc1_data"; 1477 }; 1478 1479 rclk { 1480 pins = "sdc1_rclk"; 1481 }; 1482 }; 1483 1484 sdc1_off: sdc1-off { 1485 clk { 1486 pins = "sdc1_clk"; 1487 drive-strength = <2>; 1488 bias-bus-hold; 1489 }; 1490 1491 cmd { 1492 pins = "sdc1_cmd"; 1493 drive-strength = <2>; 1494 bias-bus-hold; 1495 }; 1496 1497 data { 1498 pins = "sdc1_data"; 1499 drive-strength = <2>; 1500 bias-bus-hold; 1501 }; 1502 1503 rclk { 1504 pins = "sdc1_rclk"; 1505 bias-bus-hold; 1506 }; 1507 }; 1508 1509 sdc2_on: sdc2-on { 1510 clk { 1511 pins = "sdc2_clk"; 1512 }; 1513 1514 cmd { 1515 pins = "sdc2_cmd"; 1516 }; 1517 1518 data { 1519 pins = "sdc2_data"; 1520 }; 1521 1522 sd-cd { 1523 pins = "gpio91"; 1524 }; 1525 }; 1526 1527 sdc2_off: sdc2-off { 1528 clk { 1529 pins = "sdc2_clk"; 1530 drive-strength = <2>; 1531 bias-bus-hold; 1532 }; 1533 1534 cmd { 1535 pins ="sdc2_cmd"; 1536 drive-strength = <2>; 1537 bias-bus-hold; 1538 }; 1539 1540 data { 1541 pins ="sdc2_data"; 1542 drive-strength = <2>; 1543 bias-bus-hold; 1544 }; 1545 }; 1546 }; 1547 1548 apps_smmu: iommu@15000000 { 1549 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 1550 reg = <0 0x15000000 0 0x100000>; 1551 #iommu-cells = <2>; 1552 #global-interrupts = <1>; 1553 dma-coherent; 1554 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1555 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1568 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1570 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1572 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1574 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1575 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1579 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1580 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1581 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1582 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1583 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1584 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1585 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1586 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1587 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1617 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1621 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1622 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1623 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1626 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1635 }; 1636 1637 intc: interrupt-controller@17a00000 { 1638 compatible = "arm,gic-v3"; 1639 #address-cells = <2>; 1640 #size-cells = <2>; 1641 ranges; 1642 #interrupt-cells = <3>; 1643 interrupt-controller; 1644 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 1645 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 1646 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 1647 1648 gic-its@17a40000 { 1649 compatible = "arm,gic-v3-its"; 1650 msi-controller; 1651 #msi-cells = <1>; 1652 reg = <0 0x17a40000 0 0x20000>; 1653 status = "disabled"; 1654 }; 1655 }; 1656 1657 watchdog@17c10000 { 1658 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 1659 reg = <0 0x17c10000 0 0x1000>; 1660 clocks = <&sleep_clk>; 1661 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1662 }; 1663 1664 timer@17c20000 { 1665 #address-cells = <2>; 1666 #size-cells = <2>; 1667 ranges; 1668 compatible = "arm,armv7-timer-mem"; 1669 reg = <0 0x17c20000 0 0x1000>; 1670 1671 frame@17c21000 { 1672 frame-number = <0>; 1673 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1674 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1675 reg = <0 0x17c21000 0 0x1000>, 1676 <0 0x17c22000 0 0x1000>; 1677 }; 1678 1679 frame@17c23000 { 1680 frame-number = <1>; 1681 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1682 reg = <0 0x17c23000 0 0x1000>; 1683 status = "disabled"; 1684 }; 1685 1686 frame@17c25000 { 1687 frame-number = <2>; 1688 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1689 reg = <0 0x17c25000 0 0x1000>; 1690 status = "disabled"; 1691 }; 1692 1693 frame@17c27000 { 1694 frame-number = <3>; 1695 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1696 reg = <0 0x17c27000 0 0x1000>; 1697 status = "disabled"; 1698 }; 1699 1700 frame@17c29000 { 1701 frame-number = <4>; 1702 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1703 reg = <0 0x17c29000 0 0x1000>; 1704 status = "disabled"; 1705 }; 1706 1707 frame@17c2b000 { 1708 frame-number = <5>; 1709 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1710 reg = <0 0x17c2b000 0 0x1000>; 1711 status = "disabled"; 1712 }; 1713 1714 frame@17c2d000 { 1715 frame-number = <6>; 1716 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1717 reg = <0 0x17c2d000 0 0x1000>; 1718 status = "disabled"; 1719 }; 1720 }; 1721 1722 apps_rsc: rsc@18200000 { 1723 compatible = "qcom,rpmh-rsc"; 1724 reg = <0 0x18200000 0 0x10000>, 1725 <0 0x18210000 0 0x10000>, 1726 <0 0x18220000 0 0x10000>; 1727 reg-names = "drv-0", "drv-1", "drv-2"; 1728 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1731 qcom,tcs-offset = <0xd00>; 1732 qcom,drv-id = <2>; 1733 qcom,tcs-config = <ACTIVE_TCS 2>, 1734 <SLEEP_TCS 3>, 1735 <WAKE_TCS 3>, 1736 <CONTROL_TCS 1>; 1737 1738 apps_bcm_voter: bcm-voter { 1739 compatible = "qcom,bcm-voter"; 1740 }; 1741 1742 rpmhpd: power-controller { 1743 compatible = "qcom,sc7280-rpmhpd"; 1744 #power-domain-cells = <1>; 1745 operating-points-v2 = <&rpmhpd_opp_table>; 1746 1747 rpmhpd_opp_table: opp-table { 1748 compatible = "operating-points-v2"; 1749 1750 rpmhpd_opp_ret: opp1 { 1751 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1752 }; 1753 1754 rpmhpd_opp_low_svs: opp2 { 1755 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1756 }; 1757 1758 rpmhpd_opp_svs: opp3 { 1759 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1760 }; 1761 1762 rpmhpd_opp_svs_l1: opp4 { 1763 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1764 }; 1765 1766 rpmhpd_opp_svs_l2: opp5 { 1767 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1768 }; 1769 1770 rpmhpd_opp_nom: opp6 { 1771 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1772 }; 1773 1774 rpmhpd_opp_nom_l1: opp7 { 1775 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1776 }; 1777 1778 rpmhpd_opp_turbo: opp8 { 1779 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1780 }; 1781 1782 rpmhpd_opp_turbo_l1: opp9 { 1783 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1784 }; 1785 }; 1786 }; 1787 1788 rpmhcc: clock-controller { 1789 compatible = "qcom,sc7280-rpmh-clk"; 1790 clocks = <&xo_board>; 1791 clock-names = "xo"; 1792 #clock-cells = <1>; 1793 }; 1794 }; 1795 1796 cpufreq_hw: cpufreq@18591000 { 1797 compatible = "qcom,cpufreq-epss"; 1798 reg = <0 0x18591100 0 0x900>, 1799 <0 0x18592100 0 0x900>, 1800 <0 0x18593100 0 0x900>; 1801 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 1802 clock-names = "xo", "alternate"; 1803 #freq-domain-cells = <1>; 1804 }; 1805 }; 1806 1807 thermal_zones: thermal-zones { 1808 cpu0-thermal { 1809 polling-delay-passive = <250>; 1810 polling-delay = <0>; 1811 1812 thermal-sensors = <&tsens0 1>; 1813 1814 trips { 1815 cpu0_alert0: trip-point0 { 1816 temperature = <90000>; 1817 hysteresis = <2000>; 1818 type = "passive"; 1819 }; 1820 1821 cpu0_alert1: trip-point1 { 1822 temperature = <95000>; 1823 hysteresis = <2000>; 1824 type = "passive"; 1825 }; 1826 1827 cpu0_crit: cpu-crit { 1828 temperature = <110000>; 1829 hysteresis = <0>; 1830 type = "critical"; 1831 }; 1832 }; 1833 1834 cooling-maps { 1835 map0 { 1836 trip = <&cpu0_alert0>; 1837 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1838 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1839 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1840 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1841 }; 1842 map1 { 1843 trip = <&cpu0_alert1>; 1844 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1845 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1846 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1847 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1848 }; 1849 }; 1850 }; 1851 1852 cpu1-thermal { 1853 polling-delay-passive = <250>; 1854 polling-delay = <0>; 1855 1856 thermal-sensors = <&tsens0 2>; 1857 1858 trips { 1859 cpu1_alert0: trip-point0 { 1860 temperature = <90000>; 1861 hysteresis = <2000>; 1862 type = "passive"; 1863 }; 1864 1865 cpu1_alert1: trip-point1 { 1866 temperature = <95000>; 1867 hysteresis = <2000>; 1868 type = "passive"; 1869 }; 1870 1871 cpu1_crit: cpu-crit { 1872 temperature = <110000>; 1873 hysteresis = <0>; 1874 type = "critical"; 1875 }; 1876 }; 1877 1878 cooling-maps { 1879 map0 { 1880 trip = <&cpu1_alert0>; 1881 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1882 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1883 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1884 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1885 }; 1886 map1 { 1887 trip = <&cpu1_alert1>; 1888 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1889 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1890 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1891 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1892 }; 1893 }; 1894 }; 1895 1896 cpu2-thermal { 1897 polling-delay-passive = <250>; 1898 polling-delay = <0>; 1899 1900 thermal-sensors = <&tsens0 3>; 1901 1902 trips { 1903 cpu2_alert0: trip-point0 { 1904 temperature = <90000>; 1905 hysteresis = <2000>; 1906 type = "passive"; 1907 }; 1908 1909 cpu2_alert1: trip-point1 { 1910 temperature = <95000>; 1911 hysteresis = <2000>; 1912 type = "passive"; 1913 }; 1914 1915 cpu2_crit: cpu-crit { 1916 temperature = <110000>; 1917 hysteresis = <0>; 1918 type = "critical"; 1919 }; 1920 }; 1921 1922 cooling-maps { 1923 map0 { 1924 trip = <&cpu2_alert0>; 1925 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1926 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1927 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1928 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1929 }; 1930 map1 { 1931 trip = <&cpu2_alert1>; 1932 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1933 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1934 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1935 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1936 }; 1937 }; 1938 }; 1939 1940 cpu3-thermal { 1941 polling-delay-passive = <250>; 1942 polling-delay = <0>; 1943 1944 thermal-sensors = <&tsens0 4>; 1945 1946 trips { 1947 cpu3_alert0: trip-point0 { 1948 temperature = <90000>; 1949 hysteresis = <2000>; 1950 type = "passive"; 1951 }; 1952 1953 cpu3_alert1: trip-point1 { 1954 temperature = <95000>; 1955 hysteresis = <2000>; 1956 type = "passive"; 1957 }; 1958 1959 cpu3_crit: cpu-crit { 1960 temperature = <110000>; 1961 hysteresis = <0>; 1962 type = "critical"; 1963 }; 1964 }; 1965 1966 cooling-maps { 1967 map0 { 1968 trip = <&cpu3_alert0>; 1969 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1970 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1971 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1972 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1973 }; 1974 map1 { 1975 trip = <&cpu3_alert1>; 1976 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1977 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1978 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1979 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1980 }; 1981 }; 1982 }; 1983 1984 cpu4-thermal { 1985 polling-delay-passive = <250>; 1986 polling-delay = <0>; 1987 1988 thermal-sensors = <&tsens0 7>; 1989 1990 trips { 1991 cpu4_alert0: trip-point0 { 1992 temperature = <90000>; 1993 hysteresis = <2000>; 1994 type = "passive"; 1995 }; 1996 1997 cpu4_alert1: trip-point1 { 1998 temperature = <95000>; 1999 hysteresis = <2000>; 2000 type = "passive"; 2001 }; 2002 2003 cpu4_crit: cpu-crit { 2004 temperature = <110000>; 2005 hysteresis = <0>; 2006 type = "critical"; 2007 }; 2008 }; 2009 2010 cooling-maps { 2011 map0 { 2012 trip = <&cpu4_alert0>; 2013 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2014 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2015 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2016 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2017 }; 2018 map1 { 2019 trip = <&cpu4_alert1>; 2020 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2021 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2022 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2023 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2024 }; 2025 }; 2026 }; 2027 2028 cpu5-thermal { 2029 polling-delay-passive = <250>; 2030 polling-delay = <0>; 2031 2032 thermal-sensors = <&tsens0 8>; 2033 2034 trips { 2035 cpu5_alert0: trip-point0 { 2036 temperature = <90000>; 2037 hysteresis = <2000>; 2038 type = "passive"; 2039 }; 2040 2041 cpu5_alert1: trip-point1 { 2042 temperature = <95000>; 2043 hysteresis = <2000>; 2044 type = "passive"; 2045 }; 2046 2047 cpu5_crit: cpu-crit { 2048 temperature = <110000>; 2049 hysteresis = <0>; 2050 type = "critical"; 2051 }; 2052 }; 2053 2054 cooling-maps { 2055 map0 { 2056 trip = <&cpu5_alert0>; 2057 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2058 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2059 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2060 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2061 }; 2062 map1 { 2063 trip = <&cpu5_alert1>; 2064 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2065 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2066 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2067 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2068 }; 2069 }; 2070 }; 2071 2072 cpu6-thermal { 2073 polling-delay-passive = <250>; 2074 polling-delay = <0>; 2075 2076 thermal-sensors = <&tsens0 9>; 2077 2078 trips { 2079 cpu6_alert0: trip-point0 { 2080 temperature = <90000>; 2081 hysteresis = <2000>; 2082 type = "passive"; 2083 }; 2084 2085 cpu6_alert1: trip-point1 { 2086 temperature = <95000>; 2087 hysteresis = <2000>; 2088 type = "passive"; 2089 }; 2090 2091 cpu6_crit: cpu-crit { 2092 temperature = <110000>; 2093 hysteresis = <0>; 2094 type = "critical"; 2095 }; 2096 }; 2097 2098 cooling-maps { 2099 map0 { 2100 trip = <&cpu6_alert0>; 2101 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2102 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2103 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2104 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2105 }; 2106 map1 { 2107 trip = <&cpu6_alert1>; 2108 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2109 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2110 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2111 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2112 }; 2113 }; 2114 }; 2115 2116 cpu7-thermal { 2117 polling-delay-passive = <250>; 2118 polling-delay = <0>; 2119 2120 thermal-sensors = <&tsens0 10>; 2121 2122 trips { 2123 cpu7_alert0: trip-point0 { 2124 temperature = <90000>; 2125 hysteresis = <2000>; 2126 type = "passive"; 2127 }; 2128 2129 cpu7_alert1: trip-point1 { 2130 temperature = <95000>; 2131 hysteresis = <2000>; 2132 type = "passive"; 2133 }; 2134 2135 cpu7_crit: cpu-crit { 2136 temperature = <110000>; 2137 hysteresis = <0>; 2138 type = "critical"; 2139 }; 2140 }; 2141 2142 cooling-maps { 2143 map0 { 2144 trip = <&cpu7_alert0>; 2145 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2146 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2147 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2148 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2149 }; 2150 map1 { 2151 trip = <&cpu7_alert1>; 2152 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2153 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2154 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2155 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2156 }; 2157 }; 2158 }; 2159 2160 cpu8-thermal { 2161 polling-delay-passive = <250>; 2162 polling-delay = <0>; 2163 2164 thermal-sensors = <&tsens0 11>; 2165 2166 trips { 2167 cpu8_alert0: trip-point0 { 2168 temperature = <90000>; 2169 hysteresis = <2000>; 2170 type = "passive"; 2171 }; 2172 2173 cpu8_alert1: trip-point1 { 2174 temperature = <95000>; 2175 hysteresis = <2000>; 2176 type = "passive"; 2177 }; 2178 2179 cpu8_crit: cpu-crit { 2180 temperature = <110000>; 2181 hysteresis = <0>; 2182 type = "critical"; 2183 }; 2184 }; 2185 2186 cooling-maps { 2187 map0 { 2188 trip = <&cpu8_alert0>; 2189 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2190 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2191 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2192 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2193 }; 2194 map1 { 2195 trip = <&cpu8_alert1>; 2196 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2197 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2198 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2199 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2200 }; 2201 }; 2202 }; 2203 2204 cpu9-thermal { 2205 polling-delay-passive = <250>; 2206 polling-delay = <0>; 2207 2208 thermal-sensors = <&tsens0 12>; 2209 2210 trips { 2211 cpu9_alert0: trip-point0 { 2212 temperature = <90000>; 2213 hysteresis = <2000>; 2214 type = "passive"; 2215 }; 2216 2217 cpu9_alert1: trip-point1 { 2218 temperature = <95000>; 2219 hysteresis = <2000>; 2220 type = "passive"; 2221 }; 2222 2223 cpu9_crit: cpu-crit { 2224 temperature = <110000>; 2225 hysteresis = <0>; 2226 type = "critical"; 2227 }; 2228 }; 2229 2230 cooling-maps { 2231 map0 { 2232 trip = <&cpu9_alert0>; 2233 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2234 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2235 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2236 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2237 }; 2238 map1 { 2239 trip = <&cpu9_alert1>; 2240 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2241 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2242 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2243 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2244 }; 2245 }; 2246 }; 2247 2248 cpu10-thermal { 2249 polling-delay-passive = <250>; 2250 polling-delay = <0>; 2251 2252 thermal-sensors = <&tsens0 13>; 2253 2254 trips { 2255 cpu10_alert0: trip-point0 { 2256 temperature = <90000>; 2257 hysteresis = <2000>; 2258 type = "passive"; 2259 }; 2260 2261 cpu10_alert1: trip-point1 { 2262 temperature = <95000>; 2263 hysteresis = <2000>; 2264 type = "passive"; 2265 }; 2266 2267 cpu10_crit: cpu-crit { 2268 temperature = <110000>; 2269 hysteresis = <0>; 2270 type = "critical"; 2271 }; 2272 }; 2273 2274 cooling-maps { 2275 map0 { 2276 trip = <&cpu10_alert0>; 2277 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2278 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2279 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2280 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2281 }; 2282 map1 { 2283 trip = <&cpu10_alert1>; 2284 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2285 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2286 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2287 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2288 }; 2289 }; 2290 }; 2291 2292 cpu11-thermal { 2293 polling-delay-passive = <250>; 2294 polling-delay = <0>; 2295 2296 thermal-sensors = <&tsens0 14>; 2297 2298 trips { 2299 cpu11_alert0: trip-point0 { 2300 temperature = <90000>; 2301 hysteresis = <2000>; 2302 type = "passive"; 2303 }; 2304 2305 cpu11_alert1: trip-point1 { 2306 temperature = <95000>; 2307 hysteresis = <2000>; 2308 type = "passive"; 2309 }; 2310 2311 cpu11_crit: cpu-crit { 2312 temperature = <110000>; 2313 hysteresis = <0>; 2314 type = "critical"; 2315 }; 2316 }; 2317 2318 cooling-maps { 2319 map0 { 2320 trip = <&cpu11_alert0>; 2321 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2322 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2323 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2324 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2325 }; 2326 map1 { 2327 trip = <&cpu11_alert1>; 2328 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2329 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2330 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2331 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2332 }; 2333 }; 2334 }; 2335 2336 aoss0-thermal { 2337 polling-delay-passive = <0>; 2338 polling-delay = <0>; 2339 2340 thermal-sensors = <&tsens0 0>; 2341 2342 trips { 2343 aoss0_alert0: trip-point0 { 2344 temperature = <90000>; 2345 hysteresis = <2000>; 2346 type = "hot"; 2347 }; 2348 2349 aoss0_crit: aoss0-crit { 2350 temperature = <110000>; 2351 hysteresis = <0>; 2352 type = "critical"; 2353 }; 2354 }; 2355 }; 2356 2357 aoss1-thermal { 2358 polling-delay-passive = <0>; 2359 polling-delay = <0>; 2360 2361 thermal-sensors = <&tsens1 0>; 2362 2363 trips { 2364 aoss1_alert0: trip-point0 { 2365 temperature = <90000>; 2366 hysteresis = <2000>; 2367 type = "hot"; 2368 }; 2369 2370 aoss1_crit: aoss1-crit { 2371 temperature = <110000>; 2372 hysteresis = <0>; 2373 type = "critical"; 2374 }; 2375 }; 2376 }; 2377 2378 cpuss0-thermal { 2379 polling-delay-passive = <0>; 2380 polling-delay = <0>; 2381 2382 thermal-sensors = <&tsens0 5>; 2383 2384 trips { 2385 cpuss0_alert0: trip-point0 { 2386 temperature = <90000>; 2387 hysteresis = <2000>; 2388 type = "hot"; 2389 }; 2390 cpuss0_crit: cluster0-crit { 2391 temperature = <110000>; 2392 hysteresis = <0>; 2393 type = "critical"; 2394 }; 2395 }; 2396 }; 2397 2398 cpuss1-thermal { 2399 polling-delay-passive = <0>; 2400 polling-delay = <0>; 2401 2402 thermal-sensors = <&tsens0 6>; 2403 2404 trips { 2405 cpuss1_alert0: trip-point0 { 2406 temperature = <90000>; 2407 hysteresis = <2000>; 2408 type = "hot"; 2409 }; 2410 cpuss1_crit: cluster0-crit { 2411 temperature = <110000>; 2412 hysteresis = <0>; 2413 type = "critical"; 2414 }; 2415 }; 2416 }; 2417 2418 gpuss0-thermal { 2419 polling-delay-passive = <0>; 2420 polling-delay = <0>; 2421 2422 thermal-sensors = <&tsens1 1>; 2423 2424 trips { 2425 gpuss0_alert0: trip-point0 { 2426 temperature = <90000>; 2427 hysteresis = <2000>; 2428 type = "hot"; 2429 }; 2430 2431 gpuss0_crit: gpuss0-crit { 2432 temperature = <110000>; 2433 hysteresis = <0>; 2434 type = "critical"; 2435 }; 2436 }; 2437 }; 2438 2439 gpuss1-thermal { 2440 polling-delay-passive = <0>; 2441 polling-delay = <0>; 2442 2443 thermal-sensors = <&tsens1 2>; 2444 2445 trips { 2446 gpuss1_alert0: trip-point0 { 2447 temperature = <90000>; 2448 hysteresis = <2000>; 2449 type = "hot"; 2450 }; 2451 2452 gpuss1_crit: gpuss1-crit { 2453 temperature = <110000>; 2454 hysteresis = <0>; 2455 type = "critical"; 2456 }; 2457 }; 2458 }; 2459 2460 nspss0-thermal { 2461 polling-delay-passive = <0>; 2462 polling-delay = <0>; 2463 2464 thermal-sensors = <&tsens1 3>; 2465 2466 trips { 2467 nspss0_alert0: trip-point0 { 2468 temperature = <90000>; 2469 hysteresis = <2000>; 2470 type = "hot"; 2471 }; 2472 2473 nspss0_crit: nspss0-crit { 2474 temperature = <110000>; 2475 hysteresis = <0>; 2476 type = "critical"; 2477 }; 2478 }; 2479 }; 2480 2481 nspss1-thermal { 2482 polling-delay-passive = <0>; 2483 polling-delay = <0>; 2484 2485 thermal-sensors = <&tsens1 4>; 2486 2487 trips { 2488 nspss1_alert0: trip-point0 { 2489 temperature = <90000>; 2490 hysteresis = <2000>; 2491 type = "hot"; 2492 }; 2493 2494 nspss1_crit: nspss1-crit { 2495 temperature = <110000>; 2496 hysteresis = <0>; 2497 type = "critical"; 2498 }; 2499 }; 2500 }; 2501 2502 video-thermal { 2503 polling-delay-passive = <0>; 2504 polling-delay = <0>; 2505 2506 thermal-sensors = <&tsens1 5>; 2507 2508 trips { 2509 video_alert0: trip-point0 { 2510 temperature = <90000>; 2511 hysteresis = <2000>; 2512 type = "hot"; 2513 }; 2514 2515 video_crit: video-crit { 2516 temperature = <110000>; 2517 hysteresis = <0>; 2518 type = "critical"; 2519 }; 2520 }; 2521 }; 2522 2523 ddr-thermal { 2524 polling-delay-passive = <0>; 2525 polling-delay = <0>; 2526 2527 thermal-sensors = <&tsens1 6>; 2528 2529 trips { 2530 ddr_alert0: trip-point0 { 2531 temperature = <90000>; 2532 hysteresis = <2000>; 2533 type = "hot"; 2534 }; 2535 2536 ddr_crit: ddr-crit { 2537 temperature = <110000>; 2538 hysteresis = <0>; 2539 type = "critical"; 2540 }; 2541 }; 2542 }; 2543 2544 mdmss0-thermal { 2545 polling-delay-passive = <0>; 2546 polling-delay = <0>; 2547 2548 thermal-sensors = <&tsens1 7>; 2549 2550 trips { 2551 mdmss0_alert0: trip-point0 { 2552 temperature = <90000>; 2553 hysteresis = <2000>; 2554 type = "hot"; 2555 }; 2556 2557 mdmss0_crit: mdmss0-crit { 2558 temperature = <110000>; 2559 hysteresis = <0>; 2560 type = "critical"; 2561 }; 2562 }; 2563 }; 2564 2565 mdmss1-thermal { 2566 polling-delay-passive = <0>; 2567 polling-delay = <0>; 2568 2569 thermal-sensors = <&tsens1 8>; 2570 2571 trips { 2572 mdmss1_alert0: trip-point0 { 2573 temperature = <90000>; 2574 hysteresis = <2000>; 2575 type = "hot"; 2576 }; 2577 2578 mdmss1_crit: mdmss1-crit { 2579 temperature = <110000>; 2580 hysteresis = <0>; 2581 type = "critical"; 2582 }; 2583 }; 2584 }; 2585 2586 mdmss2-thermal { 2587 polling-delay-passive = <0>; 2588 polling-delay = <0>; 2589 2590 thermal-sensors = <&tsens1 9>; 2591 2592 trips { 2593 mdmss2_alert0: trip-point0 { 2594 temperature = <90000>; 2595 hysteresis = <2000>; 2596 type = "hot"; 2597 }; 2598 2599 mdmss2_crit: mdmss2-crit { 2600 temperature = <110000>; 2601 hysteresis = <0>; 2602 type = "critical"; 2603 }; 2604 }; 2605 }; 2606 2607 mdmss3-thermal { 2608 polling-delay-passive = <0>; 2609 polling-delay = <0>; 2610 2611 thermal-sensors = <&tsens1 10>; 2612 2613 trips { 2614 mdmss3_alert0: trip-point0 { 2615 temperature = <90000>; 2616 hysteresis = <2000>; 2617 type = "hot"; 2618 }; 2619 2620 mdmss3_crit: mdmss3-crit { 2621 temperature = <110000>; 2622 hysteresis = <0>; 2623 type = "critical"; 2624 }; 2625 }; 2626 }; 2627 2628 camera0-thermal { 2629 polling-delay-passive = <0>; 2630 polling-delay = <0>; 2631 2632 thermal-sensors = <&tsens1 11>; 2633 2634 trips { 2635 camera0_alert0: trip-point0 { 2636 temperature = <90000>; 2637 hysteresis = <2000>; 2638 type = "hot"; 2639 }; 2640 2641 camera0_crit: camera0-crit { 2642 temperature = <110000>; 2643 hysteresis = <0>; 2644 type = "critical"; 2645 }; 2646 }; 2647 }; 2648 }; 2649 2650 timer { 2651 compatible = "arm,armv8-timer"; 2652 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 2653 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 2654 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 2655 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 2656 }; 2657}; 2658