1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-sc7280.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/soc/qcom,rpmh-rsc.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 chosen { }; 20 21 clocks { 22 xo_board: xo-board { 23 compatible = "fixed-clock"; 24 clock-frequency = <76800000>; 25 #clock-cells = <0>; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 clock-frequency = <32000>; 31 #clock-cells = <0>; 32 }; 33 }; 34 35 reserved-memory { 36 #address-cells = <2>; 37 #size-cells = <2>; 38 ranges; 39 40 aop_mem: memory@80800000 { 41 reg = <0x0 0x80800000 0x0 0x60000>; 42 no-map; 43 }; 44 45 aop_cmd_db_mem: memory@80860000 { 46 reg = <0x0 0x80860000 0x0 0x20000>; 47 compatible = "qcom,cmd-db"; 48 no-map; 49 }; 50 51 cpucp_mem: memory@80b00000 { 52 no-map; 53 reg = <0x0 0x80b00000 0x0 0x100000>; 54 }; 55 }; 56 57 cpus { 58 #address-cells = <2>; 59 #size-cells = <0>; 60 61 CPU0: cpu@0 { 62 device_type = "cpu"; 63 compatible = "arm,kryo"; 64 reg = <0x0 0x0>; 65 enable-method = "psci"; 66 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 67 &LITTLE_CPU_SLEEP_1 68 &CLUSTER_SLEEP_0>; 69 next-level-cache = <&L2_0>; 70 L2_0: l2-cache { 71 compatible = "cache"; 72 next-level-cache = <&L3_0>; 73 L3_0: l3-cache { 74 compatible = "cache"; 75 }; 76 }; 77 }; 78 79 CPU1: cpu@100 { 80 device_type = "cpu"; 81 compatible = "arm,kryo"; 82 reg = <0x0 0x100>; 83 enable-method = "psci"; 84 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 85 &LITTLE_CPU_SLEEP_1 86 &CLUSTER_SLEEP_0>; 87 next-level-cache = <&L2_100>; 88 L2_100: l2-cache { 89 compatible = "cache"; 90 next-level-cache = <&L3_0>; 91 }; 92 }; 93 94 CPU2: cpu@200 { 95 device_type = "cpu"; 96 compatible = "arm,kryo"; 97 reg = <0x0 0x200>; 98 enable-method = "psci"; 99 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 100 &LITTLE_CPU_SLEEP_1 101 &CLUSTER_SLEEP_0>; 102 next-level-cache = <&L2_200>; 103 L2_200: l2-cache { 104 compatible = "cache"; 105 next-level-cache = <&L3_0>; 106 }; 107 }; 108 109 CPU3: cpu@300 { 110 device_type = "cpu"; 111 compatible = "arm,kryo"; 112 reg = <0x0 0x300>; 113 enable-method = "psci"; 114 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 115 &LITTLE_CPU_SLEEP_1 116 &CLUSTER_SLEEP_0>; 117 next-level-cache = <&L2_300>; 118 L2_300: l2-cache { 119 compatible = "cache"; 120 next-level-cache = <&L3_0>; 121 }; 122 }; 123 124 CPU4: cpu@400 { 125 device_type = "cpu"; 126 compatible = "arm,kryo"; 127 reg = <0x0 0x400>; 128 enable-method = "psci"; 129 cpu-idle-states = <&BIG_CPU_SLEEP_0 130 &BIG_CPU_SLEEP_1 131 &CLUSTER_SLEEP_0>; 132 next-level-cache = <&L2_400>; 133 L2_400: l2-cache { 134 compatible = "cache"; 135 next-level-cache = <&L3_0>; 136 }; 137 }; 138 139 CPU5: cpu@500 { 140 device_type = "cpu"; 141 compatible = "arm,kryo"; 142 reg = <0x0 0x500>; 143 enable-method = "psci"; 144 cpu-idle-states = <&BIG_CPU_SLEEP_0 145 &BIG_CPU_SLEEP_1 146 &CLUSTER_SLEEP_0>; 147 next-level-cache = <&L2_500>; 148 L2_500: l2-cache { 149 compatible = "cache"; 150 next-level-cache = <&L3_0>; 151 }; 152 }; 153 154 CPU6: cpu@600 { 155 device_type = "cpu"; 156 compatible = "arm,kryo"; 157 reg = <0x0 0x600>; 158 enable-method = "psci"; 159 cpu-idle-states = <&BIG_CPU_SLEEP_0 160 &BIG_CPU_SLEEP_1 161 &CLUSTER_SLEEP_0>; 162 next-level-cache = <&L2_600>; 163 L2_600: l2-cache { 164 compatible = "cache"; 165 next-level-cache = <&L3_0>; 166 }; 167 }; 168 169 CPU7: cpu@700 { 170 device_type = "cpu"; 171 compatible = "arm,kryo"; 172 reg = <0x0 0x700>; 173 enable-method = "psci"; 174 cpu-idle-states = <&BIG_CPU_SLEEP_0 175 &BIG_CPU_SLEEP_1 176 &CLUSTER_SLEEP_0>; 177 next-level-cache = <&L2_700>; 178 L2_700: l2-cache { 179 compatible = "cache"; 180 next-level-cache = <&L3_0>; 181 }; 182 }; 183 184 idle-states { 185 entry-method = "psci"; 186 187 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 188 compatible = "arm,idle-state"; 189 idle-state-name = "little-power-down"; 190 arm,psci-suspend-param = <0x40000003>; 191 entry-latency-us = <549>; 192 exit-latency-us = <901>; 193 min-residency-us = <1774>; 194 local-timer-stop; 195 }; 196 197 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 198 compatible = "arm,idle-state"; 199 idle-state-name = "little-rail-power-down"; 200 arm,psci-suspend-param = <0x40000004>; 201 entry-latency-us = <702>; 202 exit-latency-us = <915>; 203 min-residency-us = <4001>; 204 local-timer-stop; 205 }; 206 207 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 208 compatible = "arm,idle-state"; 209 idle-state-name = "big-power-down"; 210 arm,psci-suspend-param = <0x40000003>; 211 entry-latency-us = <523>; 212 exit-latency-us = <1244>; 213 min-residency-us = <2207>; 214 local-timer-stop; 215 }; 216 217 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 218 compatible = "arm,idle-state"; 219 idle-state-name = "big-rail-power-down"; 220 arm,psci-suspend-param = <0x40000004>; 221 entry-latency-us = <526>; 222 exit-latency-us = <1854>; 223 min-residency-us = <5555>; 224 local-timer-stop; 225 }; 226 227 CLUSTER_SLEEP_0: cluster-sleep-0 { 228 compatible = "arm,idle-state"; 229 idle-state-name = "cluster-power-down"; 230 arm,psci-suspend-param = <0x40003444>; 231 entry-latency-us = <3263>; 232 exit-latency-us = <6562>; 233 min-residency-us = <9926>; 234 local-timer-stop; 235 }; 236 }; 237 }; 238 239 memory@80000000 { 240 device_type = "memory"; 241 /* We expect the bootloader to fill in the size */ 242 reg = <0 0x80000000 0 0>; 243 }; 244 245 firmware { 246 scm { 247 compatible = "qcom,scm-sc7280", "qcom,scm"; 248 }; 249 }; 250 251 pmu { 252 compatible = "arm,armv8-pmuv3"; 253 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 254 }; 255 256 psci { 257 compatible = "arm,psci-1.0"; 258 method = "smc"; 259 }; 260 261 soc: soc@0 { 262 #address-cells = <2>; 263 #size-cells = <2>; 264 ranges = <0 0 0 0 0x10 0>; 265 dma-ranges = <0 0 0 0 0x10 0>; 266 compatible = "simple-bus"; 267 268 gcc: clock-controller@100000 { 269 compatible = "qcom,gcc-sc7280"; 270 reg = <0 0x00100000 0 0x1f0000>; 271 clocks = <&rpmhcc RPMH_CXO_CLK>, 272 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 273 <0>, <0>, <0>, <0>, <0>, <0>; 274 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 275 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 276 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 277 "ufs_phy_tx_symbol_0_clk", 278 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 279 #clock-cells = <1>; 280 #reset-cells = <1>; 281 #power-domain-cells = <1>; 282 }; 283 284 qupv3_id_0: geniqup@9c0000 { 285 compatible = "qcom,geni-se-qup"; 286 reg = <0 0x009c0000 0 0x2000>; 287 clock-names = "m-ahb", "s-ahb"; 288 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 289 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 290 #address-cells = <2>; 291 #size-cells = <2>; 292 ranges; 293 status = "disabled"; 294 295 uart5: serial@994000 { 296 compatible = "qcom,geni-debug-uart"; 297 reg = <0 0x00994000 0 0x4000>; 298 clock-names = "se"; 299 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 300 pinctrl-names = "default"; 301 pinctrl-0 = <&qup_uart5_default>; 302 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 303 status = "disabled"; 304 }; 305 }; 306 307 pdc: interrupt-controller@b220000 { 308 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 309 reg = <0 0x0b220000 0 0x30000>; 310 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 311 <55 306 4>, <59 312 3>, <62 374 2>, 312 <64 434 2>, <66 438 3>, <69 86 1>, 313 <70 520 54>, <124 609 31>, <155 63 1>, 314 <156 716 12>; 315 #interrupt-cells = <2>; 316 interrupt-parent = <&intc>; 317 interrupt-controller; 318 }; 319 320 spmi_bus: spmi@c440000 { 321 compatible = "qcom,spmi-pmic-arb"; 322 reg = <0 0x0c440000 0 0x1100>, 323 <0 0x0c600000 0 0x2000000>, 324 <0 0x0e600000 0 0x100000>, 325 <0 0x0e700000 0 0xa0000>, 326 <0 0x0c40a000 0 0x26000>; 327 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 328 interrupt-names = "periph_irq"; 329 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 330 qcom,ee = <0>; 331 qcom,channel = <0>; 332 #address-cells = <1>; 333 #size-cells = <1>; 334 interrupt-controller; 335 #interrupt-cells = <4>; 336 }; 337 338 tlmm: pinctrl@f100000 { 339 compatible = "qcom,sc7280-pinctrl"; 340 reg = <0 0x0f100000 0 0x300000>; 341 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 342 gpio-controller; 343 #gpio-cells = <2>; 344 interrupt-controller; 345 #interrupt-cells = <2>; 346 gpio-ranges = <&tlmm 0 0 175>; 347 wakeup-parent = <&pdc>; 348 349 qup_uart5_default: qup-uart5-default { 350 pins = "gpio46", "gpio47"; 351 function = "qup13"; 352 }; 353 }; 354 355 apps_smmu: iommu@15000000 { 356 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 357 reg = <0 0x15000000 0 0x100000>; 358 #iommu-cells = <2>; 359 #global-interrupts = <1>; 360 dma-coherent; 361 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 369 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 395 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 442 }; 443 444 intc: interrupt-controller@17a00000 { 445 compatible = "arm,gic-v3"; 446 #address-cells = <2>; 447 #size-cells = <2>; 448 ranges; 449 #interrupt-cells = <3>; 450 interrupt-controller; 451 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 452 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 453 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 454 455 gic-its@17a40000 { 456 compatible = "arm,gic-v3-its"; 457 msi-controller; 458 #msi-cells = <1>; 459 reg = <0 0x17a40000 0 0x20000>; 460 status = "disabled"; 461 }; 462 }; 463 464 watchdog@17c10000 { 465 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 466 reg = <0 0x17c10000 0 0x1000>; 467 clocks = <&sleep_clk>; 468 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 469 }; 470 471 timer@17c20000 { 472 #address-cells = <2>; 473 #size-cells = <2>; 474 ranges; 475 compatible = "arm,armv7-timer-mem"; 476 reg = <0 0x17c20000 0 0x1000>; 477 478 frame@17c21000 { 479 frame-number = <0>; 480 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 482 reg = <0 0x17c21000 0 0x1000>, 483 <0 0x17c22000 0 0x1000>; 484 }; 485 486 frame@17c23000 { 487 frame-number = <1>; 488 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 489 reg = <0 0x17c23000 0 0x1000>; 490 status = "disabled"; 491 }; 492 493 frame@17c25000 { 494 frame-number = <2>; 495 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 496 reg = <0 0x17c25000 0 0x1000>; 497 status = "disabled"; 498 }; 499 500 frame@17c27000 { 501 frame-number = <3>; 502 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 503 reg = <0 0x17c27000 0 0x1000>; 504 status = "disabled"; 505 }; 506 507 frame@17c29000 { 508 frame-number = <4>; 509 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 510 reg = <0 0x17c29000 0 0x1000>; 511 status = "disabled"; 512 }; 513 514 frame@17c2b000 { 515 frame-number = <5>; 516 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 517 reg = <0 0x17c2b000 0 0x1000>; 518 status = "disabled"; 519 }; 520 521 frame@17c2d000 { 522 frame-number = <6>; 523 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 524 reg = <0 0x17c2d000 0 0x1000>; 525 status = "disabled"; 526 }; 527 }; 528 529 apps_rsc: rsc@18200000 { 530 compatible = "qcom,rpmh-rsc"; 531 reg = <0 0x18200000 0 0x10000>, 532 <0 0x18210000 0 0x10000>, 533 <0 0x18220000 0 0x10000>; 534 reg-names = "drv-0", "drv-1", "drv-2"; 535 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 538 qcom,tcs-offset = <0xd00>; 539 qcom,drv-id = <2>; 540 qcom,tcs-config = <ACTIVE_TCS 2>, 541 <SLEEP_TCS 3>, 542 <WAKE_TCS 3>, 543 <CONTROL_TCS 1>; 544 545 rpmhcc: clock-controller { 546 compatible = "qcom,sc7280-rpmh-clk"; 547 clocks = <&xo_board>; 548 clock-names = "xo"; 549 #clock-cells = <1>; 550 }; 551 }; 552 }; 553 554 timer { 555 compatible = "arm,armv8-timer"; 556 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 557 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 558 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 559 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 560 }; 561}; 562