1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-sc7280.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/soc/qcom,rpmh-rsc.h> 13 14/ { 15 interrupt-parent = <&intc>; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 chosen { }; 21 22 clocks { 23 xo_board: xo-board { 24 compatible = "fixed-clock"; 25 clock-frequency = <76800000>; 26 #clock-cells = <0>; 27 }; 28 29 sleep_clk: sleep-clk { 30 compatible = "fixed-clock"; 31 clock-frequency = <32000>; 32 #clock-cells = <0>; 33 }; 34 }; 35 36 reserved-memory { 37 #address-cells = <2>; 38 #size-cells = <2>; 39 ranges; 40 41 aop_mem: memory@80800000 { 42 reg = <0x0 0x80800000 0x0 0x60000>; 43 no-map; 44 }; 45 46 aop_cmd_db_mem: memory@80860000 { 47 reg = <0x0 0x80860000 0x0 0x20000>; 48 compatible = "qcom,cmd-db"; 49 no-map; 50 }; 51 52 cpucp_mem: memory@80b00000 { 53 no-map; 54 reg = <0x0 0x80b00000 0x0 0x100000>; 55 }; 56 }; 57 58 cpus { 59 #address-cells = <2>; 60 #size-cells = <0>; 61 62 CPU0: cpu@0 { 63 device_type = "cpu"; 64 compatible = "arm,kryo"; 65 reg = <0x0 0x0>; 66 enable-method = "psci"; 67 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 68 &LITTLE_CPU_SLEEP_1 69 &CLUSTER_SLEEP_0>; 70 next-level-cache = <&L2_0>; 71 L2_0: l2-cache { 72 compatible = "cache"; 73 next-level-cache = <&L3_0>; 74 L3_0: l3-cache { 75 compatible = "cache"; 76 }; 77 }; 78 }; 79 80 CPU1: cpu@100 { 81 device_type = "cpu"; 82 compatible = "arm,kryo"; 83 reg = <0x0 0x100>; 84 enable-method = "psci"; 85 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 86 &LITTLE_CPU_SLEEP_1 87 &CLUSTER_SLEEP_0>; 88 next-level-cache = <&L2_100>; 89 L2_100: l2-cache { 90 compatible = "cache"; 91 next-level-cache = <&L3_0>; 92 }; 93 }; 94 95 CPU2: cpu@200 { 96 device_type = "cpu"; 97 compatible = "arm,kryo"; 98 reg = <0x0 0x200>; 99 enable-method = "psci"; 100 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 101 &LITTLE_CPU_SLEEP_1 102 &CLUSTER_SLEEP_0>; 103 next-level-cache = <&L2_200>; 104 L2_200: l2-cache { 105 compatible = "cache"; 106 next-level-cache = <&L3_0>; 107 }; 108 }; 109 110 CPU3: cpu@300 { 111 device_type = "cpu"; 112 compatible = "arm,kryo"; 113 reg = <0x0 0x300>; 114 enable-method = "psci"; 115 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 116 &LITTLE_CPU_SLEEP_1 117 &CLUSTER_SLEEP_0>; 118 next-level-cache = <&L2_300>; 119 L2_300: l2-cache { 120 compatible = "cache"; 121 next-level-cache = <&L3_0>; 122 }; 123 }; 124 125 CPU4: cpu@400 { 126 device_type = "cpu"; 127 compatible = "arm,kryo"; 128 reg = <0x0 0x400>; 129 enable-method = "psci"; 130 cpu-idle-states = <&BIG_CPU_SLEEP_0 131 &BIG_CPU_SLEEP_1 132 &CLUSTER_SLEEP_0>; 133 next-level-cache = <&L2_400>; 134 L2_400: l2-cache { 135 compatible = "cache"; 136 next-level-cache = <&L3_0>; 137 }; 138 }; 139 140 CPU5: cpu@500 { 141 device_type = "cpu"; 142 compatible = "arm,kryo"; 143 reg = <0x0 0x500>; 144 enable-method = "psci"; 145 cpu-idle-states = <&BIG_CPU_SLEEP_0 146 &BIG_CPU_SLEEP_1 147 &CLUSTER_SLEEP_0>; 148 next-level-cache = <&L2_500>; 149 L2_500: l2-cache { 150 compatible = "cache"; 151 next-level-cache = <&L3_0>; 152 }; 153 }; 154 155 CPU6: cpu@600 { 156 device_type = "cpu"; 157 compatible = "arm,kryo"; 158 reg = <0x0 0x600>; 159 enable-method = "psci"; 160 cpu-idle-states = <&BIG_CPU_SLEEP_0 161 &BIG_CPU_SLEEP_1 162 &CLUSTER_SLEEP_0>; 163 next-level-cache = <&L2_600>; 164 L2_600: l2-cache { 165 compatible = "cache"; 166 next-level-cache = <&L3_0>; 167 }; 168 }; 169 170 CPU7: cpu@700 { 171 device_type = "cpu"; 172 compatible = "arm,kryo"; 173 reg = <0x0 0x700>; 174 enable-method = "psci"; 175 cpu-idle-states = <&BIG_CPU_SLEEP_0 176 &BIG_CPU_SLEEP_1 177 &CLUSTER_SLEEP_0>; 178 next-level-cache = <&L2_700>; 179 L2_700: l2-cache { 180 compatible = "cache"; 181 next-level-cache = <&L3_0>; 182 }; 183 }; 184 185 idle-states { 186 entry-method = "psci"; 187 188 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 189 compatible = "arm,idle-state"; 190 idle-state-name = "little-power-down"; 191 arm,psci-suspend-param = <0x40000003>; 192 entry-latency-us = <549>; 193 exit-latency-us = <901>; 194 min-residency-us = <1774>; 195 local-timer-stop; 196 }; 197 198 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 199 compatible = "arm,idle-state"; 200 idle-state-name = "little-rail-power-down"; 201 arm,psci-suspend-param = <0x40000004>; 202 entry-latency-us = <702>; 203 exit-latency-us = <915>; 204 min-residency-us = <4001>; 205 local-timer-stop; 206 }; 207 208 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 209 compatible = "arm,idle-state"; 210 idle-state-name = "big-power-down"; 211 arm,psci-suspend-param = <0x40000003>; 212 entry-latency-us = <523>; 213 exit-latency-us = <1244>; 214 min-residency-us = <2207>; 215 local-timer-stop; 216 }; 217 218 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 219 compatible = "arm,idle-state"; 220 idle-state-name = "big-rail-power-down"; 221 arm,psci-suspend-param = <0x40000004>; 222 entry-latency-us = <526>; 223 exit-latency-us = <1854>; 224 min-residency-us = <5555>; 225 local-timer-stop; 226 }; 227 228 CLUSTER_SLEEP_0: cluster-sleep-0 { 229 compatible = "arm,idle-state"; 230 idle-state-name = "cluster-power-down"; 231 arm,psci-suspend-param = <0x40003444>; 232 entry-latency-us = <3263>; 233 exit-latency-us = <6562>; 234 min-residency-us = <9926>; 235 local-timer-stop; 236 }; 237 }; 238 }; 239 240 memory@80000000 { 241 device_type = "memory"; 242 /* We expect the bootloader to fill in the size */ 243 reg = <0 0x80000000 0 0>; 244 }; 245 246 firmware { 247 scm { 248 compatible = "qcom,scm-sc7280", "qcom,scm"; 249 }; 250 }; 251 252 pmu { 253 compatible = "arm,armv8-pmuv3"; 254 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 255 }; 256 257 psci { 258 compatible = "arm,psci-1.0"; 259 method = "smc"; 260 }; 261 262 soc: soc@0 { 263 #address-cells = <2>; 264 #size-cells = <2>; 265 ranges = <0 0 0 0 0x10 0>; 266 dma-ranges = <0 0 0 0 0x10 0>; 267 compatible = "simple-bus"; 268 269 gcc: clock-controller@100000 { 270 compatible = "qcom,gcc-sc7280"; 271 reg = <0 0x00100000 0 0x1f0000>; 272 clocks = <&rpmhcc RPMH_CXO_CLK>, 273 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 274 <0>, <0>, <0>, <0>, <0>, <0>; 275 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 276 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 277 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 278 "ufs_phy_tx_symbol_0_clk", 279 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 280 #clock-cells = <1>; 281 #reset-cells = <1>; 282 #power-domain-cells = <1>; 283 }; 284 285 qupv3_id_0: geniqup@9c0000 { 286 compatible = "qcom,geni-se-qup"; 287 reg = <0 0x009c0000 0 0x2000>; 288 clock-names = "m-ahb", "s-ahb"; 289 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 290 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 291 #address-cells = <2>; 292 #size-cells = <2>; 293 ranges; 294 status = "disabled"; 295 296 uart5: serial@994000 { 297 compatible = "qcom,geni-debug-uart"; 298 reg = <0 0x00994000 0 0x4000>; 299 clock-names = "se"; 300 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 301 pinctrl-names = "default"; 302 pinctrl-0 = <&qup_uart5_default>; 303 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 304 status = "disabled"; 305 }; 306 }; 307 308 system-cache-controller@9200000 { 309 compatible = "qcom,sc7280-llcc"; 310 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 311 reg-names = "llcc_base", "llcc_broadcast_base"; 312 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 313 }; 314 315 pdc: interrupt-controller@b220000 { 316 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 317 reg = <0 0x0b220000 0 0x30000>; 318 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 319 <55 306 4>, <59 312 3>, <62 374 2>, 320 <64 434 2>, <66 438 3>, <69 86 1>, 321 <70 520 54>, <124 609 31>, <155 63 1>, 322 <156 716 12>; 323 #interrupt-cells = <2>; 324 interrupt-parent = <&intc>; 325 interrupt-controller; 326 }; 327 328 spmi_bus: spmi@c440000 { 329 compatible = "qcom,spmi-pmic-arb"; 330 reg = <0 0x0c440000 0 0x1100>, 331 <0 0x0c600000 0 0x2000000>, 332 <0 0x0e600000 0 0x100000>, 333 <0 0x0e700000 0 0xa0000>, 334 <0 0x0c40a000 0 0x26000>; 335 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 336 interrupt-names = "periph_irq"; 337 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 338 qcom,ee = <0>; 339 qcom,channel = <0>; 340 #address-cells = <1>; 341 #size-cells = <1>; 342 interrupt-controller; 343 #interrupt-cells = <4>; 344 }; 345 346 tlmm: pinctrl@f100000 { 347 compatible = "qcom,sc7280-pinctrl"; 348 reg = <0 0x0f100000 0 0x300000>; 349 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 350 gpio-controller; 351 #gpio-cells = <2>; 352 interrupt-controller; 353 #interrupt-cells = <2>; 354 gpio-ranges = <&tlmm 0 0 175>; 355 wakeup-parent = <&pdc>; 356 357 qup_uart5_default: qup-uart5-default { 358 pins = "gpio46", "gpio47"; 359 function = "qup13"; 360 }; 361 }; 362 363 apps_smmu: iommu@15000000 { 364 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 365 reg = <0 0x15000000 0 0x100000>; 366 #iommu-cells = <2>; 367 #global-interrupts = <1>; 368 dma-coherent; 369 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 395 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 450 }; 451 452 intc: interrupt-controller@17a00000 { 453 compatible = "arm,gic-v3"; 454 #address-cells = <2>; 455 #size-cells = <2>; 456 ranges; 457 #interrupt-cells = <3>; 458 interrupt-controller; 459 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 460 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 461 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 462 463 gic-its@17a40000 { 464 compatible = "arm,gic-v3-its"; 465 msi-controller; 466 #msi-cells = <1>; 467 reg = <0 0x17a40000 0 0x20000>; 468 status = "disabled"; 469 }; 470 }; 471 472 watchdog@17c10000 { 473 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 474 reg = <0 0x17c10000 0 0x1000>; 475 clocks = <&sleep_clk>; 476 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 477 }; 478 479 timer@17c20000 { 480 #address-cells = <2>; 481 #size-cells = <2>; 482 ranges; 483 compatible = "arm,armv7-timer-mem"; 484 reg = <0 0x17c20000 0 0x1000>; 485 486 frame@17c21000 { 487 frame-number = <0>; 488 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 490 reg = <0 0x17c21000 0 0x1000>, 491 <0 0x17c22000 0 0x1000>; 492 }; 493 494 frame@17c23000 { 495 frame-number = <1>; 496 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 497 reg = <0 0x17c23000 0 0x1000>; 498 status = "disabled"; 499 }; 500 501 frame@17c25000 { 502 frame-number = <2>; 503 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 504 reg = <0 0x17c25000 0 0x1000>; 505 status = "disabled"; 506 }; 507 508 frame@17c27000 { 509 frame-number = <3>; 510 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 511 reg = <0 0x17c27000 0 0x1000>; 512 status = "disabled"; 513 }; 514 515 frame@17c29000 { 516 frame-number = <4>; 517 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 518 reg = <0 0x17c29000 0 0x1000>; 519 status = "disabled"; 520 }; 521 522 frame@17c2b000 { 523 frame-number = <5>; 524 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 525 reg = <0 0x17c2b000 0 0x1000>; 526 status = "disabled"; 527 }; 528 529 frame@17c2d000 { 530 frame-number = <6>; 531 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 532 reg = <0 0x17c2d000 0 0x1000>; 533 status = "disabled"; 534 }; 535 }; 536 537 apps_rsc: rsc@18200000 { 538 compatible = "qcom,rpmh-rsc"; 539 reg = <0 0x18200000 0 0x10000>, 540 <0 0x18210000 0 0x10000>, 541 <0 0x18220000 0 0x10000>; 542 reg-names = "drv-0", "drv-1", "drv-2"; 543 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 546 qcom,tcs-offset = <0xd00>; 547 qcom,drv-id = <2>; 548 qcom,tcs-config = <ACTIVE_TCS 2>, 549 <SLEEP_TCS 3>, 550 <WAKE_TCS 3>, 551 <CONTROL_TCS 1>; 552 553 rpmhpd: power-controller { 554 compatible = "qcom,sc7280-rpmhpd"; 555 #power-domain-cells = <1>; 556 operating-points-v2 = <&rpmhpd_opp_table>; 557 558 rpmhpd_opp_table: opp-table { 559 compatible = "operating-points-v2"; 560 561 rpmhpd_opp_ret: opp1 { 562 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 563 }; 564 565 rpmhpd_opp_low_svs: opp2 { 566 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 567 }; 568 569 rpmhpd_opp_svs: opp3 { 570 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 571 }; 572 573 rpmhpd_opp_svs_l1: opp4 { 574 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 575 }; 576 577 rpmhpd_opp_svs_l2: opp5 { 578 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 579 }; 580 581 rpmhpd_opp_nom: opp6 { 582 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 583 }; 584 585 rpmhpd_opp_nom_l1: opp7 { 586 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 587 }; 588 589 rpmhpd_opp_turbo: opp8 { 590 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 591 }; 592 593 rpmhpd_opp_turbo_l1: opp9 { 594 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 595 }; 596 }; 597 }; 598 599 rpmhcc: clock-controller { 600 compatible = "qcom,sc7280-rpmh-clk"; 601 clocks = <&xo_board>; 602 clock-names = "xo"; 603 #clock-cells = <1>; 604 }; 605 }; 606 }; 607 608 timer { 609 compatible = "arm,armv8-timer"; 610 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 611 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 612 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 613 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 614 }; 615}; 616