1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,lpass.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 mmc1 = &sdhc_1; 54 mmc2 = &sdhc_2; 55 spi0 = &spi0; 56 spi1 = &spi1; 57 spi2 = &spi2; 58 spi3 = &spi3; 59 spi4 = &spi4; 60 spi5 = &spi5; 61 spi6 = &spi6; 62 spi7 = &spi7; 63 spi8 = &spi8; 64 spi9 = &spi9; 65 spi10 = &spi10; 66 spi11 = &spi11; 67 spi12 = &spi12; 68 spi13 = &spi13; 69 spi14 = &spi14; 70 spi15 = &spi15; 71 }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 clock-frequency = <76800000>; 77 #clock-cells = <0>; 78 }; 79 80 sleep_clk: sleep-clk { 81 compatible = "fixed-clock"; 82 clock-frequency = <32000>; 83 #clock-cells = <0>; 84 }; 85 }; 86 87 reserved-memory { 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges; 91 92 wlan_ce_mem: memory@4cd000 { 93 no-map; 94 reg = <0x0 0x004cd000 0x0 0x1000>; 95 }; 96 97 hyp_mem: memory@80000000 { 98 reg = <0x0 0x80000000 0x0 0x600000>; 99 no-map; 100 }; 101 102 xbl_mem: memory@80600000 { 103 reg = <0x0 0x80600000 0x0 0x200000>; 104 no-map; 105 }; 106 107 aop_mem: memory@80800000 { 108 reg = <0x0 0x80800000 0x0 0x60000>; 109 no-map; 110 }; 111 112 aop_cmd_db_mem: memory@80860000 { 113 reg = <0x0 0x80860000 0x0 0x20000>; 114 compatible = "qcom,cmd-db"; 115 no-map; 116 }; 117 118 reserved_xbl_uefi_log: memory@80880000 { 119 reg = <0x0 0x80884000 0x0 0x10000>; 120 no-map; 121 }; 122 123 sec_apps_mem: memory@808ff000 { 124 reg = <0x0 0x808ff000 0x0 0x1000>; 125 no-map; 126 }; 127 128 smem_mem: memory@80900000 { 129 reg = <0x0 0x80900000 0x0 0x200000>; 130 no-map; 131 }; 132 133 cpucp_mem: memory@80b00000 { 134 no-map; 135 reg = <0x0 0x80b00000 0x0 0x100000>; 136 }; 137 138 wlan_fw_mem: memory@80c00000 { 139 reg = <0x0 0x80c00000 0x0 0xc00000>; 140 no-map; 141 }; 142 143 video_mem: memory@8b200000 { 144 reg = <0x0 0x8b200000 0x0 0x500000>; 145 no-map; 146 }; 147 148 ipa_fw_mem: memory@8b700000 { 149 reg = <0 0x8b700000 0 0x10000>; 150 no-map; 151 }; 152 153 rmtfs_mem: memory@9c900000 { 154 compatible = "qcom,rmtfs-mem"; 155 reg = <0x0 0x9c900000 0x0 0x280000>; 156 no-map; 157 158 qcom,client-id = <1>; 159 qcom,vmid = <15>; 160 }; 161 }; 162 163 cpus { 164 #address-cells = <2>; 165 #size-cells = <0>; 166 167 CPU0: cpu@0 { 168 device_type = "cpu"; 169 compatible = "qcom,kryo"; 170 reg = <0x0 0x0>; 171 clocks = <&cpufreq_hw 0>; 172 enable-method = "psci"; 173 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 174 &LITTLE_CPU_SLEEP_1 175 &CLUSTER_SLEEP_0>; 176 next-level-cache = <&L2_0>; 177 operating-points-v2 = <&cpu0_opp_table>; 178 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 179 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 180 qcom,freq-domain = <&cpufreq_hw 0>; 181 #cooling-cells = <2>; 182 L2_0: l2-cache { 183 compatible = "cache"; 184 cache-level = <2>; 185 cache-unified; 186 next-level-cache = <&L3_0>; 187 L3_0: l3-cache { 188 compatible = "cache"; 189 cache-level = <3>; 190 cache-unified; 191 }; 192 }; 193 }; 194 195 CPU1: cpu@100 { 196 device_type = "cpu"; 197 compatible = "qcom,kryo"; 198 reg = <0x0 0x100>; 199 clocks = <&cpufreq_hw 0>; 200 enable-method = "psci"; 201 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 202 &LITTLE_CPU_SLEEP_1 203 &CLUSTER_SLEEP_0>; 204 next-level-cache = <&L2_100>; 205 operating-points-v2 = <&cpu0_opp_table>; 206 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 207 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 208 qcom,freq-domain = <&cpufreq_hw 0>; 209 #cooling-cells = <2>; 210 L2_100: l2-cache { 211 compatible = "cache"; 212 cache-level = <2>; 213 cache-unified; 214 next-level-cache = <&L3_0>; 215 }; 216 }; 217 218 CPU2: cpu@200 { 219 device_type = "cpu"; 220 compatible = "qcom,kryo"; 221 reg = <0x0 0x200>; 222 clocks = <&cpufreq_hw 0>; 223 enable-method = "psci"; 224 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 225 &LITTLE_CPU_SLEEP_1 226 &CLUSTER_SLEEP_0>; 227 next-level-cache = <&L2_200>; 228 operating-points-v2 = <&cpu0_opp_table>; 229 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 230 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 231 qcom,freq-domain = <&cpufreq_hw 0>; 232 #cooling-cells = <2>; 233 L2_200: l2-cache { 234 compatible = "cache"; 235 cache-level = <2>; 236 cache-unified; 237 next-level-cache = <&L3_0>; 238 }; 239 }; 240 241 CPU3: cpu@300 { 242 device_type = "cpu"; 243 compatible = "qcom,kryo"; 244 reg = <0x0 0x300>; 245 clocks = <&cpufreq_hw 0>; 246 enable-method = "psci"; 247 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 248 &LITTLE_CPU_SLEEP_1 249 &CLUSTER_SLEEP_0>; 250 next-level-cache = <&L2_300>; 251 operating-points-v2 = <&cpu0_opp_table>; 252 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 253 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 254 qcom,freq-domain = <&cpufreq_hw 0>; 255 #cooling-cells = <2>; 256 L2_300: l2-cache { 257 compatible = "cache"; 258 cache-level = <2>; 259 cache-unified; 260 next-level-cache = <&L3_0>; 261 }; 262 }; 263 264 CPU4: cpu@400 { 265 device_type = "cpu"; 266 compatible = "qcom,kryo"; 267 reg = <0x0 0x400>; 268 clocks = <&cpufreq_hw 1>; 269 enable-method = "psci"; 270 cpu-idle-states = <&BIG_CPU_SLEEP_0 271 &BIG_CPU_SLEEP_1 272 &CLUSTER_SLEEP_0>; 273 next-level-cache = <&L2_400>; 274 operating-points-v2 = <&cpu4_opp_table>; 275 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 276 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 277 qcom,freq-domain = <&cpufreq_hw 1>; 278 #cooling-cells = <2>; 279 L2_400: l2-cache { 280 compatible = "cache"; 281 cache-level = <2>; 282 cache-unified; 283 next-level-cache = <&L3_0>; 284 }; 285 }; 286 287 CPU5: cpu@500 { 288 device_type = "cpu"; 289 compatible = "qcom,kryo"; 290 reg = <0x0 0x500>; 291 clocks = <&cpufreq_hw 1>; 292 enable-method = "psci"; 293 cpu-idle-states = <&BIG_CPU_SLEEP_0 294 &BIG_CPU_SLEEP_1 295 &CLUSTER_SLEEP_0>; 296 next-level-cache = <&L2_500>; 297 operating-points-v2 = <&cpu4_opp_table>; 298 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 299 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 300 qcom,freq-domain = <&cpufreq_hw 1>; 301 #cooling-cells = <2>; 302 L2_500: l2-cache { 303 compatible = "cache"; 304 cache-level = <2>; 305 cache-unified; 306 next-level-cache = <&L3_0>; 307 }; 308 }; 309 310 CPU6: cpu@600 { 311 device_type = "cpu"; 312 compatible = "qcom,kryo"; 313 reg = <0x0 0x600>; 314 clocks = <&cpufreq_hw 1>; 315 enable-method = "psci"; 316 cpu-idle-states = <&BIG_CPU_SLEEP_0 317 &BIG_CPU_SLEEP_1 318 &CLUSTER_SLEEP_0>; 319 next-level-cache = <&L2_600>; 320 operating-points-v2 = <&cpu4_opp_table>; 321 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 322 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 323 qcom,freq-domain = <&cpufreq_hw 1>; 324 #cooling-cells = <2>; 325 L2_600: l2-cache { 326 compatible = "cache"; 327 cache-level = <2>; 328 cache-unified; 329 next-level-cache = <&L3_0>; 330 }; 331 }; 332 333 CPU7: cpu@700 { 334 device_type = "cpu"; 335 compatible = "qcom,kryo"; 336 reg = <0x0 0x700>; 337 clocks = <&cpufreq_hw 2>; 338 enable-method = "psci"; 339 cpu-idle-states = <&BIG_CPU_SLEEP_0 340 &BIG_CPU_SLEEP_1 341 &CLUSTER_SLEEP_0>; 342 next-level-cache = <&L2_700>; 343 operating-points-v2 = <&cpu7_opp_table>; 344 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 345 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 346 qcom,freq-domain = <&cpufreq_hw 2>; 347 #cooling-cells = <2>; 348 L2_700: l2-cache { 349 compatible = "cache"; 350 cache-level = <2>; 351 cache-unified; 352 next-level-cache = <&L3_0>; 353 }; 354 }; 355 356 cpu-map { 357 cluster0 { 358 core0 { 359 cpu = <&CPU0>; 360 }; 361 362 core1 { 363 cpu = <&CPU1>; 364 }; 365 366 core2 { 367 cpu = <&CPU2>; 368 }; 369 370 core3 { 371 cpu = <&CPU3>; 372 }; 373 374 core4 { 375 cpu = <&CPU4>; 376 }; 377 378 core5 { 379 cpu = <&CPU5>; 380 }; 381 382 core6 { 383 cpu = <&CPU6>; 384 }; 385 386 core7 { 387 cpu = <&CPU7>; 388 }; 389 }; 390 }; 391 392 idle-states { 393 entry-method = "psci"; 394 395 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 396 compatible = "arm,idle-state"; 397 idle-state-name = "little-power-down"; 398 arm,psci-suspend-param = <0x40000003>; 399 entry-latency-us = <549>; 400 exit-latency-us = <901>; 401 min-residency-us = <1774>; 402 local-timer-stop; 403 }; 404 405 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 406 compatible = "arm,idle-state"; 407 idle-state-name = "little-rail-power-down"; 408 arm,psci-suspend-param = <0x40000004>; 409 entry-latency-us = <702>; 410 exit-latency-us = <915>; 411 min-residency-us = <4001>; 412 local-timer-stop; 413 }; 414 415 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 416 compatible = "arm,idle-state"; 417 idle-state-name = "big-power-down"; 418 arm,psci-suspend-param = <0x40000003>; 419 entry-latency-us = <523>; 420 exit-latency-us = <1244>; 421 min-residency-us = <2207>; 422 local-timer-stop; 423 }; 424 425 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 426 compatible = "arm,idle-state"; 427 idle-state-name = "big-rail-power-down"; 428 arm,psci-suspend-param = <0x40000004>; 429 entry-latency-us = <526>; 430 exit-latency-us = <1854>; 431 min-residency-us = <5555>; 432 local-timer-stop; 433 }; 434 435 CLUSTER_SLEEP_0: cluster-sleep-0 { 436 compatible = "arm,idle-state"; 437 idle-state-name = "cluster-power-down"; 438 arm,psci-suspend-param = <0x40003444>; 439 entry-latency-us = <3263>; 440 exit-latency-us = <6562>; 441 min-residency-us = <9926>; 442 local-timer-stop; 443 }; 444 }; 445 }; 446 447 cpu0_opp_table: opp-table-cpu0 { 448 compatible = "operating-points-v2"; 449 opp-shared; 450 451 cpu0_opp_300mhz: opp-300000000 { 452 opp-hz = /bits/ 64 <300000000>; 453 opp-peak-kBps = <800000 9600000>; 454 }; 455 456 cpu0_opp_691mhz: opp-691200000 { 457 opp-hz = /bits/ 64 <691200000>; 458 opp-peak-kBps = <800000 17817600>; 459 }; 460 461 cpu0_opp_806mhz: opp-806400000 { 462 opp-hz = /bits/ 64 <806400000>; 463 opp-peak-kBps = <800000 20889600>; 464 }; 465 466 cpu0_opp_941mhz: opp-940800000 { 467 opp-hz = /bits/ 64 <940800000>; 468 opp-peak-kBps = <1804000 24576000>; 469 }; 470 471 cpu0_opp_1152mhz: opp-1152000000 { 472 opp-hz = /bits/ 64 <1152000000>; 473 opp-peak-kBps = <2188000 27033600>; 474 }; 475 476 cpu0_opp_1325mhz: opp-1324800000 { 477 opp-hz = /bits/ 64 <1324800000>; 478 opp-peak-kBps = <2188000 33792000>; 479 }; 480 481 cpu0_opp_1517mhz: opp-1516800000 { 482 opp-hz = /bits/ 64 <1516800000>; 483 opp-peak-kBps = <3072000 38092800>; 484 }; 485 486 cpu0_opp_1651mhz: opp-1651200000 { 487 opp-hz = /bits/ 64 <1651200000>; 488 opp-peak-kBps = <3072000 41779200>; 489 }; 490 491 cpu0_opp_1805mhz: opp-1804800000 { 492 opp-hz = /bits/ 64 <1804800000>; 493 opp-peak-kBps = <4068000 48537600>; 494 }; 495 496 cpu0_opp_1958mhz: opp-1958400000 { 497 opp-hz = /bits/ 64 <1958400000>; 498 opp-peak-kBps = <4068000 48537600>; 499 }; 500 501 cpu0_opp_2016mhz: opp-2016000000 { 502 opp-hz = /bits/ 64 <2016000000>; 503 opp-peak-kBps = <6220000 48537600>; 504 }; 505 }; 506 507 cpu4_opp_table: opp-table-cpu4 { 508 compatible = "operating-points-v2"; 509 opp-shared; 510 511 cpu4_opp_691mhz: opp-691200000 { 512 opp-hz = /bits/ 64 <691200000>; 513 opp-peak-kBps = <1804000 9600000>; 514 }; 515 516 cpu4_opp_941mhz: opp-940800000 { 517 opp-hz = /bits/ 64 <940800000>; 518 opp-peak-kBps = <2188000 17817600>; 519 }; 520 521 cpu4_opp_1229mhz: opp-1228800000 { 522 opp-hz = /bits/ 64 <1228800000>; 523 opp-peak-kBps = <4068000 24576000>; 524 }; 525 526 cpu4_opp_1344mhz: opp-1344000000 { 527 opp-hz = /bits/ 64 <1344000000>; 528 opp-peak-kBps = <4068000 24576000>; 529 }; 530 531 cpu4_opp_1517mhz: opp-1516800000 { 532 opp-hz = /bits/ 64 <1516800000>; 533 opp-peak-kBps = <4068000 24576000>; 534 }; 535 536 cpu4_opp_1651mhz: opp-1651200000 { 537 opp-hz = /bits/ 64 <1651200000>; 538 opp-peak-kBps = <6220000 38092800>; 539 }; 540 541 cpu4_opp_1901mhz: opp-1900800000 { 542 opp-hz = /bits/ 64 <1900800000>; 543 opp-peak-kBps = <6220000 44851200>; 544 }; 545 546 cpu4_opp_2054mhz: opp-2054400000 { 547 opp-hz = /bits/ 64 <2054400000>; 548 opp-peak-kBps = <6220000 44851200>; 549 }; 550 551 cpu4_opp_2112mhz: opp-2112000000 { 552 opp-hz = /bits/ 64 <2112000000>; 553 opp-peak-kBps = <6220000 44851200>; 554 }; 555 556 cpu4_opp_2131mhz: opp-2131200000 { 557 opp-hz = /bits/ 64 <2131200000>; 558 opp-peak-kBps = <6220000 44851200>; 559 }; 560 561 cpu4_opp_2208mhz: opp-2208000000 { 562 opp-hz = /bits/ 64 <2208000000>; 563 opp-peak-kBps = <6220000 44851200>; 564 }; 565 566 cpu4_opp_2400mhz: opp-2400000000 { 567 opp-hz = /bits/ 64 <2400000000>; 568 opp-peak-kBps = <8532000 48537600>; 569 }; 570 571 cpu4_opp_2611mhz: opp-2611200000 { 572 opp-hz = /bits/ 64 <2611200000>; 573 opp-peak-kBps = <8532000 48537600>; 574 }; 575 }; 576 577 cpu7_opp_table: opp-table-cpu7 { 578 compatible = "operating-points-v2"; 579 opp-shared; 580 581 cpu7_opp_806mhz: opp-806400000 { 582 opp-hz = /bits/ 64 <806400000>; 583 opp-peak-kBps = <1804000 9600000>; 584 }; 585 586 cpu7_opp_1056mhz: opp-1056000000 { 587 opp-hz = /bits/ 64 <1056000000>; 588 opp-peak-kBps = <2188000 17817600>; 589 }; 590 591 cpu7_opp_1325mhz: opp-1324800000 { 592 opp-hz = /bits/ 64 <1324800000>; 593 opp-peak-kBps = <4068000 24576000>; 594 }; 595 596 cpu7_opp_1517mhz: opp-1516800000 { 597 opp-hz = /bits/ 64 <1516800000>; 598 opp-peak-kBps = <4068000 24576000>; 599 }; 600 601 cpu7_opp_1766mhz: opp-1766400000 { 602 opp-hz = /bits/ 64 <1766400000>; 603 opp-peak-kBps = <6220000 38092800>; 604 }; 605 606 cpu7_opp_1862mhz: opp-1862400000 { 607 opp-hz = /bits/ 64 <1862400000>; 608 opp-peak-kBps = <6220000 38092800>; 609 }; 610 611 cpu7_opp_2035mhz: opp-2035200000 { 612 opp-hz = /bits/ 64 <2035200000>; 613 opp-peak-kBps = <6220000 38092800>; 614 }; 615 616 cpu7_opp_2112mhz: opp-2112000000 { 617 opp-hz = /bits/ 64 <2112000000>; 618 opp-peak-kBps = <6220000 44851200>; 619 }; 620 621 cpu7_opp_2208mhz: opp-2208000000 { 622 opp-hz = /bits/ 64 <2208000000>; 623 opp-peak-kBps = <6220000 44851200>; 624 }; 625 626 cpu7_opp_2381mhz: opp-2380800000 { 627 opp-hz = /bits/ 64 <2380800000>; 628 opp-peak-kBps = <6832000 44851200>; 629 }; 630 631 cpu7_opp_2400mhz: opp-2400000000 { 632 opp-hz = /bits/ 64 <2400000000>; 633 opp-peak-kBps = <8532000 48537600>; 634 }; 635 636 cpu7_opp_2515mhz: opp-2515200000 { 637 opp-hz = /bits/ 64 <2515200000>; 638 opp-peak-kBps = <8532000 48537600>; 639 }; 640 641 cpu7_opp_2707mhz: opp-2707200000 { 642 opp-hz = /bits/ 64 <2707200000>; 643 opp-peak-kBps = <8532000 48537600>; 644 }; 645 646 cpu7_opp_3014mhz: opp-3014400000 { 647 opp-hz = /bits/ 64 <3014400000>; 648 opp-peak-kBps = <8532000 48537600>; 649 }; 650 }; 651 652 memory@80000000 { 653 device_type = "memory"; 654 /* We expect the bootloader to fill in the size */ 655 reg = <0 0x80000000 0 0>; 656 }; 657 658 firmware { 659 scm: scm { 660 compatible = "qcom,scm-sc7280", "qcom,scm"; 661 }; 662 }; 663 664 clk_virt: interconnect { 665 compatible = "qcom,sc7280-clk-virt"; 666 #interconnect-cells = <2>; 667 qcom,bcm-voters = <&apps_bcm_voter>; 668 }; 669 670 smem { 671 compatible = "qcom,smem"; 672 memory-region = <&smem_mem>; 673 hwlocks = <&tcsr_mutex 3>; 674 }; 675 676 smp2p-adsp { 677 compatible = "qcom,smp2p"; 678 qcom,smem = <443>, <429>; 679 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 680 IPCC_MPROC_SIGNAL_SMP2P 681 IRQ_TYPE_EDGE_RISING>; 682 mboxes = <&ipcc IPCC_CLIENT_LPASS 683 IPCC_MPROC_SIGNAL_SMP2P>; 684 685 qcom,local-pid = <0>; 686 qcom,remote-pid = <2>; 687 688 adsp_smp2p_out: master-kernel { 689 qcom,entry-name = "master-kernel"; 690 #qcom,smem-state-cells = <1>; 691 }; 692 693 adsp_smp2p_in: slave-kernel { 694 qcom,entry-name = "slave-kernel"; 695 interrupt-controller; 696 #interrupt-cells = <2>; 697 }; 698 }; 699 700 smp2p-cdsp { 701 compatible = "qcom,smp2p"; 702 qcom,smem = <94>, <432>; 703 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 704 IPCC_MPROC_SIGNAL_SMP2P 705 IRQ_TYPE_EDGE_RISING>; 706 mboxes = <&ipcc IPCC_CLIENT_CDSP 707 IPCC_MPROC_SIGNAL_SMP2P>; 708 709 qcom,local-pid = <0>; 710 qcom,remote-pid = <5>; 711 712 cdsp_smp2p_out: master-kernel { 713 qcom,entry-name = "master-kernel"; 714 #qcom,smem-state-cells = <1>; 715 }; 716 717 cdsp_smp2p_in: slave-kernel { 718 qcom,entry-name = "slave-kernel"; 719 interrupt-controller; 720 #interrupt-cells = <2>; 721 }; 722 }; 723 724 smp2p-mpss { 725 compatible = "qcom,smp2p"; 726 qcom,smem = <435>, <428>; 727 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 728 IPCC_MPROC_SIGNAL_SMP2P 729 IRQ_TYPE_EDGE_RISING>; 730 mboxes = <&ipcc IPCC_CLIENT_MPSS 731 IPCC_MPROC_SIGNAL_SMP2P>; 732 733 qcom,local-pid = <0>; 734 qcom,remote-pid = <1>; 735 736 modem_smp2p_out: master-kernel { 737 qcom,entry-name = "master-kernel"; 738 #qcom,smem-state-cells = <1>; 739 }; 740 741 modem_smp2p_in: slave-kernel { 742 qcom,entry-name = "slave-kernel"; 743 interrupt-controller; 744 #interrupt-cells = <2>; 745 }; 746 747 ipa_smp2p_out: ipa-ap-to-modem { 748 qcom,entry-name = "ipa"; 749 #qcom,smem-state-cells = <1>; 750 }; 751 752 ipa_smp2p_in: ipa-modem-to-ap { 753 qcom,entry-name = "ipa"; 754 interrupt-controller; 755 #interrupt-cells = <2>; 756 }; 757 }; 758 759 smp2p-wpss { 760 compatible = "qcom,smp2p"; 761 qcom,smem = <617>, <616>; 762 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 763 IPCC_MPROC_SIGNAL_SMP2P 764 IRQ_TYPE_EDGE_RISING>; 765 mboxes = <&ipcc IPCC_CLIENT_WPSS 766 IPCC_MPROC_SIGNAL_SMP2P>; 767 768 qcom,local-pid = <0>; 769 qcom,remote-pid = <13>; 770 771 wpss_smp2p_out: master-kernel { 772 qcom,entry-name = "master-kernel"; 773 #qcom,smem-state-cells = <1>; 774 }; 775 776 wpss_smp2p_in: slave-kernel { 777 qcom,entry-name = "slave-kernel"; 778 interrupt-controller; 779 #interrupt-cells = <2>; 780 }; 781 782 wlan_smp2p_out: wlan-ap-to-wpss { 783 qcom,entry-name = "wlan"; 784 #qcom,smem-state-cells = <1>; 785 }; 786 787 wlan_smp2p_in: wlan-wpss-to-ap { 788 qcom,entry-name = "wlan"; 789 interrupt-controller; 790 #interrupt-cells = <2>; 791 }; 792 }; 793 794 pmu { 795 compatible = "arm,armv8-pmuv3"; 796 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 797 }; 798 799 psci { 800 compatible = "arm,psci-1.0"; 801 method = "smc"; 802 }; 803 804 qspi_opp_table: opp-table-qspi { 805 compatible = "operating-points-v2"; 806 807 opp-75000000 { 808 opp-hz = /bits/ 64 <75000000>; 809 required-opps = <&rpmhpd_opp_low_svs>; 810 }; 811 812 opp-150000000 { 813 opp-hz = /bits/ 64 <150000000>; 814 required-opps = <&rpmhpd_opp_svs>; 815 }; 816 817 opp-200000000 { 818 opp-hz = /bits/ 64 <200000000>; 819 required-opps = <&rpmhpd_opp_svs_l1>; 820 }; 821 822 opp-300000000 { 823 opp-hz = /bits/ 64 <300000000>; 824 required-opps = <&rpmhpd_opp_nom>; 825 }; 826 }; 827 828 qup_opp_table: opp-table-qup { 829 compatible = "operating-points-v2"; 830 831 opp-75000000 { 832 opp-hz = /bits/ 64 <75000000>; 833 required-opps = <&rpmhpd_opp_low_svs>; 834 }; 835 836 opp-100000000 { 837 opp-hz = /bits/ 64 <100000000>; 838 required-opps = <&rpmhpd_opp_svs>; 839 }; 840 841 opp-128000000 { 842 opp-hz = /bits/ 64 <128000000>; 843 required-opps = <&rpmhpd_opp_nom>; 844 }; 845 }; 846 847 soc: soc@0 { 848 #address-cells = <2>; 849 #size-cells = <2>; 850 ranges = <0 0 0 0 0x10 0>; 851 dma-ranges = <0 0 0 0 0x10 0>; 852 compatible = "simple-bus"; 853 854 gcc: clock-controller@100000 { 855 compatible = "qcom,gcc-sc7280"; 856 reg = <0 0x00100000 0 0x1f0000>; 857 clocks = <&rpmhcc RPMH_CXO_CLK>, 858 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 859 <0>, <&pcie1_lane>, 860 <0>, <0>, <0>, 861 <&usb_1_ssphy>; 862 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 863 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 864 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 865 "ufs_phy_tx_symbol_0_clk", 866 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 867 #clock-cells = <1>; 868 #reset-cells = <1>; 869 #power-domain-cells = <1>; 870 power-domains = <&rpmhpd SC7280_CX>; 871 }; 872 873 ipcc: mailbox@408000 { 874 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 875 reg = <0 0x00408000 0 0x1000>; 876 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 877 interrupt-controller; 878 #interrupt-cells = <3>; 879 #mbox-cells = <2>; 880 }; 881 882 qfprom: efuse@784000 { 883 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 884 reg = <0 0x00784000 0 0xa20>, 885 <0 0x00780000 0 0xa20>, 886 <0 0x00782000 0 0x120>, 887 <0 0x00786000 0 0x1fff>; 888 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 889 clock-names = "core"; 890 power-domains = <&rpmhpd SC7280_MX>; 891 #address-cells = <1>; 892 #size-cells = <1>; 893 894 gpu_speed_bin: gpu_speed_bin@1e9 { 895 reg = <0x1e9 0x2>; 896 bits = <5 8>; 897 }; 898 }; 899 900 sdhc_1: mmc@7c4000 { 901 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 902 pinctrl-names = "default", "sleep"; 903 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 904 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 905 status = "disabled"; 906 907 reg = <0 0x007c4000 0 0x1000>, 908 <0 0x007c5000 0 0x1000>; 909 reg-names = "hc", "cqhci"; 910 911 iommus = <&apps_smmu 0xc0 0x0>; 912 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 914 interrupt-names = "hc_irq", "pwr_irq"; 915 916 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 917 <&gcc GCC_SDCC1_APPS_CLK>, 918 <&rpmhcc RPMH_CXO_CLK>; 919 clock-names = "iface", "core", "xo"; 920 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 921 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 922 interconnect-names = "sdhc-ddr","cpu-sdhc"; 923 power-domains = <&rpmhpd SC7280_CX>; 924 operating-points-v2 = <&sdhc1_opp_table>; 925 926 bus-width = <8>; 927 supports-cqe; 928 929 qcom,dll-config = <0x0007642c>; 930 qcom,ddr-config = <0x80040868>; 931 932 mmc-ddr-1_8v; 933 mmc-hs200-1_8v; 934 mmc-hs400-1_8v; 935 mmc-hs400-enhanced-strobe; 936 937 resets = <&gcc GCC_SDCC1_BCR>; 938 939 sdhc1_opp_table: opp-table { 940 compatible = "operating-points-v2"; 941 942 opp-100000000 { 943 opp-hz = /bits/ 64 <100000000>; 944 required-opps = <&rpmhpd_opp_low_svs>; 945 opp-peak-kBps = <1800000 400000>; 946 opp-avg-kBps = <100000 0>; 947 }; 948 949 opp-384000000 { 950 opp-hz = /bits/ 64 <384000000>; 951 required-opps = <&rpmhpd_opp_nom>; 952 opp-peak-kBps = <5400000 1600000>; 953 opp-avg-kBps = <390000 0>; 954 }; 955 }; 956 }; 957 958 gpi_dma0: dma-controller@900000 { 959 #dma-cells = <3>; 960 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 961 reg = <0 0x00900000 0 0x60000>; 962 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 974 dma-channels = <12>; 975 dma-channel-mask = <0x7f>; 976 iommus = <&apps_smmu 0x0136 0x0>; 977 status = "disabled"; 978 }; 979 980 qupv3_id_0: geniqup@9c0000 { 981 compatible = "qcom,geni-se-qup"; 982 reg = <0 0x009c0000 0 0x2000>; 983 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 984 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 985 clock-names = "m-ahb", "s-ahb"; 986 #address-cells = <2>; 987 #size-cells = <2>; 988 ranges; 989 iommus = <&apps_smmu 0x123 0x0>; 990 status = "disabled"; 991 992 i2c0: i2c@980000 { 993 compatible = "qcom,geni-i2c"; 994 reg = <0 0x00980000 0 0x4000>; 995 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 996 clock-names = "se"; 997 pinctrl-names = "default"; 998 pinctrl-0 = <&qup_i2c0_data_clk>; 999 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1003 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1004 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1005 interconnect-names = "qup-core", "qup-config", 1006 "qup-memory"; 1007 power-domains = <&rpmhpd SC7280_CX>; 1008 required-opps = <&rpmhpd_opp_low_svs>; 1009 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1010 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1011 dma-names = "tx", "rx"; 1012 status = "disabled"; 1013 }; 1014 1015 spi0: spi@980000 { 1016 compatible = "qcom,geni-spi"; 1017 reg = <0 0x00980000 0 0x4000>; 1018 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1019 clock-names = "se"; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1022 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 power-domains = <&rpmhpd SC7280_CX>; 1026 operating-points-v2 = <&qup_opp_table>; 1027 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1028 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1029 interconnect-names = "qup-core", "qup-config"; 1030 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1031 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1032 dma-names = "tx", "rx"; 1033 status = "disabled"; 1034 }; 1035 1036 uart0: serial@980000 { 1037 compatible = "qcom,geni-uart"; 1038 reg = <0 0x00980000 0 0x4000>; 1039 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1040 clock-names = "se"; 1041 pinctrl-names = "default"; 1042 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1043 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1044 power-domains = <&rpmhpd SC7280_CX>; 1045 operating-points-v2 = <&qup_opp_table>; 1046 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1047 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1048 interconnect-names = "qup-core", "qup-config"; 1049 status = "disabled"; 1050 }; 1051 1052 i2c1: i2c@984000 { 1053 compatible = "qcom,geni-i2c"; 1054 reg = <0 0x00984000 0 0x4000>; 1055 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1056 clock-names = "se"; 1057 pinctrl-names = "default"; 1058 pinctrl-0 = <&qup_i2c1_data_clk>; 1059 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1060 #address-cells = <1>; 1061 #size-cells = <0>; 1062 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1063 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1064 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1065 interconnect-names = "qup-core", "qup-config", 1066 "qup-memory"; 1067 power-domains = <&rpmhpd SC7280_CX>; 1068 required-opps = <&rpmhpd_opp_low_svs>; 1069 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1070 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1071 dma-names = "tx", "rx"; 1072 status = "disabled"; 1073 }; 1074 1075 spi1: spi@984000 { 1076 compatible = "qcom,geni-spi"; 1077 reg = <0 0x00984000 0 0x4000>; 1078 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1079 clock-names = "se"; 1080 pinctrl-names = "default"; 1081 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1082 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1083 #address-cells = <1>; 1084 #size-cells = <0>; 1085 power-domains = <&rpmhpd SC7280_CX>; 1086 operating-points-v2 = <&qup_opp_table>; 1087 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1088 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1089 interconnect-names = "qup-core", "qup-config"; 1090 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1091 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1092 dma-names = "tx", "rx"; 1093 status = "disabled"; 1094 }; 1095 1096 uart1: serial@984000 { 1097 compatible = "qcom,geni-uart"; 1098 reg = <0 0x00984000 0 0x4000>; 1099 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1100 clock-names = "se"; 1101 pinctrl-names = "default"; 1102 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1103 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1104 power-domains = <&rpmhpd SC7280_CX>; 1105 operating-points-v2 = <&qup_opp_table>; 1106 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1107 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1108 interconnect-names = "qup-core", "qup-config"; 1109 status = "disabled"; 1110 }; 1111 1112 i2c2: i2c@988000 { 1113 compatible = "qcom,geni-i2c"; 1114 reg = <0 0x00988000 0 0x4000>; 1115 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1116 clock-names = "se"; 1117 pinctrl-names = "default"; 1118 pinctrl-0 = <&qup_i2c2_data_clk>; 1119 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1120 #address-cells = <1>; 1121 #size-cells = <0>; 1122 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1123 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1124 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1125 interconnect-names = "qup-core", "qup-config", 1126 "qup-memory"; 1127 power-domains = <&rpmhpd SC7280_CX>; 1128 required-opps = <&rpmhpd_opp_low_svs>; 1129 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1130 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1131 dma-names = "tx", "rx"; 1132 status = "disabled"; 1133 }; 1134 1135 spi2: spi@988000 { 1136 compatible = "qcom,geni-spi"; 1137 reg = <0 0x00988000 0 0x4000>; 1138 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1139 clock-names = "se"; 1140 pinctrl-names = "default"; 1141 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1142 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 power-domains = <&rpmhpd SC7280_CX>; 1146 operating-points-v2 = <&qup_opp_table>; 1147 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1148 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1149 interconnect-names = "qup-core", "qup-config"; 1150 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1151 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1152 dma-names = "tx", "rx"; 1153 status = "disabled"; 1154 }; 1155 1156 uart2: serial@988000 { 1157 compatible = "qcom,geni-uart"; 1158 reg = <0 0x00988000 0 0x4000>; 1159 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1160 clock-names = "se"; 1161 pinctrl-names = "default"; 1162 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1163 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1164 power-domains = <&rpmhpd SC7280_CX>; 1165 operating-points-v2 = <&qup_opp_table>; 1166 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1167 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1168 interconnect-names = "qup-core", "qup-config"; 1169 status = "disabled"; 1170 }; 1171 1172 i2c3: i2c@98c000 { 1173 compatible = "qcom,geni-i2c"; 1174 reg = <0 0x0098c000 0 0x4000>; 1175 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1176 clock-names = "se"; 1177 pinctrl-names = "default"; 1178 pinctrl-0 = <&qup_i2c3_data_clk>; 1179 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1183 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1184 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1185 interconnect-names = "qup-core", "qup-config", 1186 "qup-memory"; 1187 power-domains = <&rpmhpd SC7280_CX>; 1188 required-opps = <&rpmhpd_opp_low_svs>; 1189 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1190 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1191 dma-names = "tx", "rx"; 1192 status = "disabled"; 1193 }; 1194 1195 spi3: spi@98c000 { 1196 compatible = "qcom,geni-spi"; 1197 reg = <0 0x0098c000 0 0x4000>; 1198 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1199 clock-names = "se"; 1200 pinctrl-names = "default"; 1201 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1202 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1203 #address-cells = <1>; 1204 #size-cells = <0>; 1205 power-domains = <&rpmhpd SC7280_CX>; 1206 operating-points-v2 = <&qup_opp_table>; 1207 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1208 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1209 interconnect-names = "qup-core", "qup-config"; 1210 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1211 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1212 dma-names = "tx", "rx"; 1213 status = "disabled"; 1214 }; 1215 1216 uart3: serial@98c000 { 1217 compatible = "qcom,geni-uart"; 1218 reg = <0 0x0098c000 0 0x4000>; 1219 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1220 clock-names = "se"; 1221 pinctrl-names = "default"; 1222 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1223 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1224 power-domains = <&rpmhpd SC7280_CX>; 1225 operating-points-v2 = <&qup_opp_table>; 1226 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1227 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1228 interconnect-names = "qup-core", "qup-config"; 1229 status = "disabled"; 1230 }; 1231 1232 i2c4: i2c@990000 { 1233 compatible = "qcom,geni-i2c"; 1234 reg = <0 0x00990000 0 0x4000>; 1235 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1236 clock-names = "se"; 1237 pinctrl-names = "default"; 1238 pinctrl-0 = <&qup_i2c4_data_clk>; 1239 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1240 #address-cells = <1>; 1241 #size-cells = <0>; 1242 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1243 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1244 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1245 interconnect-names = "qup-core", "qup-config", 1246 "qup-memory"; 1247 power-domains = <&rpmhpd SC7280_CX>; 1248 required-opps = <&rpmhpd_opp_low_svs>; 1249 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1250 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1251 dma-names = "tx", "rx"; 1252 status = "disabled"; 1253 }; 1254 1255 spi4: spi@990000 { 1256 compatible = "qcom,geni-spi"; 1257 reg = <0 0x00990000 0 0x4000>; 1258 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1259 clock-names = "se"; 1260 pinctrl-names = "default"; 1261 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1262 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1263 #address-cells = <1>; 1264 #size-cells = <0>; 1265 power-domains = <&rpmhpd SC7280_CX>; 1266 operating-points-v2 = <&qup_opp_table>; 1267 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1268 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1269 interconnect-names = "qup-core", "qup-config"; 1270 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1271 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1272 dma-names = "tx", "rx"; 1273 status = "disabled"; 1274 }; 1275 1276 uart4: serial@990000 { 1277 compatible = "qcom,geni-uart"; 1278 reg = <0 0x00990000 0 0x4000>; 1279 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1280 clock-names = "se"; 1281 pinctrl-names = "default"; 1282 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1283 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1284 power-domains = <&rpmhpd SC7280_CX>; 1285 operating-points-v2 = <&qup_opp_table>; 1286 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1287 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1288 interconnect-names = "qup-core", "qup-config"; 1289 status = "disabled"; 1290 }; 1291 1292 i2c5: i2c@994000 { 1293 compatible = "qcom,geni-i2c"; 1294 reg = <0 0x00994000 0 0x4000>; 1295 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1296 clock-names = "se"; 1297 pinctrl-names = "default"; 1298 pinctrl-0 = <&qup_i2c5_data_clk>; 1299 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1303 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1304 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1305 interconnect-names = "qup-core", "qup-config", 1306 "qup-memory"; 1307 power-domains = <&rpmhpd SC7280_CX>; 1308 required-opps = <&rpmhpd_opp_low_svs>; 1309 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1310 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1311 dma-names = "tx", "rx"; 1312 status = "disabled"; 1313 }; 1314 1315 spi5: spi@994000 { 1316 compatible = "qcom,geni-spi"; 1317 reg = <0 0x00994000 0 0x4000>; 1318 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1319 clock-names = "se"; 1320 pinctrl-names = "default"; 1321 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1322 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 power-domains = <&rpmhpd SC7280_CX>; 1326 operating-points-v2 = <&qup_opp_table>; 1327 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1328 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1329 interconnect-names = "qup-core", "qup-config"; 1330 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1331 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1332 dma-names = "tx", "rx"; 1333 status = "disabled"; 1334 }; 1335 1336 uart5: serial@994000 { 1337 compatible = "qcom,geni-uart"; 1338 reg = <0 0x00994000 0 0x4000>; 1339 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1340 clock-names = "se"; 1341 pinctrl-names = "default"; 1342 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1343 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1344 power-domains = <&rpmhpd SC7280_CX>; 1345 operating-points-v2 = <&qup_opp_table>; 1346 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1347 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1348 interconnect-names = "qup-core", "qup-config"; 1349 status = "disabled"; 1350 }; 1351 1352 i2c6: i2c@998000 { 1353 compatible = "qcom,geni-i2c"; 1354 reg = <0 0x00998000 0 0x4000>; 1355 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1356 clock-names = "se"; 1357 pinctrl-names = "default"; 1358 pinctrl-0 = <&qup_i2c6_data_clk>; 1359 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1360 #address-cells = <1>; 1361 #size-cells = <0>; 1362 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1363 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1364 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1365 interconnect-names = "qup-core", "qup-config", 1366 "qup-memory"; 1367 power-domains = <&rpmhpd SC7280_CX>; 1368 required-opps = <&rpmhpd_opp_low_svs>; 1369 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1370 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1371 dma-names = "tx", "rx"; 1372 status = "disabled"; 1373 }; 1374 1375 spi6: spi@998000 { 1376 compatible = "qcom,geni-spi"; 1377 reg = <0 0x00998000 0 0x4000>; 1378 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1379 clock-names = "se"; 1380 pinctrl-names = "default"; 1381 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1382 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1383 #address-cells = <1>; 1384 #size-cells = <0>; 1385 power-domains = <&rpmhpd SC7280_CX>; 1386 operating-points-v2 = <&qup_opp_table>; 1387 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1388 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1389 interconnect-names = "qup-core", "qup-config"; 1390 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1391 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1392 dma-names = "tx", "rx"; 1393 status = "disabled"; 1394 }; 1395 1396 uart6: serial@998000 { 1397 compatible = "qcom,geni-uart"; 1398 reg = <0 0x00998000 0 0x4000>; 1399 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1400 clock-names = "se"; 1401 pinctrl-names = "default"; 1402 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1403 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1404 power-domains = <&rpmhpd SC7280_CX>; 1405 operating-points-v2 = <&qup_opp_table>; 1406 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1407 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1408 interconnect-names = "qup-core", "qup-config"; 1409 status = "disabled"; 1410 }; 1411 1412 i2c7: i2c@99c000 { 1413 compatible = "qcom,geni-i2c"; 1414 reg = <0 0x0099c000 0 0x4000>; 1415 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1416 clock-names = "se"; 1417 pinctrl-names = "default"; 1418 pinctrl-0 = <&qup_i2c7_data_clk>; 1419 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1420 #address-cells = <1>; 1421 #size-cells = <0>; 1422 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1423 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1424 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1425 interconnect-names = "qup-core", "qup-config", 1426 "qup-memory"; 1427 power-domains = <&rpmhpd SC7280_CX>; 1428 required-opps = <&rpmhpd_opp_low_svs>; 1429 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1430 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1431 dma-names = "tx", "rx"; 1432 status = "disabled"; 1433 }; 1434 1435 spi7: spi@99c000 { 1436 compatible = "qcom,geni-spi"; 1437 reg = <0 0x0099c000 0 0x4000>; 1438 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1439 clock-names = "se"; 1440 pinctrl-names = "default"; 1441 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1442 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1443 #address-cells = <1>; 1444 #size-cells = <0>; 1445 power-domains = <&rpmhpd SC7280_CX>; 1446 operating-points-v2 = <&qup_opp_table>; 1447 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1448 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1449 interconnect-names = "qup-core", "qup-config"; 1450 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1451 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1452 dma-names = "tx", "rx"; 1453 status = "disabled"; 1454 }; 1455 1456 uart7: serial@99c000 { 1457 compatible = "qcom,geni-uart"; 1458 reg = <0 0x0099c000 0 0x4000>; 1459 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1460 clock-names = "se"; 1461 pinctrl-names = "default"; 1462 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1463 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1464 power-domains = <&rpmhpd SC7280_CX>; 1465 operating-points-v2 = <&qup_opp_table>; 1466 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1467 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1468 interconnect-names = "qup-core", "qup-config"; 1469 status = "disabled"; 1470 }; 1471 }; 1472 1473 gpi_dma1: dma-controller@a00000 { 1474 #dma-cells = <3>; 1475 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1476 reg = <0 0x00a00000 0 0x60000>; 1477 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1489 dma-channels = <12>; 1490 dma-channel-mask = <0x1e>; 1491 iommus = <&apps_smmu 0x56 0x0>; 1492 status = "disabled"; 1493 }; 1494 1495 qupv3_id_1: geniqup@ac0000 { 1496 compatible = "qcom,geni-se-qup"; 1497 reg = <0 0x00ac0000 0 0x2000>; 1498 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1499 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1500 clock-names = "m-ahb", "s-ahb"; 1501 #address-cells = <2>; 1502 #size-cells = <2>; 1503 ranges; 1504 iommus = <&apps_smmu 0x43 0x0>; 1505 status = "disabled"; 1506 1507 i2c8: i2c@a80000 { 1508 compatible = "qcom,geni-i2c"; 1509 reg = <0 0x00a80000 0 0x4000>; 1510 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1511 clock-names = "se"; 1512 pinctrl-names = "default"; 1513 pinctrl-0 = <&qup_i2c8_data_clk>; 1514 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1515 #address-cells = <1>; 1516 #size-cells = <0>; 1517 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1518 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1519 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1520 interconnect-names = "qup-core", "qup-config", 1521 "qup-memory"; 1522 power-domains = <&rpmhpd SC7280_CX>; 1523 required-opps = <&rpmhpd_opp_low_svs>; 1524 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1525 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1526 dma-names = "tx", "rx"; 1527 status = "disabled"; 1528 }; 1529 1530 spi8: spi@a80000 { 1531 compatible = "qcom,geni-spi"; 1532 reg = <0 0x00a80000 0 0x4000>; 1533 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1534 clock-names = "se"; 1535 pinctrl-names = "default"; 1536 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1537 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1538 #address-cells = <1>; 1539 #size-cells = <0>; 1540 power-domains = <&rpmhpd SC7280_CX>; 1541 operating-points-v2 = <&qup_opp_table>; 1542 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1543 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1544 interconnect-names = "qup-core", "qup-config"; 1545 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1546 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1547 dma-names = "tx", "rx"; 1548 status = "disabled"; 1549 }; 1550 1551 uart8: serial@a80000 { 1552 compatible = "qcom,geni-uart"; 1553 reg = <0 0x00a80000 0 0x4000>; 1554 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1555 clock-names = "se"; 1556 pinctrl-names = "default"; 1557 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1558 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1559 power-domains = <&rpmhpd SC7280_CX>; 1560 operating-points-v2 = <&qup_opp_table>; 1561 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1562 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1563 interconnect-names = "qup-core", "qup-config"; 1564 status = "disabled"; 1565 }; 1566 1567 i2c9: i2c@a84000 { 1568 compatible = "qcom,geni-i2c"; 1569 reg = <0 0x00a84000 0 0x4000>; 1570 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1571 clock-names = "se"; 1572 pinctrl-names = "default"; 1573 pinctrl-0 = <&qup_i2c9_data_clk>; 1574 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1575 #address-cells = <1>; 1576 #size-cells = <0>; 1577 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1578 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1579 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1580 interconnect-names = "qup-core", "qup-config", 1581 "qup-memory"; 1582 power-domains = <&rpmhpd SC7280_CX>; 1583 required-opps = <&rpmhpd_opp_low_svs>; 1584 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1585 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1586 dma-names = "tx", "rx"; 1587 status = "disabled"; 1588 }; 1589 1590 spi9: spi@a84000 { 1591 compatible = "qcom,geni-spi"; 1592 reg = <0 0x00a84000 0 0x4000>; 1593 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1594 clock-names = "se"; 1595 pinctrl-names = "default"; 1596 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1597 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1598 #address-cells = <1>; 1599 #size-cells = <0>; 1600 power-domains = <&rpmhpd SC7280_CX>; 1601 operating-points-v2 = <&qup_opp_table>; 1602 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1603 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1604 interconnect-names = "qup-core", "qup-config"; 1605 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1606 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1607 dma-names = "tx", "rx"; 1608 status = "disabled"; 1609 }; 1610 1611 uart9: serial@a84000 { 1612 compatible = "qcom,geni-uart"; 1613 reg = <0 0x00a84000 0 0x4000>; 1614 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1615 clock-names = "se"; 1616 pinctrl-names = "default"; 1617 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1618 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1619 power-domains = <&rpmhpd SC7280_CX>; 1620 operating-points-v2 = <&qup_opp_table>; 1621 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1622 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1623 interconnect-names = "qup-core", "qup-config"; 1624 status = "disabled"; 1625 }; 1626 1627 i2c10: i2c@a88000 { 1628 compatible = "qcom,geni-i2c"; 1629 reg = <0 0x00a88000 0 0x4000>; 1630 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1631 clock-names = "se"; 1632 pinctrl-names = "default"; 1633 pinctrl-0 = <&qup_i2c10_data_clk>; 1634 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1635 #address-cells = <1>; 1636 #size-cells = <0>; 1637 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1638 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1639 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1640 interconnect-names = "qup-core", "qup-config", 1641 "qup-memory"; 1642 power-domains = <&rpmhpd SC7280_CX>; 1643 required-opps = <&rpmhpd_opp_low_svs>; 1644 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1645 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1646 dma-names = "tx", "rx"; 1647 status = "disabled"; 1648 }; 1649 1650 spi10: spi@a88000 { 1651 compatible = "qcom,geni-spi"; 1652 reg = <0 0x00a88000 0 0x4000>; 1653 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1654 clock-names = "se"; 1655 pinctrl-names = "default"; 1656 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1657 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1658 #address-cells = <1>; 1659 #size-cells = <0>; 1660 power-domains = <&rpmhpd SC7280_CX>; 1661 operating-points-v2 = <&qup_opp_table>; 1662 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1663 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1664 interconnect-names = "qup-core", "qup-config"; 1665 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1666 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1667 dma-names = "tx", "rx"; 1668 status = "disabled"; 1669 }; 1670 1671 uart10: serial@a88000 { 1672 compatible = "qcom,geni-uart"; 1673 reg = <0 0x00a88000 0 0x4000>; 1674 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1675 clock-names = "se"; 1676 pinctrl-names = "default"; 1677 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1678 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1679 power-domains = <&rpmhpd SC7280_CX>; 1680 operating-points-v2 = <&qup_opp_table>; 1681 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1682 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1683 interconnect-names = "qup-core", "qup-config"; 1684 status = "disabled"; 1685 }; 1686 1687 i2c11: i2c@a8c000 { 1688 compatible = "qcom,geni-i2c"; 1689 reg = <0 0x00a8c000 0 0x4000>; 1690 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1691 clock-names = "se"; 1692 pinctrl-names = "default"; 1693 pinctrl-0 = <&qup_i2c11_data_clk>; 1694 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1695 #address-cells = <1>; 1696 #size-cells = <0>; 1697 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1698 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1699 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1700 interconnect-names = "qup-core", "qup-config", 1701 "qup-memory"; 1702 power-domains = <&rpmhpd SC7280_CX>; 1703 required-opps = <&rpmhpd_opp_low_svs>; 1704 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1705 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1706 dma-names = "tx", "rx"; 1707 status = "disabled"; 1708 }; 1709 1710 spi11: spi@a8c000 { 1711 compatible = "qcom,geni-spi"; 1712 reg = <0 0x00a8c000 0 0x4000>; 1713 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1714 clock-names = "se"; 1715 pinctrl-names = "default"; 1716 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1717 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1718 #address-cells = <1>; 1719 #size-cells = <0>; 1720 power-domains = <&rpmhpd SC7280_CX>; 1721 operating-points-v2 = <&qup_opp_table>; 1722 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1723 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1724 interconnect-names = "qup-core", "qup-config"; 1725 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1726 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1727 dma-names = "tx", "rx"; 1728 status = "disabled"; 1729 }; 1730 1731 uart11: serial@a8c000 { 1732 compatible = "qcom,geni-uart"; 1733 reg = <0 0x00a8c000 0 0x4000>; 1734 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1735 clock-names = "se"; 1736 pinctrl-names = "default"; 1737 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1738 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1739 power-domains = <&rpmhpd SC7280_CX>; 1740 operating-points-v2 = <&qup_opp_table>; 1741 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1742 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1743 interconnect-names = "qup-core", "qup-config"; 1744 status = "disabled"; 1745 }; 1746 1747 i2c12: i2c@a90000 { 1748 compatible = "qcom,geni-i2c"; 1749 reg = <0 0x00a90000 0 0x4000>; 1750 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1751 clock-names = "se"; 1752 pinctrl-names = "default"; 1753 pinctrl-0 = <&qup_i2c12_data_clk>; 1754 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1755 #address-cells = <1>; 1756 #size-cells = <0>; 1757 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1758 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1759 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1760 interconnect-names = "qup-core", "qup-config", 1761 "qup-memory"; 1762 power-domains = <&rpmhpd SC7280_CX>; 1763 required-opps = <&rpmhpd_opp_low_svs>; 1764 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1765 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1766 dma-names = "tx", "rx"; 1767 status = "disabled"; 1768 }; 1769 1770 spi12: spi@a90000 { 1771 compatible = "qcom,geni-spi"; 1772 reg = <0 0x00a90000 0 0x4000>; 1773 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1774 clock-names = "se"; 1775 pinctrl-names = "default"; 1776 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1777 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1778 #address-cells = <1>; 1779 #size-cells = <0>; 1780 power-domains = <&rpmhpd SC7280_CX>; 1781 operating-points-v2 = <&qup_opp_table>; 1782 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1783 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1784 interconnect-names = "qup-core", "qup-config"; 1785 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1786 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1787 dma-names = "tx", "rx"; 1788 status = "disabled"; 1789 }; 1790 1791 uart12: serial@a90000 { 1792 compatible = "qcom,geni-uart"; 1793 reg = <0 0x00a90000 0 0x4000>; 1794 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1795 clock-names = "se"; 1796 pinctrl-names = "default"; 1797 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1798 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1799 power-domains = <&rpmhpd SC7280_CX>; 1800 operating-points-v2 = <&qup_opp_table>; 1801 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1802 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1803 interconnect-names = "qup-core", "qup-config"; 1804 status = "disabled"; 1805 }; 1806 1807 i2c13: i2c@a94000 { 1808 compatible = "qcom,geni-i2c"; 1809 reg = <0 0x00a94000 0 0x4000>; 1810 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1811 clock-names = "se"; 1812 pinctrl-names = "default"; 1813 pinctrl-0 = <&qup_i2c13_data_clk>; 1814 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1815 #address-cells = <1>; 1816 #size-cells = <0>; 1817 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1818 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1819 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1820 interconnect-names = "qup-core", "qup-config", 1821 "qup-memory"; 1822 power-domains = <&rpmhpd SC7280_CX>; 1823 required-opps = <&rpmhpd_opp_low_svs>; 1824 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1825 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1826 dma-names = "tx", "rx"; 1827 status = "disabled"; 1828 }; 1829 1830 spi13: spi@a94000 { 1831 compatible = "qcom,geni-spi"; 1832 reg = <0 0x00a94000 0 0x4000>; 1833 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1834 clock-names = "se"; 1835 pinctrl-names = "default"; 1836 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1837 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1838 #address-cells = <1>; 1839 #size-cells = <0>; 1840 power-domains = <&rpmhpd SC7280_CX>; 1841 operating-points-v2 = <&qup_opp_table>; 1842 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1843 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1844 interconnect-names = "qup-core", "qup-config"; 1845 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1846 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1847 dma-names = "tx", "rx"; 1848 status = "disabled"; 1849 }; 1850 1851 uart13: serial@a94000 { 1852 compatible = "qcom,geni-uart"; 1853 reg = <0 0x00a94000 0 0x4000>; 1854 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1855 clock-names = "se"; 1856 pinctrl-names = "default"; 1857 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1858 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1859 power-domains = <&rpmhpd SC7280_CX>; 1860 operating-points-v2 = <&qup_opp_table>; 1861 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1862 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1863 interconnect-names = "qup-core", "qup-config"; 1864 status = "disabled"; 1865 }; 1866 1867 i2c14: i2c@a98000 { 1868 compatible = "qcom,geni-i2c"; 1869 reg = <0 0x00a98000 0 0x4000>; 1870 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1871 clock-names = "se"; 1872 pinctrl-names = "default"; 1873 pinctrl-0 = <&qup_i2c14_data_clk>; 1874 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1875 #address-cells = <1>; 1876 #size-cells = <0>; 1877 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1878 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1879 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1880 interconnect-names = "qup-core", "qup-config", 1881 "qup-memory"; 1882 power-domains = <&rpmhpd SC7280_CX>; 1883 required-opps = <&rpmhpd_opp_low_svs>; 1884 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1885 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1886 dma-names = "tx", "rx"; 1887 status = "disabled"; 1888 }; 1889 1890 spi14: spi@a98000 { 1891 compatible = "qcom,geni-spi"; 1892 reg = <0 0x00a98000 0 0x4000>; 1893 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1894 clock-names = "se"; 1895 pinctrl-names = "default"; 1896 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1897 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1898 #address-cells = <1>; 1899 #size-cells = <0>; 1900 power-domains = <&rpmhpd SC7280_CX>; 1901 operating-points-v2 = <&qup_opp_table>; 1902 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1903 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1904 interconnect-names = "qup-core", "qup-config"; 1905 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1906 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1907 dma-names = "tx", "rx"; 1908 status = "disabled"; 1909 }; 1910 1911 uart14: serial@a98000 { 1912 compatible = "qcom,geni-uart"; 1913 reg = <0 0x00a98000 0 0x4000>; 1914 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1915 clock-names = "se"; 1916 pinctrl-names = "default"; 1917 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1918 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1919 power-domains = <&rpmhpd SC7280_CX>; 1920 operating-points-v2 = <&qup_opp_table>; 1921 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1922 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1923 interconnect-names = "qup-core", "qup-config"; 1924 status = "disabled"; 1925 }; 1926 1927 i2c15: i2c@a9c000 { 1928 compatible = "qcom,geni-i2c"; 1929 reg = <0 0x00a9c000 0 0x4000>; 1930 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1931 clock-names = "se"; 1932 pinctrl-names = "default"; 1933 pinctrl-0 = <&qup_i2c15_data_clk>; 1934 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1935 #address-cells = <1>; 1936 #size-cells = <0>; 1937 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1938 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1939 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1940 interconnect-names = "qup-core", "qup-config", 1941 "qup-memory"; 1942 power-domains = <&rpmhpd SC7280_CX>; 1943 required-opps = <&rpmhpd_opp_low_svs>; 1944 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1945 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1946 dma-names = "tx", "rx"; 1947 status = "disabled"; 1948 }; 1949 1950 spi15: spi@a9c000 { 1951 compatible = "qcom,geni-spi"; 1952 reg = <0 0x00a9c000 0 0x4000>; 1953 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1954 clock-names = "se"; 1955 pinctrl-names = "default"; 1956 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1957 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1958 #address-cells = <1>; 1959 #size-cells = <0>; 1960 power-domains = <&rpmhpd SC7280_CX>; 1961 operating-points-v2 = <&qup_opp_table>; 1962 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1963 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1964 interconnect-names = "qup-core", "qup-config"; 1965 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1966 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1967 dma-names = "tx", "rx"; 1968 status = "disabled"; 1969 }; 1970 1971 uart15: serial@a9c000 { 1972 compatible = "qcom,geni-uart"; 1973 reg = <0 0x00a9c000 0 0x4000>; 1974 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1975 clock-names = "se"; 1976 pinctrl-names = "default"; 1977 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1978 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1979 power-domains = <&rpmhpd SC7280_CX>; 1980 operating-points-v2 = <&qup_opp_table>; 1981 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1982 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1983 interconnect-names = "qup-core", "qup-config"; 1984 status = "disabled"; 1985 }; 1986 }; 1987 1988 cnoc2: interconnect@1500000 { 1989 reg = <0 0x01500000 0 0x1000>; 1990 compatible = "qcom,sc7280-cnoc2"; 1991 #interconnect-cells = <2>; 1992 qcom,bcm-voters = <&apps_bcm_voter>; 1993 }; 1994 1995 cnoc3: interconnect@1502000 { 1996 reg = <0 0x01502000 0 0x1000>; 1997 compatible = "qcom,sc7280-cnoc3"; 1998 #interconnect-cells = <2>; 1999 qcom,bcm-voters = <&apps_bcm_voter>; 2000 }; 2001 2002 mc_virt: interconnect@1580000 { 2003 reg = <0 0x01580000 0 0x4>; 2004 compatible = "qcom,sc7280-mc-virt"; 2005 #interconnect-cells = <2>; 2006 qcom,bcm-voters = <&apps_bcm_voter>; 2007 }; 2008 2009 system_noc: interconnect@1680000 { 2010 reg = <0 0x01680000 0 0x15480>; 2011 compatible = "qcom,sc7280-system-noc"; 2012 #interconnect-cells = <2>; 2013 qcom,bcm-voters = <&apps_bcm_voter>; 2014 }; 2015 2016 aggre1_noc: interconnect@16e0000 { 2017 compatible = "qcom,sc7280-aggre1-noc"; 2018 reg = <0 0x016e0000 0 0x1c080>; 2019 #interconnect-cells = <2>; 2020 qcom,bcm-voters = <&apps_bcm_voter>; 2021 }; 2022 2023 aggre2_noc: interconnect@1700000 { 2024 reg = <0 0x01700000 0 0x2b080>; 2025 compatible = "qcom,sc7280-aggre2-noc"; 2026 #interconnect-cells = <2>; 2027 qcom,bcm-voters = <&apps_bcm_voter>; 2028 }; 2029 2030 mmss_noc: interconnect@1740000 { 2031 reg = <0 0x01740000 0 0x1e080>; 2032 compatible = "qcom,sc7280-mmss-noc"; 2033 #interconnect-cells = <2>; 2034 qcom,bcm-voters = <&apps_bcm_voter>; 2035 }; 2036 2037 wifi: wifi@17a10040 { 2038 compatible = "qcom,wcn6750-wifi"; 2039 reg = <0 0x17a10040 0 0x0>; 2040 iommus = <&apps_smmu 0x1c00 0x1>; 2041 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2042 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2043 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2044 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2045 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2046 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2047 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2048 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2049 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2050 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2051 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2052 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2053 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2054 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2055 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2056 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2057 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2058 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2059 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2060 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2061 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2062 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2063 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2064 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2065 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2066 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2067 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2068 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2069 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2070 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2071 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2072 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2073 qcom,rproc = <&remoteproc_wpss>; 2074 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2075 status = "disabled"; 2076 qcom,smem-states = <&wlan_smp2p_out 0>; 2077 qcom,smem-state-names = "wlan-smp2p-out"; 2078 }; 2079 2080 pcie1: pci@1c08000 { 2081 compatible = "qcom,pcie-sc7280"; 2082 reg = <0 0x01c08000 0 0x3000>, 2083 <0 0x40000000 0 0xf1d>, 2084 <0 0x40000f20 0 0xa8>, 2085 <0 0x40001000 0 0x1000>, 2086 <0 0x40100000 0 0x100000>; 2087 2088 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2089 device_type = "pci"; 2090 linux,pci-domain = <1>; 2091 bus-range = <0x00 0xff>; 2092 num-lanes = <2>; 2093 2094 #address-cells = <3>; 2095 #size-cells = <2>; 2096 2097 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2098 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2099 2100 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2101 interrupt-names = "msi"; 2102 #interrupt-cells = <1>; 2103 interrupt-map-mask = <0 0 0 0x7>; 2104 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2105 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2106 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2107 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2108 2109 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2110 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2111 <&pcie1_lane>, 2112 <&rpmhcc RPMH_CXO_CLK>, 2113 <&gcc GCC_PCIE_1_AUX_CLK>, 2114 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2115 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2116 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2117 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2118 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2119 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2120 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2121 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2122 2123 clock-names = "pipe", 2124 "pipe_mux", 2125 "phy_pipe", 2126 "ref", 2127 "aux", 2128 "cfg", 2129 "bus_master", 2130 "bus_slave", 2131 "slave_q2a", 2132 "tbu", 2133 "ddrss_sf_tbu", 2134 "aggre0", 2135 "aggre1"; 2136 2137 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2138 assigned-clock-rates = <19200000>; 2139 2140 resets = <&gcc GCC_PCIE_1_BCR>; 2141 reset-names = "pci"; 2142 2143 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2144 2145 phys = <&pcie1_lane>; 2146 phy-names = "pciephy"; 2147 2148 pinctrl-names = "default"; 2149 pinctrl-0 = <&pcie1_clkreq_n>; 2150 2151 dma-coherent; 2152 2153 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2154 <0x100 &apps_smmu 0x1c81 0x1>; 2155 2156 status = "disabled"; 2157 }; 2158 2159 pcie1_phy: phy@1c0e000 { 2160 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2161 reg = <0 0x01c0e000 0 0x1c0>; 2162 #address-cells = <2>; 2163 #size-cells = <2>; 2164 ranges; 2165 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2166 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2167 <&gcc GCC_PCIE_CLKREF_EN>, 2168 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2169 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2170 2171 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2172 reset-names = "phy"; 2173 2174 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2175 assigned-clock-rates = <100000000>; 2176 2177 status = "disabled"; 2178 2179 pcie1_lane: phy@1c0e200 { 2180 reg = <0 0x01c0e200 0 0x170>, 2181 <0 0x01c0e400 0 0x200>, 2182 <0 0x01c0ea00 0 0x1f0>, 2183 <0 0x01c0e600 0 0x170>, 2184 <0 0x01c0e800 0 0x200>, 2185 <0 0x01c0ee00 0 0xf4>; 2186 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2187 clock-names = "pipe0"; 2188 2189 #phy-cells = <0>; 2190 #clock-cells = <0>; 2191 clock-output-names = "pcie_1_pipe_clk"; 2192 }; 2193 }; 2194 2195 ipa: ipa@1e40000 { 2196 compatible = "qcom,sc7280-ipa"; 2197 2198 iommus = <&apps_smmu 0x480 0x0>, 2199 <&apps_smmu 0x482 0x0>; 2200 reg = <0 0x01e40000 0 0x8000>, 2201 <0 0x01e50000 0 0x4ad0>, 2202 <0 0x01e04000 0 0x23000>; 2203 reg-names = "ipa-reg", 2204 "ipa-shared", 2205 "gsi"; 2206 2207 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2208 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2209 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2210 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2211 interrupt-names = "ipa", 2212 "gsi", 2213 "ipa-clock-query", 2214 "ipa-setup-ready"; 2215 2216 clocks = <&rpmhcc RPMH_IPA_CLK>; 2217 clock-names = "core"; 2218 2219 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2220 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2221 interconnect-names = "memory", 2222 "config"; 2223 2224 qcom,qmp = <&aoss_qmp>; 2225 2226 qcom,smem-states = <&ipa_smp2p_out 0>, 2227 <&ipa_smp2p_out 1>; 2228 qcom,smem-state-names = "ipa-clock-enabled-valid", 2229 "ipa-clock-enabled"; 2230 2231 status = "disabled"; 2232 }; 2233 2234 tcsr_mutex: hwlock@1f40000 { 2235 compatible = "qcom,tcsr-mutex"; 2236 reg = <0 0x01f40000 0 0x20000>; 2237 #hwlock-cells = <1>; 2238 }; 2239 2240 tcsr_1: syscon@1f60000 { 2241 compatible = "qcom,sc7280-tcsr", "syscon"; 2242 reg = <0 0x01f60000 0 0x20000>; 2243 }; 2244 2245 tcsr_2: syscon@1fc0000 { 2246 compatible = "qcom,sc7280-tcsr", "syscon"; 2247 reg = <0 0x01fc0000 0 0x30000>; 2248 }; 2249 2250 lpasscc: lpasscc@3000000 { 2251 compatible = "qcom,sc7280-lpasscc"; 2252 reg = <0 0x03000000 0 0x40>, 2253 <0 0x03c04000 0 0x4>; 2254 reg-names = "qdsp6ss", "top_cc"; 2255 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2256 clock-names = "iface"; 2257 #clock-cells = <1>; 2258 status = "reserved"; /* Owned by ADSP firmware */ 2259 }; 2260 2261 lpass_rx_macro: codec@3200000 { 2262 compatible = "qcom,sc7280-lpass-rx-macro"; 2263 reg = <0 0x03200000 0 0x1000>; 2264 2265 pinctrl-names = "default"; 2266 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2267 2268 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2269 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2270 <&lpass_va_macro>; 2271 clock-names = "mclk", "npl", "fsgen"; 2272 2273 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2274 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2275 power-domain-names = "macro", "dcodec"; 2276 2277 #clock-cells = <0>; 2278 #sound-dai-cells = <1>; 2279 2280 status = "disabled"; 2281 }; 2282 2283 swr0: soundwire@3210000 { 2284 compatible = "qcom,soundwire-v1.6.0"; 2285 reg = <0 0x03210000 0 0x2000>; 2286 2287 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2288 clocks = <&lpass_rx_macro>; 2289 clock-names = "iface"; 2290 2291 qcom,din-ports = <0>; 2292 qcom,dout-ports = <5>; 2293 2294 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2295 reset-names = "swr_audio_cgcr"; 2296 2297 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2298 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2299 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2300 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2301 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2302 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2303 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2304 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2305 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2306 2307 #sound-dai-cells = <1>; 2308 #address-cells = <2>; 2309 #size-cells = <0>; 2310 2311 status = "disabled"; 2312 }; 2313 2314 lpass_tx_macro: codec@3220000 { 2315 compatible = "qcom,sc7280-lpass-tx-macro"; 2316 reg = <0 0x03220000 0 0x1000>; 2317 2318 pinctrl-names = "default"; 2319 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2320 2321 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2322 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2323 <&lpass_va_macro>; 2324 clock-names = "mclk", "npl", "fsgen"; 2325 2326 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2327 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2328 power-domain-names = "macro", "dcodec"; 2329 2330 #clock-cells = <0>; 2331 #sound-dai-cells = <1>; 2332 2333 status = "disabled"; 2334 }; 2335 2336 swr1: soundwire@3230000 { 2337 compatible = "qcom,soundwire-v1.6.0"; 2338 reg = <0 0x03230000 0 0x2000>; 2339 2340 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2341 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2342 clocks = <&lpass_tx_macro>; 2343 clock-names = "iface"; 2344 2345 qcom,din-ports = <3>; 2346 qcom,dout-ports = <0>; 2347 2348 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2349 reset-names = "swr_audio_cgcr"; 2350 2351 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2352 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2353 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2354 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2355 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2356 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2357 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2358 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2359 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2360 2361 #sound-dai-cells = <1>; 2362 #address-cells = <2>; 2363 #size-cells = <0>; 2364 2365 status = "disabled"; 2366 }; 2367 2368 lpass_audiocc: clock-controller@3300000 { 2369 compatible = "qcom,sc7280-lpassaudiocc"; 2370 reg = <0 0x03300000 0 0x30000>, 2371 <0 0x032a9000 0 0x1000>; 2372 clocks = <&rpmhcc RPMH_CXO_CLK>, 2373 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2374 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2375 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2376 #clock-cells = <1>; 2377 #power-domain-cells = <1>; 2378 #reset-cells = <1>; 2379 }; 2380 2381 lpass_va_macro: codec@3370000 { 2382 compatible = "qcom,sc7280-lpass-va-macro"; 2383 reg = <0 0x03370000 0 0x1000>; 2384 2385 pinctrl-names = "default"; 2386 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2387 2388 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2389 clock-names = "mclk"; 2390 2391 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2392 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2393 power-domain-names = "macro", "dcodec"; 2394 2395 #clock-cells = <0>; 2396 #sound-dai-cells = <1>; 2397 2398 status = "disabled"; 2399 }; 2400 2401 lpass_aon: clock-controller@3380000 { 2402 compatible = "qcom,sc7280-lpassaoncc"; 2403 reg = <0 0x03380000 0 0x30000>; 2404 clocks = <&rpmhcc RPMH_CXO_CLK>, 2405 <&rpmhcc RPMH_CXO_CLK_A>, 2406 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2407 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2408 #clock-cells = <1>; 2409 #power-domain-cells = <1>; 2410 status = "reserved"; /* Owned by ADSP firmware */ 2411 }; 2412 2413 lpass_core: clock-controller@3900000 { 2414 compatible = "qcom,sc7280-lpasscorecc"; 2415 reg = <0 0x03900000 0 0x50000>; 2416 clocks = <&rpmhcc RPMH_CXO_CLK>; 2417 clock-names = "bi_tcxo"; 2418 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2419 #clock-cells = <1>; 2420 #power-domain-cells = <1>; 2421 status = "reserved"; /* Owned by ADSP firmware */ 2422 }; 2423 2424 lpass_cpu: audio@3987000 { 2425 compatible = "qcom,sc7280-lpass-cpu"; 2426 2427 reg = <0 0x03987000 0 0x68000>, 2428 <0 0x03b00000 0 0x29000>, 2429 <0 0x03260000 0 0xc000>, 2430 <0 0x03280000 0 0x29000>, 2431 <0 0x03340000 0 0x29000>, 2432 <0 0x0336c000 0 0x3000>; 2433 reg-names = "lpass-hdmiif", 2434 "lpass-lpaif", 2435 "lpass-rxtx-cdc-dma-lpm", 2436 "lpass-rxtx-lpaif", 2437 "lpass-va-lpaif", 2438 "lpass-va-cdc-dma-lpm"; 2439 2440 iommus = <&apps_smmu 0x1820 0>, 2441 <&apps_smmu 0x1821 0>, 2442 <&apps_smmu 0x1832 0>; 2443 2444 power-domains = <&rpmhpd SC7280_LCX>; 2445 power-domain-names = "lcx"; 2446 required-opps = <&rpmhpd_opp_nom>; 2447 2448 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2449 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2450 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2451 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2452 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2453 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2454 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2455 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2456 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2457 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2458 clock-names = "aon_cc_audio_hm_h", 2459 "audio_cc_ext_mclk0", 2460 "core_cc_sysnoc_mport_core", 2461 "core_cc_ext_if0_ibit", 2462 "core_cc_ext_if1_ibit", 2463 "audio_cc_codec_mem", 2464 "audio_cc_codec_mem0", 2465 "audio_cc_codec_mem1", 2466 "audio_cc_codec_mem2", 2467 "aon_cc_va_mem0"; 2468 2469 #sound-dai-cells = <1>; 2470 #address-cells = <1>; 2471 #size-cells = <0>; 2472 2473 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2474 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2475 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2476 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2477 interrupt-names = "lpass-irq-lpaif", 2478 "lpass-irq-hdmi", 2479 "lpass-irq-vaif", 2480 "lpass-irq-rxtxif"; 2481 2482 status = "disabled"; 2483 }; 2484 2485 lpass_hm: clock-controller@3c00000 { 2486 compatible = "qcom,sc7280-lpasshm"; 2487 reg = <0 0x03c00000 0 0x28>; 2488 clocks = <&rpmhcc RPMH_CXO_CLK>; 2489 clock-names = "bi_tcxo"; 2490 #clock-cells = <1>; 2491 #power-domain-cells = <1>; 2492 status = "reserved"; /* Owned by ADSP firmware */ 2493 }; 2494 2495 lpass_ag_noc: interconnect@3c40000 { 2496 reg = <0 0x03c40000 0 0xf080>; 2497 compatible = "qcom,sc7280-lpass-ag-noc"; 2498 #interconnect-cells = <2>; 2499 qcom,bcm-voters = <&apps_bcm_voter>; 2500 }; 2501 2502 lpass_tlmm: pinctrl@33c0000 { 2503 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2504 reg = <0 0x033c0000 0x0 0x20000>, 2505 <0 0x03550000 0x0 0x10000>; 2506 qcom,adsp-bypass-mode; 2507 gpio-controller; 2508 #gpio-cells = <2>; 2509 gpio-ranges = <&lpass_tlmm 0 0 15>; 2510 2511 lpass_dmic01_clk: dmic01-clk-state { 2512 pins = "gpio6"; 2513 function = "dmic1_clk"; 2514 }; 2515 2516 lpass_dmic01_data: dmic01-data-state { 2517 pins = "gpio7"; 2518 function = "dmic1_data"; 2519 }; 2520 2521 lpass_dmic23_clk: dmic23-clk-state { 2522 pins = "gpio8"; 2523 function = "dmic2_clk"; 2524 }; 2525 2526 lpass_dmic23_data: dmic23-data-state { 2527 pins = "gpio9"; 2528 function = "dmic2_data"; 2529 }; 2530 2531 lpass_rx_swr_clk: rx-swr-clk-state { 2532 pins = "gpio3"; 2533 function = "swr_rx_clk"; 2534 }; 2535 2536 lpass_rx_swr_data: rx-swr-data-state { 2537 pins = "gpio4", "gpio5"; 2538 function = "swr_rx_data"; 2539 }; 2540 2541 lpass_tx_swr_clk: tx-swr-clk-state { 2542 pins = "gpio0"; 2543 function = "swr_tx_clk"; 2544 }; 2545 2546 lpass_tx_swr_data: tx-swr-data-state { 2547 pins = "gpio1", "gpio2", "gpio14"; 2548 function = "swr_tx_data"; 2549 }; 2550 }; 2551 2552 gpu: gpu@3d00000 { 2553 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2554 reg = <0 0x03d00000 0 0x40000>, 2555 <0 0x03d9e000 0 0x1000>, 2556 <0 0x03d61000 0 0x800>; 2557 reg-names = "kgsl_3d0_reg_memory", 2558 "cx_mem", 2559 "cx_dbgc"; 2560 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2561 iommus = <&adreno_smmu 0 0x400>, 2562 <&adreno_smmu 1 0x400>; 2563 operating-points-v2 = <&gpu_opp_table>; 2564 qcom,gmu = <&gmu>; 2565 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2566 interconnect-names = "gfx-mem"; 2567 #cooling-cells = <2>; 2568 2569 nvmem-cells = <&gpu_speed_bin>; 2570 nvmem-cell-names = "speed_bin"; 2571 2572 gpu_opp_table: opp-table { 2573 compatible = "operating-points-v2"; 2574 2575 opp-315000000 { 2576 opp-hz = /bits/ 64 <315000000>; 2577 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2578 opp-peak-kBps = <1804000>; 2579 opp-supported-hw = <0x03>; 2580 }; 2581 2582 opp-450000000 { 2583 opp-hz = /bits/ 64 <450000000>; 2584 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2585 opp-peak-kBps = <4068000>; 2586 opp-supported-hw = <0x03>; 2587 }; 2588 2589 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2590 opp-550000000-0 { 2591 opp-hz = /bits/ 64 <550000000>; 2592 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2593 opp-peak-kBps = <8368000>; 2594 opp-supported-hw = <0x01>; 2595 }; 2596 2597 opp-550000000-1 { 2598 opp-hz = /bits/ 64 <550000000>; 2599 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2600 opp-peak-kBps = <6832000>; 2601 opp-supported-hw = <0x02>; 2602 }; 2603 2604 opp-608000000 { 2605 opp-hz = /bits/ 64 <608000000>; 2606 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2607 opp-peak-kBps = <8368000>; 2608 opp-supported-hw = <0x02>; 2609 }; 2610 2611 opp-700000000 { 2612 opp-hz = /bits/ 64 <700000000>; 2613 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2614 opp-peak-kBps = <8532000>; 2615 opp-supported-hw = <0x02>; 2616 }; 2617 2618 opp-812000000 { 2619 opp-hz = /bits/ 64 <812000000>; 2620 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2621 opp-peak-kBps = <8532000>; 2622 opp-supported-hw = <0x02>; 2623 }; 2624 2625 opp-840000000 { 2626 opp-hz = /bits/ 64 <840000000>; 2627 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2628 opp-peak-kBps = <8532000>; 2629 opp-supported-hw = <0x02>; 2630 }; 2631 2632 opp-900000000 { 2633 opp-hz = /bits/ 64 <900000000>; 2634 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2635 opp-peak-kBps = <8532000>; 2636 opp-supported-hw = <0x02>; 2637 }; 2638 }; 2639 }; 2640 2641 gmu: gmu@3d6a000 { 2642 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2643 reg = <0 0x03d6a000 0 0x34000>, 2644 <0 0x3de0000 0 0x10000>, 2645 <0 0x0b290000 0 0x10000>; 2646 reg-names = "gmu", "rscc", "gmu_pdc"; 2647 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2648 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2649 interrupt-names = "hfi", "gmu"; 2650 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2651 <&gpucc GPU_CC_CXO_CLK>, 2652 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2653 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2654 <&gpucc GPU_CC_AHB_CLK>, 2655 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2656 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2657 clock-names = "gmu", 2658 "cxo", 2659 "axi", 2660 "memnoc", 2661 "ahb", 2662 "hub", 2663 "smmu_vote"; 2664 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2665 <&gpucc GPU_CC_GX_GDSC>; 2666 power-domain-names = "cx", 2667 "gx"; 2668 iommus = <&adreno_smmu 5 0x400>; 2669 operating-points-v2 = <&gmu_opp_table>; 2670 2671 gmu_opp_table: opp-table { 2672 compatible = "operating-points-v2"; 2673 2674 opp-200000000 { 2675 opp-hz = /bits/ 64 <200000000>; 2676 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2677 }; 2678 }; 2679 }; 2680 2681 gpucc: clock-controller@3d90000 { 2682 compatible = "qcom,sc7280-gpucc"; 2683 reg = <0 0x03d90000 0 0x9000>; 2684 clocks = <&rpmhcc RPMH_CXO_CLK>, 2685 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2686 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2687 clock-names = "bi_tcxo", 2688 "gcc_gpu_gpll0_clk_src", 2689 "gcc_gpu_gpll0_div_clk_src"; 2690 #clock-cells = <1>; 2691 #reset-cells = <1>; 2692 #power-domain-cells = <1>; 2693 }; 2694 2695 dma@117f000 { 2696 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 2697 reg = <0x0 0x0117f000 0x0 0x1000>, 2698 <0x0 0x01112000 0x0 0x6000>; 2699 }; 2700 2701 adreno_smmu: iommu@3da0000 { 2702 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", 2703 "qcom,smmu-500", "arm,mmu-500"; 2704 reg = <0 0x03da0000 0 0x20000>; 2705 #iommu-cells = <2>; 2706 #global-interrupts = <2>; 2707 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2708 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2709 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2710 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2711 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2712 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2713 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2714 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2715 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2716 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2717 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2718 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2719 2720 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2721 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2722 <&gpucc GPU_CC_AHB_CLK>, 2723 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2724 <&gpucc GPU_CC_CX_GMU_CLK>, 2725 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2726 <&gpucc GPU_CC_HUB_AON_CLK>; 2727 clock-names = "gcc_gpu_memnoc_gfx_clk", 2728 "gcc_gpu_snoc_dvm_gfx_clk", 2729 "gpu_cc_ahb_clk", 2730 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2731 "gpu_cc_cx_gmu_clk", 2732 "gpu_cc_hub_cx_int_clk", 2733 "gpu_cc_hub_aon_clk"; 2734 2735 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2736 }; 2737 2738 remoteproc_mpss: remoteproc@4080000 { 2739 compatible = "qcom,sc7280-mpss-pas"; 2740 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2741 reg-names = "qdsp6", "rmb"; 2742 2743 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2744 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2745 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2746 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2747 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2748 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2749 interrupt-names = "wdog", "fatal", "ready", "handover", 2750 "stop-ack", "shutdown-ack"; 2751 2752 clocks = <&rpmhcc RPMH_CXO_CLK>; 2753 clock-names = "xo"; 2754 2755 power-domains = <&rpmhpd SC7280_CX>, 2756 <&rpmhpd SC7280_MSS>; 2757 power-domain-names = "cx", "mss"; 2758 2759 memory-region = <&mpss_mem>; 2760 2761 qcom,qmp = <&aoss_qmp>; 2762 2763 qcom,smem-states = <&modem_smp2p_out 0>; 2764 qcom,smem-state-names = "stop"; 2765 2766 status = "disabled"; 2767 2768 glink-edge { 2769 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2770 IPCC_MPROC_SIGNAL_GLINK_QMP 2771 IRQ_TYPE_EDGE_RISING>; 2772 mboxes = <&ipcc IPCC_CLIENT_MPSS 2773 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2774 label = "modem"; 2775 qcom,remote-pid = <1>; 2776 }; 2777 }; 2778 2779 stm@6002000 { 2780 compatible = "arm,coresight-stm", "arm,primecell"; 2781 reg = <0 0x06002000 0 0x1000>, 2782 <0 0x16280000 0 0x180000>; 2783 reg-names = "stm-base", "stm-stimulus-base"; 2784 2785 clocks = <&aoss_qmp>; 2786 clock-names = "apb_pclk"; 2787 2788 out-ports { 2789 port { 2790 stm_out: endpoint { 2791 remote-endpoint = <&funnel0_in7>; 2792 }; 2793 }; 2794 }; 2795 }; 2796 2797 funnel@6041000 { 2798 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2799 reg = <0 0x06041000 0 0x1000>; 2800 2801 clocks = <&aoss_qmp>; 2802 clock-names = "apb_pclk"; 2803 2804 out-ports { 2805 port { 2806 funnel0_out: endpoint { 2807 remote-endpoint = <&merge_funnel_in0>; 2808 }; 2809 }; 2810 }; 2811 2812 in-ports { 2813 #address-cells = <1>; 2814 #size-cells = <0>; 2815 2816 port@7 { 2817 reg = <7>; 2818 funnel0_in7: endpoint { 2819 remote-endpoint = <&stm_out>; 2820 }; 2821 }; 2822 }; 2823 }; 2824 2825 funnel@6042000 { 2826 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2827 reg = <0 0x06042000 0 0x1000>; 2828 2829 clocks = <&aoss_qmp>; 2830 clock-names = "apb_pclk"; 2831 2832 out-ports { 2833 port { 2834 funnel1_out: endpoint { 2835 remote-endpoint = <&merge_funnel_in1>; 2836 }; 2837 }; 2838 }; 2839 2840 in-ports { 2841 #address-cells = <1>; 2842 #size-cells = <0>; 2843 2844 port@4 { 2845 reg = <4>; 2846 funnel1_in4: endpoint { 2847 remote-endpoint = <&apss_merge_funnel_out>; 2848 }; 2849 }; 2850 }; 2851 }; 2852 2853 funnel@6045000 { 2854 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2855 reg = <0 0x06045000 0 0x1000>; 2856 2857 clocks = <&aoss_qmp>; 2858 clock-names = "apb_pclk"; 2859 2860 out-ports { 2861 port { 2862 merge_funnel_out: endpoint { 2863 remote-endpoint = <&swao_funnel_in>; 2864 }; 2865 }; 2866 }; 2867 2868 in-ports { 2869 #address-cells = <1>; 2870 #size-cells = <0>; 2871 2872 port@0 { 2873 reg = <0>; 2874 merge_funnel_in0: endpoint { 2875 remote-endpoint = <&funnel0_out>; 2876 }; 2877 }; 2878 2879 port@1 { 2880 reg = <1>; 2881 merge_funnel_in1: endpoint { 2882 remote-endpoint = <&funnel1_out>; 2883 }; 2884 }; 2885 }; 2886 }; 2887 2888 replicator@6046000 { 2889 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2890 reg = <0 0x06046000 0 0x1000>; 2891 2892 clocks = <&aoss_qmp>; 2893 clock-names = "apb_pclk"; 2894 2895 out-ports { 2896 port { 2897 replicator_out: endpoint { 2898 remote-endpoint = <&etr_in>; 2899 }; 2900 }; 2901 }; 2902 2903 in-ports { 2904 port { 2905 replicator_in: endpoint { 2906 remote-endpoint = <&swao_replicator_out>; 2907 }; 2908 }; 2909 }; 2910 }; 2911 2912 etr@6048000 { 2913 compatible = "arm,coresight-tmc", "arm,primecell"; 2914 reg = <0 0x06048000 0 0x1000>; 2915 iommus = <&apps_smmu 0x04c0 0>; 2916 2917 clocks = <&aoss_qmp>; 2918 clock-names = "apb_pclk"; 2919 arm,scatter-gather; 2920 2921 in-ports { 2922 port { 2923 etr_in: endpoint { 2924 remote-endpoint = <&replicator_out>; 2925 }; 2926 }; 2927 }; 2928 }; 2929 2930 funnel@6b04000 { 2931 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2932 reg = <0 0x06b04000 0 0x1000>; 2933 2934 clocks = <&aoss_qmp>; 2935 clock-names = "apb_pclk"; 2936 2937 out-ports { 2938 port { 2939 swao_funnel_out: endpoint { 2940 remote-endpoint = <&etf_in>; 2941 }; 2942 }; 2943 }; 2944 2945 in-ports { 2946 #address-cells = <1>; 2947 #size-cells = <0>; 2948 2949 port@7 { 2950 reg = <7>; 2951 swao_funnel_in: endpoint { 2952 remote-endpoint = <&merge_funnel_out>; 2953 }; 2954 }; 2955 }; 2956 }; 2957 2958 etf@6b05000 { 2959 compatible = "arm,coresight-tmc", "arm,primecell"; 2960 reg = <0 0x06b05000 0 0x1000>; 2961 2962 clocks = <&aoss_qmp>; 2963 clock-names = "apb_pclk"; 2964 2965 out-ports { 2966 port { 2967 etf_out: endpoint { 2968 remote-endpoint = <&swao_replicator_in>; 2969 }; 2970 }; 2971 }; 2972 2973 in-ports { 2974 port { 2975 etf_in: endpoint { 2976 remote-endpoint = <&swao_funnel_out>; 2977 }; 2978 }; 2979 }; 2980 }; 2981 2982 replicator@6b06000 { 2983 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2984 reg = <0 0x06b06000 0 0x1000>; 2985 2986 clocks = <&aoss_qmp>; 2987 clock-names = "apb_pclk"; 2988 qcom,replicator-loses-context; 2989 2990 out-ports { 2991 port { 2992 swao_replicator_out: endpoint { 2993 remote-endpoint = <&replicator_in>; 2994 }; 2995 }; 2996 }; 2997 2998 in-ports { 2999 port { 3000 swao_replicator_in: endpoint { 3001 remote-endpoint = <&etf_out>; 3002 }; 3003 }; 3004 }; 3005 }; 3006 3007 etm@7040000 { 3008 compatible = "arm,coresight-etm4x", "arm,primecell"; 3009 reg = <0 0x07040000 0 0x1000>; 3010 3011 cpu = <&CPU0>; 3012 3013 clocks = <&aoss_qmp>; 3014 clock-names = "apb_pclk"; 3015 arm,coresight-loses-context-with-cpu; 3016 qcom,skip-power-up; 3017 3018 out-ports { 3019 port { 3020 etm0_out: endpoint { 3021 remote-endpoint = <&apss_funnel_in0>; 3022 }; 3023 }; 3024 }; 3025 }; 3026 3027 etm@7140000 { 3028 compatible = "arm,coresight-etm4x", "arm,primecell"; 3029 reg = <0 0x07140000 0 0x1000>; 3030 3031 cpu = <&CPU1>; 3032 3033 clocks = <&aoss_qmp>; 3034 clock-names = "apb_pclk"; 3035 arm,coresight-loses-context-with-cpu; 3036 qcom,skip-power-up; 3037 3038 out-ports { 3039 port { 3040 etm1_out: endpoint { 3041 remote-endpoint = <&apss_funnel_in1>; 3042 }; 3043 }; 3044 }; 3045 }; 3046 3047 etm@7240000 { 3048 compatible = "arm,coresight-etm4x", "arm,primecell"; 3049 reg = <0 0x07240000 0 0x1000>; 3050 3051 cpu = <&CPU2>; 3052 3053 clocks = <&aoss_qmp>; 3054 clock-names = "apb_pclk"; 3055 arm,coresight-loses-context-with-cpu; 3056 qcom,skip-power-up; 3057 3058 out-ports { 3059 port { 3060 etm2_out: endpoint { 3061 remote-endpoint = <&apss_funnel_in2>; 3062 }; 3063 }; 3064 }; 3065 }; 3066 3067 etm@7340000 { 3068 compatible = "arm,coresight-etm4x", "arm,primecell"; 3069 reg = <0 0x07340000 0 0x1000>; 3070 3071 cpu = <&CPU3>; 3072 3073 clocks = <&aoss_qmp>; 3074 clock-names = "apb_pclk"; 3075 arm,coresight-loses-context-with-cpu; 3076 qcom,skip-power-up; 3077 3078 out-ports { 3079 port { 3080 etm3_out: endpoint { 3081 remote-endpoint = <&apss_funnel_in3>; 3082 }; 3083 }; 3084 }; 3085 }; 3086 3087 etm@7440000 { 3088 compatible = "arm,coresight-etm4x", "arm,primecell"; 3089 reg = <0 0x07440000 0 0x1000>; 3090 3091 cpu = <&CPU4>; 3092 3093 clocks = <&aoss_qmp>; 3094 clock-names = "apb_pclk"; 3095 arm,coresight-loses-context-with-cpu; 3096 qcom,skip-power-up; 3097 3098 out-ports { 3099 port { 3100 etm4_out: endpoint { 3101 remote-endpoint = <&apss_funnel_in4>; 3102 }; 3103 }; 3104 }; 3105 }; 3106 3107 etm@7540000 { 3108 compatible = "arm,coresight-etm4x", "arm,primecell"; 3109 reg = <0 0x07540000 0 0x1000>; 3110 3111 cpu = <&CPU5>; 3112 3113 clocks = <&aoss_qmp>; 3114 clock-names = "apb_pclk"; 3115 arm,coresight-loses-context-with-cpu; 3116 qcom,skip-power-up; 3117 3118 out-ports { 3119 port { 3120 etm5_out: endpoint { 3121 remote-endpoint = <&apss_funnel_in5>; 3122 }; 3123 }; 3124 }; 3125 }; 3126 3127 etm@7640000 { 3128 compatible = "arm,coresight-etm4x", "arm,primecell"; 3129 reg = <0 0x07640000 0 0x1000>; 3130 3131 cpu = <&CPU6>; 3132 3133 clocks = <&aoss_qmp>; 3134 clock-names = "apb_pclk"; 3135 arm,coresight-loses-context-with-cpu; 3136 qcom,skip-power-up; 3137 3138 out-ports { 3139 port { 3140 etm6_out: endpoint { 3141 remote-endpoint = <&apss_funnel_in6>; 3142 }; 3143 }; 3144 }; 3145 }; 3146 3147 etm@7740000 { 3148 compatible = "arm,coresight-etm4x", "arm,primecell"; 3149 reg = <0 0x07740000 0 0x1000>; 3150 3151 cpu = <&CPU7>; 3152 3153 clocks = <&aoss_qmp>; 3154 clock-names = "apb_pclk"; 3155 arm,coresight-loses-context-with-cpu; 3156 qcom,skip-power-up; 3157 3158 out-ports { 3159 port { 3160 etm7_out: endpoint { 3161 remote-endpoint = <&apss_funnel_in7>; 3162 }; 3163 }; 3164 }; 3165 }; 3166 3167 funnel@7800000 { /* APSS Funnel */ 3168 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3169 reg = <0 0x07800000 0 0x1000>; 3170 3171 clocks = <&aoss_qmp>; 3172 clock-names = "apb_pclk"; 3173 3174 out-ports { 3175 port { 3176 apss_funnel_out: endpoint { 3177 remote-endpoint = <&apss_merge_funnel_in>; 3178 }; 3179 }; 3180 }; 3181 3182 in-ports { 3183 #address-cells = <1>; 3184 #size-cells = <0>; 3185 3186 port@0 { 3187 reg = <0>; 3188 apss_funnel_in0: endpoint { 3189 remote-endpoint = <&etm0_out>; 3190 }; 3191 }; 3192 3193 port@1 { 3194 reg = <1>; 3195 apss_funnel_in1: endpoint { 3196 remote-endpoint = <&etm1_out>; 3197 }; 3198 }; 3199 3200 port@2 { 3201 reg = <2>; 3202 apss_funnel_in2: endpoint { 3203 remote-endpoint = <&etm2_out>; 3204 }; 3205 }; 3206 3207 port@3 { 3208 reg = <3>; 3209 apss_funnel_in3: endpoint { 3210 remote-endpoint = <&etm3_out>; 3211 }; 3212 }; 3213 3214 port@4 { 3215 reg = <4>; 3216 apss_funnel_in4: endpoint { 3217 remote-endpoint = <&etm4_out>; 3218 }; 3219 }; 3220 3221 port@5 { 3222 reg = <5>; 3223 apss_funnel_in5: endpoint { 3224 remote-endpoint = <&etm5_out>; 3225 }; 3226 }; 3227 3228 port@6 { 3229 reg = <6>; 3230 apss_funnel_in6: endpoint { 3231 remote-endpoint = <&etm6_out>; 3232 }; 3233 }; 3234 3235 port@7 { 3236 reg = <7>; 3237 apss_funnel_in7: endpoint { 3238 remote-endpoint = <&etm7_out>; 3239 }; 3240 }; 3241 }; 3242 }; 3243 3244 funnel@7810000 { 3245 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3246 reg = <0 0x07810000 0 0x1000>; 3247 3248 clocks = <&aoss_qmp>; 3249 clock-names = "apb_pclk"; 3250 3251 out-ports { 3252 port { 3253 apss_merge_funnel_out: endpoint { 3254 remote-endpoint = <&funnel1_in4>; 3255 }; 3256 }; 3257 }; 3258 3259 in-ports { 3260 port { 3261 apss_merge_funnel_in: endpoint { 3262 remote-endpoint = <&apss_funnel_out>; 3263 }; 3264 }; 3265 }; 3266 }; 3267 3268 sdhc_2: mmc@8804000 { 3269 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3270 pinctrl-names = "default", "sleep"; 3271 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3272 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3273 status = "disabled"; 3274 3275 reg = <0 0x08804000 0 0x1000>; 3276 3277 iommus = <&apps_smmu 0x100 0x0>; 3278 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3279 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3280 interrupt-names = "hc_irq", "pwr_irq"; 3281 3282 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3283 <&gcc GCC_SDCC2_APPS_CLK>, 3284 <&rpmhcc RPMH_CXO_CLK>; 3285 clock-names = "iface", "core", "xo"; 3286 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3287 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3288 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3289 power-domains = <&rpmhpd SC7280_CX>; 3290 operating-points-v2 = <&sdhc2_opp_table>; 3291 3292 bus-width = <4>; 3293 3294 qcom,dll-config = <0x0007642c>; 3295 3296 resets = <&gcc GCC_SDCC2_BCR>; 3297 3298 sdhc2_opp_table: opp-table { 3299 compatible = "operating-points-v2"; 3300 3301 opp-100000000 { 3302 opp-hz = /bits/ 64 <100000000>; 3303 required-opps = <&rpmhpd_opp_low_svs>; 3304 opp-peak-kBps = <1800000 400000>; 3305 opp-avg-kBps = <100000 0>; 3306 }; 3307 3308 opp-202000000 { 3309 opp-hz = /bits/ 64 <202000000>; 3310 required-opps = <&rpmhpd_opp_nom>; 3311 opp-peak-kBps = <5400000 1600000>; 3312 opp-avg-kBps = <200000 0>; 3313 }; 3314 }; 3315 }; 3316 3317 usb_1_hsphy: phy@88e3000 { 3318 compatible = "qcom,sc7280-usb-hs-phy", 3319 "qcom,usb-snps-hs-7nm-phy"; 3320 reg = <0 0x088e3000 0 0x400>; 3321 status = "disabled"; 3322 #phy-cells = <0>; 3323 3324 clocks = <&rpmhcc RPMH_CXO_CLK>; 3325 clock-names = "ref"; 3326 3327 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3328 }; 3329 3330 usb_2_hsphy: phy@88e4000 { 3331 compatible = "qcom,sc7280-usb-hs-phy", 3332 "qcom,usb-snps-hs-7nm-phy"; 3333 reg = <0 0x088e4000 0 0x400>; 3334 status = "disabled"; 3335 #phy-cells = <0>; 3336 3337 clocks = <&rpmhcc RPMH_CXO_CLK>; 3338 clock-names = "ref"; 3339 3340 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3341 }; 3342 3343 usb_1_qmpphy: phy-wrapper@88e9000 { 3344 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3345 "qcom,sm8250-qmp-usb3-dp-phy"; 3346 reg = <0 0x088e9000 0 0x200>, 3347 <0 0x088e8000 0 0x40>, 3348 <0 0x088ea000 0 0x200>; 3349 status = "disabled"; 3350 #address-cells = <2>; 3351 #size-cells = <2>; 3352 ranges; 3353 3354 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3355 <&rpmhcc RPMH_CXO_CLK>, 3356 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3357 clock-names = "aux", "ref_clk_src", "com_aux"; 3358 3359 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3360 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3361 reset-names = "phy", "common"; 3362 3363 usb_1_ssphy: usb3-phy@88e9200 { 3364 reg = <0 0x088e9200 0 0x200>, 3365 <0 0x088e9400 0 0x200>, 3366 <0 0x088e9c00 0 0x400>, 3367 <0 0x088e9600 0 0x200>, 3368 <0 0x088e9800 0 0x200>, 3369 <0 0x088e9a00 0 0x100>; 3370 #clock-cells = <0>; 3371 #phy-cells = <0>; 3372 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3373 clock-names = "pipe0"; 3374 clock-output-names = "usb3_phy_pipe_clk_src"; 3375 }; 3376 3377 dp_phy: dp-phy@88ea200 { 3378 reg = <0 0x088ea200 0 0x200>, 3379 <0 0x088ea400 0 0x200>, 3380 <0 0x088eaa00 0 0x200>, 3381 <0 0x088ea600 0 0x200>, 3382 <0 0x088ea800 0 0x200>; 3383 #phy-cells = <0>; 3384 #clock-cells = <1>; 3385 }; 3386 }; 3387 3388 usb_2: usb@8cf8800 { 3389 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3390 reg = <0 0x08cf8800 0 0x400>; 3391 status = "disabled"; 3392 #address-cells = <2>; 3393 #size-cells = <2>; 3394 ranges; 3395 dma-ranges; 3396 3397 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3398 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3399 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3400 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3401 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3402 clock-names = "cfg_noc", 3403 "core", 3404 "iface", 3405 "sleep", 3406 "mock_utmi"; 3407 3408 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3409 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3410 assigned-clock-rates = <19200000>, <200000000>; 3411 3412 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3413 <&pdc 12 IRQ_TYPE_EDGE_RISING>, 3414 <&pdc 13 IRQ_TYPE_EDGE_RISING>; 3415 interrupt-names = "hs_phy_irq", 3416 "dp_hs_phy_irq", 3417 "dm_hs_phy_irq"; 3418 3419 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3420 required-opps = <&rpmhpd_opp_nom>; 3421 3422 resets = <&gcc GCC_USB30_SEC_BCR>; 3423 3424 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3425 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3426 interconnect-names = "usb-ddr", "apps-usb"; 3427 3428 usb_2_dwc3: usb@8c00000 { 3429 compatible = "snps,dwc3"; 3430 reg = <0 0x08c00000 0 0xe000>; 3431 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3432 iommus = <&apps_smmu 0xa0 0x0>; 3433 snps,dis_u2_susphy_quirk; 3434 snps,dis_enblslpm_quirk; 3435 phys = <&usb_2_hsphy>; 3436 phy-names = "usb2-phy"; 3437 maximum-speed = "high-speed"; 3438 usb-role-switch; 3439 3440 port { 3441 usb2_role_switch: endpoint { 3442 remote-endpoint = <&eud_ep>; 3443 }; 3444 }; 3445 }; 3446 }; 3447 3448 qspi: spi@88dc000 { 3449 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3450 reg = <0 0x088dc000 0 0x1000>; 3451 iommus = <&apps_smmu 0x20 0x0>; 3452 #address-cells = <1>; 3453 #size-cells = <0>; 3454 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3455 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3456 <&gcc GCC_QSPI_CORE_CLK>; 3457 clock-names = "iface", "core"; 3458 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3459 &cnoc2 SLAVE_QSPI_0 0>; 3460 interconnect-names = "qspi-config"; 3461 power-domains = <&rpmhpd SC7280_CX>; 3462 operating-points-v2 = <&qspi_opp_table>; 3463 status = "disabled"; 3464 }; 3465 3466 remoteproc_wpss: remoteproc@8a00000 { 3467 compatible = "qcom,sc7280-wpss-pil"; 3468 reg = <0 0x08a00000 0 0x10000>; 3469 3470 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3471 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3472 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3473 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3474 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3475 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3476 interrupt-names = "wdog", "fatal", "ready", "handover", 3477 "stop-ack", "shutdown-ack"; 3478 3479 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3480 <&gcc GCC_WPSS_AHB_CLK>, 3481 <&gcc GCC_WPSS_RSCP_CLK>, 3482 <&rpmhcc RPMH_CXO_CLK>; 3483 clock-names = "ahb_bdg", "ahb", 3484 "rscp", "xo"; 3485 3486 power-domains = <&rpmhpd SC7280_CX>, 3487 <&rpmhpd SC7280_MX>; 3488 power-domain-names = "cx", "mx"; 3489 3490 memory-region = <&wpss_mem>; 3491 3492 qcom,qmp = <&aoss_qmp>; 3493 3494 qcom,smem-states = <&wpss_smp2p_out 0>; 3495 qcom,smem-state-names = "stop"; 3496 3497 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3498 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3499 reset-names = "restart", "pdc_sync"; 3500 3501 qcom,halt-regs = <&tcsr_1 0x17000>; 3502 3503 status = "disabled"; 3504 3505 glink-edge { 3506 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3507 IPCC_MPROC_SIGNAL_GLINK_QMP 3508 IRQ_TYPE_EDGE_RISING>; 3509 mboxes = <&ipcc IPCC_CLIENT_WPSS 3510 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3511 3512 label = "wpss"; 3513 qcom,remote-pid = <13>; 3514 }; 3515 }; 3516 3517 pmu@9091000 { 3518 compatible = "qcom,sc7280-llcc-bwmon"; 3519 reg = <0 0x09091000 0 0x1000>; 3520 3521 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3522 3523 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3524 3525 operating-points-v2 = <&llcc_bwmon_opp_table>; 3526 3527 llcc_bwmon_opp_table: opp-table { 3528 compatible = "operating-points-v2"; 3529 3530 opp-0 { 3531 opp-peak-kBps = <800000>; 3532 }; 3533 opp-1 { 3534 opp-peak-kBps = <1804000>; 3535 }; 3536 opp-2 { 3537 opp-peak-kBps = <2188000>; 3538 }; 3539 opp-3 { 3540 opp-peak-kBps = <3072000>; 3541 }; 3542 opp-4 { 3543 opp-peak-kBps = <4068000>; 3544 }; 3545 opp-5 { 3546 opp-peak-kBps = <6220000>; 3547 }; 3548 opp-6 { 3549 opp-peak-kBps = <6832000>; 3550 }; 3551 opp-7 { 3552 opp-peak-kBps = <8532000>; 3553 }; 3554 }; 3555 }; 3556 3557 pmu@90b6400 { 3558 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; 3559 reg = <0 0x090b6400 0 0x600>; 3560 3561 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3562 3563 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3564 operating-points-v2 = <&cpu_bwmon_opp_table>; 3565 3566 cpu_bwmon_opp_table: opp-table { 3567 compatible = "operating-points-v2"; 3568 3569 opp-0 { 3570 opp-peak-kBps = <2400000>; 3571 }; 3572 opp-1 { 3573 opp-peak-kBps = <4800000>; 3574 }; 3575 opp-2 { 3576 opp-peak-kBps = <7456000>; 3577 }; 3578 opp-3 { 3579 opp-peak-kBps = <9600000>; 3580 }; 3581 opp-4 { 3582 opp-peak-kBps = <12896000>; 3583 }; 3584 opp-5 { 3585 opp-peak-kBps = <14928000>; 3586 }; 3587 opp-6 { 3588 opp-peak-kBps = <17056000>; 3589 }; 3590 }; 3591 }; 3592 3593 dc_noc: interconnect@90e0000 { 3594 reg = <0 0x090e0000 0 0x5080>; 3595 compatible = "qcom,sc7280-dc-noc"; 3596 #interconnect-cells = <2>; 3597 qcom,bcm-voters = <&apps_bcm_voter>; 3598 }; 3599 3600 gem_noc: interconnect@9100000 { 3601 reg = <0 0x09100000 0 0xe2200>; 3602 compatible = "qcom,sc7280-gem-noc"; 3603 #interconnect-cells = <2>; 3604 qcom,bcm-voters = <&apps_bcm_voter>; 3605 }; 3606 3607 system-cache-controller@9200000 { 3608 compatible = "qcom,sc7280-llcc"; 3609 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3610 <0 0x09600000 0 0x58000>; 3611 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; 3612 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3613 }; 3614 3615 eud: eud@88e0000 { 3616 compatible = "qcom,sc7280-eud", "qcom,eud"; 3617 reg = <0 0x88e0000 0 0x2000>, 3618 <0 0x88e2000 0 0x1000>; 3619 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3620 3621 status = "disabled"; 3622 3623 ports { 3624 #address-cells = <1>; 3625 #size-cells = <0>; 3626 3627 port@0 { 3628 reg = <0>; 3629 eud_ep: endpoint { 3630 remote-endpoint = <&usb2_role_switch>; 3631 }; 3632 }; 3633 }; 3634 }; 3635 3636 nsp_noc: interconnect@a0c0000 { 3637 reg = <0 0x0a0c0000 0 0x10000>; 3638 compatible = "qcom,sc7280-nsp-noc"; 3639 #interconnect-cells = <2>; 3640 qcom,bcm-voters = <&apps_bcm_voter>; 3641 }; 3642 3643 usb_1: usb@a6f8800 { 3644 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3645 reg = <0 0x0a6f8800 0 0x400>; 3646 status = "disabled"; 3647 #address-cells = <2>; 3648 #size-cells = <2>; 3649 ranges; 3650 dma-ranges; 3651 3652 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3653 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3654 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3655 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3656 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3657 clock-names = "cfg_noc", 3658 "core", 3659 "iface", 3660 "sleep", 3661 "mock_utmi"; 3662 3663 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3664 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3665 assigned-clock-rates = <19200000>, <200000000>; 3666 3667 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3668 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3669 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3670 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3671 interrupt-names = "hs_phy_irq", 3672 "dp_hs_phy_irq", 3673 "dm_hs_phy_irq", 3674 "ss_phy_irq"; 3675 3676 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3677 required-opps = <&rpmhpd_opp_nom>; 3678 3679 resets = <&gcc GCC_USB30_PRIM_BCR>; 3680 3681 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3682 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3683 interconnect-names = "usb-ddr", "apps-usb"; 3684 3685 wakeup-source; 3686 3687 usb_1_dwc3: usb@a600000 { 3688 compatible = "snps,dwc3"; 3689 reg = <0 0x0a600000 0 0xe000>; 3690 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3691 iommus = <&apps_smmu 0xe0 0x0>; 3692 snps,dis_u2_susphy_quirk; 3693 snps,dis_enblslpm_quirk; 3694 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3695 phy-names = "usb2-phy", "usb3-phy"; 3696 maximum-speed = "super-speed"; 3697 }; 3698 }; 3699 3700 venus: video-codec@aa00000 { 3701 compatible = "qcom,sc7280-venus"; 3702 reg = <0 0x0aa00000 0 0xd0600>; 3703 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3704 3705 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3706 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3707 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3708 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3709 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3710 clock-names = "core", "bus", "iface", 3711 "vcodec_core", "vcodec_bus"; 3712 3713 power-domains = <&videocc MVSC_GDSC>, 3714 <&videocc MVS0_GDSC>, 3715 <&rpmhpd SC7280_CX>; 3716 power-domain-names = "venus", "vcodec0", "cx"; 3717 operating-points-v2 = <&venus_opp_table>; 3718 3719 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3720 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3721 interconnect-names = "cpu-cfg", "video-mem"; 3722 3723 iommus = <&apps_smmu 0x2180 0x20>, 3724 <&apps_smmu 0x2184 0x20>; 3725 memory-region = <&video_mem>; 3726 3727 video-decoder { 3728 compatible = "venus-decoder"; 3729 }; 3730 3731 video-encoder { 3732 compatible = "venus-encoder"; 3733 }; 3734 3735 video-firmware { 3736 iommus = <&apps_smmu 0x21a2 0x0>; 3737 }; 3738 3739 venus_opp_table: opp-table { 3740 compatible = "operating-points-v2"; 3741 3742 opp-133330000 { 3743 opp-hz = /bits/ 64 <133330000>; 3744 required-opps = <&rpmhpd_opp_low_svs>; 3745 }; 3746 3747 opp-240000000 { 3748 opp-hz = /bits/ 64 <240000000>; 3749 required-opps = <&rpmhpd_opp_svs>; 3750 }; 3751 3752 opp-335000000 { 3753 opp-hz = /bits/ 64 <335000000>; 3754 required-opps = <&rpmhpd_opp_svs_l1>; 3755 }; 3756 3757 opp-424000000 { 3758 opp-hz = /bits/ 64 <424000000>; 3759 required-opps = <&rpmhpd_opp_nom>; 3760 }; 3761 3762 opp-460000048 { 3763 opp-hz = /bits/ 64 <460000048>; 3764 required-opps = <&rpmhpd_opp_turbo>; 3765 }; 3766 }; 3767 }; 3768 3769 videocc: clock-controller@aaf0000 { 3770 compatible = "qcom,sc7280-videocc"; 3771 reg = <0 0x0aaf0000 0 0x10000>; 3772 clocks = <&rpmhcc RPMH_CXO_CLK>, 3773 <&rpmhcc RPMH_CXO_CLK_A>; 3774 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3775 #clock-cells = <1>; 3776 #reset-cells = <1>; 3777 #power-domain-cells = <1>; 3778 }; 3779 3780 camcc: clock-controller@ad00000 { 3781 compatible = "qcom,sc7280-camcc"; 3782 reg = <0 0x0ad00000 0 0x10000>; 3783 clocks = <&rpmhcc RPMH_CXO_CLK>, 3784 <&rpmhcc RPMH_CXO_CLK_A>, 3785 <&sleep_clk>; 3786 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3787 #clock-cells = <1>; 3788 #reset-cells = <1>; 3789 #power-domain-cells = <1>; 3790 }; 3791 3792 dispcc: clock-controller@af00000 { 3793 compatible = "qcom,sc7280-dispcc"; 3794 reg = <0 0x0af00000 0 0x20000>; 3795 clocks = <&rpmhcc RPMH_CXO_CLK>, 3796 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3797 <&mdss_dsi_phy 0>, 3798 <&mdss_dsi_phy 1>, 3799 <&dp_phy 0>, 3800 <&dp_phy 1>, 3801 <&mdss_edp_phy 0>, 3802 <&mdss_edp_phy 1>; 3803 clock-names = "bi_tcxo", 3804 "gcc_disp_gpll0_clk", 3805 "dsi0_phy_pll_out_byteclk", 3806 "dsi0_phy_pll_out_dsiclk", 3807 "dp_phy_pll_link_clk", 3808 "dp_phy_pll_vco_div_clk", 3809 "edp_phy_pll_link_clk", 3810 "edp_phy_pll_vco_div_clk"; 3811 #clock-cells = <1>; 3812 #reset-cells = <1>; 3813 #power-domain-cells = <1>; 3814 }; 3815 3816 mdss: display-subsystem@ae00000 { 3817 compatible = "qcom,sc7280-mdss"; 3818 reg = <0 0x0ae00000 0 0x1000>; 3819 reg-names = "mdss"; 3820 3821 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3822 3823 clocks = <&gcc GCC_DISP_AHB_CLK>, 3824 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3825 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3826 clock-names = "iface", 3827 "ahb", 3828 "core"; 3829 3830 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3831 interrupt-controller; 3832 #interrupt-cells = <1>; 3833 3834 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3835 interconnect-names = "mdp0-mem"; 3836 3837 iommus = <&apps_smmu 0x900 0x402>; 3838 3839 #address-cells = <2>; 3840 #size-cells = <2>; 3841 ranges; 3842 3843 status = "disabled"; 3844 3845 mdss_mdp: display-controller@ae01000 { 3846 compatible = "qcom,sc7280-dpu"; 3847 reg = <0 0x0ae01000 0 0x8f030>, 3848 <0 0x0aeb0000 0 0x2008>; 3849 reg-names = "mdp", "vbif"; 3850 3851 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3852 <&gcc GCC_DISP_SF_AXI_CLK>, 3853 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3854 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3855 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3856 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3857 clock-names = "bus", 3858 "nrt_bus", 3859 "iface", 3860 "lut", 3861 "core", 3862 "vsync"; 3863 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3864 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3865 assigned-clock-rates = <19200000>, 3866 <19200000>; 3867 operating-points-v2 = <&mdp_opp_table>; 3868 power-domains = <&rpmhpd SC7280_CX>; 3869 3870 interrupt-parent = <&mdss>; 3871 interrupts = <0>; 3872 3873 ports { 3874 #address-cells = <1>; 3875 #size-cells = <0>; 3876 3877 port@0 { 3878 reg = <0>; 3879 dpu_intf1_out: endpoint { 3880 remote-endpoint = <&mdss_dsi0_in>; 3881 }; 3882 }; 3883 3884 port@1 { 3885 reg = <1>; 3886 dpu_intf5_out: endpoint { 3887 remote-endpoint = <&edp_in>; 3888 }; 3889 }; 3890 3891 port@2 { 3892 reg = <2>; 3893 dpu_intf0_out: endpoint { 3894 remote-endpoint = <&dp_in>; 3895 }; 3896 }; 3897 }; 3898 3899 mdp_opp_table: opp-table { 3900 compatible = "operating-points-v2"; 3901 3902 opp-200000000 { 3903 opp-hz = /bits/ 64 <200000000>; 3904 required-opps = <&rpmhpd_opp_low_svs>; 3905 }; 3906 3907 opp-300000000 { 3908 opp-hz = /bits/ 64 <300000000>; 3909 required-opps = <&rpmhpd_opp_svs>; 3910 }; 3911 3912 opp-380000000 { 3913 opp-hz = /bits/ 64 <380000000>; 3914 required-opps = <&rpmhpd_opp_svs_l1>; 3915 }; 3916 3917 opp-506666667 { 3918 opp-hz = /bits/ 64 <506666667>; 3919 required-opps = <&rpmhpd_opp_nom>; 3920 }; 3921 }; 3922 }; 3923 3924 mdss_dsi: dsi@ae94000 { 3925 compatible = "qcom,sc7280-dsi-ctrl", 3926 "qcom,mdss-dsi-ctrl"; 3927 reg = <0 0x0ae94000 0 0x400>; 3928 reg-names = "dsi_ctrl"; 3929 3930 interrupt-parent = <&mdss>; 3931 interrupts = <4>; 3932 3933 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3934 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3935 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3936 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3937 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3938 <&gcc GCC_DISP_HF_AXI_CLK>; 3939 clock-names = "byte", 3940 "byte_intf", 3941 "pixel", 3942 "core", 3943 "iface", 3944 "bus"; 3945 3946 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3947 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; 3948 3949 operating-points-v2 = <&dsi_opp_table>; 3950 power-domains = <&rpmhpd SC7280_CX>; 3951 3952 phys = <&mdss_dsi_phy>; 3953 3954 #address-cells = <1>; 3955 #size-cells = <0>; 3956 3957 status = "disabled"; 3958 3959 ports { 3960 #address-cells = <1>; 3961 #size-cells = <0>; 3962 3963 port@0 { 3964 reg = <0>; 3965 mdss_dsi0_in: endpoint { 3966 remote-endpoint = <&dpu_intf1_out>; 3967 }; 3968 }; 3969 3970 port@1 { 3971 reg = <1>; 3972 mdss_dsi0_out: endpoint { 3973 }; 3974 }; 3975 }; 3976 3977 dsi_opp_table: opp-table { 3978 compatible = "operating-points-v2"; 3979 3980 opp-187500000 { 3981 opp-hz = /bits/ 64 <187500000>; 3982 required-opps = <&rpmhpd_opp_low_svs>; 3983 }; 3984 3985 opp-300000000 { 3986 opp-hz = /bits/ 64 <300000000>; 3987 required-opps = <&rpmhpd_opp_svs>; 3988 }; 3989 3990 opp-358000000 { 3991 opp-hz = /bits/ 64 <358000000>; 3992 required-opps = <&rpmhpd_opp_svs_l1>; 3993 }; 3994 }; 3995 }; 3996 3997 mdss_dsi_phy: phy@ae94400 { 3998 compatible = "qcom,sc7280-dsi-phy-7nm"; 3999 reg = <0 0x0ae94400 0 0x200>, 4000 <0 0x0ae94600 0 0x280>, 4001 <0 0x0ae94900 0 0x280>; 4002 reg-names = "dsi_phy", 4003 "dsi_phy_lane", 4004 "dsi_pll"; 4005 4006 #clock-cells = <1>; 4007 #phy-cells = <0>; 4008 4009 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4010 <&rpmhcc RPMH_CXO_CLK>; 4011 clock-names = "iface", "ref"; 4012 4013 status = "disabled"; 4014 }; 4015 4016 mdss_edp: edp@aea0000 { 4017 compatible = "qcom,sc7280-edp"; 4018 pinctrl-names = "default"; 4019 pinctrl-0 = <&edp_hot_plug_det>; 4020 4021 reg = <0 0x0aea0000 0 0x200>, 4022 <0 0x0aea0200 0 0x200>, 4023 <0 0x0aea0400 0 0xc00>, 4024 <0 0x0aea1000 0 0x400>; 4025 4026 interrupt-parent = <&mdss>; 4027 interrupts = <14>; 4028 4029 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4030 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4031 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4032 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4033 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4034 clock-names = "core_iface", 4035 "core_aux", 4036 "ctrl_link", 4037 "ctrl_link_iface", 4038 "stream_pixel"; 4039 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4040 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4041 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4042 4043 phys = <&mdss_edp_phy>; 4044 phy-names = "dp"; 4045 4046 operating-points-v2 = <&edp_opp_table>; 4047 power-domains = <&rpmhpd SC7280_CX>; 4048 4049 status = "disabled"; 4050 4051 ports { 4052 #address-cells = <1>; 4053 #size-cells = <0>; 4054 4055 port@0 { 4056 reg = <0>; 4057 edp_in: endpoint { 4058 remote-endpoint = <&dpu_intf5_out>; 4059 }; 4060 }; 4061 4062 port@1 { 4063 reg = <1>; 4064 mdss_edp_out: endpoint { }; 4065 }; 4066 }; 4067 4068 edp_opp_table: opp-table { 4069 compatible = "operating-points-v2"; 4070 4071 opp-160000000 { 4072 opp-hz = /bits/ 64 <160000000>; 4073 required-opps = <&rpmhpd_opp_low_svs>; 4074 }; 4075 4076 opp-270000000 { 4077 opp-hz = /bits/ 64 <270000000>; 4078 required-opps = <&rpmhpd_opp_svs>; 4079 }; 4080 4081 opp-540000000 { 4082 opp-hz = /bits/ 64 <540000000>; 4083 required-opps = <&rpmhpd_opp_nom>; 4084 }; 4085 4086 opp-810000000 { 4087 opp-hz = /bits/ 64 <810000000>; 4088 required-opps = <&rpmhpd_opp_nom>; 4089 }; 4090 }; 4091 }; 4092 4093 mdss_edp_phy: phy@aec2a00 { 4094 compatible = "qcom,sc7280-edp-phy"; 4095 4096 reg = <0 0x0aec2a00 0 0x19c>, 4097 <0 0x0aec2200 0 0xa0>, 4098 <0 0x0aec2600 0 0xa0>, 4099 <0 0x0aec2000 0 0x1c0>; 4100 4101 clocks = <&rpmhcc RPMH_CXO_CLK>, 4102 <&gcc GCC_EDP_CLKREF_EN>; 4103 clock-names = "aux", 4104 "cfg_ahb"; 4105 4106 #clock-cells = <1>; 4107 #phy-cells = <0>; 4108 4109 status = "disabled"; 4110 }; 4111 4112 mdss_dp: displayport-controller@ae90000 { 4113 compatible = "qcom,sc7280-dp"; 4114 4115 reg = <0 0x0ae90000 0 0x200>, 4116 <0 0x0ae90200 0 0x200>, 4117 <0 0x0ae90400 0 0xc00>, 4118 <0 0x0ae91000 0 0x400>, 4119 <0 0x0ae91400 0 0x400>; 4120 4121 interrupt-parent = <&mdss>; 4122 interrupts = <12>; 4123 4124 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4125 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4126 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4127 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4128 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4129 clock-names = "core_iface", 4130 "core_aux", 4131 "ctrl_link", 4132 "ctrl_link_iface", 4133 "stream_pixel"; 4134 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4135 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4136 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4137 phys = <&dp_phy>; 4138 phy-names = "dp"; 4139 4140 operating-points-v2 = <&dp_opp_table>; 4141 power-domains = <&rpmhpd SC7280_CX>; 4142 4143 #sound-dai-cells = <0>; 4144 4145 status = "disabled"; 4146 4147 ports { 4148 #address-cells = <1>; 4149 #size-cells = <0>; 4150 4151 port@0 { 4152 reg = <0>; 4153 dp_in: endpoint { 4154 remote-endpoint = <&dpu_intf0_out>; 4155 }; 4156 }; 4157 4158 port@1 { 4159 reg = <1>; 4160 mdss_dp_out: endpoint { }; 4161 }; 4162 }; 4163 4164 dp_opp_table: opp-table { 4165 compatible = "operating-points-v2"; 4166 4167 opp-160000000 { 4168 opp-hz = /bits/ 64 <160000000>; 4169 required-opps = <&rpmhpd_opp_low_svs>; 4170 }; 4171 4172 opp-270000000 { 4173 opp-hz = /bits/ 64 <270000000>; 4174 required-opps = <&rpmhpd_opp_svs>; 4175 }; 4176 4177 opp-540000000 { 4178 opp-hz = /bits/ 64 <540000000>; 4179 required-opps = <&rpmhpd_opp_svs_l1>; 4180 }; 4181 4182 opp-810000000 { 4183 opp-hz = /bits/ 64 <810000000>; 4184 required-opps = <&rpmhpd_opp_nom>; 4185 }; 4186 }; 4187 }; 4188 }; 4189 4190 pdc: interrupt-controller@b220000 { 4191 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4192 reg = <0 0x0b220000 0 0x30000>; 4193 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4194 <55 306 4>, <59 312 3>, <62 374 2>, 4195 <64 434 2>, <66 438 3>, <69 86 1>, 4196 <70 520 54>, <124 609 31>, <155 63 1>, 4197 <156 716 12>; 4198 #interrupt-cells = <2>; 4199 interrupt-parent = <&intc>; 4200 interrupt-controller; 4201 }; 4202 4203 pdc_reset: reset-controller@b5e0000 { 4204 compatible = "qcom,sc7280-pdc-global"; 4205 reg = <0 0x0b5e0000 0 0x20000>; 4206 #reset-cells = <1>; 4207 status = "reserved"; /* Owned by firmware */ 4208 }; 4209 4210 tsens0: thermal-sensor@c263000 { 4211 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4212 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4213 <0 0x0c222000 0 0x1ff>; /* SROT */ 4214 #qcom,sensors = <15>; 4215 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4216 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4217 interrupt-names = "uplow","critical"; 4218 #thermal-sensor-cells = <1>; 4219 }; 4220 4221 tsens1: thermal-sensor@c265000 { 4222 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4223 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4224 <0 0x0c223000 0 0x1ff>; /* SROT */ 4225 #qcom,sensors = <12>; 4226 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4227 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4228 interrupt-names = "uplow","critical"; 4229 #thermal-sensor-cells = <1>; 4230 }; 4231 4232 aoss_reset: reset-controller@c2a0000 { 4233 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4234 reg = <0 0x0c2a0000 0 0x31000>; 4235 #reset-cells = <1>; 4236 }; 4237 4238 aoss_qmp: power-management@c300000 { 4239 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4240 reg = <0 0x0c300000 0 0x400>; 4241 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4242 IPCC_MPROC_SIGNAL_GLINK_QMP 4243 IRQ_TYPE_EDGE_RISING>; 4244 mboxes = <&ipcc IPCC_CLIENT_AOP 4245 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4246 4247 #clock-cells = <0>; 4248 }; 4249 4250 sram@c3f0000 { 4251 compatible = "qcom,rpmh-stats"; 4252 reg = <0 0x0c3f0000 0 0x400>; 4253 }; 4254 4255 spmi_bus: spmi@c440000 { 4256 compatible = "qcom,spmi-pmic-arb"; 4257 reg = <0 0x0c440000 0 0x1100>, 4258 <0 0x0c600000 0 0x2000000>, 4259 <0 0x0e600000 0 0x100000>, 4260 <0 0x0e700000 0 0xa0000>, 4261 <0 0x0c40a000 0 0x26000>; 4262 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4263 interrupt-names = "periph_irq"; 4264 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4265 qcom,ee = <0>; 4266 qcom,channel = <0>; 4267 #address-cells = <2>; 4268 #size-cells = <0>; 4269 interrupt-controller; 4270 #interrupt-cells = <4>; 4271 }; 4272 4273 tlmm: pinctrl@f100000 { 4274 compatible = "qcom,sc7280-pinctrl"; 4275 reg = <0 0x0f100000 0 0x300000>; 4276 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4277 gpio-controller; 4278 #gpio-cells = <2>; 4279 interrupt-controller; 4280 #interrupt-cells = <2>; 4281 gpio-ranges = <&tlmm 0 0 175>; 4282 wakeup-parent = <&pdc>; 4283 4284 dp_hot_plug_det: dp-hot-plug-det-state { 4285 pins = "gpio47"; 4286 function = "dp_hot"; 4287 }; 4288 4289 edp_hot_plug_det: edp-hot-plug-det-state { 4290 pins = "gpio60"; 4291 function = "edp_hot"; 4292 }; 4293 4294 mi2s0_data0: mi2s0-data0-state { 4295 pins = "gpio98"; 4296 function = "mi2s0_data0"; 4297 }; 4298 4299 mi2s0_data1: mi2s0-data1-state { 4300 pins = "gpio99"; 4301 function = "mi2s0_data1"; 4302 }; 4303 4304 mi2s0_mclk: mi2s0-mclk-state { 4305 pins = "gpio96"; 4306 function = "pri_mi2s"; 4307 }; 4308 4309 mi2s0_sclk: mi2s0-sclk-state { 4310 pins = "gpio97"; 4311 function = "mi2s0_sck"; 4312 }; 4313 4314 mi2s0_ws: mi2s0-ws-state { 4315 pins = "gpio100"; 4316 function = "mi2s0_ws"; 4317 }; 4318 4319 mi2s1_data0: mi2s1-data0-state { 4320 pins = "gpio107"; 4321 function = "mi2s1_data0"; 4322 }; 4323 4324 mi2s1_sclk: mi2s1-sclk-state { 4325 pins = "gpio106"; 4326 function = "mi2s1_sck"; 4327 }; 4328 4329 mi2s1_ws: mi2s1-ws-state { 4330 pins = "gpio108"; 4331 function = "mi2s1_ws"; 4332 }; 4333 4334 pcie1_clkreq_n: pcie1-clkreq-n-state { 4335 pins = "gpio79"; 4336 function = "pcie1_clkreqn"; 4337 }; 4338 4339 qspi_clk: qspi-clk-state { 4340 pins = "gpio14"; 4341 function = "qspi_clk"; 4342 }; 4343 4344 qspi_cs0: qspi-cs0-state { 4345 pins = "gpio15"; 4346 function = "qspi_cs"; 4347 }; 4348 4349 qspi_cs1: qspi-cs1-state { 4350 pins = "gpio19"; 4351 function = "qspi_cs"; 4352 }; 4353 4354 qspi_data0: qspi-data0-state { 4355 pins = "gpio12"; 4356 function = "qspi_data"; 4357 }; 4358 4359 qspi_data1: qspi-data1-state { 4360 pins = "gpio13"; 4361 function = "qspi_data"; 4362 }; 4363 4364 qspi_data23: qspi-data23-state { 4365 pins = "gpio16", "gpio17"; 4366 function = "qspi_data"; 4367 }; 4368 4369 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4370 pins = "gpio0", "gpio1"; 4371 function = "qup00"; 4372 }; 4373 4374 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4375 pins = "gpio4", "gpio5"; 4376 function = "qup01"; 4377 }; 4378 4379 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4380 pins = "gpio8", "gpio9"; 4381 function = "qup02"; 4382 }; 4383 4384 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4385 pins = "gpio12", "gpio13"; 4386 function = "qup03"; 4387 }; 4388 4389 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4390 pins = "gpio16", "gpio17"; 4391 function = "qup04"; 4392 }; 4393 4394 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4395 pins = "gpio20", "gpio21"; 4396 function = "qup05"; 4397 }; 4398 4399 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4400 pins = "gpio24", "gpio25"; 4401 function = "qup06"; 4402 }; 4403 4404 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4405 pins = "gpio28", "gpio29"; 4406 function = "qup07"; 4407 }; 4408 4409 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4410 pins = "gpio32", "gpio33"; 4411 function = "qup10"; 4412 }; 4413 4414 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4415 pins = "gpio36", "gpio37"; 4416 function = "qup11"; 4417 }; 4418 4419 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4420 pins = "gpio40", "gpio41"; 4421 function = "qup12"; 4422 }; 4423 4424 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4425 pins = "gpio44", "gpio45"; 4426 function = "qup13"; 4427 }; 4428 4429 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4430 pins = "gpio48", "gpio49"; 4431 function = "qup14"; 4432 }; 4433 4434 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4435 pins = "gpio52", "gpio53"; 4436 function = "qup15"; 4437 }; 4438 4439 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4440 pins = "gpio56", "gpio57"; 4441 function = "qup16"; 4442 }; 4443 4444 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4445 pins = "gpio60", "gpio61"; 4446 function = "qup17"; 4447 }; 4448 4449 qup_spi0_data_clk: qup-spi0-data-clk-state { 4450 pins = "gpio0", "gpio1", "gpio2"; 4451 function = "qup00"; 4452 }; 4453 4454 qup_spi0_cs: qup-spi0-cs-state { 4455 pins = "gpio3"; 4456 function = "qup00"; 4457 }; 4458 4459 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4460 pins = "gpio3"; 4461 function = "gpio"; 4462 }; 4463 4464 qup_spi1_data_clk: qup-spi1-data-clk-state { 4465 pins = "gpio4", "gpio5", "gpio6"; 4466 function = "qup01"; 4467 }; 4468 4469 qup_spi1_cs: qup-spi1-cs-state { 4470 pins = "gpio7"; 4471 function = "qup01"; 4472 }; 4473 4474 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4475 pins = "gpio7"; 4476 function = "gpio"; 4477 }; 4478 4479 qup_spi2_data_clk: qup-spi2-data-clk-state { 4480 pins = "gpio8", "gpio9", "gpio10"; 4481 function = "qup02"; 4482 }; 4483 4484 qup_spi2_cs: qup-spi2-cs-state { 4485 pins = "gpio11"; 4486 function = "qup02"; 4487 }; 4488 4489 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4490 pins = "gpio11"; 4491 function = "gpio"; 4492 }; 4493 4494 qup_spi3_data_clk: qup-spi3-data-clk-state { 4495 pins = "gpio12", "gpio13", "gpio14"; 4496 function = "qup03"; 4497 }; 4498 4499 qup_spi3_cs: qup-spi3-cs-state { 4500 pins = "gpio15"; 4501 function = "qup03"; 4502 }; 4503 4504 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4505 pins = "gpio15"; 4506 function = "gpio"; 4507 }; 4508 4509 qup_spi4_data_clk: qup-spi4-data-clk-state { 4510 pins = "gpio16", "gpio17", "gpio18"; 4511 function = "qup04"; 4512 }; 4513 4514 qup_spi4_cs: qup-spi4-cs-state { 4515 pins = "gpio19"; 4516 function = "qup04"; 4517 }; 4518 4519 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4520 pins = "gpio19"; 4521 function = "gpio"; 4522 }; 4523 4524 qup_spi5_data_clk: qup-spi5-data-clk-state { 4525 pins = "gpio20", "gpio21", "gpio22"; 4526 function = "qup05"; 4527 }; 4528 4529 qup_spi5_cs: qup-spi5-cs-state { 4530 pins = "gpio23"; 4531 function = "qup05"; 4532 }; 4533 4534 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4535 pins = "gpio23"; 4536 function = "gpio"; 4537 }; 4538 4539 qup_spi6_data_clk: qup-spi6-data-clk-state { 4540 pins = "gpio24", "gpio25", "gpio26"; 4541 function = "qup06"; 4542 }; 4543 4544 qup_spi6_cs: qup-spi6-cs-state { 4545 pins = "gpio27"; 4546 function = "qup06"; 4547 }; 4548 4549 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4550 pins = "gpio27"; 4551 function = "gpio"; 4552 }; 4553 4554 qup_spi7_data_clk: qup-spi7-data-clk-state { 4555 pins = "gpio28", "gpio29", "gpio30"; 4556 function = "qup07"; 4557 }; 4558 4559 qup_spi7_cs: qup-spi7-cs-state { 4560 pins = "gpio31"; 4561 function = "qup07"; 4562 }; 4563 4564 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4565 pins = "gpio31"; 4566 function = "gpio"; 4567 }; 4568 4569 qup_spi8_data_clk: qup-spi8-data-clk-state { 4570 pins = "gpio32", "gpio33", "gpio34"; 4571 function = "qup10"; 4572 }; 4573 4574 qup_spi8_cs: qup-spi8-cs-state { 4575 pins = "gpio35"; 4576 function = "qup10"; 4577 }; 4578 4579 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4580 pins = "gpio35"; 4581 function = "gpio"; 4582 }; 4583 4584 qup_spi9_data_clk: qup-spi9-data-clk-state { 4585 pins = "gpio36", "gpio37", "gpio38"; 4586 function = "qup11"; 4587 }; 4588 4589 qup_spi9_cs: qup-spi9-cs-state { 4590 pins = "gpio39"; 4591 function = "qup11"; 4592 }; 4593 4594 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4595 pins = "gpio39"; 4596 function = "gpio"; 4597 }; 4598 4599 qup_spi10_data_clk: qup-spi10-data-clk-state { 4600 pins = "gpio40", "gpio41", "gpio42"; 4601 function = "qup12"; 4602 }; 4603 4604 qup_spi10_cs: qup-spi10-cs-state { 4605 pins = "gpio43"; 4606 function = "qup12"; 4607 }; 4608 4609 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4610 pins = "gpio43"; 4611 function = "gpio"; 4612 }; 4613 4614 qup_spi11_data_clk: qup-spi11-data-clk-state { 4615 pins = "gpio44", "gpio45", "gpio46"; 4616 function = "qup13"; 4617 }; 4618 4619 qup_spi11_cs: qup-spi11-cs-state { 4620 pins = "gpio47"; 4621 function = "qup13"; 4622 }; 4623 4624 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 4625 pins = "gpio47"; 4626 function = "gpio"; 4627 }; 4628 4629 qup_spi12_data_clk: qup-spi12-data-clk-state { 4630 pins = "gpio48", "gpio49", "gpio50"; 4631 function = "qup14"; 4632 }; 4633 4634 qup_spi12_cs: qup-spi12-cs-state { 4635 pins = "gpio51"; 4636 function = "qup14"; 4637 }; 4638 4639 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4640 pins = "gpio51"; 4641 function = "gpio"; 4642 }; 4643 4644 qup_spi13_data_clk: qup-spi13-data-clk-state { 4645 pins = "gpio52", "gpio53", "gpio54"; 4646 function = "qup15"; 4647 }; 4648 4649 qup_spi13_cs: qup-spi13-cs-state { 4650 pins = "gpio55"; 4651 function = "qup15"; 4652 }; 4653 4654 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 4655 pins = "gpio55"; 4656 function = "gpio"; 4657 }; 4658 4659 qup_spi14_data_clk: qup-spi14-data-clk-state { 4660 pins = "gpio56", "gpio57", "gpio58"; 4661 function = "qup16"; 4662 }; 4663 4664 qup_spi14_cs: qup-spi14-cs-state { 4665 pins = "gpio59"; 4666 function = "qup16"; 4667 }; 4668 4669 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 4670 pins = "gpio59"; 4671 function = "gpio"; 4672 }; 4673 4674 qup_spi15_data_clk: qup-spi15-data-clk-state { 4675 pins = "gpio60", "gpio61", "gpio62"; 4676 function = "qup17"; 4677 }; 4678 4679 qup_spi15_cs: qup-spi15-cs-state { 4680 pins = "gpio63"; 4681 function = "qup17"; 4682 }; 4683 4684 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 4685 pins = "gpio63"; 4686 function = "gpio"; 4687 }; 4688 4689 qup_uart0_cts: qup-uart0-cts-state { 4690 pins = "gpio0"; 4691 function = "qup00"; 4692 }; 4693 4694 qup_uart0_rts: qup-uart0-rts-state { 4695 pins = "gpio1"; 4696 function = "qup00"; 4697 }; 4698 4699 qup_uart0_tx: qup-uart0-tx-state { 4700 pins = "gpio2"; 4701 function = "qup00"; 4702 }; 4703 4704 qup_uart0_rx: qup-uart0-rx-state { 4705 pins = "gpio3"; 4706 function = "qup00"; 4707 }; 4708 4709 qup_uart1_cts: qup-uart1-cts-state { 4710 pins = "gpio4"; 4711 function = "qup01"; 4712 }; 4713 4714 qup_uart1_rts: qup-uart1-rts-state { 4715 pins = "gpio5"; 4716 function = "qup01"; 4717 }; 4718 4719 qup_uart1_tx: qup-uart1-tx-state { 4720 pins = "gpio6"; 4721 function = "qup01"; 4722 }; 4723 4724 qup_uart1_rx: qup-uart1-rx-state { 4725 pins = "gpio7"; 4726 function = "qup01"; 4727 }; 4728 4729 qup_uart2_cts: qup-uart2-cts-state { 4730 pins = "gpio8"; 4731 function = "qup02"; 4732 }; 4733 4734 qup_uart2_rts: qup-uart2-rts-state { 4735 pins = "gpio9"; 4736 function = "qup02"; 4737 }; 4738 4739 qup_uart2_tx: qup-uart2-tx-state { 4740 pins = "gpio10"; 4741 function = "qup02"; 4742 }; 4743 4744 qup_uart2_rx: qup-uart2-rx-state { 4745 pins = "gpio11"; 4746 function = "qup02"; 4747 }; 4748 4749 qup_uart3_cts: qup-uart3-cts-state { 4750 pins = "gpio12"; 4751 function = "qup03"; 4752 }; 4753 4754 qup_uart3_rts: qup-uart3-rts-state { 4755 pins = "gpio13"; 4756 function = "qup03"; 4757 }; 4758 4759 qup_uart3_tx: qup-uart3-tx-state { 4760 pins = "gpio14"; 4761 function = "qup03"; 4762 }; 4763 4764 qup_uart3_rx: qup-uart3-rx-state { 4765 pins = "gpio15"; 4766 function = "qup03"; 4767 }; 4768 4769 qup_uart4_cts: qup-uart4-cts-state { 4770 pins = "gpio16"; 4771 function = "qup04"; 4772 }; 4773 4774 qup_uart4_rts: qup-uart4-rts-state { 4775 pins = "gpio17"; 4776 function = "qup04"; 4777 }; 4778 4779 qup_uart4_tx: qup-uart4-tx-state { 4780 pins = "gpio18"; 4781 function = "qup04"; 4782 }; 4783 4784 qup_uart4_rx: qup-uart4-rx-state { 4785 pins = "gpio19"; 4786 function = "qup04"; 4787 }; 4788 4789 qup_uart5_cts: qup-uart5-cts-state { 4790 pins = "gpio20"; 4791 function = "qup05"; 4792 }; 4793 4794 qup_uart5_rts: qup-uart5-rts-state { 4795 pins = "gpio21"; 4796 function = "qup05"; 4797 }; 4798 4799 qup_uart5_tx: qup-uart5-tx-state { 4800 pins = "gpio22"; 4801 function = "qup05"; 4802 }; 4803 4804 qup_uart5_rx: qup-uart5-rx-state { 4805 pins = "gpio23"; 4806 function = "qup05"; 4807 }; 4808 4809 qup_uart6_cts: qup-uart6-cts-state { 4810 pins = "gpio24"; 4811 function = "qup06"; 4812 }; 4813 4814 qup_uart6_rts: qup-uart6-rts-state { 4815 pins = "gpio25"; 4816 function = "qup06"; 4817 }; 4818 4819 qup_uart6_tx: qup-uart6-tx-state { 4820 pins = "gpio26"; 4821 function = "qup06"; 4822 }; 4823 4824 qup_uart6_rx: qup-uart6-rx-state { 4825 pins = "gpio27"; 4826 function = "qup06"; 4827 }; 4828 4829 qup_uart7_cts: qup-uart7-cts-state { 4830 pins = "gpio28"; 4831 function = "qup07"; 4832 }; 4833 4834 qup_uart7_rts: qup-uart7-rts-state { 4835 pins = "gpio29"; 4836 function = "qup07"; 4837 }; 4838 4839 qup_uart7_tx: qup-uart7-tx-state { 4840 pins = "gpio30"; 4841 function = "qup07"; 4842 }; 4843 4844 qup_uart7_rx: qup-uart7-rx-state { 4845 pins = "gpio31"; 4846 function = "qup07"; 4847 }; 4848 4849 qup_uart8_cts: qup-uart8-cts-state { 4850 pins = "gpio32"; 4851 function = "qup10"; 4852 }; 4853 4854 qup_uart8_rts: qup-uart8-rts-state { 4855 pins = "gpio33"; 4856 function = "qup10"; 4857 }; 4858 4859 qup_uart8_tx: qup-uart8-tx-state { 4860 pins = "gpio34"; 4861 function = "qup10"; 4862 }; 4863 4864 qup_uart8_rx: qup-uart8-rx-state { 4865 pins = "gpio35"; 4866 function = "qup10"; 4867 }; 4868 4869 qup_uart9_cts: qup-uart9-cts-state { 4870 pins = "gpio36"; 4871 function = "qup11"; 4872 }; 4873 4874 qup_uart9_rts: qup-uart9-rts-state { 4875 pins = "gpio37"; 4876 function = "qup11"; 4877 }; 4878 4879 qup_uart9_tx: qup-uart9-tx-state { 4880 pins = "gpio38"; 4881 function = "qup11"; 4882 }; 4883 4884 qup_uart9_rx: qup-uart9-rx-state { 4885 pins = "gpio39"; 4886 function = "qup11"; 4887 }; 4888 4889 qup_uart10_cts: qup-uart10-cts-state { 4890 pins = "gpio40"; 4891 function = "qup12"; 4892 }; 4893 4894 qup_uart10_rts: qup-uart10-rts-state { 4895 pins = "gpio41"; 4896 function = "qup12"; 4897 }; 4898 4899 qup_uart10_tx: qup-uart10-tx-state { 4900 pins = "gpio42"; 4901 function = "qup12"; 4902 }; 4903 4904 qup_uart10_rx: qup-uart10-rx-state { 4905 pins = "gpio43"; 4906 function = "qup12"; 4907 }; 4908 4909 qup_uart11_cts: qup-uart11-cts-state { 4910 pins = "gpio44"; 4911 function = "qup13"; 4912 }; 4913 4914 qup_uart11_rts: qup-uart11-rts-state { 4915 pins = "gpio45"; 4916 function = "qup13"; 4917 }; 4918 4919 qup_uart11_tx: qup-uart11-tx-state { 4920 pins = "gpio46"; 4921 function = "qup13"; 4922 }; 4923 4924 qup_uart11_rx: qup-uart11-rx-state { 4925 pins = "gpio47"; 4926 function = "qup13"; 4927 }; 4928 4929 qup_uart12_cts: qup-uart12-cts-state { 4930 pins = "gpio48"; 4931 function = "qup14"; 4932 }; 4933 4934 qup_uart12_rts: qup-uart12-rts-state { 4935 pins = "gpio49"; 4936 function = "qup14"; 4937 }; 4938 4939 qup_uart12_tx: qup-uart12-tx-state { 4940 pins = "gpio50"; 4941 function = "qup14"; 4942 }; 4943 4944 qup_uart12_rx: qup-uart12-rx-state { 4945 pins = "gpio51"; 4946 function = "qup14"; 4947 }; 4948 4949 qup_uart13_cts: qup-uart13-cts-state { 4950 pins = "gpio52"; 4951 function = "qup15"; 4952 }; 4953 4954 qup_uart13_rts: qup-uart13-rts-state { 4955 pins = "gpio53"; 4956 function = "qup15"; 4957 }; 4958 4959 qup_uart13_tx: qup-uart13-tx-state { 4960 pins = "gpio54"; 4961 function = "qup15"; 4962 }; 4963 4964 qup_uart13_rx: qup-uart13-rx-state { 4965 pins = "gpio55"; 4966 function = "qup15"; 4967 }; 4968 4969 qup_uart14_cts: qup-uart14-cts-state { 4970 pins = "gpio56"; 4971 function = "qup16"; 4972 }; 4973 4974 qup_uart14_rts: qup-uart14-rts-state { 4975 pins = "gpio57"; 4976 function = "qup16"; 4977 }; 4978 4979 qup_uart14_tx: qup-uart14-tx-state { 4980 pins = "gpio58"; 4981 function = "qup16"; 4982 }; 4983 4984 qup_uart14_rx: qup-uart14-rx-state { 4985 pins = "gpio59"; 4986 function = "qup16"; 4987 }; 4988 4989 qup_uart15_cts: qup-uart15-cts-state { 4990 pins = "gpio60"; 4991 function = "qup17"; 4992 }; 4993 4994 qup_uart15_rts: qup-uart15-rts-state { 4995 pins = "gpio61"; 4996 function = "qup17"; 4997 }; 4998 4999 qup_uart15_tx: qup-uart15-tx-state { 5000 pins = "gpio62"; 5001 function = "qup17"; 5002 }; 5003 5004 qup_uart15_rx: qup-uart15-rx-state { 5005 pins = "gpio63"; 5006 function = "qup17"; 5007 }; 5008 5009 sdc1_clk: sdc1-clk-state { 5010 pins = "sdc1_clk"; 5011 }; 5012 5013 sdc1_cmd: sdc1-cmd-state { 5014 pins = "sdc1_cmd"; 5015 }; 5016 5017 sdc1_data: sdc1-data-state { 5018 pins = "sdc1_data"; 5019 }; 5020 5021 sdc1_rclk: sdc1-rclk-state { 5022 pins = "sdc1_rclk"; 5023 }; 5024 5025 sdc1_clk_sleep: sdc1-clk-sleep-state { 5026 pins = "sdc1_clk"; 5027 drive-strength = <2>; 5028 bias-bus-hold; 5029 }; 5030 5031 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5032 pins = "sdc1_cmd"; 5033 drive-strength = <2>; 5034 bias-bus-hold; 5035 }; 5036 5037 sdc1_data_sleep: sdc1-data-sleep-state { 5038 pins = "sdc1_data"; 5039 drive-strength = <2>; 5040 bias-bus-hold; 5041 }; 5042 5043 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5044 pins = "sdc1_rclk"; 5045 drive-strength = <2>; 5046 bias-bus-hold; 5047 }; 5048 5049 sdc2_clk: sdc2-clk-state { 5050 pins = "sdc2_clk"; 5051 }; 5052 5053 sdc2_cmd: sdc2-cmd-state { 5054 pins = "sdc2_cmd"; 5055 }; 5056 5057 sdc2_data: sdc2-data-state { 5058 pins = "sdc2_data"; 5059 }; 5060 5061 sdc2_clk_sleep: sdc2-clk-sleep-state { 5062 pins = "sdc2_clk"; 5063 drive-strength = <2>; 5064 bias-bus-hold; 5065 }; 5066 5067 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 5068 pins = "sdc2_cmd"; 5069 drive-strength = <2>; 5070 bias-bus-hold; 5071 }; 5072 5073 sdc2_data_sleep: sdc2-data-sleep-state { 5074 pins = "sdc2_data"; 5075 drive-strength = <2>; 5076 bias-bus-hold; 5077 }; 5078 }; 5079 5080 sram@146a5000 { 5081 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5082 reg = <0 0x146a5000 0 0x6000>; 5083 5084 #address-cells = <1>; 5085 #size-cells = <1>; 5086 5087 ranges = <0 0 0x146a5000 0x6000>; 5088 5089 pil-reloc@594c { 5090 compatible = "qcom,pil-reloc-info"; 5091 reg = <0x594c 0xc8>; 5092 }; 5093 }; 5094 5095 apps_smmu: iommu@15000000 { 5096 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5097 reg = <0 0x15000000 0 0x100000>; 5098 #iommu-cells = <2>; 5099 #global-interrupts = <1>; 5100 dma-coherent; 5101 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5102 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5103 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5104 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5169 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5170 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5171 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5172 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5173 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5174 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5175 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5176 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5177 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5178 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5179 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5180 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5181 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5182 }; 5183 5184 intc: interrupt-controller@17a00000 { 5185 compatible = "arm,gic-v3"; 5186 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5187 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5188 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5189 #interrupt-cells = <3>; 5190 interrupt-controller; 5191 #address-cells = <2>; 5192 #size-cells = <2>; 5193 ranges; 5194 5195 msi-controller@17a40000 { 5196 compatible = "arm,gic-v3-its"; 5197 reg = <0 0x17a40000 0 0x20000>; 5198 msi-controller; 5199 #msi-cells = <1>; 5200 status = "disabled"; 5201 }; 5202 }; 5203 5204 watchdog: watchdog@17c10000 { 5205 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5206 reg = <0 0x17c10000 0 0x1000>; 5207 clocks = <&sleep_clk>; 5208 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5209 status = "reserved"; /* Owned by Gunyah hyp */ 5210 }; 5211 5212 timer@17c20000 { 5213 #address-cells = <1>; 5214 #size-cells = <1>; 5215 ranges = <0 0 0 0x20000000>; 5216 compatible = "arm,armv7-timer-mem"; 5217 reg = <0 0x17c20000 0 0x1000>; 5218 5219 frame@17c21000 { 5220 frame-number = <0>; 5221 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5222 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5223 reg = <0x17c21000 0x1000>, 5224 <0x17c22000 0x1000>; 5225 }; 5226 5227 frame@17c23000 { 5228 frame-number = <1>; 5229 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5230 reg = <0x17c23000 0x1000>; 5231 status = "disabled"; 5232 }; 5233 5234 frame@17c25000 { 5235 frame-number = <2>; 5236 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5237 reg = <0x17c25000 0x1000>; 5238 status = "disabled"; 5239 }; 5240 5241 frame@17c27000 { 5242 frame-number = <3>; 5243 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5244 reg = <0x17c27000 0x1000>; 5245 status = "disabled"; 5246 }; 5247 5248 frame@17c29000 { 5249 frame-number = <4>; 5250 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5251 reg = <0x17c29000 0x1000>; 5252 status = "disabled"; 5253 }; 5254 5255 frame@17c2b000 { 5256 frame-number = <5>; 5257 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5258 reg = <0x17c2b000 0x1000>; 5259 status = "disabled"; 5260 }; 5261 5262 frame@17c2d000 { 5263 frame-number = <6>; 5264 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5265 reg = <0x17c2d000 0x1000>; 5266 status = "disabled"; 5267 }; 5268 }; 5269 5270 apps_rsc: rsc@18200000 { 5271 compatible = "qcom,rpmh-rsc"; 5272 reg = <0 0x18200000 0 0x10000>, 5273 <0 0x18210000 0 0x10000>, 5274 <0 0x18220000 0 0x10000>; 5275 reg-names = "drv-0", "drv-1", "drv-2"; 5276 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5277 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5278 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5279 qcom,tcs-offset = <0xd00>; 5280 qcom,drv-id = <2>; 5281 qcom,tcs-config = <ACTIVE_TCS 2>, 5282 <SLEEP_TCS 3>, 5283 <WAKE_TCS 3>, 5284 <CONTROL_TCS 1>; 5285 5286 apps_bcm_voter: bcm-voter { 5287 compatible = "qcom,bcm-voter"; 5288 }; 5289 5290 rpmhpd: power-controller { 5291 compatible = "qcom,sc7280-rpmhpd"; 5292 #power-domain-cells = <1>; 5293 operating-points-v2 = <&rpmhpd_opp_table>; 5294 5295 rpmhpd_opp_table: opp-table { 5296 compatible = "operating-points-v2"; 5297 5298 rpmhpd_opp_ret: opp1 { 5299 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5300 }; 5301 5302 rpmhpd_opp_low_svs: opp2 { 5303 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5304 }; 5305 5306 rpmhpd_opp_svs: opp3 { 5307 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5308 }; 5309 5310 rpmhpd_opp_svs_l1: opp4 { 5311 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5312 }; 5313 5314 rpmhpd_opp_svs_l2: opp5 { 5315 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5316 }; 5317 5318 rpmhpd_opp_nom: opp6 { 5319 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5320 }; 5321 5322 rpmhpd_opp_nom_l1: opp7 { 5323 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5324 }; 5325 5326 rpmhpd_opp_turbo: opp8 { 5327 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5328 }; 5329 5330 rpmhpd_opp_turbo_l1: opp9 { 5331 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5332 }; 5333 }; 5334 }; 5335 5336 rpmhcc: clock-controller { 5337 compatible = "qcom,sc7280-rpmh-clk"; 5338 clocks = <&xo_board>; 5339 clock-names = "xo"; 5340 #clock-cells = <1>; 5341 }; 5342 }; 5343 5344 epss_l3: interconnect@18590000 { 5345 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 5346 reg = <0 0x18590000 0 0x1000>; 5347 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5348 clock-names = "xo", "alternate"; 5349 #interconnect-cells = <1>; 5350 }; 5351 5352 cpufreq_hw: cpufreq@18591000 { 5353 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 5354 reg = <0 0x18591000 0 0x1000>, 5355 <0 0x18592000 0 0x1000>, 5356 <0 0x18593000 0 0x1000>; 5357 5358 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5359 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5360 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5361 interrupt-names = "dcvsh-irq-0", 5362 "dcvsh-irq-1", 5363 "dcvsh-irq-2"; 5364 5365 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5366 clock-names = "xo", "alternate"; 5367 #freq-domain-cells = <1>; 5368 #clock-cells = <1>; 5369 }; 5370 }; 5371 5372 thermal_zones: thermal-zones { 5373 cpu0-thermal { 5374 polling-delay-passive = <250>; 5375 polling-delay = <0>; 5376 5377 thermal-sensors = <&tsens0 1>; 5378 5379 trips { 5380 cpu0_alert0: trip-point0 { 5381 temperature = <90000>; 5382 hysteresis = <2000>; 5383 type = "passive"; 5384 }; 5385 5386 cpu0_alert1: trip-point1 { 5387 temperature = <95000>; 5388 hysteresis = <2000>; 5389 type = "passive"; 5390 }; 5391 5392 cpu0_crit: cpu-crit { 5393 temperature = <110000>; 5394 hysteresis = <0>; 5395 type = "critical"; 5396 }; 5397 }; 5398 5399 cooling-maps { 5400 map0 { 5401 trip = <&cpu0_alert0>; 5402 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5403 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5404 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5405 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5406 }; 5407 map1 { 5408 trip = <&cpu0_alert1>; 5409 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5410 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5411 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5412 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5413 }; 5414 }; 5415 }; 5416 5417 cpu1-thermal { 5418 polling-delay-passive = <250>; 5419 polling-delay = <0>; 5420 5421 thermal-sensors = <&tsens0 2>; 5422 5423 trips { 5424 cpu1_alert0: trip-point0 { 5425 temperature = <90000>; 5426 hysteresis = <2000>; 5427 type = "passive"; 5428 }; 5429 5430 cpu1_alert1: trip-point1 { 5431 temperature = <95000>; 5432 hysteresis = <2000>; 5433 type = "passive"; 5434 }; 5435 5436 cpu1_crit: cpu-crit { 5437 temperature = <110000>; 5438 hysteresis = <0>; 5439 type = "critical"; 5440 }; 5441 }; 5442 5443 cooling-maps { 5444 map0 { 5445 trip = <&cpu1_alert0>; 5446 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5447 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5448 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5449 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5450 }; 5451 map1 { 5452 trip = <&cpu1_alert1>; 5453 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5454 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5455 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5456 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5457 }; 5458 }; 5459 }; 5460 5461 cpu2-thermal { 5462 polling-delay-passive = <250>; 5463 polling-delay = <0>; 5464 5465 thermal-sensors = <&tsens0 3>; 5466 5467 trips { 5468 cpu2_alert0: trip-point0 { 5469 temperature = <90000>; 5470 hysteresis = <2000>; 5471 type = "passive"; 5472 }; 5473 5474 cpu2_alert1: trip-point1 { 5475 temperature = <95000>; 5476 hysteresis = <2000>; 5477 type = "passive"; 5478 }; 5479 5480 cpu2_crit: cpu-crit { 5481 temperature = <110000>; 5482 hysteresis = <0>; 5483 type = "critical"; 5484 }; 5485 }; 5486 5487 cooling-maps { 5488 map0 { 5489 trip = <&cpu2_alert0>; 5490 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5491 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5492 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5493 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5494 }; 5495 map1 { 5496 trip = <&cpu2_alert1>; 5497 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5498 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5499 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5500 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5501 }; 5502 }; 5503 }; 5504 5505 cpu3-thermal { 5506 polling-delay-passive = <250>; 5507 polling-delay = <0>; 5508 5509 thermal-sensors = <&tsens0 4>; 5510 5511 trips { 5512 cpu3_alert0: trip-point0 { 5513 temperature = <90000>; 5514 hysteresis = <2000>; 5515 type = "passive"; 5516 }; 5517 5518 cpu3_alert1: trip-point1 { 5519 temperature = <95000>; 5520 hysteresis = <2000>; 5521 type = "passive"; 5522 }; 5523 5524 cpu3_crit: cpu-crit { 5525 temperature = <110000>; 5526 hysteresis = <0>; 5527 type = "critical"; 5528 }; 5529 }; 5530 5531 cooling-maps { 5532 map0 { 5533 trip = <&cpu3_alert0>; 5534 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5535 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5536 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5537 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5538 }; 5539 map1 { 5540 trip = <&cpu3_alert1>; 5541 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5542 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5543 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5544 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5545 }; 5546 }; 5547 }; 5548 5549 cpu4-thermal { 5550 polling-delay-passive = <250>; 5551 polling-delay = <0>; 5552 5553 thermal-sensors = <&tsens0 7>; 5554 5555 trips { 5556 cpu4_alert0: trip-point0 { 5557 temperature = <90000>; 5558 hysteresis = <2000>; 5559 type = "passive"; 5560 }; 5561 5562 cpu4_alert1: trip-point1 { 5563 temperature = <95000>; 5564 hysteresis = <2000>; 5565 type = "passive"; 5566 }; 5567 5568 cpu4_crit: cpu-crit { 5569 temperature = <110000>; 5570 hysteresis = <0>; 5571 type = "critical"; 5572 }; 5573 }; 5574 5575 cooling-maps { 5576 map0 { 5577 trip = <&cpu4_alert0>; 5578 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5579 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5580 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5581 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5582 }; 5583 map1 { 5584 trip = <&cpu4_alert1>; 5585 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5586 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5587 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5588 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5589 }; 5590 }; 5591 }; 5592 5593 cpu5-thermal { 5594 polling-delay-passive = <250>; 5595 polling-delay = <0>; 5596 5597 thermal-sensors = <&tsens0 8>; 5598 5599 trips { 5600 cpu5_alert0: trip-point0 { 5601 temperature = <90000>; 5602 hysteresis = <2000>; 5603 type = "passive"; 5604 }; 5605 5606 cpu5_alert1: trip-point1 { 5607 temperature = <95000>; 5608 hysteresis = <2000>; 5609 type = "passive"; 5610 }; 5611 5612 cpu5_crit: cpu-crit { 5613 temperature = <110000>; 5614 hysteresis = <0>; 5615 type = "critical"; 5616 }; 5617 }; 5618 5619 cooling-maps { 5620 map0 { 5621 trip = <&cpu5_alert0>; 5622 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5623 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5624 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5625 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5626 }; 5627 map1 { 5628 trip = <&cpu5_alert1>; 5629 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5630 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5631 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5632 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5633 }; 5634 }; 5635 }; 5636 5637 cpu6-thermal { 5638 polling-delay-passive = <250>; 5639 polling-delay = <0>; 5640 5641 thermal-sensors = <&tsens0 9>; 5642 5643 trips { 5644 cpu6_alert0: trip-point0 { 5645 temperature = <90000>; 5646 hysteresis = <2000>; 5647 type = "passive"; 5648 }; 5649 5650 cpu6_alert1: trip-point1 { 5651 temperature = <95000>; 5652 hysteresis = <2000>; 5653 type = "passive"; 5654 }; 5655 5656 cpu6_crit: cpu-crit { 5657 temperature = <110000>; 5658 hysteresis = <0>; 5659 type = "critical"; 5660 }; 5661 }; 5662 5663 cooling-maps { 5664 map0 { 5665 trip = <&cpu6_alert0>; 5666 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5667 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5668 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5669 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5670 }; 5671 map1 { 5672 trip = <&cpu6_alert1>; 5673 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5674 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5675 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5676 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5677 }; 5678 }; 5679 }; 5680 5681 cpu7-thermal { 5682 polling-delay-passive = <250>; 5683 polling-delay = <0>; 5684 5685 thermal-sensors = <&tsens0 10>; 5686 5687 trips { 5688 cpu7_alert0: trip-point0 { 5689 temperature = <90000>; 5690 hysteresis = <2000>; 5691 type = "passive"; 5692 }; 5693 5694 cpu7_alert1: trip-point1 { 5695 temperature = <95000>; 5696 hysteresis = <2000>; 5697 type = "passive"; 5698 }; 5699 5700 cpu7_crit: cpu-crit { 5701 temperature = <110000>; 5702 hysteresis = <0>; 5703 type = "critical"; 5704 }; 5705 }; 5706 5707 cooling-maps { 5708 map0 { 5709 trip = <&cpu7_alert0>; 5710 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5711 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5712 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5713 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5714 }; 5715 map1 { 5716 trip = <&cpu7_alert1>; 5717 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5718 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5719 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5720 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5721 }; 5722 }; 5723 }; 5724 5725 cpu8-thermal { 5726 polling-delay-passive = <250>; 5727 polling-delay = <0>; 5728 5729 thermal-sensors = <&tsens0 11>; 5730 5731 trips { 5732 cpu8_alert0: trip-point0 { 5733 temperature = <90000>; 5734 hysteresis = <2000>; 5735 type = "passive"; 5736 }; 5737 5738 cpu8_alert1: trip-point1 { 5739 temperature = <95000>; 5740 hysteresis = <2000>; 5741 type = "passive"; 5742 }; 5743 5744 cpu8_crit: cpu-crit { 5745 temperature = <110000>; 5746 hysteresis = <0>; 5747 type = "critical"; 5748 }; 5749 }; 5750 5751 cooling-maps { 5752 map0 { 5753 trip = <&cpu8_alert0>; 5754 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5755 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5756 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5757 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5758 }; 5759 map1 { 5760 trip = <&cpu8_alert1>; 5761 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5762 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5763 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5764 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5765 }; 5766 }; 5767 }; 5768 5769 cpu9-thermal { 5770 polling-delay-passive = <250>; 5771 polling-delay = <0>; 5772 5773 thermal-sensors = <&tsens0 12>; 5774 5775 trips { 5776 cpu9_alert0: trip-point0 { 5777 temperature = <90000>; 5778 hysteresis = <2000>; 5779 type = "passive"; 5780 }; 5781 5782 cpu9_alert1: trip-point1 { 5783 temperature = <95000>; 5784 hysteresis = <2000>; 5785 type = "passive"; 5786 }; 5787 5788 cpu9_crit: cpu-crit { 5789 temperature = <110000>; 5790 hysteresis = <0>; 5791 type = "critical"; 5792 }; 5793 }; 5794 5795 cooling-maps { 5796 map0 { 5797 trip = <&cpu9_alert0>; 5798 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5799 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5800 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5801 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5802 }; 5803 map1 { 5804 trip = <&cpu9_alert1>; 5805 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5806 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5807 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5808 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5809 }; 5810 }; 5811 }; 5812 5813 cpu10-thermal { 5814 polling-delay-passive = <250>; 5815 polling-delay = <0>; 5816 5817 thermal-sensors = <&tsens0 13>; 5818 5819 trips { 5820 cpu10_alert0: trip-point0 { 5821 temperature = <90000>; 5822 hysteresis = <2000>; 5823 type = "passive"; 5824 }; 5825 5826 cpu10_alert1: trip-point1 { 5827 temperature = <95000>; 5828 hysteresis = <2000>; 5829 type = "passive"; 5830 }; 5831 5832 cpu10_crit: cpu-crit { 5833 temperature = <110000>; 5834 hysteresis = <0>; 5835 type = "critical"; 5836 }; 5837 }; 5838 5839 cooling-maps { 5840 map0 { 5841 trip = <&cpu10_alert0>; 5842 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5843 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5844 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5845 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5846 }; 5847 map1 { 5848 trip = <&cpu10_alert1>; 5849 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5850 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5851 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5852 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5853 }; 5854 }; 5855 }; 5856 5857 cpu11-thermal { 5858 polling-delay-passive = <250>; 5859 polling-delay = <0>; 5860 5861 thermal-sensors = <&tsens0 14>; 5862 5863 trips { 5864 cpu11_alert0: trip-point0 { 5865 temperature = <90000>; 5866 hysteresis = <2000>; 5867 type = "passive"; 5868 }; 5869 5870 cpu11_alert1: trip-point1 { 5871 temperature = <95000>; 5872 hysteresis = <2000>; 5873 type = "passive"; 5874 }; 5875 5876 cpu11_crit: cpu-crit { 5877 temperature = <110000>; 5878 hysteresis = <0>; 5879 type = "critical"; 5880 }; 5881 }; 5882 5883 cooling-maps { 5884 map0 { 5885 trip = <&cpu11_alert0>; 5886 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5887 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5888 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5889 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5890 }; 5891 map1 { 5892 trip = <&cpu11_alert1>; 5893 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5894 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5895 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5896 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5897 }; 5898 }; 5899 }; 5900 5901 aoss0-thermal { 5902 polling-delay-passive = <0>; 5903 polling-delay = <0>; 5904 5905 thermal-sensors = <&tsens0 0>; 5906 5907 trips { 5908 aoss0_alert0: trip-point0 { 5909 temperature = <90000>; 5910 hysteresis = <2000>; 5911 type = "hot"; 5912 }; 5913 5914 aoss0_crit: aoss0-crit { 5915 temperature = <110000>; 5916 hysteresis = <0>; 5917 type = "critical"; 5918 }; 5919 }; 5920 }; 5921 5922 aoss1-thermal { 5923 polling-delay-passive = <0>; 5924 polling-delay = <0>; 5925 5926 thermal-sensors = <&tsens1 0>; 5927 5928 trips { 5929 aoss1_alert0: trip-point0 { 5930 temperature = <90000>; 5931 hysteresis = <2000>; 5932 type = "hot"; 5933 }; 5934 5935 aoss1_crit: aoss1-crit { 5936 temperature = <110000>; 5937 hysteresis = <0>; 5938 type = "critical"; 5939 }; 5940 }; 5941 }; 5942 5943 cpuss0-thermal { 5944 polling-delay-passive = <0>; 5945 polling-delay = <0>; 5946 5947 thermal-sensors = <&tsens0 5>; 5948 5949 trips { 5950 cpuss0_alert0: trip-point0 { 5951 temperature = <90000>; 5952 hysteresis = <2000>; 5953 type = "hot"; 5954 }; 5955 cpuss0_crit: cluster0-crit { 5956 temperature = <110000>; 5957 hysteresis = <0>; 5958 type = "critical"; 5959 }; 5960 }; 5961 }; 5962 5963 cpuss1-thermal { 5964 polling-delay-passive = <0>; 5965 polling-delay = <0>; 5966 5967 thermal-sensors = <&tsens0 6>; 5968 5969 trips { 5970 cpuss1_alert0: trip-point0 { 5971 temperature = <90000>; 5972 hysteresis = <2000>; 5973 type = "hot"; 5974 }; 5975 cpuss1_crit: cluster0-crit { 5976 temperature = <110000>; 5977 hysteresis = <0>; 5978 type = "critical"; 5979 }; 5980 }; 5981 }; 5982 5983 gpuss0-thermal { 5984 polling-delay-passive = <100>; 5985 polling-delay = <0>; 5986 5987 thermal-sensors = <&tsens1 1>; 5988 5989 trips { 5990 gpuss0_alert0: trip-point0 { 5991 temperature = <95000>; 5992 hysteresis = <2000>; 5993 type = "passive"; 5994 }; 5995 5996 gpuss0_crit: gpuss0-crit { 5997 temperature = <110000>; 5998 hysteresis = <0>; 5999 type = "critical"; 6000 }; 6001 }; 6002 6003 cooling-maps { 6004 map0 { 6005 trip = <&gpuss0_alert0>; 6006 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6007 }; 6008 }; 6009 }; 6010 6011 gpuss1-thermal { 6012 polling-delay-passive = <100>; 6013 polling-delay = <0>; 6014 6015 thermal-sensors = <&tsens1 2>; 6016 6017 trips { 6018 gpuss1_alert0: trip-point0 { 6019 temperature = <95000>; 6020 hysteresis = <2000>; 6021 type = "passive"; 6022 }; 6023 6024 gpuss1_crit: gpuss1-crit { 6025 temperature = <110000>; 6026 hysteresis = <0>; 6027 type = "critical"; 6028 }; 6029 }; 6030 6031 cooling-maps { 6032 map0 { 6033 trip = <&gpuss1_alert0>; 6034 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6035 }; 6036 }; 6037 }; 6038 6039 nspss0-thermal { 6040 polling-delay-passive = <0>; 6041 polling-delay = <0>; 6042 6043 thermal-sensors = <&tsens1 3>; 6044 6045 trips { 6046 nspss0_alert0: trip-point0 { 6047 temperature = <90000>; 6048 hysteresis = <2000>; 6049 type = "hot"; 6050 }; 6051 6052 nspss0_crit: nspss0-crit { 6053 temperature = <110000>; 6054 hysteresis = <0>; 6055 type = "critical"; 6056 }; 6057 }; 6058 }; 6059 6060 nspss1-thermal { 6061 polling-delay-passive = <0>; 6062 polling-delay = <0>; 6063 6064 thermal-sensors = <&tsens1 4>; 6065 6066 trips { 6067 nspss1_alert0: trip-point0 { 6068 temperature = <90000>; 6069 hysteresis = <2000>; 6070 type = "hot"; 6071 }; 6072 6073 nspss1_crit: nspss1-crit { 6074 temperature = <110000>; 6075 hysteresis = <0>; 6076 type = "critical"; 6077 }; 6078 }; 6079 }; 6080 6081 video-thermal { 6082 polling-delay-passive = <0>; 6083 polling-delay = <0>; 6084 6085 thermal-sensors = <&tsens1 5>; 6086 6087 trips { 6088 video_alert0: trip-point0 { 6089 temperature = <90000>; 6090 hysteresis = <2000>; 6091 type = "hot"; 6092 }; 6093 6094 video_crit: video-crit { 6095 temperature = <110000>; 6096 hysteresis = <0>; 6097 type = "critical"; 6098 }; 6099 }; 6100 }; 6101 6102 ddr-thermal { 6103 polling-delay-passive = <0>; 6104 polling-delay = <0>; 6105 6106 thermal-sensors = <&tsens1 6>; 6107 6108 trips { 6109 ddr_alert0: trip-point0 { 6110 temperature = <90000>; 6111 hysteresis = <2000>; 6112 type = "hot"; 6113 }; 6114 6115 ddr_crit: ddr-crit { 6116 temperature = <110000>; 6117 hysteresis = <0>; 6118 type = "critical"; 6119 }; 6120 }; 6121 }; 6122 6123 mdmss0-thermal { 6124 polling-delay-passive = <0>; 6125 polling-delay = <0>; 6126 6127 thermal-sensors = <&tsens1 7>; 6128 6129 trips { 6130 mdmss0_alert0: trip-point0 { 6131 temperature = <90000>; 6132 hysteresis = <2000>; 6133 type = "hot"; 6134 }; 6135 6136 mdmss0_crit: mdmss0-crit { 6137 temperature = <110000>; 6138 hysteresis = <0>; 6139 type = "critical"; 6140 }; 6141 }; 6142 }; 6143 6144 mdmss1-thermal { 6145 polling-delay-passive = <0>; 6146 polling-delay = <0>; 6147 6148 thermal-sensors = <&tsens1 8>; 6149 6150 trips { 6151 mdmss1_alert0: trip-point0 { 6152 temperature = <90000>; 6153 hysteresis = <2000>; 6154 type = "hot"; 6155 }; 6156 6157 mdmss1_crit: mdmss1-crit { 6158 temperature = <110000>; 6159 hysteresis = <0>; 6160 type = "critical"; 6161 }; 6162 }; 6163 }; 6164 6165 mdmss2-thermal { 6166 polling-delay-passive = <0>; 6167 polling-delay = <0>; 6168 6169 thermal-sensors = <&tsens1 9>; 6170 6171 trips { 6172 mdmss2_alert0: trip-point0 { 6173 temperature = <90000>; 6174 hysteresis = <2000>; 6175 type = "hot"; 6176 }; 6177 6178 mdmss2_crit: mdmss2-crit { 6179 temperature = <110000>; 6180 hysteresis = <0>; 6181 type = "critical"; 6182 }; 6183 }; 6184 }; 6185 6186 mdmss3-thermal { 6187 polling-delay-passive = <0>; 6188 polling-delay = <0>; 6189 6190 thermal-sensors = <&tsens1 10>; 6191 6192 trips { 6193 mdmss3_alert0: trip-point0 { 6194 temperature = <90000>; 6195 hysteresis = <2000>; 6196 type = "hot"; 6197 }; 6198 6199 mdmss3_crit: mdmss3-crit { 6200 temperature = <110000>; 6201 hysteresis = <0>; 6202 type = "critical"; 6203 }; 6204 }; 6205 }; 6206 6207 camera0-thermal { 6208 polling-delay-passive = <0>; 6209 polling-delay = <0>; 6210 6211 thermal-sensors = <&tsens1 11>; 6212 6213 trips { 6214 camera0_alert0: trip-point0 { 6215 temperature = <90000>; 6216 hysteresis = <2000>; 6217 type = "hot"; 6218 }; 6219 6220 camera0_crit: camera0-crit { 6221 temperature = <110000>; 6222 hysteresis = <0>; 6223 type = "critical"; 6224 }; 6225 }; 6226 }; 6227 }; 6228 6229 timer { 6230 compatible = "arm,armv8-timer"; 6231 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6232 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6233 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6234 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6235 }; 6236}; 6237