1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7280.h> 13#include <dt-bindings/interconnect/qcom,sc7280.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/reset/qcom,sdm845-aoss.h> 18#include <dt-bindings/reset/qcom,sdm845-pdc.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/thermal/thermal.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 chosen { }; 29 30 aliases { 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 i2c5 = &i2c5; 37 i2c6 = &i2c6; 38 i2c7 = &i2c7; 39 i2c8 = &i2c8; 40 i2c9 = &i2c9; 41 i2c10 = &i2c10; 42 i2c11 = &i2c11; 43 i2c12 = &i2c12; 44 i2c13 = &i2c13; 45 i2c14 = &i2c14; 46 i2c15 = &i2c15; 47 mmc1 = &sdhc_1; 48 mmc2 = &sdhc_2; 49 spi0 = &spi0; 50 spi1 = &spi1; 51 spi2 = &spi2; 52 spi3 = &spi3; 53 spi4 = &spi4; 54 spi5 = &spi5; 55 spi6 = &spi6; 56 spi7 = &spi7; 57 spi8 = &spi8; 58 spi9 = &spi9; 59 spi10 = &spi10; 60 spi11 = &spi11; 61 spi12 = &spi12; 62 spi13 = &spi13; 63 spi14 = &spi14; 64 spi15 = &spi15; 65 }; 66 67 clocks { 68 xo_board: xo-board { 69 compatible = "fixed-clock"; 70 clock-frequency = <76800000>; 71 #clock-cells = <0>; 72 }; 73 74 sleep_clk: sleep-clk { 75 compatible = "fixed-clock"; 76 clock-frequency = <32000>; 77 #clock-cells = <0>; 78 }; 79 }; 80 81 reserved-memory { 82 #address-cells = <2>; 83 #size-cells = <2>; 84 ranges; 85 86 hyp_mem: memory@80000000 { 87 reg = <0x0 0x80000000 0x0 0x600000>; 88 no-map; 89 }; 90 91 xbl_mem: memory@80600000 { 92 reg = <0x0 0x80600000 0x0 0x200000>; 93 no-map; 94 }; 95 96 aop_mem: memory@80800000 { 97 reg = <0x0 0x80800000 0x0 0x60000>; 98 no-map; 99 }; 100 101 aop_cmd_db_mem: memory@80860000 { 102 reg = <0x0 0x80860000 0x0 0x20000>; 103 compatible = "qcom,cmd-db"; 104 no-map; 105 }; 106 107 reserved_xbl_uefi_log: memory@80880000 { 108 reg = <0x0 0x80884000 0x0 0x10000>; 109 no-map; 110 }; 111 112 sec_apps_mem: memory@808ff000 { 113 reg = <0x0 0x808ff000 0x0 0x1000>; 114 no-map; 115 }; 116 117 smem_mem: memory@80900000 { 118 reg = <0x0 0x80900000 0x0 0x200000>; 119 no-map; 120 }; 121 122 cpucp_mem: memory@80b00000 { 123 no-map; 124 reg = <0x0 0x80b00000 0x0 0x100000>; 125 }; 126 127 wlan_fw_mem: memory@80c00000 { 128 reg = <0x0 0x80c00000 0x0 0xc00000>; 129 no-map; 130 }; 131 132 ipa_fw_mem: memory@8b700000 { 133 reg = <0 0x8b700000 0 0x10000>; 134 no-map; 135 }; 136 137 rmtfs_mem: memory@9c900000 { 138 compatible = "qcom,rmtfs-mem"; 139 reg = <0x0 0x9c900000 0x0 0x280000>; 140 no-map; 141 142 qcom,client-id = <1>; 143 qcom,vmid = <15>; 144 }; 145 }; 146 147 cpus { 148 #address-cells = <2>; 149 #size-cells = <0>; 150 151 CPU0: cpu@0 { 152 device_type = "cpu"; 153 compatible = "arm,kryo"; 154 reg = <0x0 0x0>; 155 enable-method = "psci"; 156 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 157 &LITTLE_CPU_SLEEP_1 158 &CLUSTER_SLEEP_0>; 159 next-level-cache = <&L2_0>; 160 qcom,freq-domain = <&cpufreq_hw 0>; 161 #cooling-cells = <2>; 162 L2_0: l2-cache { 163 compatible = "cache"; 164 next-level-cache = <&L3_0>; 165 L3_0: l3-cache { 166 compatible = "cache"; 167 }; 168 }; 169 }; 170 171 CPU1: cpu@100 { 172 device_type = "cpu"; 173 compatible = "arm,kryo"; 174 reg = <0x0 0x100>; 175 enable-method = "psci"; 176 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 177 &LITTLE_CPU_SLEEP_1 178 &CLUSTER_SLEEP_0>; 179 next-level-cache = <&L2_100>; 180 qcom,freq-domain = <&cpufreq_hw 0>; 181 #cooling-cells = <2>; 182 L2_100: l2-cache { 183 compatible = "cache"; 184 next-level-cache = <&L3_0>; 185 }; 186 }; 187 188 CPU2: cpu@200 { 189 device_type = "cpu"; 190 compatible = "arm,kryo"; 191 reg = <0x0 0x200>; 192 enable-method = "psci"; 193 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 194 &LITTLE_CPU_SLEEP_1 195 &CLUSTER_SLEEP_0>; 196 next-level-cache = <&L2_200>; 197 qcom,freq-domain = <&cpufreq_hw 0>; 198 #cooling-cells = <2>; 199 L2_200: l2-cache { 200 compatible = "cache"; 201 next-level-cache = <&L3_0>; 202 }; 203 }; 204 205 CPU3: cpu@300 { 206 device_type = "cpu"; 207 compatible = "arm,kryo"; 208 reg = <0x0 0x300>; 209 enable-method = "psci"; 210 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 211 &LITTLE_CPU_SLEEP_1 212 &CLUSTER_SLEEP_0>; 213 next-level-cache = <&L2_300>; 214 qcom,freq-domain = <&cpufreq_hw 0>; 215 #cooling-cells = <2>; 216 L2_300: l2-cache { 217 compatible = "cache"; 218 next-level-cache = <&L3_0>; 219 }; 220 }; 221 222 CPU4: cpu@400 { 223 device_type = "cpu"; 224 compatible = "arm,kryo"; 225 reg = <0x0 0x400>; 226 enable-method = "psci"; 227 cpu-idle-states = <&BIG_CPU_SLEEP_0 228 &BIG_CPU_SLEEP_1 229 &CLUSTER_SLEEP_0>; 230 next-level-cache = <&L2_400>; 231 qcom,freq-domain = <&cpufreq_hw 1>; 232 #cooling-cells = <2>; 233 L2_400: l2-cache { 234 compatible = "cache"; 235 next-level-cache = <&L3_0>; 236 }; 237 }; 238 239 CPU5: cpu@500 { 240 device_type = "cpu"; 241 compatible = "arm,kryo"; 242 reg = <0x0 0x500>; 243 enable-method = "psci"; 244 cpu-idle-states = <&BIG_CPU_SLEEP_0 245 &BIG_CPU_SLEEP_1 246 &CLUSTER_SLEEP_0>; 247 next-level-cache = <&L2_500>; 248 qcom,freq-domain = <&cpufreq_hw 1>; 249 #cooling-cells = <2>; 250 L2_500: l2-cache { 251 compatible = "cache"; 252 next-level-cache = <&L3_0>; 253 }; 254 }; 255 256 CPU6: cpu@600 { 257 device_type = "cpu"; 258 compatible = "arm,kryo"; 259 reg = <0x0 0x600>; 260 enable-method = "psci"; 261 cpu-idle-states = <&BIG_CPU_SLEEP_0 262 &BIG_CPU_SLEEP_1 263 &CLUSTER_SLEEP_0>; 264 next-level-cache = <&L2_600>; 265 qcom,freq-domain = <&cpufreq_hw 1>; 266 #cooling-cells = <2>; 267 L2_600: l2-cache { 268 compatible = "cache"; 269 next-level-cache = <&L3_0>; 270 }; 271 }; 272 273 CPU7: cpu@700 { 274 device_type = "cpu"; 275 compatible = "arm,kryo"; 276 reg = <0x0 0x700>; 277 enable-method = "psci"; 278 cpu-idle-states = <&BIG_CPU_SLEEP_0 279 &BIG_CPU_SLEEP_1 280 &CLUSTER_SLEEP_0>; 281 next-level-cache = <&L2_700>; 282 qcom,freq-domain = <&cpufreq_hw 2>; 283 #cooling-cells = <2>; 284 L2_700: l2-cache { 285 compatible = "cache"; 286 next-level-cache = <&L3_0>; 287 }; 288 }; 289 290 cpu-map { 291 cluster0 { 292 core0 { 293 cpu = <&CPU0>; 294 }; 295 296 core1 { 297 cpu = <&CPU1>; 298 }; 299 300 core2 { 301 cpu = <&CPU2>; 302 }; 303 304 core3 { 305 cpu = <&CPU3>; 306 }; 307 308 core4 { 309 cpu = <&CPU4>; 310 }; 311 312 core5 { 313 cpu = <&CPU5>; 314 }; 315 316 core6 { 317 cpu = <&CPU6>; 318 }; 319 320 core7 { 321 cpu = <&CPU7>; 322 }; 323 }; 324 }; 325 326 idle-states { 327 entry-method = "psci"; 328 329 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 330 compatible = "arm,idle-state"; 331 idle-state-name = "little-power-down"; 332 arm,psci-suspend-param = <0x40000003>; 333 entry-latency-us = <549>; 334 exit-latency-us = <901>; 335 min-residency-us = <1774>; 336 local-timer-stop; 337 }; 338 339 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 340 compatible = "arm,idle-state"; 341 idle-state-name = "little-rail-power-down"; 342 arm,psci-suspend-param = <0x40000004>; 343 entry-latency-us = <702>; 344 exit-latency-us = <915>; 345 min-residency-us = <4001>; 346 local-timer-stop; 347 }; 348 349 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 350 compatible = "arm,idle-state"; 351 idle-state-name = "big-power-down"; 352 arm,psci-suspend-param = <0x40000003>; 353 entry-latency-us = <523>; 354 exit-latency-us = <1244>; 355 min-residency-us = <2207>; 356 local-timer-stop; 357 }; 358 359 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 360 compatible = "arm,idle-state"; 361 idle-state-name = "big-rail-power-down"; 362 arm,psci-suspend-param = <0x40000004>; 363 entry-latency-us = <526>; 364 exit-latency-us = <1854>; 365 min-residency-us = <5555>; 366 local-timer-stop; 367 }; 368 369 CLUSTER_SLEEP_0: cluster-sleep-0 { 370 compatible = "arm,idle-state"; 371 idle-state-name = "cluster-power-down"; 372 arm,psci-suspend-param = <0x40003444>; 373 entry-latency-us = <3263>; 374 exit-latency-us = <6562>; 375 min-residency-us = <9926>; 376 local-timer-stop; 377 }; 378 }; 379 }; 380 381 memory@80000000 { 382 device_type = "memory"; 383 /* We expect the bootloader to fill in the size */ 384 reg = <0 0x80000000 0 0>; 385 }; 386 387 firmware { 388 scm { 389 compatible = "qcom,scm-sc7280", "qcom,scm"; 390 }; 391 }; 392 393 clk_virt: interconnect { 394 compatible = "qcom,sc7280-clk-virt"; 395 #interconnect-cells = <2>; 396 qcom,bcm-voters = <&apps_bcm_voter>; 397 }; 398 399 smem { 400 compatible = "qcom,smem"; 401 memory-region = <&smem_mem>; 402 hwlocks = <&tcsr_mutex 3>; 403 }; 404 405 smp2p-adsp { 406 compatible = "qcom,smp2p"; 407 qcom,smem = <443>, <429>; 408 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 409 IPCC_MPROC_SIGNAL_SMP2P 410 IRQ_TYPE_EDGE_RISING>; 411 mboxes = <&ipcc IPCC_CLIENT_LPASS 412 IPCC_MPROC_SIGNAL_SMP2P>; 413 414 qcom,local-pid = <0>; 415 qcom,remote-pid = <2>; 416 417 adsp_smp2p_out: master-kernel { 418 qcom,entry-name = "master-kernel"; 419 #qcom,smem-state-cells = <1>; 420 }; 421 422 adsp_smp2p_in: slave-kernel { 423 qcom,entry-name = "slave-kernel"; 424 interrupt-controller; 425 #interrupt-cells = <2>; 426 }; 427 }; 428 429 smp2p-cdsp { 430 compatible = "qcom,smp2p"; 431 qcom,smem = <94>, <432>; 432 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 433 IPCC_MPROC_SIGNAL_SMP2P 434 IRQ_TYPE_EDGE_RISING>; 435 mboxes = <&ipcc IPCC_CLIENT_CDSP 436 IPCC_MPROC_SIGNAL_SMP2P>; 437 438 qcom,local-pid = <0>; 439 qcom,remote-pid = <5>; 440 441 cdsp_smp2p_out: master-kernel { 442 qcom,entry-name = "master-kernel"; 443 #qcom,smem-state-cells = <1>; 444 }; 445 446 cdsp_smp2p_in: slave-kernel { 447 qcom,entry-name = "slave-kernel"; 448 interrupt-controller; 449 #interrupt-cells = <2>; 450 }; 451 }; 452 453 smp2p-mpss { 454 compatible = "qcom,smp2p"; 455 qcom,smem = <435>, <428>; 456 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 457 IPCC_MPROC_SIGNAL_SMP2P 458 IRQ_TYPE_EDGE_RISING>; 459 mboxes = <&ipcc IPCC_CLIENT_MPSS 460 IPCC_MPROC_SIGNAL_SMP2P>; 461 462 qcom,local-pid = <0>; 463 qcom,remote-pid = <1>; 464 465 modem_smp2p_out: master-kernel { 466 qcom,entry-name = "master-kernel"; 467 #qcom,smem-state-cells = <1>; 468 }; 469 470 modem_smp2p_in: slave-kernel { 471 qcom,entry-name = "slave-kernel"; 472 interrupt-controller; 473 #interrupt-cells = <2>; 474 }; 475 476 ipa_smp2p_out: ipa-ap-to-modem { 477 qcom,entry-name = "ipa"; 478 #qcom,smem-state-cells = <1>; 479 }; 480 481 ipa_smp2p_in: ipa-modem-to-ap { 482 qcom,entry-name = "ipa"; 483 interrupt-controller; 484 #interrupt-cells = <2>; 485 }; 486 }; 487 488 smp2p-wpss { 489 compatible = "qcom,smp2p"; 490 qcom,smem = <617>, <616>; 491 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 492 IPCC_MPROC_SIGNAL_SMP2P 493 IRQ_TYPE_EDGE_RISING>; 494 mboxes = <&ipcc IPCC_CLIENT_WPSS 495 IPCC_MPROC_SIGNAL_SMP2P>; 496 497 qcom,local-pid = <0>; 498 qcom,remote-pid = <13>; 499 500 wpss_smp2p_out: master-kernel { 501 qcom,entry-name = "master-kernel"; 502 #qcom,smem-state-cells = <1>; 503 }; 504 505 wpss_smp2p_in: slave-kernel { 506 qcom,entry-name = "slave-kernel"; 507 interrupt-controller; 508 #interrupt-cells = <2>; 509 }; 510 }; 511 512 pmu { 513 compatible = "arm,armv8-pmuv3"; 514 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 515 }; 516 517 psci { 518 compatible = "arm,psci-1.0"; 519 method = "smc"; 520 }; 521 522 qspi_opp_table: qspi-opp-table { 523 compatible = "operating-points-v2"; 524 525 opp-75000000 { 526 opp-hz = /bits/ 64 <75000000>; 527 required-opps = <&rpmhpd_opp_low_svs>; 528 }; 529 530 opp-150000000 { 531 opp-hz = /bits/ 64 <150000000>; 532 required-opps = <&rpmhpd_opp_svs>; 533 }; 534 535 opp-300000000 { 536 opp-hz = /bits/ 64 <300000000>; 537 required-opps = <&rpmhpd_opp_nom>; 538 }; 539 }; 540 541 qup_opp_table: qup-opp-table { 542 compatible = "operating-points-v2"; 543 544 opp-75000000 { 545 opp-hz = /bits/ 64 <75000000>; 546 required-opps = <&rpmhpd_opp_low_svs>; 547 }; 548 549 opp-100000000 { 550 opp-hz = /bits/ 64 <100000000>; 551 required-opps = <&rpmhpd_opp_svs>; 552 }; 553 554 opp-128000000 { 555 opp-hz = /bits/ 64 <128000000>; 556 required-opps = <&rpmhpd_opp_nom>; 557 }; 558 }; 559 560 soc: soc@0 { 561 #address-cells = <2>; 562 #size-cells = <2>; 563 ranges = <0 0 0 0 0x10 0>; 564 dma-ranges = <0 0 0 0 0x10 0>; 565 compatible = "simple-bus"; 566 567 gcc: clock-controller@100000 { 568 compatible = "qcom,gcc-sc7280"; 569 reg = <0 0x00100000 0 0x1f0000>; 570 clocks = <&rpmhcc RPMH_CXO_CLK>, 571 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 572 <0>, <0>, <0>, <0>, <0>, <0>; 573 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 574 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 575 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 576 "ufs_phy_tx_symbol_0_clk", 577 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 578 #clock-cells = <1>; 579 #reset-cells = <1>; 580 #power-domain-cells = <1>; 581 }; 582 583 ipcc: mailbox@408000 { 584 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 585 reg = <0 0x00408000 0 0x1000>; 586 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 587 interrupt-controller; 588 #interrupt-cells = <3>; 589 #mbox-cells = <2>; 590 }; 591 592 qfprom: efuse@784000 { 593 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 594 reg = <0 0x00784000 0 0xa20>, 595 <0 0x00780000 0 0xa20>, 596 <0 0x00782000 0 0x120>, 597 <0 0x00786000 0 0x1fff>; 598 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 599 clock-names = "core"; 600 power-domains = <&rpmhpd SC7280_MX>; 601 #address-cells = <1>; 602 #size-cells = <1>; 603 }; 604 605 sdhc_1: sdhci@7c4000 { 606 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 607 status = "disabled"; 608 609 reg = <0 0x007c4000 0 0x1000>, 610 <0 0x007c5000 0 0x1000>; 611 reg-names = "hc", "cqhci"; 612 613 iommus = <&apps_smmu 0xc0 0x0>; 614 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 616 interrupt-names = "hc_irq", "pwr_irq"; 617 618 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 619 <&gcc GCC_SDCC1_AHB_CLK>, 620 <&rpmhcc RPMH_CXO_CLK>; 621 clock-names = "core", "iface", "xo"; 622 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 623 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 624 interconnect-names = "sdhc-ddr","cpu-sdhc"; 625 power-domains = <&rpmhpd SC7280_CX>; 626 operating-points-v2 = <&sdhc1_opp_table>; 627 628 bus-width = <8>; 629 supports-cqe; 630 631 qcom,dll-config = <0x0007642c>; 632 qcom,ddr-config = <0x80040868>; 633 634 mmc-ddr-1_8v; 635 mmc-hs200-1_8v; 636 mmc-hs400-1_8v; 637 mmc-hs400-enhanced-strobe; 638 639 sdhc1_opp_table: opp-table { 640 compatible = "operating-points-v2"; 641 642 opp-100000000 { 643 opp-hz = /bits/ 64 <100000000>; 644 required-opps = <&rpmhpd_opp_low_svs>; 645 opp-peak-kBps = <1800000 400000>; 646 opp-avg-kBps = <100000 0>; 647 }; 648 649 opp-384000000 { 650 opp-hz = /bits/ 64 <384000000>; 651 required-opps = <&rpmhpd_opp_nom>; 652 opp-peak-kBps = <5400000 1600000>; 653 opp-avg-kBps = <390000 0>; 654 }; 655 }; 656 657 }; 658 659 qupv3_id_0: geniqup@9c0000 { 660 compatible = "qcom,geni-se-qup"; 661 reg = <0 0x009c0000 0 0x2000>; 662 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 663 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 664 clock-names = "m-ahb", "s-ahb"; 665 #address-cells = <2>; 666 #size-cells = <2>; 667 ranges; 668 iommus = <&apps_smmu 0x123 0x0>; 669 status = "disabled"; 670 671 i2c0: i2c@980000 { 672 compatible = "qcom,geni-i2c"; 673 reg = <0 0x00980000 0 0x4000>; 674 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 675 clock-names = "se"; 676 pinctrl-names = "default"; 677 pinctrl-0 = <&qup_i2c0_data_clk>; 678 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 682 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 683 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 684 interconnect-names = "qup-core", "qup-config", 685 "qup-memory"; 686 status = "disabled"; 687 }; 688 689 spi0: spi@980000 { 690 compatible = "qcom,geni-spi"; 691 reg = <0 0x00980000 0 0x4000>; 692 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 693 clock-names = "se"; 694 pinctrl-names = "default"; 695 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 696 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 697 #address-cells = <1>; 698 #size-cells = <0>; 699 power-domains = <&rpmhpd SC7280_CX>; 700 operating-points-v2 = <&qup_opp_table>; 701 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 702 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 703 interconnect-names = "qup-core", "qup-config"; 704 status = "disabled"; 705 }; 706 707 uart0: serial@980000 { 708 compatible = "qcom,geni-uart"; 709 reg = <0 0x00980000 0 0x4000>; 710 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 711 clock-names = "se"; 712 pinctrl-names = "default"; 713 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 714 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 715 power-domains = <&rpmhpd SC7280_CX>; 716 operating-points-v2 = <&qup_opp_table>; 717 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 718 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 719 interconnect-names = "qup-core", "qup-config"; 720 status = "disabled"; 721 }; 722 723 i2c1: i2c@984000 { 724 compatible = "qcom,geni-i2c"; 725 reg = <0 0x00984000 0 0x4000>; 726 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 727 clock-names = "se"; 728 pinctrl-names = "default"; 729 pinctrl-0 = <&qup_i2c1_data_clk>; 730 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 731 #address-cells = <1>; 732 #size-cells = <0>; 733 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 734 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 735 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 736 interconnect-names = "qup-core", "qup-config", 737 "qup-memory"; 738 status = "disabled"; 739 }; 740 741 spi1: spi@984000 { 742 compatible = "qcom,geni-spi"; 743 reg = <0 0x00984000 0 0x4000>; 744 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 745 clock-names = "se"; 746 pinctrl-names = "default"; 747 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 748 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 749 #address-cells = <1>; 750 #size-cells = <0>; 751 power-domains = <&rpmhpd SC7280_CX>; 752 operating-points-v2 = <&qup_opp_table>; 753 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 754 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 755 interconnect-names = "qup-core", "qup-config"; 756 status = "disabled"; 757 }; 758 759 uart1: serial@984000 { 760 compatible = "qcom,geni-uart"; 761 reg = <0 0x00984000 0 0x4000>; 762 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 763 clock-names = "se"; 764 pinctrl-names = "default"; 765 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 766 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 767 power-domains = <&rpmhpd SC7280_CX>; 768 operating-points-v2 = <&qup_opp_table>; 769 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 770 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 771 interconnect-names = "qup-core", "qup-config"; 772 status = "disabled"; 773 }; 774 775 i2c2: i2c@988000 { 776 compatible = "qcom,geni-i2c"; 777 reg = <0 0x00988000 0 0x4000>; 778 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 779 clock-names = "se"; 780 pinctrl-names = "default"; 781 pinctrl-0 = <&qup_i2c2_data_clk>; 782 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 783 #address-cells = <1>; 784 #size-cells = <0>; 785 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 786 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 787 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 788 interconnect-names = "qup-core", "qup-config", 789 "qup-memory"; 790 status = "disabled"; 791 }; 792 793 spi2: spi@988000 { 794 compatible = "qcom,geni-spi"; 795 reg = <0 0x00988000 0 0x4000>; 796 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 797 clock-names = "se"; 798 pinctrl-names = "default"; 799 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 800 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 power-domains = <&rpmhpd SC7280_CX>; 804 operating-points-v2 = <&qup_opp_table>; 805 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 806 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 807 interconnect-names = "qup-core", "qup-config"; 808 status = "disabled"; 809 }; 810 811 uart2: serial@988000 { 812 compatible = "qcom,geni-uart"; 813 reg = <0 0x00988000 0 0x4000>; 814 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 815 clock-names = "se"; 816 pinctrl-names = "default"; 817 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 818 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 819 power-domains = <&rpmhpd SC7280_CX>; 820 operating-points-v2 = <&qup_opp_table>; 821 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 822 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 823 interconnect-names = "qup-core", "qup-config"; 824 status = "disabled"; 825 }; 826 827 i2c3: i2c@98c000 { 828 compatible = "qcom,geni-i2c"; 829 reg = <0 0x0098c000 0 0x4000>; 830 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 831 clock-names = "se"; 832 pinctrl-names = "default"; 833 pinctrl-0 = <&qup_i2c3_data_clk>; 834 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 838 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 839 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 840 interconnect-names = "qup-core", "qup-config", 841 "qup-memory"; 842 status = "disabled"; 843 }; 844 845 spi3: spi@98c000 { 846 compatible = "qcom,geni-spi"; 847 reg = <0 0x0098c000 0 0x4000>; 848 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 849 clock-names = "se"; 850 pinctrl-names = "default"; 851 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 852 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 853 #address-cells = <1>; 854 #size-cells = <0>; 855 power-domains = <&rpmhpd SC7280_CX>; 856 operating-points-v2 = <&qup_opp_table>; 857 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 858 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 859 interconnect-names = "qup-core", "qup-config"; 860 status = "disabled"; 861 }; 862 863 uart3: serial@98c000 { 864 compatible = "qcom,geni-uart"; 865 reg = <0 0x0098c000 0 0x4000>; 866 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 867 clock-names = "se"; 868 pinctrl-names = "default"; 869 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 870 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 871 power-domains = <&rpmhpd SC7280_CX>; 872 operating-points-v2 = <&qup_opp_table>; 873 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 874 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 875 interconnect-names = "qup-core", "qup-config"; 876 status = "disabled"; 877 }; 878 879 i2c4: i2c@990000 { 880 compatible = "qcom,geni-i2c"; 881 reg = <0 0x00990000 0 0x4000>; 882 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 883 clock-names = "se"; 884 pinctrl-names = "default"; 885 pinctrl-0 = <&qup_i2c4_data_clk>; 886 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 887 #address-cells = <1>; 888 #size-cells = <0>; 889 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 890 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 891 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 892 interconnect-names = "qup-core", "qup-config", 893 "qup-memory"; 894 status = "disabled"; 895 }; 896 897 spi4: spi@990000 { 898 compatible = "qcom,geni-spi"; 899 reg = <0 0x00990000 0 0x4000>; 900 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 901 clock-names = "se"; 902 pinctrl-names = "default"; 903 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 904 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 power-domains = <&rpmhpd SC7280_CX>; 908 operating-points-v2 = <&qup_opp_table>; 909 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 910 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 911 interconnect-names = "qup-core", "qup-config"; 912 status = "disabled"; 913 }; 914 915 uart4: serial@990000 { 916 compatible = "qcom,geni-uart"; 917 reg = <0 0x00990000 0 0x4000>; 918 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 919 clock-names = "se"; 920 pinctrl-names = "default"; 921 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 922 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 923 power-domains = <&rpmhpd SC7280_CX>; 924 operating-points-v2 = <&qup_opp_table>; 925 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 926 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 927 interconnect-names = "qup-core", "qup-config"; 928 status = "disabled"; 929 }; 930 931 i2c5: i2c@994000 { 932 compatible = "qcom,geni-i2c"; 933 reg = <0 0x00994000 0 0x4000>; 934 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 935 clock-names = "se"; 936 pinctrl-names = "default"; 937 pinctrl-0 = <&qup_i2c5_data_clk>; 938 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 939 #address-cells = <1>; 940 #size-cells = <0>; 941 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 942 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 943 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 944 interconnect-names = "qup-core", "qup-config", 945 "qup-memory"; 946 status = "disabled"; 947 }; 948 949 spi5: spi@994000 { 950 compatible = "qcom,geni-spi"; 951 reg = <0 0x00994000 0 0x4000>; 952 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 953 clock-names = "se"; 954 pinctrl-names = "default"; 955 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 956 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 957 #address-cells = <1>; 958 #size-cells = <0>; 959 power-domains = <&rpmhpd SC7280_CX>; 960 operating-points-v2 = <&qup_opp_table>; 961 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 962 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 963 interconnect-names = "qup-core", "qup-config"; 964 status = "disabled"; 965 }; 966 967 uart5: serial@994000 { 968 compatible = "qcom,geni-uart"; 969 reg = <0 0x00994000 0 0x4000>; 970 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 971 clock-names = "se"; 972 pinctrl-names = "default"; 973 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 974 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 975 power-domains = <&rpmhpd SC7280_CX>; 976 operating-points-v2 = <&qup_opp_table>; 977 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 978 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 979 interconnect-names = "qup-core", "qup-config"; 980 status = "disabled"; 981 }; 982 983 i2c6: i2c@998000 { 984 compatible = "qcom,geni-i2c"; 985 reg = <0 0x00998000 0 0x4000>; 986 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 987 clock-names = "se"; 988 pinctrl-names = "default"; 989 pinctrl-0 = <&qup_i2c6_data_clk>; 990 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 991 #address-cells = <1>; 992 #size-cells = <0>; 993 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 994 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 995 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 996 interconnect-names = "qup-core", "qup-config", 997 "qup-memory"; 998 status = "disabled"; 999 }; 1000 1001 spi6: spi@998000 { 1002 compatible = "qcom,geni-spi"; 1003 reg = <0 0x00998000 0 0x4000>; 1004 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1005 clock-names = "se"; 1006 pinctrl-names = "default"; 1007 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1008 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1009 #address-cells = <1>; 1010 #size-cells = <0>; 1011 power-domains = <&rpmhpd SC7280_CX>; 1012 operating-points-v2 = <&qup_opp_table>; 1013 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1014 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1015 interconnect-names = "qup-core", "qup-config"; 1016 status = "disabled"; 1017 }; 1018 1019 uart6: serial@998000 { 1020 compatible = "qcom,geni-uart"; 1021 reg = <0 0x00998000 0 0x4000>; 1022 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1023 clock-names = "se"; 1024 pinctrl-names = "default"; 1025 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1026 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1027 power-domains = <&rpmhpd SC7280_CX>; 1028 operating-points-v2 = <&qup_opp_table>; 1029 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1030 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1031 interconnect-names = "qup-core", "qup-config"; 1032 status = "disabled"; 1033 }; 1034 1035 i2c7: i2c@99c000 { 1036 compatible = "qcom,geni-i2c"; 1037 reg = <0 0x0099c000 0 0x4000>; 1038 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1039 clock-names = "se"; 1040 pinctrl-names = "default"; 1041 pinctrl-0 = <&qup_i2c7_data_clk>; 1042 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1043 #address-cells = <1>; 1044 #size-cells = <0>; 1045 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1046 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1047 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1048 interconnect-names = "qup-core", "qup-config", 1049 "qup-memory"; 1050 status = "disabled"; 1051 }; 1052 1053 spi7: spi@99c000 { 1054 compatible = "qcom,geni-spi"; 1055 reg = <0 0x0099c000 0 0x4000>; 1056 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1057 clock-names = "se"; 1058 pinctrl-names = "default"; 1059 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1060 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 power-domains = <&rpmhpd SC7280_CX>; 1064 operating-points-v2 = <&qup_opp_table>; 1065 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1066 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1067 interconnect-names = "qup-core", "qup-config"; 1068 status = "disabled"; 1069 }; 1070 1071 uart7: serial@99c000 { 1072 compatible = "qcom,geni-uart"; 1073 reg = <0 0x0099c000 0 0x4000>; 1074 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1075 clock-names = "se"; 1076 pinctrl-names = "default"; 1077 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1078 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1079 power-domains = <&rpmhpd SC7280_CX>; 1080 operating-points-v2 = <&qup_opp_table>; 1081 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1082 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1083 interconnect-names = "qup-core", "qup-config"; 1084 status = "disabled"; 1085 }; 1086 }; 1087 1088 qupv3_id_1: geniqup@ac0000 { 1089 compatible = "qcom,geni-se-qup"; 1090 reg = <0 0x00ac0000 0 0x2000>; 1091 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1092 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1093 clock-names = "m-ahb", "s-ahb"; 1094 #address-cells = <2>; 1095 #size-cells = <2>; 1096 ranges; 1097 iommus = <&apps_smmu 0x43 0x0>; 1098 status = "disabled"; 1099 1100 i2c8: i2c@a80000 { 1101 compatible = "qcom,geni-i2c"; 1102 reg = <0 0x00a80000 0 0x4000>; 1103 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1104 clock-names = "se"; 1105 pinctrl-names = "default"; 1106 pinctrl-0 = <&qup_i2c8_data_clk>; 1107 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1111 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1112 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1113 interconnect-names = "qup-core", "qup-config", 1114 "qup-memory"; 1115 status = "disabled"; 1116 }; 1117 1118 spi8: spi@a80000 { 1119 compatible = "qcom,geni-spi"; 1120 reg = <0 0x00a80000 0 0x4000>; 1121 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1122 clock-names = "se"; 1123 pinctrl-names = "default"; 1124 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1125 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 power-domains = <&rpmhpd SC7280_CX>; 1129 operating-points-v2 = <&qup_opp_table>; 1130 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1131 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1132 interconnect-names = "qup-core", "qup-config"; 1133 status = "disabled"; 1134 }; 1135 1136 uart8: serial@a80000 { 1137 compatible = "qcom,geni-uart"; 1138 reg = <0 0x00a80000 0 0x4000>; 1139 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1140 clock-names = "se"; 1141 pinctrl-names = "default"; 1142 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1143 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1144 power-domains = <&rpmhpd SC7280_CX>; 1145 operating-points-v2 = <&qup_opp_table>; 1146 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1147 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1148 interconnect-names = "qup-core", "qup-config"; 1149 status = "disabled"; 1150 }; 1151 1152 i2c9: i2c@a84000 { 1153 compatible = "qcom,geni-i2c"; 1154 reg = <0 0x00a84000 0 0x4000>; 1155 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1156 clock-names = "se"; 1157 pinctrl-names = "default"; 1158 pinctrl-0 = <&qup_i2c9_data_clk>; 1159 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1163 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1164 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1165 interconnect-names = "qup-core", "qup-config", 1166 "qup-memory"; 1167 status = "disabled"; 1168 }; 1169 1170 spi9: spi@a84000 { 1171 compatible = "qcom,geni-spi"; 1172 reg = <0 0x00a84000 0 0x4000>; 1173 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1174 clock-names = "se"; 1175 pinctrl-names = "default"; 1176 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1177 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1178 #address-cells = <1>; 1179 #size-cells = <0>; 1180 power-domains = <&rpmhpd SC7280_CX>; 1181 operating-points-v2 = <&qup_opp_table>; 1182 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1183 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1184 interconnect-names = "qup-core", "qup-config"; 1185 status = "disabled"; 1186 }; 1187 1188 uart9: serial@a84000 { 1189 compatible = "qcom,geni-uart"; 1190 reg = <0 0x00a84000 0 0x4000>; 1191 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1192 clock-names = "se"; 1193 pinctrl-names = "default"; 1194 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1195 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1196 power-domains = <&rpmhpd SC7280_CX>; 1197 operating-points-v2 = <&qup_opp_table>; 1198 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1199 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1200 interconnect-names = "qup-core", "qup-config"; 1201 status = "disabled"; 1202 }; 1203 1204 i2c10: i2c@a88000 { 1205 compatible = "qcom,geni-i2c"; 1206 reg = <0 0x00a88000 0 0x4000>; 1207 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1208 clock-names = "se"; 1209 pinctrl-names = "default"; 1210 pinctrl-0 = <&qup_i2c10_data_clk>; 1211 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1215 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1216 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1217 interconnect-names = "qup-core", "qup-config", 1218 "qup-memory"; 1219 status = "disabled"; 1220 }; 1221 1222 spi10: spi@a88000 { 1223 compatible = "qcom,geni-spi"; 1224 reg = <0 0x00a88000 0 0x4000>; 1225 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1226 clock-names = "se"; 1227 pinctrl-names = "default"; 1228 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1229 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1230 #address-cells = <1>; 1231 #size-cells = <0>; 1232 power-domains = <&rpmhpd SC7280_CX>; 1233 operating-points-v2 = <&qup_opp_table>; 1234 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1235 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1236 interconnect-names = "qup-core", "qup-config"; 1237 status = "disabled"; 1238 }; 1239 1240 uart10: serial@a88000 { 1241 compatible = "qcom,geni-uart"; 1242 reg = <0 0x00a88000 0 0x4000>; 1243 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1244 clock-names = "se"; 1245 pinctrl-names = "default"; 1246 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1247 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1248 power-domains = <&rpmhpd SC7280_CX>; 1249 operating-points-v2 = <&qup_opp_table>; 1250 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1251 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1252 interconnect-names = "qup-core", "qup-config"; 1253 status = "disabled"; 1254 }; 1255 1256 i2c11: i2c@a8c000 { 1257 compatible = "qcom,geni-i2c"; 1258 reg = <0 0x00a8c000 0 0x4000>; 1259 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1260 clock-names = "se"; 1261 pinctrl-names = "default"; 1262 pinctrl-0 = <&qup_i2c11_data_clk>; 1263 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1264 #address-cells = <1>; 1265 #size-cells = <0>; 1266 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1267 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1268 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1269 interconnect-names = "qup-core", "qup-config", 1270 "qup-memory"; 1271 status = "disabled"; 1272 }; 1273 1274 spi11: spi@a8c000 { 1275 compatible = "qcom,geni-spi"; 1276 reg = <0 0x00a8c000 0 0x4000>; 1277 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1278 clock-names = "se"; 1279 pinctrl-names = "default"; 1280 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1281 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 power-domains = <&rpmhpd SC7280_CX>; 1285 operating-points-v2 = <&qup_opp_table>; 1286 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1287 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1288 interconnect-names = "qup-core", "qup-config"; 1289 status = "disabled"; 1290 }; 1291 1292 uart11: serial@a8c000 { 1293 compatible = "qcom,geni-uart"; 1294 reg = <0 0x00a8c000 0 0x4000>; 1295 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1296 clock-names = "se"; 1297 pinctrl-names = "default"; 1298 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1299 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1300 power-domains = <&rpmhpd SC7280_CX>; 1301 operating-points-v2 = <&qup_opp_table>; 1302 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1303 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1304 interconnect-names = "qup-core", "qup-config"; 1305 status = "disabled"; 1306 }; 1307 1308 i2c12: i2c@a90000 { 1309 compatible = "qcom,geni-i2c"; 1310 reg = <0 0x00a90000 0 0x4000>; 1311 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1312 clock-names = "se"; 1313 pinctrl-names = "default"; 1314 pinctrl-0 = <&qup_i2c12_data_clk>; 1315 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1316 #address-cells = <1>; 1317 #size-cells = <0>; 1318 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1319 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1320 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1321 interconnect-names = "qup-core", "qup-config", 1322 "qup-memory"; 1323 status = "disabled"; 1324 }; 1325 1326 spi12: spi@a90000 { 1327 compatible = "qcom,geni-spi"; 1328 reg = <0 0x00a90000 0 0x4000>; 1329 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1330 clock-names = "se"; 1331 pinctrl-names = "default"; 1332 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1333 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1334 #address-cells = <1>; 1335 #size-cells = <0>; 1336 power-domains = <&rpmhpd SC7280_CX>; 1337 operating-points-v2 = <&qup_opp_table>; 1338 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1339 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1340 interconnect-names = "qup-core", "qup-config"; 1341 status = "disabled"; 1342 }; 1343 1344 uart12: serial@a90000 { 1345 compatible = "qcom,geni-uart"; 1346 reg = <0 0x00a90000 0 0x4000>; 1347 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1348 clock-names = "se"; 1349 pinctrl-names = "default"; 1350 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1351 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1352 power-domains = <&rpmhpd SC7280_CX>; 1353 operating-points-v2 = <&qup_opp_table>; 1354 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1355 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1356 interconnect-names = "qup-core", "qup-config"; 1357 status = "disabled"; 1358 }; 1359 1360 i2c13: i2c@a94000 { 1361 compatible = "qcom,geni-i2c"; 1362 reg = <0 0x00a94000 0 0x4000>; 1363 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1364 clock-names = "se"; 1365 pinctrl-names = "default"; 1366 pinctrl-0 = <&qup_i2c13_data_clk>; 1367 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1368 #address-cells = <1>; 1369 #size-cells = <0>; 1370 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1371 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1372 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1373 interconnect-names = "qup-core", "qup-config", 1374 "qup-memory"; 1375 status = "disabled"; 1376 }; 1377 1378 spi13: spi@a94000 { 1379 compatible = "qcom,geni-spi"; 1380 reg = <0 0x00a94000 0 0x4000>; 1381 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1382 clock-names = "se"; 1383 pinctrl-names = "default"; 1384 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1385 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1386 #address-cells = <1>; 1387 #size-cells = <0>; 1388 power-domains = <&rpmhpd SC7280_CX>; 1389 operating-points-v2 = <&qup_opp_table>; 1390 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1391 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1392 interconnect-names = "qup-core", "qup-config"; 1393 status = "disabled"; 1394 }; 1395 1396 uart13: serial@a94000 { 1397 compatible = "qcom,geni-uart"; 1398 reg = <0 0x00a94000 0 0x4000>; 1399 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1400 clock-names = "se"; 1401 pinctrl-names = "default"; 1402 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1403 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1404 power-domains = <&rpmhpd SC7280_CX>; 1405 operating-points-v2 = <&qup_opp_table>; 1406 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1407 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1408 interconnect-names = "qup-core", "qup-config"; 1409 status = "disabled"; 1410 }; 1411 1412 i2c14: i2c@a98000 { 1413 compatible = "qcom,geni-i2c"; 1414 reg = <0 0x00a98000 0 0x4000>; 1415 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1416 clock-names = "se"; 1417 pinctrl-names = "default"; 1418 pinctrl-0 = <&qup_i2c14_data_clk>; 1419 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1420 #address-cells = <1>; 1421 #size-cells = <0>; 1422 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1423 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1424 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1425 interconnect-names = "qup-core", "qup-config", 1426 "qup-memory"; 1427 status = "disabled"; 1428 }; 1429 1430 spi14: spi@a98000 { 1431 compatible = "qcom,geni-spi"; 1432 reg = <0 0x00a98000 0 0x4000>; 1433 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1434 clock-names = "se"; 1435 pinctrl-names = "default"; 1436 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1437 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1438 #address-cells = <1>; 1439 #size-cells = <0>; 1440 power-domains = <&rpmhpd SC7280_CX>; 1441 operating-points-v2 = <&qup_opp_table>; 1442 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1443 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1444 interconnect-names = "qup-core", "qup-config"; 1445 status = "disabled"; 1446 }; 1447 1448 uart14: serial@a98000 { 1449 compatible = "qcom,geni-uart"; 1450 reg = <0 0x00a98000 0 0x4000>; 1451 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1452 clock-names = "se"; 1453 pinctrl-names = "default"; 1454 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1455 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1456 power-domains = <&rpmhpd SC7280_CX>; 1457 operating-points-v2 = <&qup_opp_table>; 1458 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1459 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1460 interconnect-names = "qup-core", "qup-config"; 1461 status = "disabled"; 1462 }; 1463 1464 i2c15: i2c@a9c000 { 1465 compatible = "qcom,geni-i2c"; 1466 reg = <0 0x00a9c000 0 0x4000>; 1467 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1468 clock-names = "se"; 1469 pinctrl-names = "default"; 1470 pinctrl-0 = <&qup_i2c15_data_clk>; 1471 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1472 #address-cells = <1>; 1473 #size-cells = <0>; 1474 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1475 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1476 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1477 interconnect-names = "qup-core", "qup-config", 1478 "qup-memory"; 1479 status = "disabled"; 1480 }; 1481 1482 spi15: spi@a9c000 { 1483 compatible = "qcom,geni-spi"; 1484 reg = <0 0x00a9c000 0 0x4000>; 1485 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1486 clock-names = "se"; 1487 pinctrl-names = "default"; 1488 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1489 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1490 #address-cells = <1>; 1491 #size-cells = <0>; 1492 power-domains = <&rpmhpd SC7280_CX>; 1493 operating-points-v2 = <&qup_opp_table>; 1494 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1495 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1496 interconnect-names = "qup-core", "qup-config"; 1497 status = "disabled"; 1498 }; 1499 1500 uart15: serial@a9c000 { 1501 compatible = "qcom,geni-uart"; 1502 reg = <0 0x00a9c000 0 0x4000>; 1503 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1504 clock-names = "se"; 1505 pinctrl-names = "default"; 1506 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1507 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1508 power-domains = <&rpmhpd SC7280_CX>; 1509 operating-points-v2 = <&qup_opp_table>; 1510 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1511 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1512 interconnect-names = "qup-core", "qup-config"; 1513 status = "disabled"; 1514 }; 1515 }; 1516 1517 cnoc2: interconnect@1500000 { 1518 reg = <0 0x01500000 0 0x1000>; 1519 compatible = "qcom,sc7280-cnoc2"; 1520 #interconnect-cells = <2>; 1521 qcom,bcm-voters = <&apps_bcm_voter>; 1522 }; 1523 1524 cnoc3: interconnect@1502000 { 1525 reg = <0 0x01502000 0 0x1000>; 1526 compatible = "qcom,sc7280-cnoc3"; 1527 #interconnect-cells = <2>; 1528 qcom,bcm-voters = <&apps_bcm_voter>; 1529 }; 1530 1531 mc_virt: interconnect@1580000 { 1532 reg = <0 0x01580000 0 0x4>; 1533 compatible = "qcom,sc7280-mc-virt"; 1534 #interconnect-cells = <2>; 1535 qcom,bcm-voters = <&apps_bcm_voter>; 1536 }; 1537 1538 system_noc: interconnect@1680000 { 1539 reg = <0 0x01680000 0 0x15480>; 1540 compatible = "qcom,sc7280-system-noc"; 1541 #interconnect-cells = <2>; 1542 qcom,bcm-voters = <&apps_bcm_voter>; 1543 }; 1544 1545 aggre1_noc: interconnect@16e0000 { 1546 compatible = "qcom,sc7280-aggre1-noc"; 1547 reg = <0 0x016e0000 0 0x1c080>; 1548 #interconnect-cells = <2>; 1549 qcom,bcm-voters = <&apps_bcm_voter>; 1550 }; 1551 1552 aggre2_noc: interconnect@1700000 { 1553 reg = <0 0x01700000 0 0x2b080>; 1554 compatible = "qcom,sc7280-aggre2-noc"; 1555 #interconnect-cells = <2>; 1556 qcom,bcm-voters = <&apps_bcm_voter>; 1557 }; 1558 1559 mmss_noc: interconnect@1740000 { 1560 reg = <0 0x01740000 0 0x1e080>; 1561 compatible = "qcom,sc7280-mmss-noc"; 1562 #interconnect-cells = <2>; 1563 qcom,bcm-voters = <&apps_bcm_voter>; 1564 }; 1565 1566 ipa: ipa@1e40000 { 1567 compatible = "qcom,sc7280-ipa"; 1568 1569 iommus = <&apps_smmu 0x480 0x0>, 1570 <&apps_smmu 0x482 0x0>; 1571 reg = <0 0x1e40000 0 0x8000>, 1572 <0 0x1e50000 0 0x4ad0>, 1573 <0 0x1e04000 0 0x23000>; 1574 reg-names = "ipa-reg", 1575 "ipa-shared", 1576 "gsi"; 1577 1578 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 1579 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1580 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1581 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1582 interrupt-names = "ipa", 1583 "gsi", 1584 "ipa-clock-query", 1585 "ipa-setup-ready"; 1586 1587 clocks = <&rpmhcc RPMH_IPA_CLK>; 1588 clock-names = "core"; 1589 1590 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1591 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 1592 interconnect-names = "memory", 1593 "config"; 1594 1595 qcom,smem-states = <&ipa_smp2p_out 0>, 1596 <&ipa_smp2p_out 1>; 1597 qcom,smem-state-names = "ipa-clock-enabled-valid", 1598 "ipa-clock-enabled"; 1599 1600 status = "disabled"; 1601 }; 1602 1603 tcsr_mutex: hwlock@1f40000 { 1604 compatible = "qcom,tcsr-mutex", "syscon"; 1605 reg = <0 0x01f40000 0 0x40000>; 1606 #hwlock-cells = <1>; 1607 }; 1608 1609 tcsr: syscon@1fc0000 { 1610 compatible = "qcom,sc7280-tcsr", "syscon"; 1611 reg = <0 0x01fc0000 0 0x30000>; 1612 }; 1613 1614 lpasscc: lpasscc@3000000 { 1615 compatible = "qcom,sc7280-lpasscc"; 1616 reg = <0 0x03000000 0 0x40>, 1617 <0 0x03c04000 0 0x4>, 1618 <0 0x03389000 0 0x24>; 1619 reg-names = "qdsp6ss", "top_cc", "cc"; 1620 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 1621 clock-names = "iface"; 1622 #clock-cells = <1>; 1623 }; 1624 1625 lpass_ag_noc: interconnect@3c40000 { 1626 reg = <0 0x03c40000 0 0xf080>; 1627 compatible = "qcom,sc7280-lpass-ag-noc"; 1628 #interconnect-cells = <2>; 1629 qcom,bcm-voters = <&apps_bcm_voter>; 1630 }; 1631 1632 gpu: gpu@3d00000 { 1633 compatible = "qcom,adreno-635.0", "qcom,adreno"; 1634 #stream-id-cells = <16>; 1635 reg = <0 0x03d00000 0 0x40000>, 1636 <0 0x03d9e000 0 0x1000>, 1637 <0 0x03d61000 0 0x800>; 1638 reg-names = "kgsl_3d0_reg_memory", 1639 "cx_mem", 1640 "cx_dbgc"; 1641 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1642 iommus = <&adreno_smmu 0 0x401>; 1643 operating-points-v2 = <&gpu_opp_table>; 1644 qcom,gmu = <&gmu>; 1645 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 1646 interconnect-names = "gfx-mem"; 1647 #cooling-cells = <2>; 1648 1649 gpu_opp_table: opp-table { 1650 compatible = "operating-points-v2"; 1651 1652 opp-315000000 { 1653 opp-hz = /bits/ 64 <315000000>; 1654 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1655 opp-peak-kBps = <1804000>; 1656 }; 1657 1658 opp-450000000 { 1659 opp-hz = /bits/ 64 <450000000>; 1660 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1661 opp-peak-kBps = <4068000>; 1662 }; 1663 1664 opp-550000000 { 1665 opp-hz = /bits/ 64 <550000000>; 1666 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1667 opp-peak-kBps = <6832000>; 1668 }; 1669 }; 1670 }; 1671 1672 gmu: gmu@3d69000 { 1673 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 1674 reg = <0 0x03d6a000 0 0x34000>, 1675 <0 0x3de0000 0 0x10000>, 1676 <0 0x0b290000 0 0x10000>; 1677 reg-names = "gmu", "rscc", "gmu_pdc"; 1678 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1680 interrupt-names = "hfi", "gmu"; 1681 clocks = <&gpucc 5>, 1682 <&gpucc 8>, 1683 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1684 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1685 <&gpucc 2>, 1686 <&gpucc 15>, 1687 <&gpucc 11>; 1688 clock-names = "gmu", 1689 "cxo", 1690 "axi", 1691 "memnoc", 1692 "ahb", 1693 "hub", 1694 "smmu_vote"; 1695 power-domains = <&gpucc 0>, 1696 <&gpucc 1>; 1697 power-domain-names = "cx", 1698 "gx"; 1699 iommus = <&adreno_smmu 5 0x400>; 1700 operating-points-v2 = <&gmu_opp_table>; 1701 1702 gmu_opp_table: opp-table { 1703 compatible = "operating-points-v2"; 1704 1705 opp-200000000 { 1706 opp-hz = /bits/ 64 <200000000>; 1707 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1708 }; 1709 }; 1710 }; 1711 1712 gpucc: clock-controller@3d90000 { 1713 compatible = "qcom,sc7280-gpucc"; 1714 reg = <0 0x03d90000 0 0x9000>; 1715 clocks = <&rpmhcc RPMH_CXO_CLK>, 1716 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1717 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1718 clock-names = "bi_tcxo", 1719 "gcc_gpu_gpll0_clk_src", 1720 "gcc_gpu_gpll0_div_clk_src"; 1721 #clock-cells = <1>; 1722 #reset-cells = <1>; 1723 #power-domain-cells = <1>; 1724 }; 1725 1726 adreno_smmu: iommu@3da0000 { 1727 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 1728 reg = <0 0x03da0000 0 0x20000>; 1729 #iommu-cells = <2>; 1730 #global-interrupts = <2>; 1731 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1743 1744 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1745 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1746 <&gpucc 2>, 1747 <&gpucc 11>, 1748 <&gpucc 5>, 1749 <&gpucc 15>, 1750 <&gpucc 13>; 1751 clock-names = "gcc_gpu_memnoc_gfx_clk", 1752 "gcc_gpu_snoc_dvm_gfx_clk", 1753 "gpu_cc_ahb_clk", 1754 "gpu_cc_hlos1_vote_gpu_smmu_clk", 1755 "gpu_cc_cx_gmu_clk", 1756 "gpu_cc_hub_cx_int_clk", 1757 "gpu_cc_hub_aon_clk"; 1758 1759 power-domains = <&gpucc 0>; 1760 }; 1761 1762 remoteproc_mpss: remoteproc@4080000 { 1763 compatible = "qcom,sc7280-mpss-pas"; 1764 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 1765 reg-names = "qdsp6", "rmb"; 1766 1767 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 1768 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1769 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1770 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1771 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1772 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1773 interrupt-names = "wdog", "fatal", "ready", "handover", 1774 "stop-ack", "shutdown-ack"; 1775 1776 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1777 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 1778 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1779 <&rpmhcc RPMH_PKA_CLK>, 1780 <&rpmhcc RPMH_CXO_CLK>; 1781 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 1782 1783 power-domains = <&rpmhpd SC7280_CX>, 1784 <&rpmhpd SC7280_MSS>; 1785 power-domain-names = "cx", "mss"; 1786 1787 memory-region = <&mpss_mem>; 1788 1789 qcom,qmp = <&aoss_qmp>; 1790 1791 qcom,smem-states = <&modem_smp2p_out 0>; 1792 qcom,smem-state-names = "stop"; 1793 1794 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 1795 <&pdc_reset PDC_MODEM_SYNC_RESET>; 1796 reset-names = "mss_restart", "pdc_reset"; 1797 1798 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; 1799 qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>; 1800 qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>; 1801 1802 status = "disabled"; 1803 1804 glink-edge { 1805 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1806 IPCC_MPROC_SIGNAL_GLINK_QMP 1807 IRQ_TYPE_EDGE_RISING>; 1808 mboxes = <&ipcc IPCC_CLIENT_MPSS 1809 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1810 label = "modem"; 1811 qcom,remote-pid = <1>; 1812 }; 1813 }; 1814 1815 stm@6002000 { 1816 compatible = "arm,coresight-stm", "arm,primecell"; 1817 reg = <0 0x06002000 0 0x1000>, 1818 <0 0x16280000 0 0x180000>; 1819 reg-names = "stm-base", "stm-stimulus-base"; 1820 1821 clocks = <&aoss_qmp>; 1822 clock-names = "apb_pclk"; 1823 1824 out-ports { 1825 port { 1826 stm_out: endpoint { 1827 remote-endpoint = <&funnel0_in7>; 1828 }; 1829 }; 1830 }; 1831 }; 1832 1833 funnel@6041000 { 1834 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1835 reg = <0 0x06041000 0 0x1000>; 1836 1837 clocks = <&aoss_qmp>; 1838 clock-names = "apb_pclk"; 1839 1840 out-ports { 1841 port { 1842 funnel0_out: endpoint { 1843 remote-endpoint = <&merge_funnel_in0>; 1844 }; 1845 }; 1846 }; 1847 1848 in-ports { 1849 #address-cells = <1>; 1850 #size-cells = <0>; 1851 1852 port@7 { 1853 reg = <7>; 1854 funnel0_in7: endpoint { 1855 remote-endpoint = <&stm_out>; 1856 }; 1857 }; 1858 }; 1859 }; 1860 1861 funnel@6042000 { 1862 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1863 reg = <0 0x06042000 0 0x1000>; 1864 1865 clocks = <&aoss_qmp>; 1866 clock-names = "apb_pclk"; 1867 1868 out-ports { 1869 port { 1870 funnel1_out: endpoint { 1871 remote-endpoint = <&merge_funnel_in1>; 1872 }; 1873 }; 1874 }; 1875 1876 in-ports { 1877 #address-cells = <1>; 1878 #size-cells = <0>; 1879 1880 port@4 { 1881 reg = <4>; 1882 funnel1_in4: endpoint { 1883 remote-endpoint = <&apss_merge_funnel_out>; 1884 }; 1885 }; 1886 }; 1887 }; 1888 1889 funnel@6045000 { 1890 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1891 reg = <0 0x06045000 0 0x1000>; 1892 1893 clocks = <&aoss_qmp>; 1894 clock-names = "apb_pclk"; 1895 1896 out-ports { 1897 port { 1898 merge_funnel_out: endpoint { 1899 remote-endpoint = <&swao_funnel_in>; 1900 }; 1901 }; 1902 }; 1903 1904 in-ports { 1905 #address-cells = <1>; 1906 #size-cells = <0>; 1907 1908 port@0 { 1909 reg = <0>; 1910 merge_funnel_in0: endpoint { 1911 remote-endpoint = <&funnel0_out>; 1912 }; 1913 }; 1914 1915 port@1 { 1916 reg = <1>; 1917 merge_funnel_in1: endpoint { 1918 remote-endpoint = <&funnel1_out>; 1919 }; 1920 }; 1921 }; 1922 }; 1923 1924 replicator@6046000 { 1925 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1926 reg = <0 0x06046000 0 0x1000>; 1927 1928 clocks = <&aoss_qmp>; 1929 clock-names = "apb_pclk"; 1930 1931 out-ports { 1932 port { 1933 replicator_out: endpoint { 1934 remote-endpoint = <&etr_in>; 1935 }; 1936 }; 1937 }; 1938 1939 in-ports { 1940 port { 1941 replicator_in: endpoint { 1942 remote-endpoint = <&swao_replicator_out>; 1943 }; 1944 }; 1945 }; 1946 }; 1947 1948 etr@6048000 { 1949 compatible = "arm,coresight-tmc", "arm,primecell"; 1950 reg = <0 0x06048000 0 0x1000>; 1951 iommus = <&apps_smmu 0x04c0 0>; 1952 1953 clocks = <&aoss_qmp>; 1954 clock-names = "apb_pclk"; 1955 arm,scatter-gather; 1956 1957 in-ports { 1958 port { 1959 etr_in: endpoint { 1960 remote-endpoint = <&replicator_out>; 1961 }; 1962 }; 1963 }; 1964 }; 1965 1966 funnel@6b04000 { 1967 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1968 reg = <0 0x06b04000 0 0x1000>; 1969 1970 clocks = <&aoss_qmp>; 1971 clock-names = "apb_pclk"; 1972 1973 out-ports { 1974 port { 1975 swao_funnel_out: endpoint { 1976 remote-endpoint = <&etf_in>; 1977 }; 1978 }; 1979 }; 1980 1981 in-ports { 1982 #address-cells = <1>; 1983 #size-cells = <0>; 1984 1985 port@7 { 1986 reg = <7>; 1987 swao_funnel_in: endpoint { 1988 remote-endpoint = <&merge_funnel_out>; 1989 }; 1990 }; 1991 }; 1992 }; 1993 1994 etf@6b05000 { 1995 compatible = "arm,coresight-tmc", "arm,primecell"; 1996 reg = <0 0x06b05000 0 0x1000>; 1997 1998 clocks = <&aoss_qmp>; 1999 clock-names = "apb_pclk"; 2000 2001 out-ports { 2002 port { 2003 etf_out: endpoint { 2004 remote-endpoint = <&swao_replicator_in>; 2005 }; 2006 }; 2007 }; 2008 2009 in-ports { 2010 port { 2011 etf_in: endpoint { 2012 remote-endpoint = <&swao_funnel_out>; 2013 }; 2014 }; 2015 }; 2016 }; 2017 2018 replicator@6b06000 { 2019 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2020 reg = <0 0x06b06000 0 0x1000>; 2021 2022 clocks = <&aoss_qmp>; 2023 clock-names = "apb_pclk"; 2024 qcom,replicator-loses-context; 2025 2026 out-ports { 2027 port { 2028 swao_replicator_out: endpoint { 2029 remote-endpoint = <&replicator_in>; 2030 }; 2031 }; 2032 }; 2033 2034 in-ports { 2035 port { 2036 swao_replicator_in: endpoint { 2037 remote-endpoint = <&etf_out>; 2038 }; 2039 }; 2040 }; 2041 }; 2042 2043 etm@7040000 { 2044 compatible = "arm,coresight-etm4x", "arm,primecell"; 2045 reg = <0 0x07040000 0 0x1000>; 2046 2047 cpu = <&CPU0>; 2048 2049 clocks = <&aoss_qmp>; 2050 clock-names = "apb_pclk"; 2051 arm,coresight-loses-context-with-cpu; 2052 qcom,skip-power-up; 2053 2054 out-ports { 2055 port { 2056 etm0_out: endpoint { 2057 remote-endpoint = <&apss_funnel_in0>; 2058 }; 2059 }; 2060 }; 2061 }; 2062 2063 etm@7140000 { 2064 compatible = "arm,coresight-etm4x", "arm,primecell"; 2065 reg = <0 0x07140000 0 0x1000>; 2066 2067 cpu = <&CPU1>; 2068 2069 clocks = <&aoss_qmp>; 2070 clock-names = "apb_pclk"; 2071 arm,coresight-loses-context-with-cpu; 2072 qcom,skip-power-up; 2073 2074 out-ports { 2075 port { 2076 etm1_out: endpoint { 2077 remote-endpoint = <&apss_funnel_in1>; 2078 }; 2079 }; 2080 }; 2081 }; 2082 2083 etm@7240000 { 2084 compatible = "arm,coresight-etm4x", "arm,primecell"; 2085 reg = <0 0x07240000 0 0x1000>; 2086 2087 cpu = <&CPU2>; 2088 2089 clocks = <&aoss_qmp>; 2090 clock-names = "apb_pclk"; 2091 arm,coresight-loses-context-with-cpu; 2092 qcom,skip-power-up; 2093 2094 out-ports { 2095 port { 2096 etm2_out: endpoint { 2097 remote-endpoint = <&apss_funnel_in2>; 2098 }; 2099 }; 2100 }; 2101 }; 2102 2103 etm@7340000 { 2104 compatible = "arm,coresight-etm4x", "arm,primecell"; 2105 reg = <0 0x07340000 0 0x1000>; 2106 2107 cpu = <&CPU3>; 2108 2109 clocks = <&aoss_qmp>; 2110 clock-names = "apb_pclk"; 2111 arm,coresight-loses-context-with-cpu; 2112 qcom,skip-power-up; 2113 2114 out-ports { 2115 port { 2116 etm3_out: endpoint { 2117 remote-endpoint = <&apss_funnel_in3>; 2118 }; 2119 }; 2120 }; 2121 }; 2122 2123 etm@7440000 { 2124 compatible = "arm,coresight-etm4x", "arm,primecell"; 2125 reg = <0 0x07440000 0 0x1000>; 2126 2127 cpu = <&CPU4>; 2128 2129 clocks = <&aoss_qmp>; 2130 clock-names = "apb_pclk"; 2131 arm,coresight-loses-context-with-cpu; 2132 qcom,skip-power-up; 2133 2134 out-ports { 2135 port { 2136 etm4_out: endpoint { 2137 remote-endpoint = <&apss_funnel_in4>; 2138 }; 2139 }; 2140 }; 2141 }; 2142 2143 etm@7540000 { 2144 compatible = "arm,coresight-etm4x", "arm,primecell"; 2145 reg = <0 0x07540000 0 0x1000>; 2146 2147 cpu = <&CPU5>; 2148 2149 clocks = <&aoss_qmp>; 2150 clock-names = "apb_pclk"; 2151 arm,coresight-loses-context-with-cpu; 2152 qcom,skip-power-up; 2153 2154 out-ports { 2155 port { 2156 etm5_out: endpoint { 2157 remote-endpoint = <&apss_funnel_in5>; 2158 }; 2159 }; 2160 }; 2161 }; 2162 2163 etm@7640000 { 2164 compatible = "arm,coresight-etm4x", "arm,primecell"; 2165 reg = <0 0x07640000 0 0x1000>; 2166 2167 cpu = <&CPU6>; 2168 2169 clocks = <&aoss_qmp>; 2170 clock-names = "apb_pclk"; 2171 arm,coresight-loses-context-with-cpu; 2172 qcom,skip-power-up; 2173 2174 out-ports { 2175 port { 2176 etm6_out: endpoint { 2177 remote-endpoint = <&apss_funnel_in6>; 2178 }; 2179 }; 2180 }; 2181 }; 2182 2183 etm@7740000 { 2184 compatible = "arm,coresight-etm4x", "arm,primecell"; 2185 reg = <0 0x07740000 0 0x1000>; 2186 2187 cpu = <&CPU7>; 2188 2189 clocks = <&aoss_qmp>; 2190 clock-names = "apb_pclk"; 2191 arm,coresight-loses-context-with-cpu; 2192 qcom,skip-power-up; 2193 2194 out-ports { 2195 port { 2196 etm7_out: endpoint { 2197 remote-endpoint = <&apss_funnel_in7>; 2198 }; 2199 }; 2200 }; 2201 }; 2202 2203 funnel@7800000 { /* APSS Funnel */ 2204 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2205 reg = <0 0x07800000 0 0x1000>; 2206 2207 clocks = <&aoss_qmp>; 2208 clock-names = "apb_pclk"; 2209 2210 out-ports { 2211 port { 2212 apss_funnel_out: endpoint { 2213 remote-endpoint = <&apss_merge_funnel_in>; 2214 }; 2215 }; 2216 }; 2217 2218 in-ports { 2219 #address-cells = <1>; 2220 #size-cells = <0>; 2221 2222 port@0 { 2223 reg = <0>; 2224 apss_funnel_in0: endpoint { 2225 remote-endpoint = <&etm0_out>; 2226 }; 2227 }; 2228 2229 port@1 { 2230 reg = <1>; 2231 apss_funnel_in1: endpoint { 2232 remote-endpoint = <&etm1_out>; 2233 }; 2234 }; 2235 2236 port@2 { 2237 reg = <2>; 2238 apss_funnel_in2: endpoint { 2239 remote-endpoint = <&etm2_out>; 2240 }; 2241 }; 2242 2243 port@3 { 2244 reg = <3>; 2245 apss_funnel_in3: endpoint { 2246 remote-endpoint = <&etm3_out>; 2247 }; 2248 }; 2249 2250 port@4 { 2251 reg = <4>; 2252 apss_funnel_in4: endpoint { 2253 remote-endpoint = <&etm4_out>; 2254 }; 2255 }; 2256 2257 port@5 { 2258 reg = <5>; 2259 apss_funnel_in5: endpoint { 2260 remote-endpoint = <&etm5_out>; 2261 }; 2262 }; 2263 2264 port@6 { 2265 reg = <6>; 2266 apss_funnel_in6: endpoint { 2267 remote-endpoint = <&etm6_out>; 2268 }; 2269 }; 2270 2271 port@7 { 2272 reg = <7>; 2273 apss_funnel_in7: endpoint { 2274 remote-endpoint = <&etm7_out>; 2275 }; 2276 }; 2277 }; 2278 }; 2279 2280 funnel@7810000 { 2281 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2282 reg = <0 0x07810000 0 0x1000>; 2283 2284 clocks = <&aoss_qmp>; 2285 clock-names = "apb_pclk"; 2286 2287 out-ports { 2288 port { 2289 apss_merge_funnel_out: endpoint { 2290 remote-endpoint = <&funnel1_in4>; 2291 }; 2292 }; 2293 }; 2294 2295 in-ports { 2296 port { 2297 apss_merge_funnel_in: endpoint { 2298 remote-endpoint = <&apss_funnel_out>; 2299 }; 2300 }; 2301 }; 2302 }; 2303 2304 sdhc_2: sdhci@8804000 { 2305 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 2306 status = "disabled"; 2307 2308 reg = <0 0x08804000 0 0x1000>; 2309 2310 iommus = <&apps_smmu 0x100 0x0>; 2311 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2312 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2313 interrupt-names = "hc_irq", "pwr_irq"; 2314 2315 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2316 <&gcc GCC_SDCC2_AHB_CLK>, 2317 <&rpmhcc RPMH_CXO_CLK>; 2318 clock-names = "core", "iface", "xo"; 2319 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2320 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 2321 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2322 power-domains = <&rpmhpd SC7280_CX>; 2323 operating-points-v2 = <&sdhc2_opp_table>; 2324 2325 bus-width = <4>; 2326 2327 qcom,dll-config = <0x0007642c>; 2328 2329 sdhc2_opp_table: opp-table { 2330 compatible = "operating-points-v2"; 2331 2332 opp-100000000 { 2333 opp-hz = /bits/ 64 <100000000>; 2334 required-opps = <&rpmhpd_opp_low_svs>; 2335 opp-peak-kBps = <1800000 400000>; 2336 opp-avg-kBps = <100000 0>; 2337 }; 2338 2339 opp-202000000 { 2340 opp-hz = /bits/ 64 <202000000>; 2341 required-opps = <&rpmhpd_opp_nom>; 2342 opp-peak-kBps = <5400000 1600000>; 2343 opp-avg-kBps = <200000 0>; 2344 }; 2345 }; 2346 2347 }; 2348 2349 usb_1_hsphy: phy@88e3000 { 2350 compatible = "qcom,sc7280-usb-hs-phy", 2351 "qcom,usb-snps-hs-7nm-phy"; 2352 reg = <0 0x088e3000 0 0x400>; 2353 status = "disabled"; 2354 #phy-cells = <0>; 2355 2356 clocks = <&rpmhcc RPMH_CXO_CLK>; 2357 clock-names = "ref"; 2358 2359 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2360 }; 2361 2362 usb_2_hsphy: phy@88e4000 { 2363 compatible = "qcom,sc7280-usb-hs-phy", 2364 "qcom,usb-snps-hs-7nm-phy"; 2365 reg = <0 0x088e4000 0 0x400>; 2366 status = "disabled"; 2367 #phy-cells = <0>; 2368 2369 clocks = <&rpmhcc RPMH_CXO_CLK>; 2370 clock-names = "ref"; 2371 2372 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2373 }; 2374 2375 usb_1_qmpphy: phy-wrapper@88e9000 { 2376 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 2377 "qcom,sm8250-qmp-usb3-dp-phy"; 2378 reg = <0 0x088e9000 0 0x200>, 2379 <0 0x088e8000 0 0x40>, 2380 <0 0x088ea000 0 0x200>; 2381 status = "disabled"; 2382 #address-cells = <2>; 2383 #size-cells = <2>; 2384 ranges; 2385 2386 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2387 <&rpmhcc RPMH_CXO_CLK>, 2388 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2389 clock-names = "aux", "ref_clk_src", "com_aux"; 2390 2391 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2392 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2393 reset-names = "phy", "common"; 2394 2395 usb_1_ssphy: usb3-phy@88e9200 { 2396 reg = <0 0x088e9200 0 0x200>, 2397 <0 0x088e9400 0 0x200>, 2398 <0 0x088e9c00 0 0x400>, 2399 <0 0x088e9600 0 0x200>, 2400 <0 0x088e9800 0 0x200>, 2401 <0 0x088e9a00 0 0x100>; 2402 #clock-cells = <0>; 2403 #phy-cells = <0>; 2404 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2405 clock-names = "pipe0"; 2406 clock-output-names = "usb3_phy_pipe_clk_src"; 2407 }; 2408 2409 dp_phy: dp-phy@88ea200 { 2410 reg = <0 0x088ea200 0 0x200>, 2411 <0 0x088ea400 0 0x200>, 2412 <0 0x088eaa00 0 0x200>, 2413 <0 0x088ea600 0 0x200>, 2414 <0 0x088ea800 0 0x200>; 2415 #phy-cells = <0>; 2416 #clock-cells = <1>; 2417 }; 2418 }; 2419 2420 usb_2: usb@8cf8800 { 2421 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2422 reg = <0 0x08cf8800 0 0x400>; 2423 status = "disabled"; 2424 #address-cells = <2>; 2425 #size-cells = <2>; 2426 ranges; 2427 dma-ranges; 2428 2429 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2430 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2431 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2432 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2433 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 2434 clock-names = "cfg_noc", "core", "iface","mock_utmi", 2435 "sleep"; 2436 2437 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2438 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2439 assigned-clock-rates = <19200000>, <200000000>; 2440 2441 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2442 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 2443 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 2444 interrupt-names = "hs_phy_irq", 2445 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2446 2447 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 2448 2449 resets = <&gcc GCC_USB30_SEC_BCR>; 2450 2451 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 2452 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 2453 interconnect-names = "usb-ddr", "apps-usb"; 2454 2455 usb_2_dwc3: usb@8c00000 { 2456 compatible = "snps,dwc3"; 2457 reg = <0 0x08c00000 0 0xe000>; 2458 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2459 iommus = <&apps_smmu 0xa0 0x0>; 2460 snps,dis_u2_susphy_quirk; 2461 snps,dis_enblslpm_quirk; 2462 phys = <&usb_2_hsphy>; 2463 phy-names = "usb2-phy"; 2464 maximum-speed = "high-speed"; 2465 }; 2466 }; 2467 2468 qspi: spi@88dc000 { 2469 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 2470 reg = <0 0x088dc000 0 0x1000>; 2471 #address-cells = <1>; 2472 #size-cells = <0>; 2473 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2474 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2475 <&gcc GCC_QSPI_CORE_CLK>; 2476 clock-names = "iface", "core"; 2477 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2478 &cnoc2 SLAVE_QSPI_0 0>; 2479 interconnect-names = "qspi-config"; 2480 power-domains = <&rpmhpd SC7280_CX>; 2481 operating-points-v2 = <&qspi_opp_table>; 2482 status = "disabled"; 2483 }; 2484 2485 dc_noc: interconnect@90e0000 { 2486 reg = <0 0x090e0000 0 0x5080>; 2487 compatible = "qcom,sc7280-dc-noc"; 2488 #interconnect-cells = <2>; 2489 qcom,bcm-voters = <&apps_bcm_voter>; 2490 }; 2491 2492 gem_noc: interconnect@9100000 { 2493 reg = <0 0x9100000 0 0xe2200>; 2494 compatible = "qcom,sc7280-gem-noc"; 2495 #interconnect-cells = <2>; 2496 qcom,bcm-voters = <&apps_bcm_voter>; 2497 }; 2498 2499 system-cache-controller@9200000 { 2500 compatible = "qcom,sc7280-llcc"; 2501 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 2502 reg-names = "llcc_base", "llcc_broadcast_base"; 2503 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2504 }; 2505 2506 nsp_noc: interconnect@a0c0000 { 2507 reg = <0 0x0a0c0000 0 0x10000>; 2508 compatible = "qcom,sc7280-nsp-noc"; 2509 #interconnect-cells = <2>; 2510 qcom,bcm-voters = <&apps_bcm_voter>; 2511 }; 2512 2513 usb_1: usb@a6f8800 { 2514 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2515 reg = <0 0x0a6f8800 0 0x400>; 2516 status = "disabled"; 2517 #address-cells = <2>; 2518 #size-cells = <2>; 2519 ranges; 2520 dma-ranges; 2521 2522 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2523 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2524 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2525 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2526 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2527 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2528 "sleep"; 2529 2530 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2531 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2532 assigned-clock-rates = <19200000>, <200000000>; 2533 2534 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2535 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2536 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2537 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2538 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2539 "dm_hs_phy_irq", "ss_phy_irq"; 2540 2541 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 2542 2543 resets = <&gcc GCC_USB30_PRIM_BCR>; 2544 2545 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2546 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 2547 interconnect-names = "usb-ddr", "apps-usb"; 2548 2549 usb_1_dwc3: usb@a600000 { 2550 compatible = "snps,dwc3"; 2551 reg = <0 0x0a600000 0 0xe000>; 2552 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2553 iommus = <&apps_smmu 0xe0 0x0>; 2554 snps,dis_u2_susphy_quirk; 2555 snps,dis_enblslpm_quirk; 2556 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2557 phy-names = "usb2-phy", "usb3-phy"; 2558 maximum-speed = "super-speed"; 2559 }; 2560 }; 2561 2562 videocc: clock-controller@aaf0000 { 2563 compatible = "qcom,sc7280-videocc"; 2564 reg = <0 0xaaf0000 0 0x10000>; 2565 clocks = <&rpmhcc RPMH_CXO_CLK>, 2566 <&rpmhcc RPMH_CXO_CLK_A>; 2567 clock-names = "bi_tcxo", "bi_tcxo_ao"; 2568 #clock-cells = <1>; 2569 #reset-cells = <1>; 2570 #power-domain-cells = <1>; 2571 }; 2572 2573 dispcc: clock-controller@af00000 { 2574 compatible = "qcom,sc7280-dispcc"; 2575 reg = <0 0xaf00000 0 0x20000>; 2576 clocks = <&rpmhcc RPMH_CXO_CLK>, 2577 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2578 <0>, <0>, <0>, <0>, <0>, <0>; 2579 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 2580 "dsi0_phy_pll_out_byteclk", 2581 "dsi0_phy_pll_out_dsiclk", 2582 "dp_phy_pll_link_clk", 2583 "dp_phy_pll_vco_div_clk", 2584 "edp_phy_pll_link_clk", 2585 "edp_phy_pll_vco_div_clk"; 2586 #clock-cells = <1>; 2587 #reset-cells = <1>; 2588 #power-domain-cells = <1>; 2589 }; 2590 2591 pdc: interrupt-controller@b220000 { 2592 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 2593 reg = <0 0x0b220000 0 0x30000>; 2594 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 2595 <55 306 4>, <59 312 3>, <62 374 2>, 2596 <64 434 2>, <66 438 3>, <69 86 1>, 2597 <70 520 54>, <124 609 31>, <155 63 1>, 2598 <156 716 12>; 2599 #interrupt-cells = <2>; 2600 interrupt-parent = <&intc>; 2601 interrupt-controller; 2602 }; 2603 2604 pdc_reset: reset-controller@b5e0000 { 2605 compatible = "qcom,sc7280-pdc-global"; 2606 reg = <0 0x0b5e0000 0 0x20000>; 2607 #reset-cells = <1>; 2608 }; 2609 2610 tsens0: thermal-sensor@c263000 { 2611 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 2612 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2613 <0 0x0c222000 0 0x1ff>; /* SROT */ 2614 #qcom,sensors = <15>; 2615 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2616 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2617 interrupt-names = "uplow","critical"; 2618 #thermal-sensor-cells = <1>; 2619 }; 2620 2621 tsens1: thermal-sensor@c265000 { 2622 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 2623 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2624 <0 0x0c223000 0 0x1ff>; /* SROT */ 2625 #qcom,sensors = <12>; 2626 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2627 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2628 interrupt-names = "uplow","critical"; 2629 #thermal-sensor-cells = <1>; 2630 }; 2631 2632 aoss_reset: reset-controller@c2a0000 { 2633 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 2634 reg = <0 0x0c2a0000 0 0x31000>; 2635 #reset-cells = <1>; 2636 }; 2637 2638 aoss_qmp: power-controller@c300000 { 2639 compatible = "qcom,sc7280-aoss-qmp"; 2640 reg = <0 0x0c300000 0 0x100000>; 2641 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 2642 IPCC_MPROC_SIGNAL_GLINK_QMP 2643 IRQ_TYPE_EDGE_RISING>; 2644 mboxes = <&ipcc IPCC_CLIENT_AOP 2645 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2646 2647 #clock-cells = <0>; 2648 }; 2649 2650 spmi_bus: spmi@c440000 { 2651 compatible = "qcom,spmi-pmic-arb"; 2652 reg = <0 0x0c440000 0 0x1100>, 2653 <0 0x0c600000 0 0x2000000>, 2654 <0 0x0e600000 0 0x100000>, 2655 <0 0x0e700000 0 0xa0000>, 2656 <0 0x0c40a000 0 0x26000>; 2657 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2658 interrupt-names = "periph_irq"; 2659 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2660 qcom,ee = <0>; 2661 qcom,channel = <0>; 2662 #address-cells = <1>; 2663 #size-cells = <1>; 2664 interrupt-controller; 2665 #interrupt-cells = <4>; 2666 }; 2667 2668 tlmm: pinctrl@f100000 { 2669 compatible = "qcom,sc7280-pinctrl"; 2670 reg = <0 0x0f100000 0 0x300000>; 2671 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2672 gpio-controller; 2673 #gpio-cells = <2>; 2674 interrupt-controller; 2675 #interrupt-cells = <2>; 2676 gpio-ranges = <&tlmm 0 0 175>; 2677 wakeup-parent = <&pdc>; 2678 2679 qspi_clk: qspi-clk { 2680 pins = "gpio14"; 2681 function = "qspi_clk"; 2682 }; 2683 2684 qspi_cs0: qspi-cs0 { 2685 pins = "gpio15"; 2686 function = "qspi_cs"; 2687 }; 2688 2689 qspi_cs1: qspi-cs1 { 2690 pins = "gpio19"; 2691 function = "qspi_cs"; 2692 }; 2693 2694 qspi_data01: qspi-data01 { 2695 pins = "gpio12", "gpio13"; 2696 function = "qspi_data"; 2697 }; 2698 2699 qspi_data12: qspi-data12 { 2700 pins = "gpio16", "gpio17"; 2701 function = "qspi_data"; 2702 }; 2703 2704 qup_i2c0_data_clk: qup-i2c0-data-clk { 2705 pins = "gpio0", "gpio1"; 2706 function = "qup00"; 2707 }; 2708 2709 qup_i2c1_data_clk: qup-i2c1-data-clk { 2710 pins = "gpio4", "gpio5"; 2711 function = "qup01"; 2712 }; 2713 2714 qup_i2c2_data_clk: qup-i2c2-data-clk { 2715 pins = "gpio8", "gpio9"; 2716 function = "qup02"; 2717 }; 2718 2719 qup_i2c3_data_clk: qup-i2c3-data-clk { 2720 pins = "gpio12", "gpio13"; 2721 function = "qup03"; 2722 }; 2723 2724 qup_i2c4_data_clk: qup-i2c4-data-clk { 2725 pins = "gpio16", "gpio17"; 2726 function = "qup04"; 2727 }; 2728 2729 qup_i2c5_data_clk: qup-i2c5-data-clk { 2730 pins = "gpio20", "gpio21"; 2731 function = "qup05"; 2732 }; 2733 2734 qup_i2c6_data_clk: qup-i2c6-data-clk { 2735 pins = "gpio24", "gpio25"; 2736 function = "qup06"; 2737 }; 2738 2739 qup_i2c7_data_clk: qup-i2c7-data-clk { 2740 pins = "gpio28", "gpio29"; 2741 function = "qup07"; 2742 }; 2743 2744 qup_i2c8_data_clk: qup-i2c8-data-clk { 2745 pins = "gpio32", "gpio33"; 2746 function = "qup10"; 2747 }; 2748 2749 qup_i2c9_data_clk: qup-i2c9-data-clk { 2750 pins = "gpio36", "gpio37"; 2751 function = "qup11"; 2752 }; 2753 2754 qup_i2c10_data_clk: qup-i2c10-data-clk { 2755 pins = "gpio40", "gpio41"; 2756 function = "qup12"; 2757 }; 2758 2759 qup_i2c11_data_clk: qup-i2c11-data-clk { 2760 pins = "gpio44", "gpio45"; 2761 function = "qup13"; 2762 }; 2763 2764 qup_i2c12_data_clk: qup-i2c12-data-clk { 2765 pins = "gpio48", "gpio49"; 2766 function = "qup14"; 2767 }; 2768 2769 qup_i2c13_data_clk: qup-i2c13-data-clk { 2770 pins = "gpio52", "gpio53"; 2771 function = "qup15"; 2772 }; 2773 2774 qup_i2c14_data_clk: qup-i2c14-data-clk { 2775 pins = "gpio56", "gpio57"; 2776 function = "qup16"; 2777 }; 2778 2779 qup_i2c15_data_clk: qup-i2c15-data-clk { 2780 pins = "gpio60", "gpio61"; 2781 function = "qup17"; 2782 }; 2783 2784 qup_spi0_data_clk: qup-spi0-data-clk { 2785 pins = "gpio0", "gpio1", "gpio2"; 2786 function = "qup00"; 2787 }; 2788 2789 qup_spi0_cs: qup-spi0-cs { 2790 pins = "gpio3"; 2791 function = "qup00"; 2792 }; 2793 2794 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 2795 pins = "gpio3"; 2796 function = "gpio"; 2797 }; 2798 2799 qup_spi1_data_clk: qup-spi1-data-clk { 2800 pins = "gpio4", "gpio5", "gpio6"; 2801 function = "qup01"; 2802 }; 2803 2804 qup_spi1_cs: qup-spi1-cs { 2805 pins = "gpio7"; 2806 function = "qup01"; 2807 }; 2808 2809 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 2810 pins = "gpio7"; 2811 function = "gpio"; 2812 }; 2813 2814 qup_spi2_data_clk: qup-spi2-data-clk { 2815 pins = "gpio8", "gpio9", "gpio10"; 2816 function = "qup02"; 2817 }; 2818 2819 qup_spi2_cs: qup-spi2-cs { 2820 pins = "gpio11"; 2821 function = "qup02"; 2822 }; 2823 2824 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 2825 pins = "gpio11"; 2826 function = "gpio"; 2827 }; 2828 2829 qup_spi3_data_clk: qup-spi3-data-clk { 2830 pins = "gpio12", "gpio13", "gpio14"; 2831 function = "qup03"; 2832 }; 2833 2834 qup_spi3_cs: qup-spi3-cs { 2835 pins = "gpio15"; 2836 function = "qup03"; 2837 }; 2838 2839 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 2840 pins = "gpio15"; 2841 function = "gpio"; 2842 }; 2843 2844 qup_spi4_data_clk: qup-spi4-data-clk { 2845 pins = "gpio16", "gpio17", "gpio18"; 2846 function = "qup04"; 2847 }; 2848 2849 qup_spi4_cs: qup-spi4-cs { 2850 pins = "gpio19"; 2851 function = "qup04"; 2852 }; 2853 2854 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 2855 pins = "gpio19"; 2856 function = "gpio"; 2857 }; 2858 2859 qup_spi5_data_clk: qup-spi5-data-clk { 2860 pins = "gpio20", "gpio21", "gpio22"; 2861 function = "qup05"; 2862 }; 2863 2864 qup_spi5_cs: qup-spi5-cs { 2865 pins = "gpio23"; 2866 function = "qup05"; 2867 }; 2868 2869 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 2870 pins = "gpio23"; 2871 function = "gpio"; 2872 }; 2873 2874 qup_spi6_data_clk: qup-spi6-data-clk { 2875 pins = "gpio24", "gpio25", "gpio26"; 2876 function = "qup06"; 2877 }; 2878 2879 qup_spi6_cs: qup-spi6-cs { 2880 pins = "gpio27"; 2881 function = "qup06"; 2882 }; 2883 2884 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 2885 pins = "gpio27"; 2886 function = "gpio"; 2887 }; 2888 2889 qup_spi7_data_clk: qup-spi7-data-clk { 2890 pins = "gpio28", "gpio29", "gpio30"; 2891 function = "qup07"; 2892 }; 2893 2894 qup_spi7_cs: qup-spi7-cs { 2895 pins = "gpio31"; 2896 function = "qup07"; 2897 }; 2898 2899 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 2900 pins = "gpio31"; 2901 function = "gpio"; 2902 }; 2903 2904 qup_spi8_data_clk: qup-spi8-data-clk { 2905 pins = "gpio32", "gpio33", "gpio34"; 2906 function = "qup10"; 2907 }; 2908 2909 qup_spi8_cs: qup-spi8-cs { 2910 pins = "gpio35"; 2911 function = "qup10"; 2912 }; 2913 2914 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 2915 pins = "gpio35"; 2916 function = "gpio"; 2917 }; 2918 2919 qup_spi9_data_clk: qup-spi9-data-clk { 2920 pins = "gpio36", "gpio37", "gpio38"; 2921 function = "qup11"; 2922 }; 2923 2924 qup_spi9_cs: qup-spi9-cs { 2925 pins = "gpio39"; 2926 function = "qup11"; 2927 }; 2928 2929 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 2930 pins = "gpio39"; 2931 function = "gpio"; 2932 }; 2933 2934 qup_spi10_data_clk: qup-spi10-data-clk { 2935 pins = "gpio40", "gpio41", "gpio42"; 2936 function = "qup12"; 2937 }; 2938 2939 qup_spi10_cs: qup-spi10-cs { 2940 pins = "gpio43"; 2941 function = "qup12"; 2942 }; 2943 2944 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 2945 pins = "gpio43"; 2946 function = "gpio"; 2947 }; 2948 2949 qup_spi11_data_clk: qup-spi11-data-clk { 2950 pins = "gpio44", "gpio45", "gpio46"; 2951 function = "qup13"; 2952 }; 2953 2954 qup_spi11_cs: qup-spi11-cs { 2955 pins = "gpio47"; 2956 function = "qup13"; 2957 }; 2958 2959 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 2960 pins = "gpio47"; 2961 function = "gpio"; 2962 }; 2963 2964 qup_spi12_data_clk: qup-spi12-data-clk { 2965 pins = "gpio48", "gpio49", "gpio50"; 2966 function = "qup14"; 2967 }; 2968 2969 qup_spi12_cs: qup-spi12-cs { 2970 pins = "gpio51"; 2971 function = "qup14"; 2972 }; 2973 2974 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 2975 pins = "gpio51"; 2976 function = "gpio"; 2977 }; 2978 2979 qup_spi13_data_clk: qup-spi13-data-clk { 2980 pins = "gpio52", "gpio53", "gpio54"; 2981 function = "qup15"; 2982 }; 2983 2984 qup_spi13_cs: qup-spi13-cs { 2985 pins = "gpio55"; 2986 function = "qup15"; 2987 }; 2988 2989 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 2990 pins = "gpio55"; 2991 function = "gpio"; 2992 }; 2993 2994 qup_spi14_data_clk: qup-spi14-data-clk { 2995 pins = "gpio56", "gpio57", "gpio58"; 2996 function = "qup16"; 2997 }; 2998 2999 qup_spi14_cs: qup-spi14-cs { 3000 pins = "gpio59"; 3001 function = "qup16"; 3002 }; 3003 3004 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 3005 pins = "gpio59"; 3006 function = "gpio"; 3007 }; 3008 3009 qup_spi15_data_clk: qup-spi15-data-clk { 3010 pins = "gpio60", "gpio61", "gpio62"; 3011 function = "qup17"; 3012 }; 3013 3014 qup_spi15_cs: qup-spi15-cs { 3015 pins = "gpio63"; 3016 function = "qup17"; 3017 }; 3018 3019 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 3020 pins = "gpio63"; 3021 function = "gpio"; 3022 }; 3023 3024 qup_uart0_cts: qup-uart0-cts { 3025 pins = "gpio0"; 3026 function = "qup00"; 3027 }; 3028 3029 qup_uart0_rts: qup-uart0-rts { 3030 pins = "gpio1"; 3031 function = "qup00"; 3032 }; 3033 3034 qup_uart0_tx: qup-uart0-tx { 3035 pins = "gpio2"; 3036 function = "qup00"; 3037 }; 3038 3039 qup_uart0_rx: qup-uart0-rx { 3040 pins = "gpio3"; 3041 function = "qup00"; 3042 }; 3043 3044 qup_uart1_cts: qup-uart1-cts { 3045 pins = "gpio4"; 3046 function = "qup01"; 3047 }; 3048 3049 qup_uart1_rts: qup-uart1-rts { 3050 pins = "gpio5"; 3051 function = "qup01"; 3052 }; 3053 3054 qup_uart1_tx: qup-uart1-tx { 3055 pins = "gpio6"; 3056 function = "qup01"; 3057 }; 3058 3059 qup_uart1_rx: qup-uart1-rx { 3060 pins = "gpio7"; 3061 function = "qup01"; 3062 }; 3063 3064 qup_uart2_cts: qup-uart2-cts { 3065 pins = "gpio8"; 3066 function = "qup02"; 3067 }; 3068 3069 qup_uart2_rts: qup-uart2-rts { 3070 pins = "gpio9"; 3071 function = "qup02"; 3072 }; 3073 3074 qup_uart2_tx: qup-uart2-tx { 3075 pins = "gpio10"; 3076 function = "qup02"; 3077 }; 3078 3079 qup_uart2_rx: qup-uart2-rx { 3080 pins = "gpio11"; 3081 function = "qup02"; 3082 }; 3083 3084 qup_uart3_cts: qup-uart3-cts { 3085 pins = "gpio12"; 3086 function = "qup03"; 3087 }; 3088 3089 qup_uart3_rts: qup-uart3-rts { 3090 pins = "gpio13"; 3091 function = "qup03"; 3092 }; 3093 3094 qup_uart3_tx: qup-uart3-tx { 3095 pins = "gpio14"; 3096 function = "qup03"; 3097 }; 3098 3099 qup_uart3_rx: qup-uart3-rx { 3100 pins = "gpio15"; 3101 function = "qup03"; 3102 }; 3103 3104 qup_uart4_cts: qup-uart4-cts { 3105 pins = "gpio16"; 3106 function = "qup04"; 3107 }; 3108 3109 qup_uart4_rts: qup-uart4-rts { 3110 pins = "gpio17"; 3111 function = "qup04"; 3112 }; 3113 3114 qup_uart4_tx: qup-uart4-tx { 3115 pins = "gpio18"; 3116 function = "qup04"; 3117 }; 3118 3119 qup_uart4_rx: qup-uart4-rx { 3120 pins = "gpio19"; 3121 function = "qup04"; 3122 }; 3123 3124 qup_uart5_cts: qup-uart5-cts { 3125 pins = "gpio20"; 3126 function = "qup05"; 3127 }; 3128 3129 qup_uart5_rts: qup-uart5-rts { 3130 pins = "gpio21"; 3131 function = "qup05"; 3132 }; 3133 3134 qup_uart5_tx: qup-uart5-tx { 3135 pins = "gpio22"; 3136 function = "qup05"; 3137 }; 3138 3139 qup_uart5_rx: qup-uart5-rx { 3140 pins = "gpio23"; 3141 function = "qup05"; 3142 }; 3143 3144 qup_uart6_cts: qup-uart6-cts { 3145 pins = "gpio24"; 3146 function = "qup06"; 3147 }; 3148 3149 qup_uart6_rts: qup-uart6-rts { 3150 pins = "gpio25"; 3151 function = "qup06"; 3152 }; 3153 3154 qup_uart6_tx: qup-uart6-tx { 3155 pins = "gpio26"; 3156 function = "qup06"; 3157 }; 3158 3159 qup_uart6_rx: qup-uart6-rx { 3160 pins = "gpio27"; 3161 function = "qup06"; 3162 }; 3163 3164 qup_uart7_cts: qup-uart7-cts { 3165 pins = "gpio28"; 3166 function = "qup07"; 3167 }; 3168 3169 qup_uart7_rts: qup-uart7-rts { 3170 pins = "gpio29"; 3171 function = "qup07"; 3172 }; 3173 3174 qup_uart7_tx: qup-uart7-tx { 3175 pins = "gpio30"; 3176 function = "qup07"; 3177 }; 3178 3179 qup_uart7_rx: qup-uart7-rx { 3180 pins = "gpio31"; 3181 function = "qup07"; 3182 }; 3183 3184 sdc1_on: sdc1-on { 3185 clk { 3186 pins = "sdc1_clk"; 3187 }; 3188 3189 cmd { 3190 pins = "sdc1_cmd"; 3191 }; 3192 3193 data { 3194 pins = "sdc1_data"; 3195 }; 3196 3197 rclk { 3198 pins = "sdc1_rclk"; 3199 }; 3200 }; 3201 3202 sdc1_off: sdc1-off { 3203 clk { 3204 pins = "sdc1_clk"; 3205 drive-strength = <2>; 3206 bias-bus-hold; 3207 }; 3208 3209 cmd { 3210 pins = "sdc1_cmd"; 3211 drive-strength = <2>; 3212 bias-bus-hold; 3213 }; 3214 3215 data { 3216 pins = "sdc1_data"; 3217 drive-strength = <2>; 3218 bias-bus-hold; 3219 }; 3220 3221 rclk { 3222 pins = "sdc1_rclk"; 3223 bias-bus-hold; 3224 }; 3225 }; 3226 3227 sdc2_on: sdc2-on { 3228 clk { 3229 pins = "sdc2_clk"; 3230 }; 3231 3232 cmd { 3233 pins = "sdc2_cmd"; 3234 }; 3235 3236 data { 3237 pins = "sdc2_data"; 3238 }; 3239 }; 3240 3241 sdc2_off: sdc2-off { 3242 clk { 3243 pins = "sdc2_clk"; 3244 drive-strength = <2>; 3245 bias-bus-hold; 3246 }; 3247 3248 cmd { 3249 pins ="sdc2_cmd"; 3250 drive-strength = <2>; 3251 bias-bus-hold; 3252 }; 3253 3254 data { 3255 pins ="sdc2_data"; 3256 drive-strength = <2>; 3257 bias-bus-hold; 3258 }; 3259 }; 3260 3261 qup_uart8_cts: qup-uart8-cts { 3262 pins = "gpio32"; 3263 function = "qup10"; 3264 }; 3265 3266 qup_uart8_rts: qup-uart8-rts { 3267 pins = "gpio33"; 3268 function = "qup10"; 3269 }; 3270 3271 qup_uart8_tx: qup-uart8-tx { 3272 pins = "gpio34"; 3273 function = "qup10"; 3274 }; 3275 3276 qup_uart8_rx: qup-uart8-rx { 3277 pins = "gpio35"; 3278 function = "qup10"; 3279 }; 3280 3281 qup_uart9_cts: qup-uart9-cts { 3282 pins = "gpio36"; 3283 function = "qup11"; 3284 }; 3285 3286 qup_uart9_rts: qup-uart9-rts { 3287 pins = "gpio37"; 3288 function = "qup11"; 3289 }; 3290 3291 qup_uart9_tx: qup-uart9-tx { 3292 pins = "gpio38"; 3293 function = "qup11"; 3294 }; 3295 3296 qup_uart9_rx: qup-uart9-rx { 3297 pins = "gpio39"; 3298 function = "qup11"; 3299 }; 3300 3301 qup_uart10_cts: qup-uart10-cts { 3302 pins = "gpio40"; 3303 function = "qup12"; 3304 }; 3305 3306 qup_uart10_rts: qup-uart10-rts { 3307 pins = "gpio41"; 3308 function = "qup12"; 3309 }; 3310 3311 qup_uart10_tx: qup-uart10-tx { 3312 pins = "gpio42"; 3313 function = "qup12"; 3314 }; 3315 3316 qup_uart10_rx: qup-uart10-rx { 3317 pins = "gpio43"; 3318 function = "qup12"; 3319 }; 3320 3321 qup_uart11_cts: qup-uart11-cts { 3322 pins = "gpio44"; 3323 function = "qup13"; 3324 }; 3325 3326 qup_uart11_rts: qup-uart11-rts { 3327 pins = "gpio45"; 3328 function = "qup13"; 3329 }; 3330 3331 qup_uart11_tx: qup-uart11-tx { 3332 pins = "gpio46"; 3333 function = "qup13"; 3334 }; 3335 3336 qup_uart11_rx: qup-uart11-rx { 3337 pins = "gpio47"; 3338 function = "qup13"; 3339 }; 3340 3341 qup_uart12_cts: qup-uart12-cts { 3342 pins = "gpio48"; 3343 function = "qup14"; 3344 }; 3345 3346 qup_uart12_rts: qup-uart12-rts { 3347 pins = "gpio49"; 3348 function = "qup14"; 3349 }; 3350 3351 qup_uart12_tx: qup-uart12-tx { 3352 pins = "gpio50"; 3353 function = "qup14"; 3354 }; 3355 3356 qup_uart12_rx: qup-uart12-rx { 3357 pins = "gpio51"; 3358 function = "qup14"; 3359 }; 3360 3361 qup_uart13_cts: qup-uart13-cts { 3362 pins = "gpio52"; 3363 function = "qup15"; 3364 }; 3365 3366 qup_uart13_rts: qup-uart13-rts { 3367 pins = "gpio53"; 3368 function = "qup15"; 3369 }; 3370 3371 qup_uart13_tx: qup-uart13-tx { 3372 pins = "gpio54"; 3373 function = "qup15"; 3374 }; 3375 3376 qup_uart13_rx: qup-uart13-rx { 3377 pins = "gpio55"; 3378 function = "qup15"; 3379 }; 3380 3381 qup_uart14_cts: qup-uart14-cts { 3382 pins = "gpio56"; 3383 function = "qup16"; 3384 }; 3385 3386 qup_uart14_rts: qup-uart14-rts { 3387 pins = "gpio57"; 3388 function = "qup16"; 3389 }; 3390 3391 qup_uart14_tx: qup-uart14-tx { 3392 pins = "gpio58"; 3393 function = "qup16"; 3394 }; 3395 3396 qup_uart14_rx: qup-uart14-rx { 3397 pins = "gpio59"; 3398 function = "qup16"; 3399 }; 3400 3401 qup_uart15_cts: qup-uart15-cts { 3402 pins = "gpio60"; 3403 function = "qup17"; 3404 }; 3405 3406 qup_uart15_rts: qup-uart15-rts { 3407 pins = "gpio61"; 3408 function = "qup17"; 3409 }; 3410 3411 qup_uart15_tx: qup-uart15-tx { 3412 pins = "gpio62"; 3413 function = "qup17"; 3414 }; 3415 3416 qup_uart15_rx: qup-uart15-rx { 3417 pins = "gpio63"; 3418 function = "qup17"; 3419 }; 3420 }; 3421 3422 imem@146a5000 { 3423 compatible = "qcom,sc7280-imem", "syscon"; 3424 reg = <0 0x146a5000 0 0x6000>; 3425 3426 #address-cells = <1>; 3427 #size-cells = <1>; 3428 3429 ranges = <0 0 0x146a5000 0x6000>; 3430 3431 pil-reloc@594c { 3432 compatible = "qcom,pil-reloc-info"; 3433 reg = <0x594c 0xc8>; 3434 }; 3435 }; 3436 3437 apps_smmu: iommu@15000000 { 3438 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 3439 reg = <0 0x15000000 0 0x100000>; 3440 #iommu-cells = <2>; 3441 #global-interrupts = <1>; 3442 dma-coherent; 3443 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3444 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3445 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3446 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3447 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3448 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3449 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3450 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3451 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3452 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3453 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3454 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3455 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3456 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3457 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3458 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3459 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3460 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3461 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3462 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3463 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3464 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3465 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3466 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3467 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3468 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3469 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3470 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3471 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3472 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3473 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3474 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3475 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3476 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3477 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3478 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3479 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3480 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3481 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3482 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3483 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3484 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3485 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3486 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3487 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3488 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3489 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3490 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3491 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3492 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3493 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3494 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3495 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3496 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3497 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3498 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3499 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3500 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3501 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3502 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3503 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3504 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3505 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3506 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3507 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3508 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3509 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3510 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3511 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3512 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3513 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3514 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3515 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3516 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3517 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3518 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3519 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3520 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3521 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3522 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3523 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 3524 }; 3525 3526 intc: interrupt-controller@17a00000 { 3527 compatible = "arm,gic-v3"; 3528 #address-cells = <2>; 3529 #size-cells = <2>; 3530 ranges; 3531 #interrupt-cells = <3>; 3532 interrupt-controller; 3533 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3534 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3535 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 3536 3537 gic-its@17a40000 { 3538 compatible = "arm,gic-v3-its"; 3539 msi-controller; 3540 #msi-cells = <1>; 3541 reg = <0 0x17a40000 0 0x20000>; 3542 status = "disabled"; 3543 }; 3544 }; 3545 3546 watchdog@17c10000 { 3547 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 3548 reg = <0 0x17c10000 0 0x1000>; 3549 clocks = <&sleep_clk>; 3550 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3551 }; 3552 3553 timer@17c20000 { 3554 #address-cells = <2>; 3555 #size-cells = <2>; 3556 ranges; 3557 compatible = "arm,armv7-timer-mem"; 3558 reg = <0 0x17c20000 0 0x1000>; 3559 3560 frame@17c21000 { 3561 frame-number = <0>; 3562 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3563 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3564 reg = <0 0x17c21000 0 0x1000>, 3565 <0 0x17c22000 0 0x1000>; 3566 }; 3567 3568 frame@17c23000 { 3569 frame-number = <1>; 3570 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3571 reg = <0 0x17c23000 0 0x1000>; 3572 status = "disabled"; 3573 }; 3574 3575 frame@17c25000 { 3576 frame-number = <2>; 3577 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3578 reg = <0 0x17c25000 0 0x1000>; 3579 status = "disabled"; 3580 }; 3581 3582 frame@17c27000 { 3583 frame-number = <3>; 3584 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3585 reg = <0 0x17c27000 0 0x1000>; 3586 status = "disabled"; 3587 }; 3588 3589 frame@17c29000 { 3590 frame-number = <4>; 3591 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3592 reg = <0 0x17c29000 0 0x1000>; 3593 status = "disabled"; 3594 }; 3595 3596 frame@17c2b000 { 3597 frame-number = <5>; 3598 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3599 reg = <0 0x17c2b000 0 0x1000>; 3600 status = "disabled"; 3601 }; 3602 3603 frame@17c2d000 { 3604 frame-number = <6>; 3605 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3606 reg = <0 0x17c2d000 0 0x1000>; 3607 status = "disabled"; 3608 }; 3609 }; 3610 3611 apps_rsc: rsc@18200000 { 3612 compatible = "qcom,rpmh-rsc"; 3613 reg = <0 0x18200000 0 0x10000>, 3614 <0 0x18210000 0 0x10000>, 3615 <0 0x18220000 0 0x10000>; 3616 reg-names = "drv-0", "drv-1", "drv-2"; 3617 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3618 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3619 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3620 qcom,tcs-offset = <0xd00>; 3621 qcom,drv-id = <2>; 3622 qcom,tcs-config = <ACTIVE_TCS 2>, 3623 <SLEEP_TCS 3>, 3624 <WAKE_TCS 3>, 3625 <CONTROL_TCS 1>; 3626 3627 apps_bcm_voter: bcm-voter { 3628 compatible = "qcom,bcm-voter"; 3629 }; 3630 3631 rpmhpd: power-controller { 3632 compatible = "qcom,sc7280-rpmhpd"; 3633 #power-domain-cells = <1>; 3634 operating-points-v2 = <&rpmhpd_opp_table>; 3635 3636 rpmhpd_opp_table: opp-table { 3637 compatible = "operating-points-v2"; 3638 3639 rpmhpd_opp_ret: opp1 { 3640 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3641 }; 3642 3643 rpmhpd_opp_low_svs: opp2 { 3644 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3645 }; 3646 3647 rpmhpd_opp_svs: opp3 { 3648 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3649 }; 3650 3651 rpmhpd_opp_svs_l1: opp4 { 3652 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3653 }; 3654 3655 rpmhpd_opp_svs_l2: opp5 { 3656 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3657 }; 3658 3659 rpmhpd_opp_nom: opp6 { 3660 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3661 }; 3662 3663 rpmhpd_opp_nom_l1: opp7 { 3664 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3665 }; 3666 3667 rpmhpd_opp_turbo: opp8 { 3668 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3669 }; 3670 3671 rpmhpd_opp_turbo_l1: opp9 { 3672 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3673 }; 3674 }; 3675 }; 3676 3677 rpmhcc: clock-controller { 3678 compatible = "qcom,sc7280-rpmh-clk"; 3679 clocks = <&xo_board>; 3680 clock-names = "xo"; 3681 #clock-cells = <1>; 3682 }; 3683 }; 3684 3685 cpufreq_hw: cpufreq@18591000 { 3686 compatible = "qcom,cpufreq-epss"; 3687 reg = <0 0x18591100 0 0x900>, 3688 <0 0x18592100 0 0x900>, 3689 <0 0x18593100 0 0x900>; 3690 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3691 clock-names = "xo", "alternate"; 3692 #freq-domain-cells = <1>; 3693 }; 3694 }; 3695 3696 thermal_zones: thermal-zones { 3697 cpu0-thermal { 3698 polling-delay-passive = <250>; 3699 polling-delay = <0>; 3700 3701 thermal-sensors = <&tsens0 1>; 3702 3703 trips { 3704 cpu0_alert0: trip-point0 { 3705 temperature = <90000>; 3706 hysteresis = <2000>; 3707 type = "passive"; 3708 }; 3709 3710 cpu0_alert1: trip-point1 { 3711 temperature = <95000>; 3712 hysteresis = <2000>; 3713 type = "passive"; 3714 }; 3715 3716 cpu0_crit: cpu-crit { 3717 temperature = <110000>; 3718 hysteresis = <0>; 3719 type = "critical"; 3720 }; 3721 }; 3722 3723 cooling-maps { 3724 map0 { 3725 trip = <&cpu0_alert0>; 3726 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3727 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3728 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3729 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3730 }; 3731 map1 { 3732 trip = <&cpu0_alert1>; 3733 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3734 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3735 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3736 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3737 }; 3738 }; 3739 }; 3740 3741 cpu1-thermal { 3742 polling-delay-passive = <250>; 3743 polling-delay = <0>; 3744 3745 thermal-sensors = <&tsens0 2>; 3746 3747 trips { 3748 cpu1_alert0: trip-point0 { 3749 temperature = <90000>; 3750 hysteresis = <2000>; 3751 type = "passive"; 3752 }; 3753 3754 cpu1_alert1: trip-point1 { 3755 temperature = <95000>; 3756 hysteresis = <2000>; 3757 type = "passive"; 3758 }; 3759 3760 cpu1_crit: cpu-crit { 3761 temperature = <110000>; 3762 hysteresis = <0>; 3763 type = "critical"; 3764 }; 3765 }; 3766 3767 cooling-maps { 3768 map0 { 3769 trip = <&cpu1_alert0>; 3770 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3771 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3772 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3773 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3774 }; 3775 map1 { 3776 trip = <&cpu1_alert1>; 3777 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3778 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3779 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3780 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3781 }; 3782 }; 3783 }; 3784 3785 cpu2-thermal { 3786 polling-delay-passive = <250>; 3787 polling-delay = <0>; 3788 3789 thermal-sensors = <&tsens0 3>; 3790 3791 trips { 3792 cpu2_alert0: trip-point0 { 3793 temperature = <90000>; 3794 hysteresis = <2000>; 3795 type = "passive"; 3796 }; 3797 3798 cpu2_alert1: trip-point1 { 3799 temperature = <95000>; 3800 hysteresis = <2000>; 3801 type = "passive"; 3802 }; 3803 3804 cpu2_crit: cpu-crit { 3805 temperature = <110000>; 3806 hysteresis = <0>; 3807 type = "critical"; 3808 }; 3809 }; 3810 3811 cooling-maps { 3812 map0 { 3813 trip = <&cpu2_alert0>; 3814 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3815 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3816 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3817 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3818 }; 3819 map1 { 3820 trip = <&cpu2_alert1>; 3821 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3822 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3823 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3824 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3825 }; 3826 }; 3827 }; 3828 3829 cpu3-thermal { 3830 polling-delay-passive = <250>; 3831 polling-delay = <0>; 3832 3833 thermal-sensors = <&tsens0 4>; 3834 3835 trips { 3836 cpu3_alert0: trip-point0 { 3837 temperature = <90000>; 3838 hysteresis = <2000>; 3839 type = "passive"; 3840 }; 3841 3842 cpu3_alert1: trip-point1 { 3843 temperature = <95000>; 3844 hysteresis = <2000>; 3845 type = "passive"; 3846 }; 3847 3848 cpu3_crit: cpu-crit { 3849 temperature = <110000>; 3850 hysteresis = <0>; 3851 type = "critical"; 3852 }; 3853 }; 3854 3855 cooling-maps { 3856 map0 { 3857 trip = <&cpu3_alert0>; 3858 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3859 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3860 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3861 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3862 }; 3863 map1 { 3864 trip = <&cpu3_alert1>; 3865 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3866 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3867 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3868 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3869 }; 3870 }; 3871 }; 3872 3873 cpu4-thermal { 3874 polling-delay-passive = <250>; 3875 polling-delay = <0>; 3876 3877 thermal-sensors = <&tsens0 7>; 3878 3879 trips { 3880 cpu4_alert0: trip-point0 { 3881 temperature = <90000>; 3882 hysteresis = <2000>; 3883 type = "passive"; 3884 }; 3885 3886 cpu4_alert1: trip-point1 { 3887 temperature = <95000>; 3888 hysteresis = <2000>; 3889 type = "passive"; 3890 }; 3891 3892 cpu4_crit: cpu-crit { 3893 temperature = <110000>; 3894 hysteresis = <0>; 3895 type = "critical"; 3896 }; 3897 }; 3898 3899 cooling-maps { 3900 map0 { 3901 trip = <&cpu4_alert0>; 3902 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3903 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3904 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3905 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3906 }; 3907 map1 { 3908 trip = <&cpu4_alert1>; 3909 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3910 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3911 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3912 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3913 }; 3914 }; 3915 }; 3916 3917 cpu5-thermal { 3918 polling-delay-passive = <250>; 3919 polling-delay = <0>; 3920 3921 thermal-sensors = <&tsens0 8>; 3922 3923 trips { 3924 cpu5_alert0: trip-point0 { 3925 temperature = <90000>; 3926 hysteresis = <2000>; 3927 type = "passive"; 3928 }; 3929 3930 cpu5_alert1: trip-point1 { 3931 temperature = <95000>; 3932 hysteresis = <2000>; 3933 type = "passive"; 3934 }; 3935 3936 cpu5_crit: cpu-crit { 3937 temperature = <110000>; 3938 hysteresis = <0>; 3939 type = "critical"; 3940 }; 3941 }; 3942 3943 cooling-maps { 3944 map0 { 3945 trip = <&cpu5_alert0>; 3946 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3947 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3948 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3949 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3950 }; 3951 map1 { 3952 trip = <&cpu5_alert1>; 3953 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3954 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3955 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3956 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3957 }; 3958 }; 3959 }; 3960 3961 cpu6-thermal { 3962 polling-delay-passive = <250>; 3963 polling-delay = <0>; 3964 3965 thermal-sensors = <&tsens0 9>; 3966 3967 trips { 3968 cpu6_alert0: trip-point0 { 3969 temperature = <90000>; 3970 hysteresis = <2000>; 3971 type = "passive"; 3972 }; 3973 3974 cpu6_alert1: trip-point1 { 3975 temperature = <95000>; 3976 hysteresis = <2000>; 3977 type = "passive"; 3978 }; 3979 3980 cpu6_crit: cpu-crit { 3981 temperature = <110000>; 3982 hysteresis = <0>; 3983 type = "critical"; 3984 }; 3985 }; 3986 3987 cooling-maps { 3988 map0 { 3989 trip = <&cpu6_alert0>; 3990 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3991 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3992 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3993 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3994 }; 3995 map1 { 3996 trip = <&cpu6_alert1>; 3997 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3998 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3999 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4000 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4001 }; 4002 }; 4003 }; 4004 4005 cpu7-thermal { 4006 polling-delay-passive = <250>; 4007 polling-delay = <0>; 4008 4009 thermal-sensors = <&tsens0 10>; 4010 4011 trips { 4012 cpu7_alert0: trip-point0 { 4013 temperature = <90000>; 4014 hysteresis = <2000>; 4015 type = "passive"; 4016 }; 4017 4018 cpu7_alert1: trip-point1 { 4019 temperature = <95000>; 4020 hysteresis = <2000>; 4021 type = "passive"; 4022 }; 4023 4024 cpu7_crit: cpu-crit { 4025 temperature = <110000>; 4026 hysteresis = <0>; 4027 type = "critical"; 4028 }; 4029 }; 4030 4031 cooling-maps { 4032 map0 { 4033 trip = <&cpu7_alert0>; 4034 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4035 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4036 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4037 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4038 }; 4039 map1 { 4040 trip = <&cpu7_alert1>; 4041 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4042 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4043 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4044 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4045 }; 4046 }; 4047 }; 4048 4049 cpu8-thermal { 4050 polling-delay-passive = <250>; 4051 polling-delay = <0>; 4052 4053 thermal-sensors = <&tsens0 11>; 4054 4055 trips { 4056 cpu8_alert0: trip-point0 { 4057 temperature = <90000>; 4058 hysteresis = <2000>; 4059 type = "passive"; 4060 }; 4061 4062 cpu8_alert1: trip-point1 { 4063 temperature = <95000>; 4064 hysteresis = <2000>; 4065 type = "passive"; 4066 }; 4067 4068 cpu8_crit: cpu-crit { 4069 temperature = <110000>; 4070 hysteresis = <0>; 4071 type = "critical"; 4072 }; 4073 }; 4074 4075 cooling-maps { 4076 map0 { 4077 trip = <&cpu8_alert0>; 4078 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4079 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4080 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4081 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4082 }; 4083 map1 { 4084 trip = <&cpu8_alert1>; 4085 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4086 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4087 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4088 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4089 }; 4090 }; 4091 }; 4092 4093 cpu9-thermal { 4094 polling-delay-passive = <250>; 4095 polling-delay = <0>; 4096 4097 thermal-sensors = <&tsens0 12>; 4098 4099 trips { 4100 cpu9_alert0: trip-point0 { 4101 temperature = <90000>; 4102 hysteresis = <2000>; 4103 type = "passive"; 4104 }; 4105 4106 cpu9_alert1: trip-point1 { 4107 temperature = <95000>; 4108 hysteresis = <2000>; 4109 type = "passive"; 4110 }; 4111 4112 cpu9_crit: cpu-crit { 4113 temperature = <110000>; 4114 hysteresis = <0>; 4115 type = "critical"; 4116 }; 4117 }; 4118 4119 cooling-maps { 4120 map0 { 4121 trip = <&cpu9_alert0>; 4122 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4123 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4124 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4125 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4126 }; 4127 map1 { 4128 trip = <&cpu9_alert1>; 4129 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4130 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4131 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4132 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4133 }; 4134 }; 4135 }; 4136 4137 cpu10-thermal { 4138 polling-delay-passive = <250>; 4139 polling-delay = <0>; 4140 4141 thermal-sensors = <&tsens0 13>; 4142 4143 trips { 4144 cpu10_alert0: trip-point0 { 4145 temperature = <90000>; 4146 hysteresis = <2000>; 4147 type = "passive"; 4148 }; 4149 4150 cpu10_alert1: trip-point1 { 4151 temperature = <95000>; 4152 hysteresis = <2000>; 4153 type = "passive"; 4154 }; 4155 4156 cpu10_crit: cpu-crit { 4157 temperature = <110000>; 4158 hysteresis = <0>; 4159 type = "critical"; 4160 }; 4161 }; 4162 4163 cooling-maps { 4164 map0 { 4165 trip = <&cpu10_alert0>; 4166 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4167 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4168 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4169 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4170 }; 4171 map1 { 4172 trip = <&cpu10_alert1>; 4173 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4174 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4175 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4176 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4177 }; 4178 }; 4179 }; 4180 4181 cpu11-thermal { 4182 polling-delay-passive = <250>; 4183 polling-delay = <0>; 4184 4185 thermal-sensors = <&tsens0 14>; 4186 4187 trips { 4188 cpu11_alert0: trip-point0 { 4189 temperature = <90000>; 4190 hysteresis = <2000>; 4191 type = "passive"; 4192 }; 4193 4194 cpu11_alert1: trip-point1 { 4195 temperature = <95000>; 4196 hysteresis = <2000>; 4197 type = "passive"; 4198 }; 4199 4200 cpu11_crit: cpu-crit { 4201 temperature = <110000>; 4202 hysteresis = <0>; 4203 type = "critical"; 4204 }; 4205 }; 4206 4207 cooling-maps { 4208 map0 { 4209 trip = <&cpu11_alert0>; 4210 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4211 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4212 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4213 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4214 }; 4215 map1 { 4216 trip = <&cpu11_alert1>; 4217 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4218 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4219 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4220 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4221 }; 4222 }; 4223 }; 4224 4225 aoss0-thermal { 4226 polling-delay-passive = <0>; 4227 polling-delay = <0>; 4228 4229 thermal-sensors = <&tsens0 0>; 4230 4231 trips { 4232 aoss0_alert0: trip-point0 { 4233 temperature = <90000>; 4234 hysteresis = <2000>; 4235 type = "hot"; 4236 }; 4237 4238 aoss0_crit: aoss0-crit { 4239 temperature = <110000>; 4240 hysteresis = <0>; 4241 type = "critical"; 4242 }; 4243 }; 4244 }; 4245 4246 aoss1-thermal { 4247 polling-delay-passive = <0>; 4248 polling-delay = <0>; 4249 4250 thermal-sensors = <&tsens1 0>; 4251 4252 trips { 4253 aoss1_alert0: trip-point0 { 4254 temperature = <90000>; 4255 hysteresis = <2000>; 4256 type = "hot"; 4257 }; 4258 4259 aoss1_crit: aoss1-crit { 4260 temperature = <110000>; 4261 hysteresis = <0>; 4262 type = "critical"; 4263 }; 4264 }; 4265 }; 4266 4267 cpuss0-thermal { 4268 polling-delay-passive = <0>; 4269 polling-delay = <0>; 4270 4271 thermal-sensors = <&tsens0 5>; 4272 4273 trips { 4274 cpuss0_alert0: trip-point0 { 4275 temperature = <90000>; 4276 hysteresis = <2000>; 4277 type = "hot"; 4278 }; 4279 cpuss0_crit: cluster0-crit { 4280 temperature = <110000>; 4281 hysteresis = <0>; 4282 type = "critical"; 4283 }; 4284 }; 4285 }; 4286 4287 cpuss1-thermal { 4288 polling-delay-passive = <0>; 4289 polling-delay = <0>; 4290 4291 thermal-sensors = <&tsens0 6>; 4292 4293 trips { 4294 cpuss1_alert0: trip-point0 { 4295 temperature = <90000>; 4296 hysteresis = <2000>; 4297 type = "hot"; 4298 }; 4299 cpuss1_crit: cluster0-crit { 4300 temperature = <110000>; 4301 hysteresis = <0>; 4302 type = "critical"; 4303 }; 4304 }; 4305 }; 4306 4307 gpuss0-thermal { 4308 polling-delay-passive = <100>; 4309 polling-delay = <0>; 4310 4311 thermal-sensors = <&tsens1 1>; 4312 4313 trips { 4314 gpuss0_alert0: trip-point0 { 4315 temperature = <95000>; 4316 hysteresis = <2000>; 4317 type = "passive"; 4318 }; 4319 4320 gpuss0_crit: gpuss0-crit { 4321 temperature = <110000>; 4322 hysteresis = <0>; 4323 type = "critical"; 4324 }; 4325 }; 4326 4327 cooling-maps { 4328 map0 { 4329 trip = <&gpuss0_alert0>; 4330 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4331 }; 4332 }; 4333 }; 4334 4335 gpuss1-thermal { 4336 polling-delay-passive = <100>; 4337 polling-delay = <0>; 4338 4339 thermal-sensors = <&tsens1 2>; 4340 4341 trips { 4342 gpuss1_alert0: trip-point0 { 4343 temperature = <95000>; 4344 hysteresis = <2000>; 4345 type = "passive"; 4346 }; 4347 4348 gpuss1_crit: gpuss1-crit { 4349 temperature = <110000>; 4350 hysteresis = <0>; 4351 type = "critical"; 4352 }; 4353 }; 4354 4355 cooling-maps { 4356 map0 { 4357 trip = <&gpuss1_alert0>; 4358 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4359 }; 4360 }; 4361 }; 4362 4363 nspss0-thermal { 4364 polling-delay-passive = <0>; 4365 polling-delay = <0>; 4366 4367 thermal-sensors = <&tsens1 3>; 4368 4369 trips { 4370 nspss0_alert0: trip-point0 { 4371 temperature = <90000>; 4372 hysteresis = <2000>; 4373 type = "hot"; 4374 }; 4375 4376 nspss0_crit: nspss0-crit { 4377 temperature = <110000>; 4378 hysteresis = <0>; 4379 type = "critical"; 4380 }; 4381 }; 4382 }; 4383 4384 nspss1-thermal { 4385 polling-delay-passive = <0>; 4386 polling-delay = <0>; 4387 4388 thermal-sensors = <&tsens1 4>; 4389 4390 trips { 4391 nspss1_alert0: trip-point0 { 4392 temperature = <90000>; 4393 hysteresis = <2000>; 4394 type = "hot"; 4395 }; 4396 4397 nspss1_crit: nspss1-crit { 4398 temperature = <110000>; 4399 hysteresis = <0>; 4400 type = "critical"; 4401 }; 4402 }; 4403 }; 4404 4405 video-thermal { 4406 polling-delay-passive = <0>; 4407 polling-delay = <0>; 4408 4409 thermal-sensors = <&tsens1 5>; 4410 4411 trips { 4412 video_alert0: trip-point0 { 4413 temperature = <90000>; 4414 hysteresis = <2000>; 4415 type = "hot"; 4416 }; 4417 4418 video_crit: video-crit { 4419 temperature = <110000>; 4420 hysteresis = <0>; 4421 type = "critical"; 4422 }; 4423 }; 4424 }; 4425 4426 ddr-thermal { 4427 polling-delay-passive = <0>; 4428 polling-delay = <0>; 4429 4430 thermal-sensors = <&tsens1 6>; 4431 4432 trips { 4433 ddr_alert0: trip-point0 { 4434 temperature = <90000>; 4435 hysteresis = <2000>; 4436 type = "hot"; 4437 }; 4438 4439 ddr_crit: ddr-crit { 4440 temperature = <110000>; 4441 hysteresis = <0>; 4442 type = "critical"; 4443 }; 4444 }; 4445 }; 4446 4447 mdmss0-thermal { 4448 polling-delay-passive = <0>; 4449 polling-delay = <0>; 4450 4451 thermal-sensors = <&tsens1 7>; 4452 4453 trips { 4454 mdmss0_alert0: trip-point0 { 4455 temperature = <90000>; 4456 hysteresis = <2000>; 4457 type = "hot"; 4458 }; 4459 4460 mdmss0_crit: mdmss0-crit { 4461 temperature = <110000>; 4462 hysteresis = <0>; 4463 type = "critical"; 4464 }; 4465 }; 4466 }; 4467 4468 mdmss1-thermal { 4469 polling-delay-passive = <0>; 4470 polling-delay = <0>; 4471 4472 thermal-sensors = <&tsens1 8>; 4473 4474 trips { 4475 mdmss1_alert0: trip-point0 { 4476 temperature = <90000>; 4477 hysteresis = <2000>; 4478 type = "hot"; 4479 }; 4480 4481 mdmss1_crit: mdmss1-crit { 4482 temperature = <110000>; 4483 hysteresis = <0>; 4484 type = "critical"; 4485 }; 4486 }; 4487 }; 4488 4489 mdmss2-thermal { 4490 polling-delay-passive = <0>; 4491 polling-delay = <0>; 4492 4493 thermal-sensors = <&tsens1 9>; 4494 4495 trips { 4496 mdmss2_alert0: trip-point0 { 4497 temperature = <90000>; 4498 hysteresis = <2000>; 4499 type = "hot"; 4500 }; 4501 4502 mdmss2_crit: mdmss2-crit { 4503 temperature = <110000>; 4504 hysteresis = <0>; 4505 type = "critical"; 4506 }; 4507 }; 4508 }; 4509 4510 mdmss3-thermal { 4511 polling-delay-passive = <0>; 4512 polling-delay = <0>; 4513 4514 thermal-sensors = <&tsens1 10>; 4515 4516 trips { 4517 mdmss3_alert0: trip-point0 { 4518 temperature = <90000>; 4519 hysteresis = <2000>; 4520 type = "hot"; 4521 }; 4522 4523 mdmss3_crit: mdmss3-crit { 4524 temperature = <110000>; 4525 hysteresis = <0>; 4526 type = "critical"; 4527 }; 4528 }; 4529 }; 4530 4531 camera0-thermal { 4532 polling-delay-passive = <0>; 4533 polling-delay = <0>; 4534 4535 thermal-sensors = <&tsens1 11>; 4536 4537 trips { 4538 camera0_alert0: trip-point0 { 4539 temperature = <90000>; 4540 hysteresis = <2000>; 4541 type = "hot"; 4542 }; 4543 4544 camera0_crit: camera0-crit { 4545 temperature = <110000>; 4546 hysteresis = <0>; 4547 type = "critical"; 4548 }; 4549 }; 4550 }; 4551 }; 4552 4553 timer { 4554 compatible = "arm,armv8-timer"; 4555 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 4556 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 4557 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 4558 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 4559 }; 4560}; 4561