1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ9574 SoC device tree source 4 * 5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 6 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 7 */ 8 9#include <dt-bindings/clock/qcom,apss-ipq.h> 10#include <dt-bindings/clock/qcom,ipq9574-gcc.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/reset/qcom,ipq9574-gcc.h> 13 14/ { 15 interrupt-parent = <&intc>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 clocks { 20 sleep_clk: sleep-clk { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 }; 24 25 xo_board_clk: xo-board-clk { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 }; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 CPU0: cpu@0 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a73"; 38 reg = <0x0>; 39 enable-method = "psci"; 40 next-level-cache = <&L2_0>; 41 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 42 clock-names = "cpu"; 43 operating-points-v2 = <&cpu_opp_table>; 44 cpu-supply = <&ipq9574_s1>; 45 }; 46 47 CPU1: cpu@1 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a73"; 50 reg = <0x1>; 51 enable-method = "psci"; 52 next-level-cache = <&L2_0>; 53 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 54 clock-names = "cpu"; 55 operating-points-v2 = <&cpu_opp_table>; 56 cpu-supply = <&ipq9574_s1>; 57 }; 58 59 CPU2: cpu@2 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a73"; 62 reg = <0x2>; 63 enable-method = "psci"; 64 next-level-cache = <&L2_0>; 65 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 66 clock-names = "cpu"; 67 operating-points-v2 = <&cpu_opp_table>; 68 cpu-supply = <&ipq9574_s1>; 69 }; 70 71 CPU3: cpu@3 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a73"; 74 reg = <0x3>; 75 enable-method = "psci"; 76 next-level-cache = <&L2_0>; 77 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 78 clock-names = "cpu"; 79 operating-points-v2 = <&cpu_opp_table>; 80 cpu-supply = <&ipq9574_s1>; 81 }; 82 83 L2_0: l2-cache { 84 compatible = "cache"; 85 cache-level = <2>; 86 cache-unified; 87 }; 88 }; 89 90 firmware { 91 scm { 92 compatible = "qcom,scm-ipq9574", "qcom,scm"; 93 qcom,dload-mode = <&tcsr 0x6100>; 94 }; 95 }; 96 97 memory@40000000 { 98 device_type = "memory"; 99 /* We expect the bootloader to fill in the size */ 100 reg = <0x0 0x40000000 0x0 0x0>; 101 }; 102 103 cpu_opp_table: opp-table-cpu { 104 compatible = "operating-points-v2"; 105 opp-shared; 106 107 opp-936000000 { 108 opp-hz = /bits/ 64 <936000000>; 109 opp-microvolt = <725000>; 110 clock-latency-ns = <200000>; 111 }; 112 113 opp-1104000000 { 114 opp-hz = /bits/ 64 <1104000000>; 115 opp-microvolt = <787500>; 116 clock-latency-ns = <200000>; 117 }; 118 119 opp-1416000000 { 120 opp-hz = /bits/ 64 <1416000000>; 121 opp-microvolt = <862500>; 122 clock-latency-ns = <200000>; 123 }; 124 125 opp-1488000000 { 126 opp-hz = /bits/ 64 <1488000000>; 127 opp-microvolt = <925000>; 128 clock-latency-ns = <200000>; 129 }; 130 131 opp-1800000000 { 132 opp-hz = /bits/ 64 <1800000000>; 133 opp-microvolt = <987500>; 134 clock-latency-ns = <200000>; 135 }; 136 137 opp-2208000000 { 138 opp-hz = /bits/ 64 <2208000000>; 139 opp-microvolt = <1062500>; 140 clock-latency-ns = <200000>; 141 }; 142 }; 143 144 pmu { 145 compatible = "arm,cortex-a73-pmu"; 146 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 147 }; 148 149 psci { 150 compatible = "arm,psci-1.0"; 151 method = "smc"; 152 }; 153 154 reserved-memory { 155 #address-cells = <2>; 156 #size-cells = <2>; 157 ranges; 158 159 bootloader@4a100000 { 160 reg = <0x0 0x4a100000 0x0 0x400000>; 161 no-map; 162 }; 163 164 sbl@4a500000 { 165 reg = <0x0 0x4a500000 0x0 0x100000>; 166 no-map; 167 }; 168 169 tz_region: tz@4a600000 { 170 reg = <0x0 0x4a600000 0x0 0x400000>; 171 no-map; 172 }; 173 174 smem@4aa00000 { 175 compatible = "qcom,smem"; 176 reg = <0x0 0x4aa00000 0x0 0x100000>; 177 hwlocks = <&tcsr_mutex 0>; 178 no-map; 179 }; 180 }; 181 182 rpm-glink { 183 compatible = "qcom,glink-rpm"; 184 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 185 qcom,rpm-msg-ram = <&rpm_msg_ram>; 186 mboxes = <&apcs_glb 0>; 187 188 rpm_requests: rpm-requests { 189 compatible = "qcom,rpm-ipq9574"; 190 qcom,glink-channels = "rpm_requests"; 191 }; 192 }; 193 194 soc: soc@0 { 195 compatible = "simple-bus"; 196 #address-cells = <1>; 197 #size-cells = <1>; 198 ranges = <0 0 0 0xffffffff>; 199 200 rpm_msg_ram: sram@60000 { 201 compatible = "qcom,rpm-msg-ram"; 202 reg = <0x00060000 0x6000>; 203 }; 204 205 rng: rng@e3000 { 206 compatible = "qcom,prng-ee"; 207 reg = <0x000e3000 0x1000>; 208 clocks = <&gcc GCC_PRNG_AHB_CLK>; 209 clock-names = "core"; 210 }; 211 212 qfprom: efuse@a4000 { 213 compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; 214 reg = <0x000a4000 0x5a1>; 215 #address-cells = <1>; 216 #size-cells = <1>; 217 }; 218 219 cryptobam: dma-controller@704000 { 220 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 221 reg = <0x00704000 0x20000>; 222 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 223 #dma-cells = <1>; 224 qcom,ee = <1>; 225 qcom,controlled-remotely; 226 }; 227 228 crypto: crypto@73a000 { 229 compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce"; 230 reg = <0x0073a000 0x6000>; 231 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 232 <&gcc GCC_CRYPTO_AXI_CLK>, 233 <&gcc GCC_CRYPTO_CLK>; 234 clock-names = "iface", "bus", "core"; 235 dmas = <&cryptobam 2>, <&cryptobam 3>; 236 dma-names = "rx", "tx"; 237 }; 238 239 tsens: thermal-sensor@4a9000 { 240 compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens"; 241 reg = <0x004a9000 0x1000>, 242 <0x004a8000 0x1000>; 243 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 244 interrupt-names = "combined"; 245 #qcom,sensors = <16>; 246 #thermal-sensor-cells = <1>; 247 }; 248 249 tlmm: pinctrl@1000000 { 250 compatible = "qcom,ipq9574-tlmm"; 251 reg = <0x01000000 0x300000>; 252 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 253 gpio-controller; 254 #gpio-cells = <2>; 255 gpio-ranges = <&tlmm 0 0 65>; 256 interrupt-controller; 257 #interrupt-cells = <2>; 258 259 uart2_pins: uart2-state { 260 pins = "gpio34", "gpio35"; 261 function = "blsp2_uart"; 262 drive-strength = <8>; 263 bias-disable; 264 }; 265 }; 266 267 gcc: clock-controller@1800000 { 268 compatible = "qcom,ipq9574-gcc"; 269 reg = <0x01800000 0x80000>; 270 clocks = <&xo_board_clk>, 271 <&sleep_clk>, 272 <0>, 273 <0>, 274 <0>, 275 <0>, 276 <0>, 277 <0>; 278 #clock-cells = <1>; 279 #reset-cells = <1>; 280 #power-domain-cells = <1>; 281 }; 282 283 tcsr_mutex: hwlock@1905000 { 284 compatible = "qcom,tcsr-mutex"; 285 reg = <0x01905000 0x20000>; 286 #hwlock-cells = <1>; 287 }; 288 289 tcsr: syscon@1937000 { 290 compatible = "qcom,tcsr-ipq9574", "syscon"; 291 reg = <0x01937000 0x21000>; 292 }; 293 294 sdhc_1: mmc@7804000 { 295 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; 296 reg = <0x07804000 0x1000>, <0x07805000 0x1000>; 297 reg-names = "hc", "cqhci"; 298 299 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 301 interrupt-names = "hc_irq", "pwr_irq"; 302 303 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 304 <&gcc GCC_SDCC1_APPS_CLK>, 305 <&xo_board_clk>; 306 clock-names = "iface", "core", "xo"; 307 non-removable; 308 status = "disabled"; 309 }; 310 311 blsp_dma: dma-controller@7884000 { 312 compatible = "qcom,bam-v1.7.0"; 313 reg = <0x07884000 0x2b000>; 314 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 316 clock-names = "bam_clk"; 317 #dma-cells = <1>; 318 qcom,ee = <0>; 319 }; 320 321 blsp1_uart0: serial@78af000 { 322 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 323 reg = <0x078af000 0x200>; 324 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 326 <&gcc GCC_BLSP1_AHB_CLK>; 327 clock-names = "core", "iface"; 328 status = "disabled"; 329 }; 330 331 blsp1_uart1: serial@78b0000 { 332 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 333 reg = <0x078b0000 0x200>; 334 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 336 <&gcc GCC_BLSP1_AHB_CLK>; 337 clock-names = "core", "iface"; 338 status = "disabled"; 339 }; 340 341 blsp1_uart2: serial@78b1000 { 342 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 343 reg = <0x078b1000 0x200>; 344 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 346 <&gcc GCC_BLSP1_AHB_CLK>; 347 clock-names = "core", "iface"; 348 status = "disabled"; 349 }; 350 351 blsp1_uart3: serial@78b2000 { 352 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 353 reg = <0x078b2000 0x200>; 354 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, 356 <&gcc GCC_BLSP1_AHB_CLK>; 357 clock-names = "core", "iface"; 358 status = "disabled"; 359 }; 360 361 blsp1_uart4: serial@78b3000 { 362 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 363 reg = <0x078b3000 0x200>; 364 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 366 <&gcc GCC_BLSP1_AHB_CLK>; 367 clock-names = "core", "iface"; 368 status = "disabled"; 369 }; 370 371 blsp1_uart5: serial@78b4000 { 372 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 373 reg = <0x078b4000 0x200>; 374 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>, 376 <&gcc GCC_BLSP1_AHB_CLK>; 377 clock-names = "core", "iface"; 378 status = "disabled"; 379 }; 380 381 blsp1_spi0: spi@78b5000 { 382 compatible = "qcom,spi-qup-v2.2.1"; 383 reg = <0x078b5000 0x600>; 384 #address-cells = <1>; 385 #size-cells = <0>; 386 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 388 <&gcc GCC_BLSP1_AHB_CLK>; 389 clock-names = "core", "iface"; 390 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 391 dma-names = "tx", "rx"; 392 status = "disabled"; 393 }; 394 395 blsp1_i2c1: i2c@78b6000 { 396 compatible = "qcom,i2c-qup-v2.2.1"; 397 reg = <0x078b6000 0x600>; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 402 <&gcc GCC_BLSP1_AHB_CLK>; 403 clock-names = "core", "iface"; 404 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 405 dma-names = "tx", "rx"; 406 status = "disabled"; 407 }; 408 409 blsp1_spi1: spi@78b6000 { 410 compatible = "qcom,spi-qup-v2.2.1"; 411 reg = <0x078b6000 0x600>; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 416 <&gcc GCC_BLSP1_AHB_CLK>; 417 clock-names = "core", "iface"; 418 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 419 dma-names = "tx", "rx"; 420 status = "disabled"; 421 }; 422 423 blsp1_i2c2: i2c@78b7000 { 424 compatible = "qcom,i2c-qup-v2.2.1"; 425 reg = <0x078b7000 0x600>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 430 <&gcc GCC_BLSP1_AHB_CLK>; 431 clock-names = "core", "iface"; 432 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 433 dma-names = "tx", "rx"; 434 status = "disabled"; 435 }; 436 437 blsp1_spi2: spi@78b7000 { 438 compatible = "qcom,spi-qup-v2.2.1"; 439 reg = <0x078b7000 0x600>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 444 <&gcc GCC_BLSP1_AHB_CLK>; 445 clock-names = "core", "iface"; 446 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 447 dma-names = "tx", "rx"; 448 status = "disabled"; 449 }; 450 451 blsp1_i2c3: i2c@78b8000 { 452 compatible = "qcom,i2c-qup-v2.2.1"; 453 reg = <0x078b8000 0x600>; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 458 <&gcc GCC_BLSP1_AHB_CLK>; 459 clock-names = "core", "iface"; 460 dmas = <&blsp_dma 18>, <&blsp_dma 19>; 461 dma-names = "tx", "rx"; 462 status = "disabled"; 463 }; 464 465 blsp1_spi3: spi@78b8000 { 466 compatible = "qcom,spi-qup-v2.2.1"; 467 reg = <0x078b8000 0x600>; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 471 spi-max-frequency = <50000000>; 472 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 473 <&gcc GCC_BLSP1_AHB_CLK>; 474 clock-names = "core", "iface"; 475 dmas = <&blsp_dma 18>, <&blsp_dma 19>; 476 dma-names = "tx", "rx"; 477 status = "disabled"; 478 }; 479 480 blsp1_i2c4: i2c@78b9000 { 481 compatible = "qcom,i2c-qup-v2.2.1"; 482 reg = <0x078b9000 0x600>; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 487 <&gcc GCC_BLSP1_AHB_CLK>; 488 clock-names = "core", "iface"; 489 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 490 dma-names = "tx", "rx"; 491 status = "disabled"; 492 }; 493 494 blsp1_spi4: spi@78b9000 { 495 compatible = "qcom,spi-qup-v2.2.1"; 496 reg = <0x078b9000 0x600>; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 501 <&gcc GCC_BLSP1_AHB_CLK>; 502 clock-names = "core", "iface"; 503 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 504 dma-names = "tx", "rx"; 505 status = "disabled"; 506 }; 507 508 intc: interrupt-controller@b000000 { 509 compatible = "qcom,msm-qgic2"; 510 reg = <0x0b000000 0x1000>, /* GICD */ 511 <0x0b002000 0x2000>, /* GICC */ 512 <0x0b001000 0x1000>, /* GICH */ 513 <0x0b004000 0x2000>; /* GICV */ 514 #address-cells = <1>; 515 #size-cells = <1>; 516 interrupt-controller; 517 #interrupt-cells = <3>; 518 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 519 ranges = <0 0x0b00c000 0x3000>; 520 521 v2m0: v2m@0 { 522 compatible = "arm,gic-v2m-frame"; 523 reg = <0x00000000 0xffd>; 524 msi-controller; 525 }; 526 527 v2m1: v2m@1000 { 528 compatible = "arm,gic-v2m-frame"; 529 reg = <0x00001000 0xffd>; 530 msi-controller; 531 }; 532 533 v2m2: v2m@2000 { 534 compatible = "arm,gic-v2m-frame"; 535 reg = <0x00002000 0xffd>; 536 msi-controller; 537 }; 538 }; 539 540 watchdog: watchdog@b017000 { 541 compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt"; 542 reg = <0x0b017000 0x1000>; 543 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 544 clocks = <&sleep_clk>; 545 timeout-sec = <30>; 546 }; 547 548 apcs_glb: mailbox@b111000 { 549 compatible = "qcom,ipq9574-apcs-apps-global", 550 "qcom,ipq6018-apcs-apps-global"; 551 reg = <0x0b111000 0x1000>; 552 #clock-cells = <1>; 553 clocks = <&a73pll>, <&xo_board_clk>; 554 clock-names = "pll", "xo"; 555 #mbox-cells = <1>; 556 }; 557 558 a73pll: clock@b116000 { 559 compatible = "qcom,ipq9574-a73pll"; 560 reg = <0x0b116000 0x40>; 561 #clock-cells = <0>; 562 clocks = <&xo_board_clk>; 563 clock-names = "xo"; 564 }; 565 566 timer@b120000 { 567 compatible = "arm,armv7-timer-mem"; 568 reg = <0x0b120000 0x1000>; 569 #address-cells = <1>; 570 #size-cells = <1>; 571 ranges; 572 573 frame@b120000 { 574 reg = <0x0b121000 0x1000>, 575 <0x0b122000 0x1000>; 576 frame-number = <0>; 577 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 579 }; 580 581 frame@b123000 { 582 reg = <0x0b123000 0x1000>; 583 frame-number = <1>; 584 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 585 status = "disabled"; 586 }; 587 588 frame@b124000 { 589 reg = <0x0b124000 0x1000>; 590 frame-number = <2>; 591 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 592 status = "disabled"; 593 }; 594 595 frame@b125000 { 596 reg = <0x0b125000 0x1000>; 597 frame-number = <3>; 598 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 599 status = "disabled"; 600 }; 601 602 frame@b126000 { 603 reg = <0x0b126000 0x1000>; 604 frame-number = <4>; 605 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 606 status = "disabled"; 607 }; 608 609 frame@b127000 { 610 reg = <0x0b127000 0x1000>; 611 frame-number = <5>; 612 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 613 status = "disabled"; 614 }; 615 616 frame@b128000 { 617 reg = <0x0b128000 0x1000>; 618 frame-number = <6>; 619 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 620 status = "disabled"; 621 }; 622 }; 623 }; 624 625 thermal-zones { 626 nss-top-thermal { 627 polling-delay-passive = <0>; 628 polling-delay = <0>; 629 thermal-sensors = <&tsens 3>; 630 631 trips { 632 nss-top-critical { 633 temperature = <125000>; 634 hysteresis = <1000>; 635 type = "critical"; 636 }; 637 }; 638 }; 639 640 ubi-0-thermal { 641 polling-delay-passive = <0>; 642 polling-delay = <0>; 643 thermal-sensors = <&tsens 4>; 644 645 trips { 646 ubi_0-critical { 647 temperature = <125000>; 648 hysteresis = <1000>; 649 type = "critical"; 650 }; 651 }; 652 }; 653 654 ubi-1-thermal { 655 polling-delay-passive = <0>; 656 polling-delay = <0>; 657 thermal-sensors = <&tsens 5>; 658 659 trips { 660 ubi_1-critical { 661 temperature = <125000>; 662 hysteresis = <1000>; 663 type = "critical"; 664 }; 665 }; 666 }; 667 668 ubi-2-thermal { 669 polling-delay-passive = <0>; 670 polling-delay = <0>; 671 thermal-sensors = <&tsens 6>; 672 673 trips { 674 ubi_2-critical { 675 temperature = <125000>; 676 hysteresis = <1000>; 677 type = "critical"; 678 }; 679 }; 680 }; 681 682 ubi-3-thermal { 683 polling-delay-passive = <0>; 684 polling-delay = <0>; 685 thermal-sensors = <&tsens 7>; 686 687 trips { 688 ubi_3-critical { 689 temperature = <125000>; 690 hysteresis = <1000>; 691 type = "critical"; 692 }; 693 }; 694 }; 695 696 cpuss0-thermal { 697 polling-delay-passive = <0>; 698 polling-delay = <0>; 699 thermal-sensors = <&tsens 8>; 700 701 trips { 702 cpu-critical { 703 temperature = <125000>; 704 hysteresis = <1000>; 705 type = "critical"; 706 }; 707 }; 708 }; 709 710 cpuss1-thermal { 711 polling-delay-passive = <0>; 712 polling-delay = <0>; 713 thermal-sensors = <&tsens 9>; 714 715 trips { 716 cpu-critical { 717 temperature = <125000>; 718 hysteresis = <1000>; 719 type = "critical"; 720 }; 721 }; 722 }; 723 724 cpu0-thermal { 725 polling-delay-passive = <0>; 726 polling-delay = <0>; 727 thermal-sensors = <&tsens 10>; 728 729 trips { 730 cpu-critical { 731 temperature = <120000>; 732 hysteresis = <10000>; 733 type = "critical"; 734 }; 735 736 cpu-passive { 737 temperature = <110000>; 738 hysteresis = <1000>; 739 type = "passive"; 740 }; 741 }; 742 }; 743 744 cpu1-thermal { 745 polling-delay-passive = <0>; 746 polling-delay = <0>; 747 thermal-sensors = <&tsens 11>; 748 749 trips { 750 cpu-critical { 751 temperature = <120000>; 752 hysteresis = <10000>; 753 type = "critical"; 754 }; 755 756 cpu-passive { 757 temperature = <110000>; 758 hysteresis = <1000>; 759 type = "passive"; 760 }; 761 }; 762 }; 763 764 cpu2-thermal { 765 polling-delay-passive = <0>; 766 polling-delay = <0>; 767 thermal-sensors = <&tsens 12>; 768 769 trips { 770 cpu-critical { 771 temperature = <120000>; 772 hysteresis = <10000>; 773 type = "critical"; 774 }; 775 776 cpu-passive { 777 temperature = <110000>; 778 hysteresis = <1000>; 779 type = "passive"; 780 }; 781 }; 782 }; 783 784 cpu3-thermal { 785 polling-delay-passive = <0>; 786 polling-delay = <0>; 787 thermal-sensors = <&tsens 13>; 788 789 trips { 790 cpu-critical { 791 temperature = <120000>; 792 hysteresis = <10000>; 793 type = "critical"; 794 }; 795 796 cpu-passive { 797 temperature = <110000>; 798 hysteresis = <1000>; 799 type = "passive"; 800 }; 801 }; 802 }; 803 804 wcss-phyb-thermal { 805 polling-delay-passive = <0>; 806 polling-delay = <0>; 807 thermal-sensors = <&tsens 14>; 808 809 trips { 810 wcss_phyb-critical { 811 temperature = <125000>; 812 hysteresis = <1000>; 813 type = "critical"; 814 }; 815 }; 816 }; 817 818 top-glue-thermal { 819 polling-delay-passive = <0>; 820 polling-delay = <0>; 821 thermal-sensors = <&tsens 15>; 822 823 trips { 824 top_glue-critical { 825 temperature = <125000>; 826 hysteresis = <1000>; 827 type = "critical"; 828 }; 829 }; 830 }; 831 }; 832 833 timer { 834 compatible = "arm,armv8-timer"; 835 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 836 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 837 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 838 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 839 }; 840}; 841