1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ9574 SoC device tree source 4 * 5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 6 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/qcom,ipq9574-gcc.h> 11#include <dt-bindings/reset/qcom,ipq9574-gcc.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 clocks { 19 bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk { 20 compatible = "fixed-clock"; 21 clock-frequency = <353000000>; 22 #clock-cells = <0>; 23 }; 24 25 sleep_clk: sleep-clk { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 }; 29 30 xo_board_clk: xo-board-clk { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 }; 34 }; 35 36 cpus { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 40 CPU0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a73"; 43 reg = <0x0>; 44 enable-method = "psci"; 45 next-level-cache = <&L2_0>; 46 }; 47 48 CPU1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a73"; 51 reg = <0x1>; 52 enable-method = "psci"; 53 next-level-cache = <&L2_0>; 54 }; 55 56 CPU2: cpu@2 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a73"; 59 reg = <0x2>; 60 enable-method = "psci"; 61 next-level-cache = <&L2_0>; 62 }; 63 64 CPU3: cpu@3 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a73"; 67 reg = <0x3>; 68 enable-method = "psci"; 69 next-level-cache = <&L2_0>; 70 }; 71 72 L2_0: l2-cache { 73 compatible = "cache"; 74 cache-level = <2>; 75 cache-unified; 76 }; 77 }; 78 79 memory@40000000 { 80 device_type = "memory"; 81 /* We expect the bootloader to fill in the size */ 82 reg = <0x0 0x40000000 0x0 0x0>; 83 }; 84 85 pmu { 86 compatible = "arm,cortex-a73-pmu"; 87 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 88 }; 89 90 psci { 91 compatible = "arm,psci-1.0"; 92 method = "smc"; 93 }; 94 95 reserved-memory { 96 #address-cells = <2>; 97 #size-cells = <2>; 98 ranges; 99 100 tz_region: tz@4a600000 { 101 reg = <0x0 0x4a600000 0x0 0x400000>; 102 no-map; 103 }; 104 }; 105 106 soc: soc@0 { 107 compatible = "simple-bus"; 108 #address-cells = <1>; 109 #size-cells = <1>; 110 ranges = <0 0 0 0xffffffff>; 111 112 tlmm: pinctrl@1000000 { 113 compatible = "qcom,ipq9574-tlmm"; 114 reg = <0x01000000 0x300000>; 115 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 116 gpio-controller; 117 #gpio-cells = <2>; 118 gpio-ranges = <&tlmm 0 0 65>; 119 interrupt-controller; 120 #interrupt-cells = <2>; 121 122 uart2_pins: uart2-state { 123 pins = "gpio34", "gpio35"; 124 function = "blsp2_uart"; 125 drive-strength = <8>; 126 bias-disable; 127 }; 128 }; 129 130 gcc: clock-controller@1800000 { 131 compatible = "qcom,ipq9574-gcc"; 132 reg = <0x01800000 0x80000>; 133 clocks = <&xo_board_clk>, 134 <&sleep_clk>, 135 <&bias_pll_ubi_nc_clk>, 136 <0>, 137 <0>, 138 <0>, 139 <0>, 140 <0>; 141 #clock-cells = <1>; 142 #reset-cells = <1>; 143 #power-domain-cells = <1>; 144 }; 145 146 sdhc_1: mmc@7804000 { 147 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; 148 reg = <0x07804000 0x1000>, <0x07805000 0x1000>; 149 reg-names = "hc", "cqhci"; 150 151 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 153 interrupt-names = "hc_irq", "pwr_irq"; 154 155 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 156 <&gcc GCC_SDCC1_APPS_CLK>, 157 <&xo_board_clk>; 158 clock-names = "iface", "core", "xo"; 159 non-removable; 160 status = "disabled"; 161 }; 162 163 blsp1_uart2: serial@78b1000 { 164 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 165 reg = <0x078b1000 0x200>; 166 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 167 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 168 <&gcc GCC_BLSP1_AHB_CLK>; 169 clock-names = "core", "iface"; 170 status = "disabled"; 171 }; 172 173 intc: interrupt-controller@b000000 { 174 compatible = "qcom,msm-qgic2"; 175 reg = <0x0b000000 0x1000>, /* GICD */ 176 <0x0b002000 0x1000>, /* GICC */ 177 <0x0b001000 0x1000>, /* GICH */ 178 <0x0b004000 0x1000>; /* GICV */ 179 #address-cells = <1>; 180 #size-cells = <1>; 181 interrupt-controller; 182 #interrupt-cells = <3>; 183 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 184 ranges = <0 0x0b00c000 0x3000>; 185 186 v2m0: v2m@0 { 187 compatible = "arm,gic-v2m-frame"; 188 reg = <0x00000000 0xffd>; 189 msi-controller; 190 }; 191 192 v2m1: v2m@1000 { 193 compatible = "arm,gic-v2m-frame"; 194 reg = <0x00001000 0xffd>; 195 msi-controller; 196 }; 197 198 v2m2: v2m@2000 { 199 compatible = "arm,gic-v2m-frame"; 200 reg = <0x00002000 0xffd>; 201 msi-controller; 202 }; 203 }; 204 205 timer@b120000 { 206 compatible = "arm,armv7-timer-mem"; 207 reg = <0x0b120000 0x1000>; 208 #address-cells = <1>; 209 #size-cells = <1>; 210 ranges; 211 212 frame@b120000 { 213 reg = <0x0b121000 0x1000>, 214 <0x0b122000 0x1000>; 215 frame-number = <0>; 216 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 218 }; 219 220 frame@b123000 { 221 reg = <0x0b123000 0x1000>; 222 frame-number = <1>; 223 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 224 status = "disabled"; 225 }; 226 227 frame@b124000 { 228 reg = <0x0b124000 0x1000>; 229 frame-number = <2>; 230 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 231 status = "disabled"; 232 }; 233 234 frame@b125000 { 235 reg = <0x0b125000 0x1000>; 236 frame-number = <3>; 237 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 238 status = "disabled"; 239 }; 240 241 frame@b126000 { 242 reg = <0x0b126000 0x1000>; 243 frame-number = <4>; 244 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 245 status = "disabled"; 246 }; 247 248 frame@b127000 { 249 reg = <0x0b127000 0x1000>; 250 frame-number = <5>; 251 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 252 status = "disabled"; 253 }; 254 255 frame@b128000 { 256 reg = <0x0b128000 0x1000>; 257 frame-number = <6>; 258 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 259 status = "disabled"; 260 }; 261 }; 262 }; 263 264 timer { 265 compatible = "arm,armv8-timer"; 266 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 267 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 268 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 269 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 270 }; 271}; 272