1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ9574 SoC device tree source 4 * 5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 6 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/qcom,ipq9574-gcc.h> 11#include <dt-bindings/reset/qcom,ipq9574-gcc.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 clocks { 19 bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk { 20 compatible = "fixed-clock"; 21 clock-frequency = <353000000>; 22 #clock-cells = <0>; 23 }; 24 25 sleep_clk: sleep-clk { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 }; 29 30 xo_board_clk: xo-board-clk { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 }; 34 }; 35 36 cpus { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 40 CPU0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a73"; 43 reg = <0x0>; 44 enable-method = "psci"; 45 next-level-cache = <&L2_0>; 46 }; 47 48 CPU1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a73"; 51 reg = <0x1>; 52 enable-method = "psci"; 53 next-level-cache = <&L2_0>; 54 }; 55 56 CPU2: cpu@2 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a73"; 59 reg = <0x2>; 60 enable-method = "psci"; 61 next-level-cache = <&L2_0>; 62 }; 63 64 CPU3: cpu@3 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a73"; 67 reg = <0x3>; 68 enable-method = "psci"; 69 next-level-cache = <&L2_0>; 70 }; 71 72 L2_0: l2-cache { 73 compatible = "cache"; 74 cache-level = <2>; 75 }; 76 }; 77 78 memory@40000000 { 79 device_type = "memory"; 80 /* We expect the bootloader to fill in the size */ 81 reg = <0x0 0x40000000 0x0 0x0>; 82 }; 83 84 pmu { 85 compatible = "arm,cortex-a73-pmu"; 86 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 87 }; 88 89 psci { 90 compatible = "arm,psci-1.0"; 91 method = "smc"; 92 }; 93 94 reserved-memory { 95 #address-cells = <2>; 96 #size-cells = <2>; 97 ranges; 98 99 tz_region: tz@4a600000 { 100 reg = <0x0 0x4a600000 0x0 0x400000>; 101 no-map; 102 }; 103 }; 104 105 soc: soc@0 { 106 compatible = "simple-bus"; 107 #address-cells = <1>; 108 #size-cells = <1>; 109 ranges = <0 0 0 0xffffffff>; 110 111 tlmm: pinctrl@1000000 { 112 compatible = "qcom,ipq9574-tlmm"; 113 reg = <0x01000000 0x300000>; 114 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 115 gpio-controller; 116 #gpio-cells = <2>; 117 gpio-ranges = <&tlmm 0 0 65>; 118 interrupt-controller; 119 #interrupt-cells = <2>; 120 121 uart2_pins: uart2-state { 122 pins = "gpio34", "gpio35"; 123 function = "blsp2_uart"; 124 drive-strength = <8>; 125 bias-disable; 126 }; 127 }; 128 129 gcc: clock-controller@1800000 { 130 compatible = "qcom,ipq9574-gcc"; 131 reg = <0x01800000 0x80000>; 132 clocks = <&xo_board_clk>, 133 <&sleep_clk>, 134 <&bias_pll_ubi_nc_clk>, 135 <0>, 136 <0>, 137 <0>, 138 <0>, 139 <0>; 140 #clock-cells = <1>; 141 #reset-cells = <1>; 142 #power-domain-cells = <1>; 143 }; 144 145 sdhc_1: mmc@7804000 { 146 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; 147 reg = <0x07804000 0x1000>, <0x07805000 0x1000>; 148 reg-names = "hc", "cqhci"; 149 150 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 152 interrupt-names = "hc_irq", "pwr_irq"; 153 154 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 155 <&gcc GCC_SDCC1_APPS_CLK>, 156 <&xo_board_clk>; 157 clock-names = "iface", "core", "xo"; 158 non-removable; 159 status = "disabled"; 160 }; 161 162 blsp1_uart2: serial@78b1000 { 163 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 164 reg = <0x078b1000 0x200>; 165 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 166 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 167 <&gcc GCC_BLSP1_AHB_CLK>; 168 clock-names = "core", "iface"; 169 status = "disabled"; 170 }; 171 172 intc: interrupt-controller@b000000 { 173 compatible = "qcom,msm-qgic2"; 174 reg = <0x0b000000 0x1000>, /* GICD */ 175 <0x0b002000 0x1000>, /* GICC */ 176 <0x0b001000 0x1000>, /* GICH */ 177 <0x0b004000 0x1000>; /* GICV */ 178 #address-cells = <1>; 179 #size-cells = <1>; 180 interrupt-controller; 181 #interrupt-cells = <3>; 182 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 183 ranges = <0 0x0b00c000 0x3000>; 184 185 v2m0: v2m@0 { 186 compatible = "arm,gic-v2m-frame"; 187 reg = <0x00000000 0xffd>; 188 msi-controller; 189 }; 190 191 v2m1: v2m@1000 { 192 compatible = "arm,gic-v2m-frame"; 193 reg = <0x00001000 0xffd>; 194 msi-controller; 195 }; 196 197 v2m2: v2m@2000 { 198 compatible = "arm,gic-v2m-frame"; 199 reg = <0x00002000 0xffd>; 200 msi-controller; 201 }; 202 }; 203 204 timer@b120000 { 205 compatible = "arm,armv7-timer-mem"; 206 reg = <0x0b120000 0x1000>; 207 #address-cells = <1>; 208 #size-cells = <1>; 209 ranges; 210 211 frame@b120000 { 212 reg = <0x0b121000 0x1000>, 213 <0x0b122000 0x1000>; 214 frame-number = <0>; 215 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 217 }; 218 219 frame@b123000 { 220 reg = <0x0b123000 0x1000>; 221 frame-number = <1>; 222 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 223 status = "disabled"; 224 }; 225 226 frame@b124000 { 227 reg = <0x0b124000 0x1000>; 228 frame-number = <2>; 229 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 230 status = "disabled"; 231 }; 232 233 frame@b125000 { 234 reg = <0x0b125000 0x1000>; 235 frame-number = <3>; 236 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 237 status = "disabled"; 238 }; 239 240 frame@b126000 { 241 reg = <0x0b126000 0x1000>; 242 frame-number = <4>; 243 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 244 status = "disabled"; 245 }; 246 247 frame@b127000 { 248 reg = <0x0b127000 0x1000>; 249 frame-number = <5>; 250 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 251 status = "disabled"; 252 }; 253 254 frame@b128000 { 255 reg = <0x0b128000 0x1000>; 256 frame-number = <6>; 257 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 258 status = "disabled"; 259 }; 260 }; 261 }; 262 263 timer { 264 compatible = "arm,armv8-timer"; 265 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 266 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 267 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 268 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 269 }; 270}; 271