1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ9574 SoC device tree source 4 * 5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 6 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 7 */ 8 9#include <dt-bindings/clock/qcom,apss-ipq.h> 10#include <dt-bindings/clock/qcom,ipq9574-gcc.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/reset/qcom,ipq9574-gcc.h> 13 14/ { 15 interrupt-parent = <&intc>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 clocks { 20 sleep_clk: sleep-clk { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 }; 24 25 xo_board_clk: xo-board-clk { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 }; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 CPU0: cpu@0 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a73"; 38 reg = <0x0>; 39 enable-method = "psci"; 40 next-level-cache = <&L2_0>; 41 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 42 clock-names = "cpu"; 43 operating-points-v2 = <&cpu_opp_table>; 44 cpu-supply = <&ipq9574_s1>; 45 }; 46 47 CPU1: cpu@1 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a73"; 50 reg = <0x1>; 51 enable-method = "psci"; 52 next-level-cache = <&L2_0>; 53 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 54 clock-names = "cpu"; 55 operating-points-v2 = <&cpu_opp_table>; 56 cpu-supply = <&ipq9574_s1>; 57 }; 58 59 CPU2: cpu@2 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a73"; 62 reg = <0x2>; 63 enable-method = "psci"; 64 next-level-cache = <&L2_0>; 65 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 66 clock-names = "cpu"; 67 operating-points-v2 = <&cpu_opp_table>; 68 cpu-supply = <&ipq9574_s1>; 69 }; 70 71 CPU3: cpu@3 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a73"; 74 reg = <0x3>; 75 enable-method = "psci"; 76 next-level-cache = <&L2_0>; 77 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 78 clock-names = "cpu"; 79 operating-points-v2 = <&cpu_opp_table>; 80 cpu-supply = <&ipq9574_s1>; 81 }; 82 83 L2_0: l2-cache { 84 compatible = "cache"; 85 cache-level = <2>; 86 }; 87 }; 88 89 firmware { 90 scm { 91 compatible = "qcom,scm-ipq9574", "qcom,scm"; 92 qcom,dload-mode = <&tcsr 0x6100>; 93 }; 94 }; 95 96 memory@40000000 { 97 device_type = "memory"; 98 /* We expect the bootloader to fill in the size */ 99 reg = <0x0 0x40000000 0x0 0x0>; 100 }; 101 102 cpu_opp_table: opp-table-cpu { 103 compatible = "operating-points-v2"; 104 opp-shared; 105 106 opp-936000000 { 107 opp-hz = /bits/ 64 <936000000>; 108 opp-microvolt = <725000>; 109 clock-latency-ns = <200000>; 110 }; 111 112 opp-1104000000 { 113 opp-hz = /bits/ 64 <1104000000>; 114 opp-microvolt = <787500>; 115 clock-latency-ns = <200000>; 116 }; 117 118 opp-1416000000 { 119 opp-hz = /bits/ 64 <1416000000>; 120 opp-microvolt = <862500>; 121 clock-latency-ns = <200000>; 122 }; 123 124 opp-1488000000 { 125 opp-hz = /bits/ 64 <1488000000>; 126 opp-microvolt = <925000>; 127 clock-latency-ns = <200000>; 128 }; 129 130 opp-1800000000 { 131 opp-hz = /bits/ 64 <1800000000>; 132 opp-microvolt = <987500>; 133 clock-latency-ns = <200000>; 134 }; 135 136 opp-2208000000 { 137 opp-hz = /bits/ 64 <2208000000>; 138 opp-microvolt = <1062500>; 139 clock-latency-ns = <200000>; 140 }; 141 }; 142 143 pmu { 144 compatible = "arm,cortex-a73-pmu"; 145 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 146 }; 147 148 psci { 149 compatible = "arm,psci-1.0"; 150 method = "smc"; 151 }; 152 153 reserved-memory { 154 #address-cells = <2>; 155 #size-cells = <2>; 156 ranges; 157 158 tz_region: tz@4a600000 { 159 reg = <0x0 0x4a600000 0x0 0x400000>; 160 no-map; 161 }; 162 163 smem@4aa00000 { 164 compatible = "qcom,smem"; 165 reg = <0x0 0x4aa00000 0x0 0x00100000>; 166 hwlocks = <&tcsr_mutex 0>; 167 no-map; 168 }; 169 }; 170 171 rpm-glink { 172 compatible = "qcom,glink-rpm"; 173 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 174 qcom,rpm-msg-ram = <&rpm_msg_ram>; 175 mboxes = <&apcs_glb 0>; 176 177 rpm_requests: rpm-requests { 178 compatible = "qcom,rpm-ipq9574"; 179 qcom,glink-channels = "rpm_requests"; 180 }; 181 }; 182 183 soc: soc@0 { 184 compatible = "simple-bus"; 185 #address-cells = <1>; 186 #size-cells = <1>; 187 ranges = <0 0 0 0xffffffff>; 188 189 rpm_msg_ram: sram@60000 { 190 compatible = "qcom,rpm-msg-ram"; 191 reg = <0x00060000 0x6000>; 192 }; 193 194 rng: rng@e3000 { 195 compatible = "qcom,prng-ee"; 196 reg = <0x000e3000 0x1000>; 197 clocks = <&gcc GCC_PRNG_AHB_CLK>; 198 clock-names = "core"; 199 }; 200 201 qfprom: efuse@a4000 { 202 compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; 203 reg = <0x000a4000 0x5a1>; 204 #address-cells = <1>; 205 #size-cells = <1>; 206 }; 207 208 tlmm: pinctrl@1000000 { 209 compatible = "qcom,ipq9574-tlmm"; 210 reg = <0x01000000 0x300000>; 211 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 212 gpio-controller; 213 #gpio-cells = <2>; 214 gpio-ranges = <&tlmm 0 0 65>; 215 interrupt-controller; 216 #interrupt-cells = <2>; 217 218 uart2_pins: uart2-state { 219 pins = "gpio34", "gpio35"; 220 function = "blsp2_uart"; 221 drive-strength = <8>; 222 bias-disable; 223 }; 224 }; 225 226 gcc: clock-controller@1800000 { 227 compatible = "qcom,ipq9574-gcc"; 228 reg = <0x01800000 0x80000>; 229 clocks = <&xo_board_clk>, 230 <&sleep_clk>, 231 <0>, 232 <0>, 233 <0>, 234 <0>, 235 <0>, 236 <0>; 237 #clock-cells = <1>; 238 #reset-cells = <1>; 239 #power-domain-cells = <1>; 240 }; 241 242 tcsr_mutex: hwlock@1905000 { 243 compatible = "qcom,tcsr-mutex"; 244 reg = <0x01905000 0x20000>; 245 #hwlock-cells = <1>; 246 }; 247 248 tcsr: syscon@1937000 { 249 compatible = "qcom,tcsr-ipq9574", "syscon"; 250 reg = <0x01937000 0x21000>; 251 }; 252 253 sdhc_1: mmc@7804000 { 254 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; 255 reg = <0x07804000 0x1000>, <0x07805000 0x1000>; 256 reg-names = "hc", "cqhci"; 257 258 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 260 interrupt-names = "hc_irq", "pwr_irq"; 261 262 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 263 <&gcc GCC_SDCC1_APPS_CLK>, 264 <&xo_board_clk>; 265 clock-names = "iface", "core", "xo"; 266 non-removable; 267 status = "disabled"; 268 }; 269 270 blsp_dma: dma-controller@7884000 { 271 compatible = "qcom,bam-v1.7.0"; 272 reg = <0x07884000 0x2b000>; 273 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 274 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 275 clock-names = "bam_clk"; 276 #dma-cells = <1>; 277 qcom,ee = <0>; 278 }; 279 280 blsp1_uart0: serial@78af000 { 281 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 282 reg = <0x078af000 0x200>; 283 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 285 <&gcc GCC_BLSP1_AHB_CLK>; 286 clock-names = "core", "iface"; 287 status = "disabled"; 288 }; 289 290 blsp1_uart1: serial@78b0000 { 291 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 292 reg = <0x078b0000 0x200>; 293 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 295 <&gcc GCC_BLSP1_AHB_CLK>; 296 clock-names = "core", "iface"; 297 status = "disabled"; 298 }; 299 300 blsp1_uart2: serial@78b1000 { 301 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 302 reg = <0x078b1000 0x200>; 303 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 305 <&gcc GCC_BLSP1_AHB_CLK>; 306 clock-names = "core", "iface"; 307 status = "disabled"; 308 }; 309 310 blsp1_uart3: serial@78b2000 { 311 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 312 reg = <0x078b2000 0x200>; 313 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, 315 <&gcc GCC_BLSP1_AHB_CLK>; 316 clock-names = "core", "iface"; 317 status = "disabled"; 318 }; 319 320 blsp1_uart4: serial@78b3000 { 321 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 322 reg = <0x078b3000 0x200>; 323 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 325 <&gcc GCC_BLSP1_AHB_CLK>; 326 clock-names = "core", "iface"; 327 status = "disabled"; 328 }; 329 330 blsp1_uart5: serial@78b4000 { 331 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 332 reg = <0x078b4000 0x200>; 333 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>, 335 <&gcc GCC_BLSP1_AHB_CLK>; 336 clock-names = "core", "iface"; 337 status = "disabled"; 338 }; 339 340 blsp1_spi0: spi@78b5000 { 341 compatible = "qcom,spi-qup-v2.2.1"; 342 reg = <0x078b5000 0x600>; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 347 <&gcc GCC_BLSP1_AHB_CLK>; 348 clock-names = "core", "iface"; 349 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 350 dma-names = "tx", "rx"; 351 status = "disabled"; 352 }; 353 354 blsp1_i2c1: i2c@78b6000 { 355 compatible = "qcom,i2c-qup-v2.2.1"; 356 reg = <0x078b6000 0x600>; 357 #address-cells = <1>; 358 #size-cells = <0>; 359 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 361 <&gcc GCC_BLSP1_AHB_CLK>; 362 clock-names = "core", "iface"; 363 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 364 dma-names = "tx", "rx"; 365 status = "disabled"; 366 }; 367 368 blsp1_spi1: spi@78b6000 { 369 compatible = "qcom,spi-qup-v2.2.1"; 370 reg = <0x078b6000 0x600>; 371 #address-cells = <1>; 372 #size-cells = <0>; 373 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 375 <&gcc GCC_BLSP1_AHB_CLK>; 376 clock-names = "core", "iface"; 377 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 378 dma-names = "tx", "rx"; 379 status = "disabled"; 380 }; 381 382 blsp1_i2c2: i2c@78b7000 { 383 compatible = "qcom,i2c-qup-v2.2.1"; 384 reg = <0x078b7000 0x600>; 385 #address-cells = <1>; 386 #size-cells = <0>; 387 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 388 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 389 <&gcc GCC_BLSP1_AHB_CLK>; 390 clock-names = "core", "iface"; 391 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 392 dma-names = "tx", "rx"; 393 status = "disabled"; 394 }; 395 396 blsp1_spi2: spi@78b7000 { 397 compatible = "qcom,spi-qup-v2.2.1"; 398 reg = <0x078b7000 0x600>; 399 #address-cells = <1>; 400 #size-cells = <0>; 401 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 403 <&gcc GCC_BLSP1_AHB_CLK>; 404 clock-names = "core", "iface"; 405 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 406 dma-names = "tx", "rx"; 407 status = "disabled"; 408 }; 409 410 blsp1_i2c3: i2c@78b8000 { 411 compatible = "qcom,i2c-qup-v2.2.1"; 412 reg = <0x078b8000 0x600>; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 416 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 417 <&gcc GCC_BLSP1_AHB_CLK>; 418 clock-names = "core", "iface"; 419 dmas = <&blsp_dma 18>, <&blsp_dma 19>; 420 dma-names = "tx", "rx"; 421 status = "disabled"; 422 }; 423 424 blsp1_spi3: spi@78b8000 { 425 compatible = "qcom,spi-qup-v2.2.1"; 426 reg = <0x078b8000 0x600>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 430 spi-max-frequency = <50000000>; 431 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 432 <&gcc GCC_BLSP1_AHB_CLK>; 433 clock-names = "core", "iface"; 434 dmas = <&blsp_dma 18>, <&blsp_dma 19>; 435 dma-names = "tx", "rx"; 436 status = "disabled"; 437 }; 438 439 blsp1_i2c4: i2c@78b9000 { 440 compatible = "qcom,i2c-qup-v2.2.1"; 441 reg = <0x078b9000 0x600>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 446 <&gcc GCC_BLSP1_AHB_CLK>; 447 clock-names = "core", "iface"; 448 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 449 dma-names = "tx", "rx"; 450 status = "disabled"; 451 }; 452 453 blsp1_spi4: spi@78b9000 { 454 compatible = "qcom,spi-qup-v2.2.1"; 455 reg = <0x078b9000 0x600>; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 460 <&gcc GCC_BLSP1_AHB_CLK>; 461 clock-names = "core", "iface"; 462 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 463 dma-names = "tx", "rx"; 464 status = "disabled"; 465 }; 466 467 intc: interrupt-controller@b000000 { 468 compatible = "qcom,msm-qgic2"; 469 reg = <0x0b000000 0x1000>, /* GICD */ 470 <0x0b002000 0x2000>, /* GICC */ 471 <0x0b001000 0x1000>, /* GICH */ 472 <0x0b004000 0x2000>; /* GICV */ 473 #address-cells = <1>; 474 #size-cells = <1>; 475 interrupt-controller; 476 #interrupt-cells = <3>; 477 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 478 ranges = <0 0x0b00c000 0x3000>; 479 480 v2m0: v2m@0 { 481 compatible = "arm,gic-v2m-frame"; 482 reg = <0x00000000 0xffd>; 483 msi-controller; 484 }; 485 486 v2m1: v2m@1000 { 487 compatible = "arm,gic-v2m-frame"; 488 reg = <0x00001000 0xffd>; 489 msi-controller; 490 }; 491 492 v2m2: v2m@2000 { 493 compatible = "arm,gic-v2m-frame"; 494 reg = <0x00002000 0xffd>; 495 msi-controller; 496 }; 497 }; 498 499 watchdog: watchdog@b017000 { 500 compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt"; 501 reg = <0x0b017000 0x1000>; 502 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 503 clocks = <&sleep_clk>; 504 timeout-sec = <30>; 505 }; 506 507 apcs_glb: mailbox@b111000 { 508 compatible = "qcom,ipq9574-apcs-apps-global", 509 "qcom,ipq6018-apcs-apps-global"; 510 reg = <0x0b111000 0x1000>; 511 #clock-cells = <1>; 512 clocks = <&a73pll>, <&xo_board_clk>; 513 clock-names = "pll", "xo"; 514 #mbox-cells = <1>; 515 }; 516 517 a73pll: clock@b116000 { 518 compatible = "qcom,ipq9574-a73pll"; 519 reg = <0x0b116000 0x40>; 520 #clock-cells = <0>; 521 clocks = <&xo_board_clk>; 522 clock-names = "xo"; 523 }; 524 525 timer@b120000 { 526 compatible = "arm,armv7-timer-mem"; 527 reg = <0x0b120000 0x1000>; 528 #address-cells = <1>; 529 #size-cells = <1>; 530 ranges; 531 532 frame@b120000 { 533 reg = <0x0b121000 0x1000>, 534 <0x0b122000 0x1000>; 535 frame-number = <0>; 536 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 538 }; 539 540 frame@b123000 { 541 reg = <0x0b123000 0x1000>; 542 frame-number = <1>; 543 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 544 status = "disabled"; 545 }; 546 547 frame@b124000 { 548 reg = <0x0b124000 0x1000>; 549 frame-number = <2>; 550 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 551 status = "disabled"; 552 }; 553 554 frame@b125000 { 555 reg = <0x0b125000 0x1000>; 556 frame-number = <3>; 557 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 558 status = "disabled"; 559 }; 560 561 frame@b126000 { 562 reg = <0x0b126000 0x1000>; 563 frame-number = <4>; 564 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 565 status = "disabled"; 566 }; 567 568 frame@b127000 { 569 reg = <0x0b127000 0x1000>; 570 frame-number = <5>; 571 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 572 status = "disabled"; 573 }; 574 575 frame@b128000 { 576 reg = <0x0b128000 0x1000>; 577 frame-number = <6>; 578 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 579 status = "disabled"; 580 }; 581 }; 582 }; 583 584 timer { 585 compatible = "arm,armv8-timer"; 586 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 587 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 588 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 589 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 590 }; 591}; 592