1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ6018 SoC device tree source 4 * 5 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,gcc-ipq6018.h> 10#include <dt-bindings/reset/qcom,gcc-ipq6018.h> 11#include <dt-bindings/clock/qcom,apss-ipq.h> 12 13/ { 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&intc>; 17 18 clocks { 19 sleep_clk: sleep-clk { 20 compatible = "fixed-clock"; 21 clock-frequency = <32000>; 22 #clock-cells = <0>; 23 }; 24 25 xo: xo { 26 compatible = "fixed-clock"; 27 clock-frequency = <24000000>; 28 #clock-cells = <0>; 29 }; 30 }; 31 32 cpus: cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 CPU0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a53"; 39 reg = <0x0>; 40 enable-method = "psci"; 41 next-level-cache = <&L2_0>; 42 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 43 clock-names = "cpu"; 44 operating-points-v2 = <&cpu_opp_table>; 45 cpu-supply = <&ipq6018_s2>; 46 }; 47 48 CPU1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53"; 51 enable-method = "psci"; 52 reg = <0x1>; 53 next-level-cache = <&L2_0>; 54 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 55 clock-names = "cpu"; 56 operating-points-v2 = <&cpu_opp_table>; 57 cpu-supply = <&ipq6018_s2>; 58 }; 59 60 CPU2: cpu@2 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 enable-method = "psci"; 64 reg = <0x2>; 65 next-level-cache = <&L2_0>; 66 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 67 clock-names = "cpu"; 68 operating-points-v2 = <&cpu_opp_table>; 69 cpu-supply = <&ipq6018_s2>; 70 }; 71 72 CPU3: cpu@3 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a53"; 75 enable-method = "psci"; 76 reg = <0x3>; 77 next-level-cache = <&L2_0>; 78 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 79 clock-names = "cpu"; 80 operating-points-v2 = <&cpu_opp_table>; 81 cpu-supply = <&ipq6018_s2>; 82 }; 83 84 L2_0: l2-cache { 85 compatible = "cache"; 86 cache-level = <0x2>; 87 }; 88 }; 89 90 cpu_opp_table: cpu_opp_table { 91 compatible = "operating-points-v2"; 92 opp-shared; 93 94 opp-864000000 { 95 opp-hz = /bits/ 64 <864000000>; 96 opp-microvolt = <725000>; 97 clock-latency-ns = <200000>; 98 }; 99 opp-1056000000 { 100 opp-hz = /bits/ 64 <1056000000>; 101 opp-microvolt = <787500>; 102 clock-latency-ns = <200000>; 103 }; 104 opp-1320000000 { 105 opp-hz = /bits/ 64 <1320000000>; 106 opp-microvolt = <862500>; 107 clock-latency-ns = <200000>; 108 }; 109 opp-1440000000 { 110 opp-hz = /bits/ 64 <1440000000>; 111 opp-microvolt = <925000>; 112 clock-latency-ns = <200000>; 113 }; 114 opp-1608000000 { 115 opp-hz = /bits/ 64 <1608000000>; 116 opp-microvolt = <987500>; 117 clock-latency-ns = <200000>; 118 }; 119 opp-1800000000 { 120 opp-hz = /bits/ 64 <1800000000>; 121 opp-microvolt = <1062500>; 122 clock-latency-ns = <200000>; 123 }; 124 }; 125 126 firmware { 127 scm { 128 compatible = "qcom,scm"; 129 }; 130 }; 131 132 tcsr_mutex: hwlock { 133 compatible = "qcom,tcsr-mutex"; 134 syscon = <&tcsr_mutex_regs 0 0x80>; 135 #hwlock-cells = <1>; 136 }; 137 138 pmuv8: pmu { 139 compatible = "arm,cortex-a53-pmu"; 140 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 141 IRQ_TYPE_LEVEL_HIGH)>; 142 }; 143 144 psci: psci { 145 compatible = "arm,psci-1.0"; 146 method = "smc"; 147 }; 148 149 reserved-memory { 150 #address-cells = <2>; 151 #size-cells = <2>; 152 ranges; 153 154 rpm_msg_ram: memory@0x60000 { 155 reg = <0x0 0x60000 0x0 0x6000>; 156 no-map; 157 }; 158 159 tz: tz@48500000 { 160 reg = <0x0 0x48500000 0x0 0x00200000>; 161 no-map; 162 }; 163 164 smem_region: memory@4aa00000 { 165 reg = <0x0 0x4aa00000 0x0 0x00100000>; 166 no-map; 167 }; 168 169 q6_region: memory@4ab00000 { 170 reg = <0x0 0x4ab00000 0x0 0x02800000>; 171 no-map; 172 }; 173 }; 174 175 smem { 176 compatible = "qcom,smem"; 177 memory-region = <&smem_region>; 178 hwlocks = <&tcsr_mutex 0>; 179 }; 180 181 soc: soc { 182 #address-cells = <2>; 183 #size-cells = <2>; 184 ranges = <0 0 0 0 0x0 0xffffffff>; 185 dma-ranges; 186 compatible = "simple-bus"; 187 188 prng: qrng@e1000 { 189 compatible = "qcom,prng-ee"; 190 reg = <0x0 0xe3000 0x0 0x1000>; 191 clocks = <&gcc GCC_PRNG_AHB_CLK>; 192 clock-names = "core"; 193 }; 194 195 cryptobam: dma@704000 { 196 compatible = "qcom,bam-v1.7.0"; 197 reg = <0x0 0x00704000 0x0 0x20000>; 198 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 200 clock-names = "bam_clk"; 201 #dma-cells = <1>; 202 qcom,ee = <1>; 203 qcom,controlled-remotely = <1>; 204 qcom,config-pipe-trust-reg = <0>; 205 }; 206 207 crypto: crypto@73a000 { 208 compatible = "qcom,crypto-v5.1"; 209 reg = <0x0 0x0073a000 0x0 0x6000>; 210 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 211 <&gcc GCC_CRYPTO_AXI_CLK>, 212 <&gcc GCC_CRYPTO_CLK>; 213 clock-names = "iface", "bus", "core"; 214 dmas = <&cryptobam 2>, <&cryptobam 3>; 215 dma-names = "rx", "tx"; 216 }; 217 218 tlmm: pinctrl@1000000 { 219 compatible = "qcom,ipq6018-pinctrl"; 220 reg = <0x0 0x01000000 0x0 0x300000>; 221 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 222 gpio-controller; 223 #gpio-cells = <2>; 224 gpio-ranges = <&tlmm 0 80>; 225 interrupt-controller; 226 #interrupt-cells = <2>; 227 228 serial_3_pins: serial3-pinmux { 229 pins = "gpio44", "gpio45"; 230 function = "blsp2_uart"; 231 drive-strength = <8>; 232 bias-pull-down; 233 }; 234 }; 235 236 gcc: gcc@1800000 { 237 compatible = "qcom,gcc-ipq6018"; 238 reg = <0x0 0x01800000 0x0 0x80000>; 239 clocks = <&xo>, <&sleep_clk>; 240 clock-names = "xo", "sleep_clk"; 241 #clock-cells = <1>; 242 #reset-cells = <1>; 243 }; 244 245 tcsr_mutex_regs: syscon@1905000 { 246 compatible = "syscon"; 247 reg = <0x0 0x01905000 0x0 0x8000>; 248 }; 249 250 tcsr_q6: syscon@1945000 { 251 compatible = "syscon"; 252 reg = <0x0 0x01945000 0x0 0xe000>; 253 }; 254 255 blsp_dma: dma@7884000 { 256 compatible = "qcom,bam-v1.7.0"; 257 reg = <0x0 0x07884000 0x0 0x2b000>; 258 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 260 clock-names = "bam_clk"; 261 #dma-cells = <1>; 262 qcom,ee = <0>; 263 }; 264 265 blsp1_uart3: serial@78b1000 { 266 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 267 reg = <0x0 0x078b1000 0x0 0x200>; 268 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 269 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 270 <&gcc GCC_BLSP1_AHB_CLK>; 271 clock-names = "core", "iface"; 272 status = "disabled"; 273 }; 274 275 spi_0: spi@78b5000 { 276 compatible = "qcom,spi-qup-v2.2.1"; 277 #address-cells = <1>; 278 #size-cells = <0>; 279 reg = <0x0 0x078b5000 0x0 0x600>; 280 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 281 spi-max-frequency = <50000000>; 282 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 283 <&gcc GCC_BLSP1_AHB_CLK>; 284 clock-names = "core", "iface"; 285 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 286 dma-names = "tx", "rx"; 287 status = "disabled"; 288 }; 289 290 spi_1: spi@78b6000 { 291 compatible = "qcom,spi-qup-v2.2.1"; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 reg = <0x0 0x078b6000 0x0 0x600>; 295 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 296 spi-max-frequency = <50000000>; 297 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 298 <&gcc GCC_BLSP1_AHB_CLK>; 299 clock-names = "core", "iface"; 300 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 301 dma-names = "tx", "rx"; 302 status = "disabled"; 303 }; 304 305 i2c_0: i2c@78b6000 { 306 compatible = "qcom,i2c-qup-v2.2.1"; 307 #address-cells = <1>; 308 #size-cells = <0>; 309 reg = <0x0 0x078b6000 0x0 0x600>; 310 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 312 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 313 clock-names = "iface", "core"; 314 clock-frequency = <400000>; 315 dmas = <&blsp_dma 15>, <&blsp_dma 14>; 316 dma-names = "rx", "tx"; 317 status = "disabled"; 318 }; 319 320 i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */ 321 compatible = "qcom,i2c-qup-v2.2.1"; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 reg = <0x0 0x078b7000 0x0 0x600>; 325 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 327 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 328 clock-names = "iface", "core"; 329 clock-frequency = <400000>; 330 dmas = <&blsp_dma 17>, <&blsp_dma 16>; 331 dma-names = "rx", "tx"; 332 status = "disabled"; 333 }; 334 335 intc: interrupt-controller@b000000 { 336 compatible = "qcom,msm-qgic2"; 337 interrupt-controller; 338 #interrupt-cells = <0x3>; 339 reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ 340 <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ 341 <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ 342 <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ 343 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 344 }; 345 346 watchdog@b017000 { 347 compatible = "qcom,kpss-wdt"; 348 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 349 reg = <0x0 0x0b017000 0x0 0x40>; 350 clocks = <&sleep_clk>; 351 timeout-sec = <10>; 352 }; 353 354 apcs_glb: mailbox@b111000 { 355 compatible = "qcom,ipq6018-apcs-apps-global"; 356 reg = <0x0 0x0b111000 0x0 0x1000>; 357 #clock-cells = <1>; 358 clocks = <&a53pll>, <&xo>; 359 clock-names = "pll", "xo"; 360 #mbox-cells = <1>; 361 }; 362 363 a53pll: clock@b116000 { 364 compatible = "qcom,ipq6018-a53pll"; 365 reg = <0x0 0x0b116000 0x0 0x40>; 366 #clock-cells = <0>; 367 clocks = <&xo>; 368 clock-names = "xo"; 369 }; 370 371 timer { 372 compatible = "arm,armv8-timer"; 373 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 374 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 375 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 376 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 377 }; 378 379 timer@b120000 { 380 #address-cells = <2>; 381 #size-cells = <2>; 382 ranges; 383 compatible = "arm,armv7-timer-mem"; 384 reg = <0x0 0x0b120000 0x0 0x1000>; 385 clock-frequency = <19200000>; 386 387 frame@b120000 { 388 frame-number = <0>; 389 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 391 reg = <0x0 0x0b121000 0x0 0x1000>, 392 <0x0 0x0b122000 0x0 0x1000>; 393 }; 394 395 frame@b123000 { 396 frame-number = <1>; 397 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 398 reg = <0x0 0xb123000 0x0 0x1000>; 399 status = "disabled"; 400 }; 401 402 frame@b124000 { 403 frame-number = <2>; 404 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 405 reg = <0x0 0x0b124000 0x0 0x1000>; 406 status = "disabled"; 407 }; 408 409 frame@b125000 { 410 frame-number = <3>; 411 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 412 reg = <0x0 0x0b125000 0x0 0x1000>; 413 status = "disabled"; 414 }; 415 416 frame@b126000 { 417 frame-number = <4>; 418 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 419 reg = <0x0 0x0b126000 0x0 0x1000>; 420 status = "disabled"; 421 }; 422 423 frame@b127000 { 424 frame-number = <5>; 425 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 426 reg = <0x0 0x0b127000 0x0 0x1000>; 427 status = "disabled"; 428 }; 429 430 frame@b128000 { 431 frame-number = <6>; 432 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 433 reg = <0x0 0x0b128000 0x0 0x1000>; 434 status = "disabled"; 435 }; 436 }; 437 438 q6v5_wcss: remoteproc@cd00000 { 439 compatible = "qcom,ipq8074-wcss-pil"; 440 reg = <0x0 0x0cd00000 0x0 0x4040>, 441 <0x0 0x004ab000 0x0 0x20>; 442 reg-names = "qdsp6", 443 "rmb"; 444 interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, 445 <&wcss_smp2p_in 0 0>, 446 <&wcss_smp2p_in 1 0>, 447 <&wcss_smp2p_in 2 0>, 448 <&wcss_smp2p_in 3 0>; 449 interrupt-names = "wdog", 450 "fatal", 451 "ready", 452 "handover", 453 "stop-ack"; 454 455 resets = <&gcc GCC_WCSSAON_RESET>, 456 <&gcc GCC_WCSS_BCR>, 457 <&gcc GCC_WCSS_Q6_BCR>; 458 459 reset-names = "wcss_aon_reset", 460 "wcss_reset", 461 "wcss_q6_reset"; 462 463 clocks = <&gcc GCC_PRNG_AHB_CLK>; 464 clock-names = "prng"; 465 466 qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>; 467 468 qcom,smem-states = <&wcss_smp2p_out 0>, 469 <&wcss_smp2p_out 1>; 470 qcom,smem-state-names = "shutdown", 471 "stop"; 472 473 memory-region = <&q6_region>; 474 475 glink-edge { 476 interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>; 477 qcom,remote-pid = <1>; 478 mboxes = <&apcs_glb 8>; 479 480 qrtr_requests { 481 qcom,glink-channels = "IPCRTR"; 482 }; 483 }; 484 }; 485 486 }; 487 488 wcss: wcss-smp2p { 489 compatible = "qcom,smp2p"; 490 qcom,smem = <435>, <428>; 491 492 interrupt-parent = <&intc>; 493 interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>; 494 495 mboxes = <&apcs_glb 9>; 496 497 qcom,local-pid = <0>; 498 qcom,remote-pid = <1>; 499 500 wcss_smp2p_out: master-kernel { 501 qcom,entry-name = "master-kernel"; 502 #qcom,smem-state-cells = <1>; 503 }; 504 505 wcss_smp2p_in: slave-kernel { 506 qcom,entry-name = "slave-kernel"; 507 interrupt-controller; 508 #interrupt-cells = <2>; 509 }; 510 }; 511 512 rpm-glink { 513 compatible = "qcom,glink-rpm"; 514 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 515 qcom,rpm-msg-ram = <&rpm_msg_ram>; 516 mboxes = <&apcs_glb 0>; 517 518 rpm_requests: glink-channel { 519 compatible = "qcom,rpm-ipq6018"; 520 qcom,glink-channels = "rpm_requests"; 521 522 regulators { 523 compatible = "qcom,rpm-mp5496-regulators"; 524 525 ipq6018_s2: s2 { 526 regulator-min-microvolt = <725000>; 527 regulator-max-microvolt = <1062500>; 528 regulator-always-on; 529 }; 530 }; 531 }; 532 }; 533}; 534