1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ6018 SoC device tree source 4 * 5 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,gcc-ipq6018.h> 10#include <dt-bindings/reset/qcom,gcc-ipq6018.h> 11#include <dt-bindings/clock/qcom,apss-ipq.h> 12 13/ { 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&intc>; 17 18 clocks { 19 sleep_clk: sleep-clk { 20 compatible = "fixed-clock"; 21 clock-frequency = <32000>; 22 #clock-cells = <0>; 23 }; 24 25 xo: xo { 26 compatible = "fixed-clock"; 27 clock-frequency = <24000000>; 28 #clock-cells = <0>; 29 }; 30 }; 31 32 cpus: cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 CPU0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a53"; 39 reg = <0x0>; 40 enable-method = "psci"; 41 next-level-cache = <&L2_0>; 42 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 43 clock-names = "cpu"; 44 operating-points-v2 = <&cpu_opp_table>; 45 cpu-supply = <&ipq6018_s2>; 46 }; 47 48 CPU1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53"; 51 enable-method = "psci"; 52 reg = <0x1>; 53 next-level-cache = <&L2_0>; 54 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 55 clock-names = "cpu"; 56 operating-points-v2 = <&cpu_opp_table>; 57 cpu-supply = <&ipq6018_s2>; 58 }; 59 60 CPU2: cpu@2 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 enable-method = "psci"; 64 reg = <0x2>; 65 next-level-cache = <&L2_0>; 66 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 67 clock-names = "cpu"; 68 operating-points-v2 = <&cpu_opp_table>; 69 cpu-supply = <&ipq6018_s2>; 70 }; 71 72 CPU3: cpu@3 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a53"; 75 enable-method = "psci"; 76 reg = <0x3>; 77 next-level-cache = <&L2_0>; 78 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 79 clock-names = "cpu"; 80 operating-points-v2 = <&cpu_opp_table>; 81 cpu-supply = <&ipq6018_s2>; 82 }; 83 84 L2_0: l2-cache { 85 compatible = "cache"; 86 cache-level = <2>; 87 cache-unified; 88 }; 89 }; 90 91 firmware { 92 scm { 93 compatible = "qcom,scm-ipq6018", "qcom,scm"; 94 }; 95 }; 96 97 cpu_opp_table: opp-table-cpu { 98 compatible = "operating-points-v2"; 99 opp-shared; 100 101 opp-864000000 { 102 opp-hz = /bits/ 64 <864000000>; 103 opp-microvolt = <725000>; 104 clock-latency-ns = <200000>; 105 }; 106 107 opp-1056000000 { 108 opp-hz = /bits/ 64 <1056000000>; 109 opp-microvolt = <787500>; 110 clock-latency-ns = <200000>; 111 }; 112 113 opp-1320000000 { 114 opp-hz = /bits/ 64 <1320000000>; 115 opp-microvolt = <862500>; 116 clock-latency-ns = <200000>; 117 }; 118 119 opp-1440000000 { 120 opp-hz = /bits/ 64 <1440000000>; 121 opp-microvolt = <925000>; 122 clock-latency-ns = <200000>; 123 }; 124 125 opp-1608000000 { 126 opp-hz = /bits/ 64 <1608000000>; 127 opp-microvolt = <987500>; 128 clock-latency-ns = <200000>; 129 }; 130 131 opp-1800000000 { 132 opp-hz = /bits/ 64 <1800000000>; 133 opp-microvolt = <1062500>; 134 clock-latency-ns = <200000>; 135 }; 136 }; 137 138 pmuv8: pmu { 139 compatible = "arm,cortex-a53-pmu"; 140 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 141 }; 142 143 psci: psci { 144 compatible = "arm,psci-1.0"; 145 method = "smc"; 146 }; 147 148 reserved-memory { 149 #address-cells = <2>; 150 #size-cells = <2>; 151 ranges; 152 153 rpm_msg_ram: memory@60000 { 154 reg = <0x0 0x00060000 0x0 0x6000>; 155 no-map; 156 }; 157 158 tz: memory@4a600000 { 159 reg = <0x0 0x4a600000 0x0 0x00400000>; 160 no-map; 161 }; 162 163 smem_region: memory@4aa00000 { 164 reg = <0x0 0x4aa00000 0x0 0x00100000>; 165 no-map; 166 }; 167 168 q6_region: memory@4ab00000 { 169 reg = <0x0 0x4ab00000 0x0 0x05500000>; 170 no-map; 171 }; 172 }; 173 174 rpm-glink { 175 compatible = "qcom,glink-rpm"; 176 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 177 qcom,rpm-msg-ram = <&rpm_msg_ram>; 178 mboxes = <&apcs_glb 0>; 179 180 rpm_requests: rpm-requests { 181 compatible = "qcom,rpm-ipq6018"; 182 qcom,glink-channels = "rpm_requests"; 183 184 regulators { 185 compatible = "qcom,rpm-mp5496-regulators"; 186 187 ipq6018_s2: s2 { 188 regulator-min-microvolt = <725000>; 189 regulator-max-microvolt = <1062500>; 190 regulator-always-on; 191 }; 192 }; 193 }; 194 }; 195 196 smem { 197 compatible = "qcom,smem"; 198 memory-region = <&smem_region>; 199 hwlocks = <&tcsr_mutex 0>; 200 }; 201 202 soc: soc { 203 #address-cells = <2>; 204 #size-cells = <2>; 205 ranges = <0 0 0 0 0x0 0xffffffff>; 206 dma-ranges; 207 compatible = "simple-bus"; 208 209 qusb_phy_1: qusb@59000 { 210 compatible = "qcom,ipq6018-qusb2-phy"; 211 reg = <0x0 0x00059000 0x0 0x180>; 212 #phy-cells = <0>; 213 214 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 215 <&xo>; 216 clock-names = "cfg_ahb", "ref"; 217 218 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 219 status = "disabled"; 220 }; 221 222 ssphy_0: ssphy@78000 { 223 compatible = "qcom,ipq6018-qmp-usb3-phy"; 224 reg = <0x0 0x00078000 0x0 0x1c4>; 225 #address-cells = <2>; 226 #size-cells = <2>; 227 ranges; 228 229 clocks = <&gcc GCC_USB0_AUX_CLK>, 230 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>; 231 clock-names = "aux", "cfg_ahb", "ref"; 232 233 resets = <&gcc GCC_USB0_PHY_BCR>, 234 <&gcc GCC_USB3PHY_0_PHY_BCR>; 235 reset-names = "phy","common"; 236 status = "disabled"; 237 238 usb0_ssphy: phy@78200 { 239 reg = <0x0 0x00078200 0x0 0x130>, /* Tx */ 240 <0x0 0x00078400 0x0 0x200>, /* Rx */ 241 <0x0 0x00078800 0x0 0x1f8>, /* PCS */ 242 <0x0 0x00078600 0x0 0x044>; /* PCS misc */ 243 #phy-cells = <0>; 244 #clock-cells = <0>; 245 clocks = <&gcc GCC_USB0_PIPE_CLK>; 246 clock-names = "pipe0"; 247 clock-output-names = "gcc_usb0_pipe_clk_src"; 248 }; 249 }; 250 251 qusb_phy_0: qusb@79000 { 252 compatible = "qcom,ipq6018-qusb2-phy"; 253 reg = <0x0 0x00079000 0x0 0x180>; 254 #phy-cells = <0>; 255 256 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 257 <&xo>; 258 clock-names = "cfg_ahb", "ref"; 259 260 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 261 status = "disabled"; 262 }; 263 264 pcie_phy: phy@84000 { 265 compatible = "qcom,ipq6018-qmp-pcie-phy"; 266 reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */ 267 status = "disabled"; 268 #address-cells = <2>; 269 #size-cells = <2>; 270 ranges; 271 272 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 273 <&gcc GCC_PCIE0_AHB_CLK>; 274 clock-names = "aux", "cfg_ahb"; 275 276 resets = <&gcc GCC_PCIE0_PHY_BCR>, 277 <&gcc GCC_PCIE0PHY_PHY_BCR>; 278 reset-names = "phy", 279 "common"; 280 281 pcie_phy0: phy@84200 { 282 reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */ 283 <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */ 284 <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */ 285 <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */ 286 #phy-cells = <0>; 287 288 clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 289 clock-names = "pipe0"; 290 clock-output-names = "gcc_pcie0_pipe_clk_src"; 291 #clock-cells = <0>; 292 }; 293 }; 294 295 mdio: mdio@90000 { 296 #address-cells = <1>; 297 #size-cells = <0>; 298 compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio"; 299 reg = <0x0 0x00090000 0x0 0x64>; 300 clocks = <&gcc GCC_MDIO_AHB_CLK>; 301 clock-names = "gcc_mdio_ahb_clk"; 302 status = "disabled"; 303 }; 304 305 prng: qrng@e1000 { 306 compatible = "qcom,prng-ee"; 307 reg = <0x0 0x000e3000 0x0 0x1000>; 308 clocks = <&gcc GCC_PRNG_AHB_CLK>; 309 clock-names = "core"; 310 }; 311 312 cryptobam: dma-controller@704000 { 313 compatible = "qcom,bam-v1.7.0"; 314 reg = <0x0 0x00704000 0x0 0x20000>; 315 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 316 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 317 clock-names = "bam_clk"; 318 #dma-cells = <1>; 319 qcom,ee = <1>; 320 qcom,controlled-remotely; 321 }; 322 323 crypto: crypto@73a000 { 324 compatible = "qcom,crypto-v5.1"; 325 reg = <0x0 0x0073a000 0x0 0x6000>; 326 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 327 <&gcc GCC_CRYPTO_AXI_CLK>, 328 <&gcc GCC_CRYPTO_CLK>; 329 clock-names = "iface", "bus", "core"; 330 dmas = <&cryptobam 2>, <&cryptobam 3>; 331 dma-names = "rx", "tx"; 332 }; 333 334 tlmm: pinctrl@1000000 { 335 compatible = "qcom,ipq6018-pinctrl"; 336 reg = <0x0 0x01000000 0x0 0x300000>; 337 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 338 gpio-controller; 339 #gpio-cells = <2>; 340 gpio-ranges = <&tlmm 0 0 80>; 341 interrupt-controller; 342 #interrupt-cells = <2>; 343 344 serial_3_pins: serial3-state { 345 pins = "gpio44", "gpio45"; 346 function = "blsp2_uart"; 347 drive-strength = <8>; 348 bias-pull-down; 349 }; 350 351 qpic_pins: qpic-state { 352 pins = "gpio1", "gpio3", "gpio4", 353 "gpio5", "gpio6", "gpio7", 354 "gpio8", "gpio10", "gpio11", 355 "gpio12", "gpio13", "gpio14", 356 "gpio15", "gpio17"; 357 function = "qpic_pad"; 358 drive-strength = <8>; 359 bias-disable; 360 }; 361 }; 362 363 gcc: gcc@1800000 { 364 compatible = "qcom,gcc-ipq6018"; 365 reg = <0x0 0x01800000 0x0 0x80000>; 366 clocks = <&xo>, <&sleep_clk>; 367 clock-names = "xo", "sleep_clk"; 368 #clock-cells = <1>; 369 #reset-cells = <1>; 370 }; 371 372 tcsr_mutex: hwlock@1905000 { 373 compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex"; 374 reg = <0x0 0x01905000 0x0 0x1000>; 375 #hwlock-cells = <1>; 376 }; 377 378 tcsr: syscon@1937000 { 379 compatible = "qcom,tcsr-ipq6018", "syscon"; 380 reg = <0x0 0x01937000 0x0 0x21000>; 381 }; 382 383 usb2: usb@70f8800 { 384 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; 385 reg = <0x0 0x070f8800 0x0 0x400>; 386 #address-cells = <2>; 387 #size-cells = <2>; 388 ranges; 389 clocks = <&gcc GCC_USB1_MASTER_CLK>, 390 <&gcc GCC_USB1_SLEEP_CLK>, 391 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 392 clock-names = "core", 393 "sleep", 394 "mock_utmi"; 395 396 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, 397 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 398 assigned-clock-rates = <133330000>, 399 <24000000>; 400 resets = <&gcc GCC_USB1_BCR>; 401 status = "disabled"; 402 403 dwc_1: usb@7000000 { 404 compatible = "snps,dwc3"; 405 reg = <0x0 0x07000000 0x0 0xcd00>; 406 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 407 phys = <&qusb_phy_1>; 408 phy-names = "usb2-phy"; 409 tx-fifo-resize; 410 snps,is-utmi-l1-suspend; 411 snps,hird-threshold = /bits/ 8 <0x0>; 412 snps,dis_u2_susphy_quirk; 413 snps,dis_u3_susphy_quirk; 414 dr_mode = "host"; 415 }; 416 }; 417 418 blsp_dma: dma-controller@7884000 { 419 compatible = "qcom,bam-v1.7.0"; 420 reg = <0x0 0x07884000 0x0 0x2b000>; 421 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 423 clock-names = "bam_clk"; 424 #dma-cells = <1>; 425 qcom,ee = <0>; 426 }; 427 428 blsp1_uart3: serial@78b1000 { 429 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 430 reg = <0x0 0x078b1000 0x0 0x200>; 431 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 433 <&gcc GCC_BLSP1_AHB_CLK>; 434 clock-names = "core", "iface"; 435 status = "disabled"; 436 }; 437 438 blsp1_spi1: spi@78b5000 { 439 compatible = "qcom,spi-qup-v2.2.1"; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 reg = <0x0 0x078b5000 0x0 0x600>; 443 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 444 spi-max-frequency = <50000000>; 445 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 446 <&gcc GCC_BLSP1_AHB_CLK>; 447 clock-names = "core", "iface"; 448 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 449 dma-names = "tx", "rx"; 450 status = "disabled"; 451 }; 452 453 blsp1_spi2: spi@78b6000 { 454 compatible = "qcom,spi-qup-v2.2.1"; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 reg = <0x0 0x078b6000 0x0 0x600>; 458 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 459 spi-max-frequency = <50000000>; 460 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 461 <&gcc GCC_BLSP1_AHB_CLK>; 462 clock-names = "core", "iface"; 463 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 464 dma-names = "tx", "rx"; 465 status = "disabled"; 466 }; 467 468 blsp1_i2c2: i2c@78b6000 { 469 compatible = "qcom,i2c-qup-v2.2.1"; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 reg = <0x0 0x078b6000 0x0 0x600>; 473 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 475 <&gcc GCC_BLSP1_AHB_CLK>; 476 clock-names = "core", "iface"; 477 clock-frequency = <400000>; 478 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 479 dma-names = "tx", "rx"; 480 status = "disabled"; 481 }; 482 483 blsp1_i2c3: i2c@78b7000 { 484 compatible = "qcom,i2c-qup-v2.2.1"; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 reg = <0x0 0x078b7000 0x0 0x600>; 488 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 490 <&gcc GCC_BLSP1_AHB_CLK>; 491 clock-names = "core", "iface"; 492 clock-frequency = <400000>; 493 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 494 dma-names = "tx", "rx"; 495 status = "disabled"; 496 }; 497 498 qpic_bam: dma-controller@7984000 { 499 compatible = "qcom,bam-v1.7.0"; 500 reg = <0x0 0x07984000 0x0 0x1a000>; 501 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&gcc GCC_QPIC_AHB_CLK>; 503 clock-names = "bam_clk"; 504 #dma-cells = <1>; 505 qcom,ee = <0>; 506 status = "disabled"; 507 }; 508 509 qpic_nand: nand-controller@79b0000 { 510 compatible = "qcom,ipq6018-nand"; 511 reg = <0x0 0x079b0000 0x0 0x10000>; 512 #address-cells = <1>; 513 #size-cells = <0>; 514 clocks = <&gcc GCC_QPIC_CLK>, 515 <&gcc GCC_QPIC_AHB_CLK>; 516 clock-names = "core", "aon"; 517 518 dmas = <&qpic_bam 0>, 519 <&qpic_bam 1>, 520 <&qpic_bam 2>; 521 dma-names = "tx", "rx", "cmd"; 522 pinctrl-0 = <&qpic_pins>; 523 pinctrl-names = "default"; 524 status = "disabled"; 525 }; 526 527 usb3: usb@8af8800 { 528 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; 529 reg = <0x0 0x08af8800 0x0 0x400>; 530 #address-cells = <2>; 531 #size-cells = <2>; 532 ranges; 533 534 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 535 <&gcc GCC_USB0_MASTER_CLK>, 536 <&gcc GCC_USB0_SLEEP_CLK>, 537 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 538 clock-names = "cfg_noc", 539 "core", 540 "sleep", 541 "mock_utmi"; 542 543 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 544 <&gcc GCC_USB0_MASTER_CLK>, 545 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 546 assigned-clock-rates = <133330000>, 547 <133330000>, 548 <20000000>; 549 550 resets = <&gcc GCC_USB0_BCR>; 551 status = "disabled"; 552 553 dwc_0: usb@8a00000 { 554 compatible = "snps,dwc3"; 555 reg = <0x0 0x08a00000 0x0 0xcd00>; 556 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 557 phys = <&qusb_phy_0>, <&usb0_ssphy>; 558 phy-names = "usb2-phy", "usb3-phy"; 559 clocks = <&xo>; 560 clock-names = "ref"; 561 tx-fifo-resize; 562 snps,is-utmi-l1-suspend; 563 snps,hird-threshold = /bits/ 8 <0x0>; 564 snps,dis_u2_susphy_quirk; 565 snps,dis_u3_susphy_quirk; 566 dr_mode = "host"; 567 }; 568 }; 569 570 intc: interrupt-controller@b000000 { 571 compatible = "qcom,msm-qgic2"; 572 #address-cells = <2>; 573 #size-cells = <2>; 574 interrupt-controller; 575 #interrupt-cells = <0x3>; 576 reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ 577 <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ 578 <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ 579 <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ 580 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 581 ranges = <0 0 0 0xb00a000 0 0xffd>; 582 583 v2m@0 { 584 compatible = "arm,gic-v2m-frame"; 585 msi-controller; 586 reg = <0x0 0x0 0x0 0xffd>; 587 }; 588 }; 589 590 watchdog@b017000 { 591 compatible = "qcom,kpss-wdt"; 592 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 593 reg = <0x0 0x0b017000 0x0 0x40>; 594 clocks = <&sleep_clk>; 595 timeout-sec = <10>; 596 }; 597 598 apcs_glb: mailbox@b111000 { 599 compatible = "qcom,ipq6018-apcs-apps-global"; 600 reg = <0x0 0x0b111000 0x0 0x1000>; 601 #clock-cells = <1>; 602 clocks = <&a53pll>, <&xo>; 603 clock-names = "pll", "xo"; 604 #mbox-cells = <1>; 605 }; 606 607 a53pll: clock@b116000 { 608 compatible = "qcom,ipq6018-a53pll"; 609 reg = <0x0 0x0b116000 0x0 0x40>; 610 #clock-cells = <0>; 611 clocks = <&xo>; 612 clock-names = "xo"; 613 }; 614 615 timer@b120000 { 616 #address-cells = <1>; 617 #size-cells = <1>; 618 ranges = <0 0 0 0x10000000>; 619 compatible = "arm,armv7-timer-mem"; 620 reg = <0x0 0x0b120000 0x0 0x1000>; 621 622 frame@b120000 { 623 frame-number = <0>; 624 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 626 reg = <0x0b121000 0x1000>, 627 <0x0b122000 0x1000>; 628 }; 629 630 frame@b123000 { 631 frame-number = <1>; 632 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 633 reg = <0x0b123000 0x1000>; 634 status = "disabled"; 635 }; 636 637 frame@b124000 { 638 frame-number = <2>; 639 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 640 reg = <0x0b124000 0x1000>; 641 status = "disabled"; 642 }; 643 644 frame@b125000 { 645 frame-number = <3>; 646 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 647 reg = <0x0b125000 0x1000>; 648 status = "disabled"; 649 }; 650 651 frame@b126000 { 652 frame-number = <4>; 653 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 654 reg = <0x0b126000 0x1000>; 655 status = "disabled"; 656 }; 657 658 frame@b127000 { 659 frame-number = <5>; 660 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 661 reg = <0x0b127000 0x1000>; 662 status = "disabled"; 663 }; 664 665 frame@b128000 { 666 frame-number = <6>; 667 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 668 reg = <0x0b128000 0x1000>; 669 status = "disabled"; 670 }; 671 }; 672 673 q6v5_wcss: remoteproc@cd00000 { 674 compatible = "qcom,ipq6018-wcss-pil"; 675 reg = <0x0 0x0cd00000 0x0 0x4040>, 676 <0x0 0x004ab000 0x0 0x20>; 677 reg-names = "qdsp6", 678 "rmb"; 679 interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, 680 <&wcss_smp2p_in 0 0>, 681 <&wcss_smp2p_in 1 0>, 682 <&wcss_smp2p_in 2 0>, 683 <&wcss_smp2p_in 3 0>; 684 interrupt-names = "wdog", 685 "fatal", 686 "ready", 687 "handover", 688 "stop-ack"; 689 690 resets = <&gcc GCC_WCSSAON_RESET>, 691 <&gcc GCC_WCSS_BCR>, 692 <&gcc GCC_WCSS_Q6_BCR>; 693 694 reset-names = "wcss_aon_reset", 695 "wcss_reset", 696 "wcss_q6_reset"; 697 698 clocks = <&gcc GCC_PRNG_AHB_CLK>; 699 clock-names = "prng"; 700 701 qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>; 702 703 qcom,smem-states = <&wcss_smp2p_out 0>, 704 <&wcss_smp2p_out 1>; 705 qcom,smem-state-names = "shutdown", 706 "stop"; 707 708 memory-region = <&q6_region>; 709 710 glink-edge { 711 interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>; 712 label = "rtr"; 713 qcom,remote-pid = <1>; 714 mboxes = <&apcs_glb 8>; 715 716 qrtr_requests { 717 qcom,glink-channels = "IPCRTR"; 718 }; 719 }; 720 }; 721 722 pcie0: pci@20000000 { 723 compatible = "qcom,pcie-ipq6018"; 724 reg = <0x0 0x20000000 0x0 0xf1d>, 725 <0x0 0x20000f20 0x0 0xa8>, 726 <0x0 0x20001000 0x0 0x1000>, 727 <0x0 0x80000 0x0 0x4000>, 728 <0x0 0x20100000 0x0 0x1000>; 729 reg-names = "dbi", "elbi", "atu", "parf", "config"; 730 731 device_type = "pci"; 732 linux,pci-domain = <0>; 733 bus-range = <0x00 0xff>; 734 num-lanes = <1>; 735 max-link-speed = <3>; 736 #address-cells = <3>; 737 #size-cells = <2>; 738 739 phys = <&pcie_phy0>; 740 phy-names = "pciephy"; 741 742 ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>, 743 <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>; 744 745 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 746 interrupt-names = "msi"; 747 748 #interrupt-cells = <1>; 749 interrupt-map-mask = <0 0 0 0x7>; 750 interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 751 <0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 752 <0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 753 <0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 754 755 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 756 <&gcc GCC_PCIE0_AXI_M_CLK>, 757 <&gcc GCC_PCIE0_AXI_S_CLK>, 758 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 759 <&gcc PCIE0_RCHNG_CLK>; 760 clock-names = "iface", 761 "axi_m", 762 "axi_s", 763 "axi_bridge", 764 "rchng"; 765 766 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 767 <&gcc GCC_PCIE0_SLEEP_ARES>, 768 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 769 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 770 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 771 <&gcc GCC_PCIE0_AHB_ARES>, 772 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, 773 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; 774 reset-names = "pipe", 775 "sleep", 776 "sticky", 777 "axi_m", 778 "axi_s", 779 "ahb", 780 "axi_m_sticky", 781 "axi_s_sticky"; 782 783 status = "disabled"; 784 }; 785 }; 786 787 timer { 788 compatible = "arm,armv8-timer"; 789 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 790 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 791 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 792 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 793 }; 794 795 wcss: wcss-smp2p { 796 compatible = "qcom,smp2p"; 797 qcom,smem = <435>, <428>; 798 799 interrupt-parent = <&intc>; 800 interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>; 801 802 mboxes = <&apcs_glb 9>; 803 804 qcom,local-pid = <0>; 805 qcom,remote-pid = <1>; 806 807 wcss_smp2p_out: master-kernel { 808 qcom,entry-name = "master-kernel"; 809 #qcom,smem-state-cells = <1>; 810 }; 811 812 wcss_smp2p_in: slave-kernel { 813 qcom,entry-name = "slave-kernel"; 814 interrupt-controller; 815 #interrupt-cells = <2>; 816 }; 817 }; 818}; 819