1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ6018 SoC device tree source 4 * 5 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,gcc-ipq6018.h> 10#include <dt-bindings/reset/qcom,gcc-ipq6018.h> 11 12/ { 13 #address-cells = <2>; 14 #size-cells = <2>; 15 interrupt-parent = <&intc>; 16 17 clocks { 18 sleep_clk: sleep-clk { 19 compatible = "fixed-clock"; 20 clock-frequency = <32000>; 21 #clock-cells = <0>; 22 }; 23 24 xo: xo { 25 compatible = "fixed-clock"; 26 clock-frequency = <24000000>; 27 #clock-cells = <0>; 28 }; 29 }; 30 31 cpus: cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 CPU0: cpu@0 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a53"; 38 reg = <0x0>; 39 enable-method = "psci"; 40 next-level-cache = <&L2_0>; 41 }; 42 43 CPU1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a53"; 46 enable-method = "psci"; 47 reg = <0x1>; 48 next-level-cache = <&L2_0>; 49 }; 50 51 CPU2: cpu@2 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 enable-method = "psci"; 55 reg = <0x2>; 56 next-level-cache = <&L2_0>; 57 }; 58 59 CPU3: cpu@3 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 enable-method = "psci"; 63 reg = <0x3>; 64 next-level-cache = <&L2_0>; 65 }; 66 67 L2_0: l2-cache { 68 compatible = "cache"; 69 cache-level = <0x2>; 70 }; 71 }; 72 73 firmware { 74 scm { 75 compatible = "qcom,scm"; 76 }; 77 }; 78 79 tcsr_mutex: hwlock { 80 compatible = "qcom,tcsr-mutex"; 81 syscon = <&tcsr_mutex_regs 0 0x80>; 82 #hwlock-cells = <1>; 83 }; 84 85 pmuv8: pmu { 86 compatible = "arm,cortex-a53-pmu"; 87 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 88 IRQ_TYPE_LEVEL_HIGH)>; 89 }; 90 91 psci: psci { 92 compatible = "arm,psci-1.0"; 93 method = "smc"; 94 }; 95 96 reserved-memory { 97 #address-cells = <2>; 98 #size-cells = <2>; 99 ranges; 100 101 tz: tz@48500000 { 102 reg = <0x0 0x48500000 0x0 0x00200000>; 103 no-map; 104 }; 105 106 smem_region: memory@4aa00000 { 107 reg = <0x0 0x4aa00000 0x0 0x00100000>; 108 no-map; 109 }; 110 111 q6_region: memory@4ab00000 { 112 reg = <0x0 0x4ab00000 0x0 0x02800000>; 113 no-map; 114 }; 115 }; 116 117 smem { 118 compatible = "qcom,smem"; 119 memory-region = <&smem_region>; 120 hwlocks = <&tcsr_mutex 0>; 121 }; 122 123 soc: soc { 124 #address-cells = <1>; 125 #size-cells = <1>; 126 ranges = <0 0 0 0xffffffff>; 127 dma-ranges; 128 compatible = "simple-bus"; 129 130 prng: qrng@e1000 { 131 compatible = "qcom,prng-ee"; 132 reg = <0xe3000 0x1000>; 133 clocks = <&gcc GCC_PRNG_AHB_CLK>; 134 clock-names = "core"; 135 }; 136 137 cryptobam: dma@704000 { 138 compatible = "qcom,bam-v1.7.0"; 139 reg = <0x00704000 0x20000>; 140 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 141 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 142 clock-names = "bam_clk"; 143 #dma-cells = <1>; 144 qcom,ee = <1>; 145 qcom,controlled-remotely = <1>; 146 qcom,config-pipe-trust-reg = <0>; 147 }; 148 149 crypto: crypto@73a000 { 150 compatible = "qcom,crypto-v5.1"; 151 reg = <0x0073a000 0x6000>; 152 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 153 <&gcc GCC_CRYPTO_AXI_CLK>, 154 <&gcc GCC_CRYPTO_CLK>; 155 clock-names = "iface", "bus", "core"; 156 dmas = <&cryptobam 2>, <&cryptobam 3>; 157 dma-names = "rx", "tx"; 158 }; 159 160 tlmm: pinctrl@1000000 { 161 compatible = "qcom,ipq6018-pinctrl"; 162 reg = <0x01000000 0x300000>; 163 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 164 gpio-controller; 165 #gpio-cells = <2>; 166 gpio-ranges = <&tlmm 0 80>; 167 interrupt-controller; 168 #interrupt-cells = <2>; 169 170 serial_3_pins: serial3-pinmux { 171 pins = "gpio44", "gpio45"; 172 function = "blsp2_uart"; 173 drive-strength = <8>; 174 bias-pull-down; 175 }; 176 }; 177 178 gcc: gcc@1800000 { 179 compatible = "qcom,gcc-ipq6018"; 180 reg = <0x01800000 0x80000>; 181 clocks = <&xo>, <&sleep_clk>; 182 clock-names = "xo", "sleep_clk"; 183 #clock-cells = <1>; 184 #reset-cells = <1>; 185 }; 186 187 tcsr_mutex_regs: syscon@1905000 { 188 compatible = "syscon"; 189 reg = <0x01905000 0x8000>; 190 }; 191 192 tcsr_q6: syscon@1945000 { 193 compatible = "syscon"; 194 reg = <0x01945000 0xe000>; 195 }; 196 197 blsp_dma: dma@7884000 { 198 compatible = "qcom,bam-v1.7.0"; 199 reg = <0x07884000 0x2b000>; 200 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 201 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 202 clock-names = "bam_clk"; 203 #dma-cells = <1>; 204 qcom,ee = <0>; 205 }; 206 207 blsp1_uart3: serial@78b1000 { 208 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 209 reg = <0x078b1000 0x200>; 210 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 212 <&gcc GCC_BLSP1_AHB_CLK>; 213 clock-names = "core", "iface"; 214 status = "disabled"; 215 }; 216 217 spi_0: spi@78b5000 { 218 compatible = "qcom,spi-qup-v2.2.1"; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 reg = <0x078b5000 0x600>; 222 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 223 spi-max-frequency = <50000000>; 224 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 225 <&gcc GCC_BLSP1_AHB_CLK>; 226 clock-names = "core", "iface"; 227 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 228 dma-names = "tx", "rx"; 229 status = "disabled"; 230 }; 231 232 spi_1: spi@78b6000 { 233 compatible = "qcom,spi-qup-v2.2.1"; 234 #address-cells = <1>; 235 #size-cells = <0>; 236 reg = <0x078b6000 0x600>; 237 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 238 spi-max-frequency = <50000000>; 239 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 240 <&gcc GCC_BLSP1_AHB_CLK>; 241 clock-names = "core", "iface"; 242 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 243 dma-names = "tx", "rx"; 244 status = "disabled"; 245 }; 246 247 i2c_0: i2c@78b6000 { 248 compatible = "qcom,i2c-qup-v2.2.1"; 249 #address-cells = <1>; 250 #size-cells = <0>; 251 reg = <0x078b6000 0x600>; 252 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 254 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 255 clock-names = "iface", "core"; 256 clock-frequency = <400000>; 257 dmas = <&blsp_dma 15>, <&blsp_dma 14>; 258 dma-names = "rx", "tx"; 259 status = "disabled"; 260 }; 261 262 i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */ 263 compatible = "qcom,i2c-qup-v2.2.1"; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 reg = <0x078b7000 0x600>; 267 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 269 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 270 clock-names = "iface", "core"; 271 clock-frequency = <400000>; 272 dmas = <&blsp_dma 17>, <&blsp_dma 16>; 273 dma-names = "rx", "tx"; 274 status = "disabled"; 275 }; 276 277 intc: interrupt-controller@b000000 { 278 compatible = "qcom,msm-qgic2"; 279 interrupt-controller; 280 #interrupt-cells = <0x3>; 281 reg = <0x0b000000 0x1000>, /*GICD*/ 282 <0x0b002000 0x1000>, /*GICC*/ 283 <0x0b001000 0x1000>, /*GICH*/ 284 <0x0b004000 0x1000>; /*GICV*/ 285 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 286 }; 287 288 watchdog@b017000 { 289 compatible = "qcom,kpss-wdt"; 290 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 291 reg = <0x0b017000 0x40>; 292 clocks = <&sleep_clk>; 293 timeout-sec = <10>; 294 }; 295 296 apcs_glb: mailbox@b111000 { 297 compatible = "qcom,ipq8074-apcs-apps-global"; 298 reg = <0x0b111000 0xc>; 299 300 #mbox-cells = <1>; 301 }; 302 303 timer { 304 compatible = "arm,armv8-timer"; 305 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 306 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 307 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 308 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 309 }; 310 311 timer@b120000 { 312 #address-cells = <1>; 313 #size-cells = <1>; 314 ranges; 315 compatible = "arm,armv7-timer-mem"; 316 reg = <0x0b120000 0x1000>; 317 clock-frequency = <19200000>; 318 319 frame@b120000 { 320 frame-number = <0>; 321 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 323 reg = <0x0b121000 0x1000>, 324 <0x0b122000 0x1000>; 325 }; 326 327 frame@b123000 { 328 frame-number = <1>; 329 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 330 reg = <0xb123000 0x1000>; 331 status = "disabled"; 332 }; 333 334 frame@b124000 { 335 frame-number = <2>; 336 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 337 reg = <0x0b124000 0x1000>; 338 status = "disabled"; 339 }; 340 341 frame@b125000 { 342 frame-number = <3>; 343 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 344 reg = <0x0b125000 0x1000>; 345 status = "disabled"; 346 }; 347 348 frame@b126000 { 349 frame-number = <4>; 350 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 351 reg = <0x0b126000 0x1000>; 352 status = "disabled"; 353 }; 354 355 frame@b127000 { 356 frame-number = <5>; 357 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 358 reg = <0x0b127000 0x1000>; 359 status = "disabled"; 360 }; 361 362 frame@b128000 { 363 frame-number = <6>; 364 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 365 reg = <0x0b128000 0x1000>; 366 status = "disabled"; 367 }; 368 }; 369 370 q6v5_wcss: remoteproc@cd00000 { 371 compatible = "qcom,ipq8074-wcss-pil"; 372 reg = <0x0cd00000 0x4040>, 373 <0x004ab000 0x20>; 374 reg-names = "qdsp6", 375 "rmb"; 376 interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, 377 <&wcss_smp2p_in 0 0>, 378 <&wcss_smp2p_in 1 0>, 379 <&wcss_smp2p_in 2 0>, 380 <&wcss_smp2p_in 3 0>; 381 interrupt-names = "wdog", 382 "fatal", 383 "ready", 384 "handover", 385 "stop-ack"; 386 387 resets = <&gcc GCC_WCSSAON_RESET>, 388 <&gcc GCC_WCSS_BCR>, 389 <&gcc GCC_WCSS_Q6_BCR>; 390 391 reset-names = "wcss_aon_reset", 392 "wcss_reset", 393 "wcss_q6_reset"; 394 395 clocks = <&gcc GCC_PRNG_AHB_CLK>; 396 clock-names = "prng"; 397 398 qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>; 399 400 qcom,smem-states = <&wcss_smp2p_out 0>, 401 <&wcss_smp2p_out 1>; 402 qcom,smem-state-names = "shutdown", 403 "stop"; 404 405 memory-region = <&q6_region>; 406 407 glink-edge { 408 interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>; 409 qcom,remote-pid = <1>; 410 mboxes = <&apcs_glb 8>; 411 412 qrtr_requests { 413 qcom,glink-channels = "IPCRTR"; 414 }; 415 }; 416 }; 417 418 }; 419 420 wcss: wcss-smp2p { 421 compatible = "qcom,smp2p"; 422 qcom,smem = <435>, <428>; 423 424 interrupt-parent = <&intc>; 425 interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>; 426 427 mboxes = <&apcs_glb 9>; 428 429 qcom,local-pid = <0>; 430 qcom,remote-pid = <1>; 431 432 wcss_smp2p_out: master-kernel { 433 qcom,entry-name = "master-kernel"; 434 #qcom,smem-state-cells = <1>; 435 }; 436 437 wcss_smp2p_in: slave-kernel { 438 qcom,entry-name = "slave-kernel"; 439 interrupt-controller; 440 #interrupt-cells = <2>; 441 }; 442 }; 443}; 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