1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ6018 SoC device tree source 4 * 5 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,gcc-ipq6018.h> 10#include <dt-bindings/reset/qcom,gcc-ipq6018.h> 11#include <dt-bindings/clock/qcom,apss-ipq.h> 12 13/ { 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&intc>; 17 18 clocks { 19 sleep_clk: sleep-clk { 20 compatible = "fixed-clock"; 21 clock-frequency = <32000>; 22 #clock-cells = <0>; 23 }; 24 25 xo: xo { 26 compatible = "fixed-clock"; 27 clock-frequency = <24000000>; 28 #clock-cells = <0>; 29 }; 30 }; 31 32 cpus: cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 CPU0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a53"; 39 reg = <0x0>; 40 enable-method = "psci"; 41 next-level-cache = <&L2_0>; 42 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 43 clock-names = "cpu"; 44 operating-points-v2 = <&cpu_opp_table>; 45 cpu-supply = <&ipq6018_s2>; 46 }; 47 48 CPU1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53"; 51 enable-method = "psci"; 52 reg = <0x1>; 53 next-level-cache = <&L2_0>; 54 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 55 clock-names = "cpu"; 56 operating-points-v2 = <&cpu_opp_table>; 57 cpu-supply = <&ipq6018_s2>; 58 }; 59 60 CPU2: cpu@2 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 enable-method = "psci"; 64 reg = <0x2>; 65 next-level-cache = <&L2_0>; 66 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 67 clock-names = "cpu"; 68 operating-points-v2 = <&cpu_opp_table>; 69 cpu-supply = <&ipq6018_s2>; 70 }; 71 72 CPU3: cpu@3 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a53"; 75 enable-method = "psci"; 76 reg = <0x3>; 77 next-level-cache = <&L2_0>; 78 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 79 clock-names = "cpu"; 80 operating-points-v2 = <&cpu_opp_table>; 81 cpu-supply = <&ipq6018_s2>; 82 }; 83 84 L2_0: l2-cache { 85 compatible = "cache"; 86 cache-level = <0x2>; 87 }; 88 }; 89 90 cpu_opp_table: cpu_opp_table { 91 compatible = "operating-points-v2"; 92 opp-shared; 93 94 opp-864000000 { 95 opp-hz = /bits/ 64 <864000000>; 96 opp-microvolt = <725000>; 97 clock-latency-ns = <200000>; 98 }; 99 opp-1056000000 { 100 opp-hz = /bits/ 64 <1056000000>; 101 opp-microvolt = <787500>; 102 clock-latency-ns = <200000>; 103 }; 104 opp-1320000000 { 105 opp-hz = /bits/ 64 <1320000000>; 106 opp-microvolt = <862500>; 107 clock-latency-ns = <200000>; 108 }; 109 opp-1440000000 { 110 opp-hz = /bits/ 64 <1440000000>; 111 opp-microvolt = <925000>; 112 clock-latency-ns = <200000>; 113 }; 114 opp-1608000000 { 115 opp-hz = /bits/ 64 <1608000000>; 116 opp-microvolt = <987500>; 117 clock-latency-ns = <200000>; 118 }; 119 opp-1800000000 { 120 opp-hz = /bits/ 64 <1800000000>; 121 opp-microvolt = <1062500>; 122 clock-latency-ns = <200000>; 123 }; 124 }; 125 126 firmware { 127 scm { 128 compatible = "qcom,scm"; 129 }; 130 }; 131 132 tcsr_mutex: hwlock { 133 compatible = "qcom,tcsr-mutex"; 134 syscon = <&tcsr_mutex_regs 0 0x80>; 135 #hwlock-cells = <1>; 136 }; 137 138 pmuv8: pmu { 139 compatible = "arm,cortex-a53-pmu"; 140 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 141 IRQ_TYPE_LEVEL_HIGH)>; 142 }; 143 144 psci: psci { 145 compatible = "arm,psci-1.0"; 146 method = "smc"; 147 }; 148 149 reserved-memory { 150 #address-cells = <2>; 151 #size-cells = <2>; 152 ranges; 153 154 rpm_msg_ram: memory@0x60000 { 155 reg = <0x0 0x60000 0x0 0x6000>; 156 no-map; 157 }; 158 159 tz: memory@4a600000 { 160 reg = <0x0 0x4a600000 0x0 0x00400000>; 161 no-map; 162 }; 163 164 smem_region: memory@4aa00000 { 165 reg = <0x0 0x4aa00000 0x0 0x00100000>; 166 no-map; 167 }; 168 169 q6_region: memory@4ab00000 { 170 reg = <0x0 0x4ab00000 0x0 0x05500000>; 171 no-map; 172 }; 173 }; 174 175 smem { 176 compatible = "qcom,smem"; 177 memory-region = <&smem_region>; 178 hwlocks = <&tcsr_mutex 0>; 179 }; 180 181 soc: soc { 182 #address-cells = <2>; 183 #size-cells = <2>; 184 ranges = <0 0 0 0 0x0 0xffffffff>; 185 dma-ranges; 186 compatible = "simple-bus"; 187 188 prng: qrng@e1000 { 189 compatible = "qcom,prng-ee"; 190 reg = <0x0 0xe3000 0x0 0x1000>; 191 clocks = <&gcc GCC_PRNG_AHB_CLK>; 192 clock-names = "core"; 193 }; 194 195 cryptobam: dma-controller@704000 { 196 compatible = "qcom,bam-v1.7.0"; 197 reg = <0x0 0x00704000 0x0 0x20000>; 198 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 200 clock-names = "bam_clk"; 201 #dma-cells = <1>; 202 qcom,ee = <1>; 203 qcom,controlled-remotely = <1>; 204 qcom,config-pipe-trust-reg = <0>; 205 }; 206 207 crypto: crypto@73a000 { 208 compatible = "qcom,crypto-v5.1"; 209 reg = <0x0 0x0073a000 0x0 0x6000>; 210 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 211 <&gcc GCC_CRYPTO_AXI_CLK>, 212 <&gcc GCC_CRYPTO_CLK>; 213 clock-names = "iface", "bus", "core"; 214 dmas = <&cryptobam 2>, <&cryptobam 3>; 215 dma-names = "rx", "tx"; 216 }; 217 218 tlmm: pinctrl@1000000 { 219 compatible = "qcom,ipq6018-pinctrl"; 220 reg = <0x0 0x01000000 0x0 0x300000>; 221 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 222 gpio-controller; 223 #gpio-cells = <2>; 224 gpio-ranges = <&tlmm 0 80>; 225 interrupt-controller; 226 #interrupt-cells = <2>; 227 228 serial_3_pins: serial3-pinmux { 229 pins = "gpio44", "gpio45"; 230 function = "blsp2_uart"; 231 drive-strength = <8>; 232 bias-pull-down; 233 }; 234 235 qpic_pins: qpic-pins { 236 pins = "gpio1", "gpio3", "gpio4", 237 "gpio5", "gpio6", "gpio7", 238 "gpio8", "gpio10", "gpio11", 239 "gpio12", "gpio13", "gpio14", 240 "gpio15", "gpio17"; 241 function = "qpic_pad"; 242 drive-strength = <8>; 243 bias-disable; 244 }; 245 }; 246 247 gcc: gcc@1800000 { 248 compatible = "qcom,gcc-ipq6018"; 249 reg = <0x0 0x01800000 0x0 0x80000>; 250 clocks = <&xo>, <&sleep_clk>; 251 clock-names = "xo", "sleep_clk"; 252 #clock-cells = <1>; 253 #reset-cells = <1>; 254 }; 255 256 tcsr_mutex_regs: syscon@1905000 { 257 compatible = "syscon"; 258 reg = <0x0 0x01905000 0x0 0x8000>; 259 }; 260 261 tcsr_q6: syscon@1945000 { 262 compatible = "syscon"; 263 reg = <0x0 0x01945000 0x0 0xe000>; 264 }; 265 266 blsp_dma: dma-controller@7884000 { 267 compatible = "qcom,bam-v1.7.0"; 268 reg = <0x0 0x07884000 0x0 0x2b000>; 269 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 271 clock-names = "bam_clk"; 272 #dma-cells = <1>; 273 qcom,ee = <0>; 274 }; 275 276 blsp1_uart3: serial@78b1000 { 277 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 278 reg = <0x0 0x078b1000 0x0 0x200>; 279 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 280 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 281 <&gcc GCC_BLSP1_AHB_CLK>; 282 clock-names = "core", "iface"; 283 status = "disabled"; 284 }; 285 286 spi_0: spi@78b5000 { 287 compatible = "qcom,spi-qup-v2.2.1"; 288 #address-cells = <1>; 289 #size-cells = <0>; 290 reg = <0x0 0x078b5000 0x0 0x600>; 291 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 292 spi-max-frequency = <50000000>; 293 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 294 <&gcc GCC_BLSP1_AHB_CLK>; 295 clock-names = "core", "iface"; 296 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 297 dma-names = "tx", "rx"; 298 status = "disabled"; 299 }; 300 301 spi_1: spi@78b6000 { 302 compatible = "qcom,spi-qup-v2.2.1"; 303 #address-cells = <1>; 304 #size-cells = <0>; 305 reg = <0x0 0x078b6000 0x0 0x600>; 306 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 307 spi-max-frequency = <50000000>; 308 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 309 <&gcc GCC_BLSP1_AHB_CLK>; 310 clock-names = "core", "iface"; 311 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 312 dma-names = "tx", "rx"; 313 status = "disabled"; 314 }; 315 316 i2c_0: i2c@78b6000 { 317 compatible = "qcom,i2c-qup-v2.2.1"; 318 #address-cells = <1>; 319 #size-cells = <0>; 320 reg = <0x0 0x078b6000 0x0 0x600>; 321 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 323 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 324 clock-names = "iface", "core"; 325 clock-frequency = <400000>; 326 dmas = <&blsp_dma 15>, <&blsp_dma 14>; 327 dma-names = "rx", "tx"; 328 status = "disabled"; 329 }; 330 331 i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */ 332 compatible = "qcom,i2c-qup-v2.2.1"; 333 #address-cells = <1>; 334 #size-cells = <0>; 335 reg = <0x0 0x078b7000 0x0 0x600>; 336 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 338 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 339 clock-names = "iface", "core"; 340 clock-frequency = <400000>; 341 dmas = <&blsp_dma 17>, <&blsp_dma 16>; 342 dma-names = "rx", "tx"; 343 status = "disabled"; 344 }; 345 346 qpic_bam: dma-controller@7984000 { 347 compatible = "qcom,bam-v1.7.0"; 348 reg = <0x0 0x07984000 0x0 0x1a000>; 349 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 350 clocks = <&gcc GCC_QPIC_CLK>, 351 <&gcc GCC_QPIC_AHB_CLK>; 352 clock-names = "iface_clk", "bam_clk"; 353 #dma-cells = <1>; 354 qcom,ee = <0>; 355 status = "disabled"; 356 }; 357 358 qpic_nand: nand@79b0000 { 359 compatible = "qcom,ipq6018-nand"; 360 reg = <0x0 0x079b0000 0x0 0x10000>; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 clocks = <&gcc GCC_QPIC_CLK>, 364 <&gcc GCC_QPIC_AHB_CLK>; 365 clock-names = "core", "aon"; 366 367 dmas = <&qpic_bam 0>, 368 <&qpic_bam 1>, 369 <&qpic_bam 2>; 370 dma-names = "tx", "rx", "cmd"; 371 pinctrl-0 = <&qpic_pins>; 372 pinctrl-names = "default"; 373 status = "disabled"; 374 }; 375 376 intc: interrupt-controller@b000000 { 377 compatible = "qcom,msm-qgic2"; 378 interrupt-controller; 379 #interrupt-cells = <0x3>; 380 reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ 381 <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ 382 <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ 383 <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ 384 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 385 }; 386 387 watchdog@b017000 { 388 compatible = "qcom,kpss-wdt"; 389 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 390 reg = <0x0 0x0b017000 0x0 0x40>; 391 clocks = <&sleep_clk>; 392 timeout-sec = <10>; 393 }; 394 395 apcs_glb: mailbox@b111000 { 396 compatible = "qcom,ipq6018-apcs-apps-global"; 397 reg = <0x0 0x0b111000 0x0 0x1000>; 398 #clock-cells = <1>; 399 clocks = <&a53pll>, <&xo>; 400 clock-names = "pll", "xo"; 401 #mbox-cells = <1>; 402 }; 403 404 a53pll: clock@b116000 { 405 compatible = "qcom,ipq6018-a53pll"; 406 reg = <0x0 0x0b116000 0x0 0x40>; 407 #clock-cells = <0>; 408 clocks = <&xo>; 409 clock-names = "xo"; 410 }; 411 412 timer { 413 compatible = "arm,armv8-timer"; 414 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 415 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 416 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 417 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 418 }; 419 420 timer@b120000 { 421 #address-cells = <2>; 422 #size-cells = <2>; 423 ranges; 424 compatible = "arm,armv7-timer-mem"; 425 reg = <0x0 0x0b120000 0x0 0x1000>; 426 clock-frequency = <19200000>; 427 428 frame@b120000 { 429 frame-number = <0>; 430 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 432 reg = <0x0 0x0b121000 0x0 0x1000>, 433 <0x0 0x0b122000 0x0 0x1000>; 434 }; 435 436 frame@b123000 { 437 frame-number = <1>; 438 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 439 reg = <0x0 0xb123000 0x0 0x1000>; 440 status = "disabled"; 441 }; 442 443 frame@b124000 { 444 frame-number = <2>; 445 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 446 reg = <0x0 0x0b124000 0x0 0x1000>; 447 status = "disabled"; 448 }; 449 450 frame@b125000 { 451 frame-number = <3>; 452 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 453 reg = <0x0 0x0b125000 0x0 0x1000>; 454 status = "disabled"; 455 }; 456 457 frame@b126000 { 458 frame-number = <4>; 459 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 460 reg = <0x0 0x0b126000 0x0 0x1000>; 461 status = "disabled"; 462 }; 463 464 frame@b127000 { 465 frame-number = <5>; 466 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 467 reg = <0x0 0x0b127000 0x0 0x1000>; 468 status = "disabled"; 469 }; 470 471 frame@b128000 { 472 frame-number = <6>; 473 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 474 reg = <0x0 0x0b128000 0x0 0x1000>; 475 status = "disabled"; 476 }; 477 }; 478 479 q6v5_wcss: remoteproc@cd00000 { 480 compatible = "qcom,ipq8074-wcss-pil"; 481 reg = <0x0 0x0cd00000 0x0 0x4040>, 482 <0x0 0x004ab000 0x0 0x20>; 483 reg-names = "qdsp6", 484 "rmb"; 485 interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, 486 <&wcss_smp2p_in 0 0>, 487 <&wcss_smp2p_in 1 0>, 488 <&wcss_smp2p_in 2 0>, 489 <&wcss_smp2p_in 3 0>; 490 interrupt-names = "wdog", 491 "fatal", 492 "ready", 493 "handover", 494 "stop-ack"; 495 496 resets = <&gcc GCC_WCSSAON_RESET>, 497 <&gcc GCC_WCSS_BCR>, 498 <&gcc GCC_WCSS_Q6_BCR>; 499 500 reset-names = "wcss_aon_reset", 501 "wcss_reset", 502 "wcss_q6_reset"; 503 504 clocks = <&gcc GCC_PRNG_AHB_CLK>; 505 clock-names = "prng"; 506 507 qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>; 508 509 qcom,smem-states = <&wcss_smp2p_out 0>, 510 <&wcss_smp2p_out 1>; 511 qcom,smem-state-names = "shutdown", 512 "stop"; 513 514 memory-region = <&q6_region>; 515 516 glink-edge { 517 interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>; 518 qcom,remote-pid = <1>; 519 mboxes = <&apcs_glb 8>; 520 521 qrtr_requests { 522 qcom,glink-channels = "IPCRTR"; 523 }; 524 }; 525 }; 526 527 }; 528 529 wcss: wcss-smp2p { 530 compatible = "qcom,smp2p"; 531 qcom,smem = <435>, <428>; 532 533 interrupt-parent = <&intc>; 534 interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>; 535 536 mboxes = <&apcs_glb 9>; 537 538 qcom,local-pid = <0>; 539 qcom,remote-pid = <1>; 540 541 wcss_smp2p_out: master-kernel { 542 qcom,entry-name = "master-kernel"; 543 #qcom,smem-state-cells = <1>; 544 }; 545 546 wcss_smp2p_in: slave-kernel { 547 qcom,entry-name = "slave-kernel"; 548 interrupt-controller; 549 #interrupt-cells = <2>; 550 }; 551 }; 552 553 rpm-glink { 554 compatible = "qcom,glink-rpm"; 555 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 556 qcom,rpm-msg-ram = <&rpm_msg_ram>; 557 mboxes = <&apcs_glb 0>; 558 559 rpm_requests: glink-channel { 560 compatible = "qcom,rpm-ipq6018"; 561 qcom,glink-channels = "rpm_requests"; 562 563 regulators { 564 compatible = "qcom,rpm-mp5496-regulators"; 565 566 ipq6018_s2: s2 { 567 regulator-min-microvolt = <725000>; 568 regulator-max-microvolt = <1062500>; 569 regulator-always-on; 570 }; 571 }; 572 }; 573 }; 574}; 575