1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ6018 SoC device tree source 4 * 5 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,gcc-ipq6018.h> 10#include <dt-bindings/reset/qcom,gcc-ipq6018.h> 11#include <dt-bindings/clock/qcom,apss-ipq.h> 12 13/ { 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&intc>; 17 18 clocks { 19 sleep_clk: sleep-clk { 20 compatible = "fixed-clock"; 21 clock-frequency = <32000>; 22 #clock-cells = <0>; 23 }; 24 25 xo: xo { 26 compatible = "fixed-clock"; 27 clock-frequency = <24000000>; 28 #clock-cells = <0>; 29 }; 30 }; 31 32 cpus: cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 CPU0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a53"; 39 reg = <0x0>; 40 enable-method = "psci"; 41 next-level-cache = <&L2_0>; 42 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 43 clock-names = "cpu"; 44 operating-points-v2 = <&cpu_opp_table>; 45 cpu-supply = <&ipq6018_s2>; 46 }; 47 48 CPU1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53"; 51 enable-method = "psci"; 52 reg = <0x1>; 53 next-level-cache = <&L2_0>; 54 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 55 clock-names = "cpu"; 56 operating-points-v2 = <&cpu_opp_table>; 57 cpu-supply = <&ipq6018_s2>; 58 }; 59 60 CPU2: cpu@2 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 enable-method = "psci"; 64 reg = <0x2>; 65 next-level-cache = <&L2_0>; 66 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 67 clock-names = "cpu"; 68 operating-points-v2 = <&cpu_opp_table>; 69 cpu-supply = <&ipq6018_s2>; 70 }; 71 72 CPU3: cpu@3 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a53"; 75 enable-method = "psci"; 76 reg = <0x3>; 77 next-level-cache = <&L2_0>; 78 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 79 clock-names = "cpu"; 80 operating-points-v2 = <&cpu_opp_table>; 81 cpu-supply = <&ipq6018_s2>; 82 }; 83 84 L2_0: l2-cache { 85 compatible = "cache"; 86 cache-level = <0x2>; 87 }; 88 }; 89 90 cpu_opp_table: cpu_opp_table { 91 compatible = "operating-points-v2"; 92 opp-shared; 93 94 opp-864000000 { 95 opp-hz = /bits/ 64 <864000000>; 96 opp-microvolt = <725000>; 97 clock-latency-ns = <200000>; 98 }; 99 opp-1056000000 { 100 opp-hz = /bits/ 64 <1056000000>; 101 opp-microvolt = <787500>; 102 clock-latency-ns = <200000>; 103 }; 104 opp-1320000000 { 105 opp-hz = /bits/ 64 <1320000000>; 106 opp-microvolt = <862500>; 107 clock-latency-ns = <200000>; 108 }; 109 opp-1440000000 { 110 opp-hz = /bits/ 64 <1440000000>; 111 opp-microvolt = <925000>; 112 clock-latency-ns = <200000>; 113 }; 114 opp-1608000000 { 115 opp-hz = /bits/ 64 <1608000000>; 116 opp-microvolt = <987500>; 117 clock-latency-ns = <200000>; 118 }; 119 opp-1800000000 { 120 opp-hz = /bits/ 64 <1800000000>; 121 opp-microvolt = <1062500>; 122 clock-latency-ns = <200000>; 123 }; 124 }; 125 126 firmware { 127 scm { 128 compatible = "qcom,scm"; 129 }; 130 }; 131 132 tcsr_mutex: hwlock { 133 compatible = "qcom,tcsr-mutex"; 134 syscon = <&tcsr_mutex_regs 0 0x80>; 135 #hwlock-cells = <1>; 136 }; 137 138 pmuv8: pmu { 139 compatible = "arm,cortex-a53-pmu"; 140 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 141 IRQ_TYPE_LEVEL_HIGH)>; 142 }; 143 144 psci: psci { 145 compatible = "arm,psci-1.0"; 146 method = "smc"; 147 }; 148 149 reserved-memory { 150 #address-cells = <2>; 151 #size-cells = <2>; 152 ranges; 153 154 rpm_msg_ram: memory@60000 { 155 reg = <0x0 0x60000 0x0 0x6000>; 156 no-map; 157 }; 158 159 tz: memory@4a600000 { 160 reg = <0x0 0x4a600000 0x0 0x00400000>; 161 no-map; 162 }; 163 164 smem_region: memory@4aa00000 { 165 reg = <0x0 0x4aa00000 0x0 0x00100000>; 166 no-map; 167 }; 168 169 q6_region: memory@4ab00000 { 170 reg = <0x0 0x4ab00000 0x0 0x05500000>; 171 no-map; 172 }; 173 }; 174 175 smem { 176 compatible = "qcom,smem"; 177 memory-region = <&smem_region>; 178 hwlocks = <&tcsr_mutex 0>; 179 }; 180 181 soc: soc { 182 #address-cells = <2>; 183 #size-cells = <2>; 184 ranges = <0 0 0 0 0x0 0xffffffff>; 185 dma-ranges; 186 compatible = "simple-bus"; 187 188 prng: qrng@e1000 { 189 compatible = "qcom,prng-ee"; 190 reg = <0x0 0xe3000 0x0 0x1000>; 191 clocks = <&gcc GCC_PRNG_AHB_CLK>; 192 clock-names = "core"; 193 }; 194 195 cryptobam: dma-controller@704000 { 196 compatible = "qcom,bam-v1.7.0"; 197 reg = <0x0 0x00704000 0x0 0x20000>; 198 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 200 clock-names = "bam_clk"; 201 #dma-cells = <1>; 202 qcom,ee = <1>; 203 qcom,controlled-remotely; 204 }; 205 206 crypto: crypto@73a000 { 207 compatible = "qcom,crypto-v5.1"; 208 reg = <0x0 0x0073a000 0x0 0x6000>; 209 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 210 <&gcc GCC_CRYPTO_AXI_CLK>, 211 <&gcc GCC_CRYPTO_CLK>; 212 clock-names = "iface", "bus", "core"; 213 dmas = <&cryptobam 2>, <&cryptobam 3>; 214 dma-names = "rx", "tx"; 215 }; 216 217 tlmm: pinctrl@1000000 { 218 compatible = "qcom,ipq6018-pinctrl"; 219 reg = <0x0 0x01000000 0x0 0x300000>; 220 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 221 gpio-controller; 222 #gpio-cells = <2>; 223 gpio-ranges = <&tlmm 0 0 80>; 224 interrupt-controller; 225 #interrupt-cells = <2>; 226 227 serial_3_pins: serial3-pinmux { 228 pins = "gpio44", "gpio45"; 229 function = "blsp2_uart"; 230 drive-strength = <8>; 231 bias-pull-down; 232 }; 233 234 qpic_pins: qpic-pins { 235 pins = "gpio1", "gpio3", "gpio4", 236 "gpio5", "gpio6", "gpio7", 237 "gpio8", "gpio10", "gpio11", 238 "gpio12", "gpio13", "gpio14", 239 "gpio15", "gpio17"; 240 function = "qpic_pad"; 241 drive-strength = <8>; 242 bias-disable; 243 }; 244 }; 245 246 gcc: gcc@1800000 { 247 compatible = "qcom,gcc-ipq6018"; 248 reg = <0x0 0x01800000 0x0 0x80000>; 249 clocks = <&xo>, <&sleep_clk>; 250 clock-names = "xo", "sleep_clk"; 251 #clock-cells = <1>; 252 #reset-cells = <1>; 253 }; 254 255 tcsr_mutex_regs: syscon@1905000 { 256 compatible = "syscon"; 257 reg = <0x0 0x01905000 0x0 0x8000>; 258 }; 259 260 tcsr: syscon@1937000 { 261 compatible = "syscon"; 262 reg = <0x0 0x01937000 0x0 0x21000>; 263 }; 264 265 blsp_dma: dma-controller@7884000 { 266 compatible = "qcom,bam-v1.7.0"; 267 reg = <0x0 0x07884000 0x0 0x2b000>; 268 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 269 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 270 clock-names = "bam_clk"; 271 #dma-cells = <1>; 272 qcom,ee = <0>; 273 }; 274 275 blsp1_uart3: serial@78b1000 { 276 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 277 reg = <0x0 0x078b1000 0x0 0x200>; 278 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 280 <&gcc GCC_BLSP1_AHB_CLK>; 281 clock-names = "core", "iface"; 282 status = "disabled"; 283 }; 284 285 spi_0: spi@78b5000 { 286 compatible = "qcom,spi-qup-v2.2.1"; 287 #address-cells = <1>; 288 #size-cells = <0>; 289 reg = <0x0 0x078b5000 0x0 0x600>; 290 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 291 spi-max-frequency = <50000000>; 292 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 293 <&gcc GCC_BLSP1_AHB_CLK>; 294 clock-names = "core", "iface"; 295 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 296 dma-names = "tx", "rx"; 297 status = "disabled"; 298 }; 299 300 spi_1: spi@78b6000 { 301 compatible = "qcom,spi-qup-v2.2.1"; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 reg = <0x0 0x078b6000 0x0 0x600>; 305 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 306 spi-max-frequency = <50000000>; 307 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 308 <&gcc GCC_BLSP1_AHB_CLK>; 309 clock-names = "core", "iface"; 310 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 311 dma-names = "tx", "rx"; 312 status = "disabled"; 313 }; 314 315 i2c_0: i2c@78b6000 { 316 compatible = "qcom,i2c-qup-v2.2.1"; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 reg = <0x0 0x078b6000 0x0 0x600>; 320 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 322 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 323 clock-names = "iface", "core"; 324 clock-frequency = <400000>; 325 dmas = <&blsp_dma 15>, <&blsp_dma 14>; 326 dma-names = "rx", "tx"; 327 status = "disabled"; 328 }; 329 330 i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */ 331 compatible = "qcom,i2c-qup-v2.2.1"; 332 #address-cells = <1>; 333 #size-cells = <0>; 334 reg = <0x0 0x078b7000 0x0 0x600>; 335 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 337 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 338 clock-names = "iface", "core"; 339 clock-frequency = <400000>; 340 dmas = <&blsp_dma 17>, <&blsp_dma 16>; 341 dma-names = "rx", "tx"; 342 status = "disabled"; 343 }; 344 345 qpic_bam: dma-controller@7984000 { 346 compatible = "qcom,bam-v1.7.0"; 347 reg = <0x0 0x07984000 0x0 0x1a000>; 348 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&gcc GCC_QPIC_AHB_CLK>; 350 clock-names = "bam_clk"; 351 #dma-cells = <1>; 352 qcom,ee = <0>; 353 status = "disabled"; 354 }; 355 356 qpic_nand: nand@79b0000 { 357 compatible = "qcom,ipq6018-nand"; 358 reg = <0x0 0x079b0000 0x0 0x10000>; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 clocks = <&gcc GCC_QPIC_CLK>, 362 <&gcc GCC_QPIC_AHB_CLK>; 363 clock-names = "core", "aon"; 364 365 dmas = <&qpic_bam 0>, 366 <&qpic_bam 1>, 367 <&qpic_bam 2>; 368 dma-names = "tx", "rx", "cmd"; 369 pinctrl-0 = <&qpic_pins>; 370 pinctrl-names = "default"; 371 status = "disabled"; 372 }; 373 374 intc: interrupt-controller@b000000 { 375 compatible = "qcom,msm-qgic2"; 376 interrupt-controller; 377 #interrupt-cells = <0x3>; 378 reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ 379 <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ 380 <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ 381 <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ 382 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 383 }; 384 385 pcie_phy: phy@84000 { 386 compatible = "qcom,ipq6018-qmp-pcie-phy"; 387 reg = <0x0 0x84000 0x0 0x1bc>; /* Serdes PLL */ 388 status = "disabled"; 389 #address-cells = <2>; 390 #size-cells = <2>; 391 ranges; 392 393 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 394 <&gcc GCC_PCIE0_AHB_CLK>; 395 clock-names = "aux", "cfg_ahb"; 396 397 resets = <&gcc GCC_PCIE0_PHY_BCR>, 398 <&gcc GCC_PCIE0PHY_PHY_BCR>; 399 reset-names = "phy", 400 "common"; 401 402 pcie_phy0: phy@84200 { 403 reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */ 404 <0x0 0x84400 0x0 0x200>, /* Serdes Rx */ 405 <0x0 0x84800 0x0 0x4f4>; /* PCS: Lane0, COM, PCIE */ 406 #phy-cells = <0>; 407 408 clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 409 clock-names = "pipe0"; 410 clock-output-names = "gcc_pcie0_pipe_clk_src"; 411 #clock-cells = <0>; 412 }; 413 }; 414 415 pcie0: pci@20000000 { 416 compatible = "qcom,pcie-ipq6018"; 417 reg = <0x0 0x20000000 0x0 0xf1d>, 418 <0x0 0x20000f20 0x0 0xa8>, 419 <0x0 0x20001000 0x0 0x1000>, 420 <0x0 0x80000 0x0 0x4000>, 421 <0x0 0x20100000 0x0 0x1000>; 422 reg-names = "dbi", "elbi", "atu", "parf", "config"; 423 424 device_type = "pci"; 425 linux,pci-domain = <0>; 426 bus-range = <0x00 0xff>; 427 num-lanes = <1>; 428 #address-cells = <3>; 429 #size-cells = <2>; 430 431 phys = <&pcie_phy0>; 432 phy-names = "pciephy"; 433 434 ranges = <0x81000000 0 0x20200000 0 0x20200000 435 0 0x10000>, /* downstream I/O */ 436 <0x82000000 0 0x20220000 0 0x20220000 437 0 0xfde0000>; /* non-prefetchable memory */ 438 439 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 440 interrupt-names = "msi"; 441 442 #interrupt-cells = <1>; 443 interrupt-map-mask = <0 0 0 0x7>; 444 interrupt-map = <0 0 0 1 &intc 0 75 445 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 446 <0 0 0 2 &intc 0 78 447 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 448 <0 0 0 3 &intc 0 79 449 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 450 <0 0 0 4 &intc 0 83 451 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 452 453 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 454 <&gcc GCC_PCIE0_AXI_M_CLK>, 455 <&gcc GCC_PCIE0_AXI_S_CLK>, 456 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 457 <&gcc PCIE0_RCHNG_CLK>; 458 clock-names = "iface", 459 "axi_m", 460 "axi_s", 461 "axi_bridge", 462 "rchng"; 463 464 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 465 <&gcc GCC_PCIE0_SLEEP_ARES>, 466 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 467 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 468 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 469 <&gcc GCC_PCIE0_AHB_ARES>, 470 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, 471 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; 472 reset-names = "pipe", 473 "sleep", 474 "sticky", 475 "axi_m", 476 "axi_s", 477 "ahb", 478 "axi_m_sticky", 479 "axi_s_sticky"; 480 481 status = "disabled"; 482 }; 483 484 watchdog@b017000 { 485 compatible = "qcom,kpss-wdt"; 486 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 487 reg = <0x0 0x0b017000 0x0 0x40>; 488 clocks = <&sleep_clk>; 489 timeout-sec = <10>; 490 }; 491 492 apcs_glb: mailbox@b111000 { 493 compatible = "qcom,ipq6018-apcs-apps-global"; 494 reg = <0x0 0x0b111000 0x0 0x1000>; 495 #clock-cells = <1>; 496 clocks = <&a53pll>, <&xo>; 497 clock-names = "pll", "xo"; 498 #mbox-cells = <1>; 499 }; 500 501 a53pll: clock@b116000 { 502 compatible = "qcom,ipq6018-a53pll"; 503 reg = <0x0 0x0b116000 0x0 0x40>; 504 #clock-cells = <0>; 505 clocks = <&xo>; 506 clock-names = "xo"; 507 }; 508 509 timer { 510 compatible = "arm,armv8-timer"; 511 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 512 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 513 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 514 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 515 }; 516 517 timer@b120000 { 518 #address-cells = <2>; 519 #size-cells = <2>; 520 ranges; 521 compatible = "arm,armv7-timer-mem"; 522 reg = <0x0 0x0b120000 0x0 0x1000>; 523 clock-frequency = <19200000>; 524 525 frame@b120000 { 526 frame-number = <0>; 527 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 529 reg = <0x0 0x0b121000 0x0 0x1000>, 530 <0x0 0x0b122000 0x0 0x1000>; 531 }; 532 533 frame@b123000 { 534 frame-number = <1>; 535 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 536 reg = <0x0 0xb123000 0x0 0x1000>; 537 status = "disabled"; 538 }; 539 540 frame@b124000 { 541 frame-number = <2>; 542 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 543 reg = <0x0 0x0b124000 0x0 0x1000>; 544 status = "disabled"; 545 }; 546 547 frame@b125000 { 548 frame-number = <3>; 549 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 550 reg = <0x0 0x0b125000 0x0 0x1000>; 551 status = "disabled"; 552 }; 553 554 frame@b126000 { 555 frame-number = <4>; 556 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 557 reg = <0x0 0x0b126000 0x0 0x1000>; 558 status = "disabled"; 559 }; 560 561 frame@b127000 { 562 frame-number = <5>; 563 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 564 reg = <0x0 0x0b127000 0x0 0x1000>; 565 status = "disabled"; 566 }; 567 568 frame@b128000 { 569 frame-number = <6>; 570 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 571 reg = <0x0 0x0b128000 0x0 0x1000>; 572 status = "disabled"; 573 }; 574 }; 575 576 q6v5_wcss: remoteproc@cd00000 { 577 compatible = "qcom,ipq6018-wcss-pil"; 578 reg = <0x0 0x0cd00000 0x0 0x4040>, 579 <0x0 0x004ab000 0x0 0x20>; 580 reg-names = "qdsp6", 581 "rmb"; 582 interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, 583 <&wcss_smp2p_in 0 0>, 584 <&wcss_smp2p_in 1 0>, 585 <&wcss_smp2p_in 2 0>, 586 <&wcss_smp2p_in 3 0>; 587 interrupt-names = "wdog", 588 "fatal", 589 "ready", 590 "handover", 591 "stop-ack"; 592 593 resets = <&gcc GCC_WCSSAON_RESET>, 594 <&gcc GCC_WCSS_BCR>, 595 <&gcc GCC_WCSS_Q6_BCR>; 596 597 reset-names = "wcss_aon_reset", 598 "wcss_reset", 599 "wcss_q6_reset"; 600 601 clocks = <&gcc GCC_PRNG_AHB_CLK>; 602 clock-names = "prng"; 603 604 qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>; 605 606 qcom,smem-states = <&wcss_smp2p_out 0>, 607 <&wcss_smp2p_out 1>; 608 qcom,smem-state-names = "shutdown", 609 "stop"; 610 611 memory-region = <&q6_region>; 612 613 glink-edge { 614 interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>; 615 qcom,remote-pid = <1>; 616 mboxes = <&apcs_glb 8>; 617 618 qrtr_requests { 619 qcom,glink-channels = "IPCRTR"; 620 }; 621 }; 622 }; 623 624 qusb_phy_1: qusb@59000 { 625 compatible = "qcom,ipq6018-qusb2-phy"; 626 reg = <0x0 0x059000 0x0 0x180>; 627 #phy-cells = <0>; 628 629 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 630 <&xo>; 631 clock-names = "cfg_ahb", "ref"; 632 633 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 634 status = "disabled"; 635 }; 636 637 usb2: usb2@7000000 { 638 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; 639 reg = <0x0 0x070F8800 0x0 0x400>; 640 #address-cells = <2>; 641 #size-cells = <2>; 642 ranges; 643 clocks = <&gcc GCC_USB1_MASTER_CLK>, 644 <&gcc GCC_USB1_SLEEP_CLK>, 645 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 646 clock-names = "master", 647 "sleep", 648 "mock_utmi"; 649 650 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, 651 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 652 assigned-clock-rates = <133330000>, 653 <24000000>; 654 resets = <&gcc GCC_USB1_BCR>; 655 status = "disabled"; 656 657 dwc_1: usb@7000000 { 658 compatible = "snps,dwc3"; 659 reg = <0x0 0x7000000 0x0 0xcd00>; 660 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 661 phys = <&qusb_phy_1>; 662 phy-names = "usb2-phy"; 663 tx-fifo-resize; 664 snps,is-utmi-l1-suspend; 665 snps,hird-threshold = /bits/ 8 <0x0>; 666 snps,dis_u2_susphy_quirk; 667 snps,dis_u3_susphy_quirk; 668 dr_mode = "host"; 669 }; 670 }; 671 672 ssphy_0: ssphy@78000 { 673 compatible = "qcom,ipq6018-qmp-usb3-phy"; 674 reg = <0x0 0x78000 0x0 0x1C4>; 675 #address-cells = <2>; 676 #size-cells = <2>; 677 #clock-cells = <1>; 678 ranges; 679 680 clocks = <&gcc GCC_USB0_AUX_CLK>, 681 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>; 682 clock-names = "aux", "cfg_ahb", "ref"; 683 684 resets = <&gcc GCC_USB0_PHY_BCR>, 685 <&gcc GCC_USB3PHY_0_PHY_BCR>; 686 reset-names = "phy","common"; 687 status = "disabled"; 688 689 usb0_ssphy: lane@78200 { 690 reg = <0x0 0x00078200 0x0 0x130>, /* Tx */ 691 <0x0 0x00078400 0x0 0x200>, /* Rx */ 692 <0x0 0x00078800 0x0 0x1F8>, /* PCS */ 693 <0x0 0x00078600 0x0 0x044>; /* PCS misc */ 694 #phy-cells = <0>; 695 clocks = <&gcc GCC_USB0_PIPE_CLK>; 696 clock-names = "pipe0"; 697 clock-output-names = "gcc_usb0_pipe_clk_src"; 698 }; 699 }; 700 701 qusb_phy_0: qusb@79000 { 702 compatible = "qcom,ipq6018-qusb2-phy"; 703 reg = <0x0 0x079000 0x0 0x180>; 704 #phy-cells = <0>; 705 706 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 707 <&xo>; 708 clock-names = "cfg_ahb", "ref"; 709 710 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 711 status = "disabled"; 712 }; 713 714 usb3: usb3@8A00000 { 715 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; 716 reg = <0x0 0x8AF8800 0x0 0x400>; 717 #address-cells = <2>; 718 #size-cells = <2>; 719 ranges; 720 721 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 722 <&gcc GCC_USB0_MASTER_CLK>, 723 <&gcc GCC_USB0_SLEEP_CLK>, 724 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 725 clock-names = "sys_noc_axi", 726 "master", 727 "sleep", 728 "mock_utmi"; 729 730 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 731 <&gcc GCC_USB0_MASTER_CLK>, 732 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 733 assigned-clock-rates = <133330000>, 734 <133330000>, 735 <20000000>; 736 737 resets = <&gcc GCC_USB0_BCR>; 738 status = "disabled"; 739 740 dwc_0: usb@8A00000 { 741 compatible = "snps,dwc3"; 742 reg = <0x0 0x8A00000 0x0 0xcd00>; 743 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 744 phys = <&qusb_phy_0>, <&usb0_ssphy>; 745 phy-names = "usb2-phy", "usb3-phy"; 746 tx-fifo-resize; 747 snps,is-utmi-l1-suspend; 748 snps,hird-threshold = /bits/ 8 <0x0>; 749 snps,dis_u2_susphy_quirk; 750 snps,dis_u3_susphy_quirk; 751 snps,ref-clock-period-ns = <0x32>; 752 dr_mode = "host"; 753 }; 754 }; 755 }; 756 757 wcss: wcss-smp2p { 758 compatible = "qcom,smp2p"; 759 qcom,smem = <435>, <428>; 760 761 interrupt-parent = <&intc>; 762 interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>; 763 764 mboxes = <&apcs_glb 9>; 765 766 qcom,local-pid = <0>; 767 qcom,remote-pid = <1>; 768 769 wcss_smp2p_out: master-kernel { 770 qcom,entry-name = "master-kernel"; 771 #qcom,smem-state-cells = <1>; 772 }; 773 774 wcss_smp2p_in: slave-kernel { 775 qcom,entry-name = "slave-kernel"; 776 interrupt-controller; 777 #interrupt-cells = <2>; 778 }; 779 }; 780 781 rpm-glink { 782 compatible = "qcom,glink-rpm"; 783 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 784 qcom,rpm-msg-ram = <&rpm_msg_ram>; 785 mboxes = <&apcs_glb 0>; 786 787 rpm_requests: glink-channel { 788 compatible = "qcom,rpm-ipq6018"; 789 qcom,glink-channels = "rpm_requests"; 790 791 regulators { 792 compatible = "qcom,rpm-mp5496-regulators"; 793 794 ipq6018_s2: s2 { 795 regulator-min-microvolt = <725000>; 796 regulator-max-microvolt = <1062500>; 797 regulator-always-on; 798 }; 799 }; 800 }; 801 }; 802}; 803