1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ6018 SoC device tree source 4 * 5 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,gcc-ipq6018.h> 10#include <dt-bindings/reset/qcom,gcc-ipq6018.h> 11#include <dt-bindings/clock/qcom,apss-ipq.h> 12 13/ { 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&intc>; 17 18 clocks { 19 sleep_clk: sleep-clk { 20 compatible = "fixed-clock"; 21 clock-frequency = <32000>; 22 #clock-cells = <0>; 23 }; 24 25 xo: xo { 26 compatible = "fixed-clock"; 27 clock-frequency = <24000000>; 28 #clock-cells = <0>; 29 }; 30 }; 31 32 cpus: cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 CPU0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a53"; 39 reg = <0x0>; 40 enable-method = "psci"; 41 next-level-cache = <&L2_0>; 42 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 43 clock-names = "cpu"; 44 operating-points-v2 = <&cpu_opp_table>; 45 cpu-supply = <&ipq6018_s2>; 46 }; 47 48 CPU1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53"; 51 enable-method = "psci"; 52 reg = <0x1>; 53 next-level-cache = <&L2_0>; 54 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 55 clock-names = "cpu"; 56 operating-points-v2 = <&cpu_opp_table>; 57 cpu-supply = <&ipq6018_s2>; 58 }; 59 60 CPU2: cpu@2 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 enable-method = "psci"; 64 reg = <0x2>; 65 next-level-cache = <&L2_0>; 66 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 67 clock-names = "cpu"; 68 operating-points-v2 = <&cpu_opp_table>; 69 cpu-supply = <&ipq6018_s2>; 70 }; 71 72 CPU3: cpu@3 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a53"; 75 enable-method = "psci"; 76 reg = <0x3>; 77 next-level-cache = <&L2_0>; 78 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 79 clock-names = "cpu"; 80 operating-points-v2 = <&cpu_opp_table>; 81 cpu-supply = <&ipq6018_s2>; 82 }; 83 84 L2_0: l2-cache { 85 compatible = "cache"; 86 cache-level = <0x2>; 87 }; 88 }; 89 90 firmware { 91 scm { 92 compatible = "qcom,scm-ipq6018", "qcom,scm"; 93 qcom,dload-mode = <&tcsr 0x6100>; 94 }; 95 }; 96 97 cpu_opp_table: opp-table-cpu { 98 compatible = "operating-points-v2"; 99 opp-shared; 100 101 opp-864000000 { 102 opp-hz = /bits/ 64 <864000000>; 103 opp-microvolt = <725000>; 104 clock-latency-ns = <200000>; 105 }; 106 107 opp-1056000000 { 108 opp-hz = /bits/ 64 <1056000000>; 109 opp-microvolt = <787500>; 110 clock-latency-ns = <200000>; 111 }; 112 113 opp-1320000000 { 114 opp-hz = /bits/ 64 <1320000000>; 115 opp-microvolt = <862500>; 116 clock-latency-ns = <200000>; 117 }; 118 119 opp-1440000000 { 120 opp-hz = /bits/ 64 <1440000000>; 121 opp-microvolt = <925000>; 122 clock-latency-ns = <200000>; 123 }; 124 125 opp-1608000000 { 126 opp-hz = /bits/ 64 <1608000000>; 127 opp-microvolt = <987500>; 128 clock-latency-ns = <200000>; 129 }; 130 131 opp-1800000000 { 132 opp-hz = /bits/ 64 <1800000000>; 133 opp-microvolt = <1062500>; 134 clock-latency-ns = <200000>; 135 }; 136 }; 137 138 pmuv8: pmu { 139 compatible = "arm,cortex-a53-pmu"; 140 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 141 }; 142 143 psci: psci { 144 compatible = "arm,psci-1.0"; 145 method = "smc"; 146 }; 147 148 reserved-memory { 149 #address-cells = <2>; 150 #size-cells = <2>; 151 ranges; 152 153 rpm_msg_ram: memory@60000 { 154 reg = <0x0 0x00060000 0x0 0x6000>; 155 no-map; 156 }; 157 158 bootloader@4a100000 { 159 reg = <0x0 0x4a100000 0x0 0x400000>; 160 no-map; 161 }; 162 163 sbl@4a500000 { 164 reg = <0x0 0x4a500000 0x0 0x100000>; 165 no-map; 166 }; 167 168 tz: memory@4a600000 { 169 reg = <0x0 0x4a600000 0x0 0x400000>; 170 no-map; 171 }; 172 173 smem_region: memory@4aa00000 { 174 reg = <0x0 0x4aa00000 0x0 0x100000>; 175 no-map; 176 }; 177 178 q6_region: memory@4ab00000 { 179 reg = <0x0 0x4ab00000 0x0 0x5500000>; 180 no-map; 181 }; 182 }; 183 184 rpm-glink { 185 compatible = "qcom,glink-rpm"; 186 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 187 qcom,rpm-msg-ram = <&rpm_msg_ram>; 188 mboxes = <&apcs_glb 0>; 189 190 rpm_requests: rpm-requests { 191 compatible = "qcom,rpm-ipq6018"; 192 qcom,glink-channels = "rpm_requests"; 193 194 regulators { 195 compatible = "qcom,rpm-mp5496-regulators"; 196 197 ipq6018_s2: s2 { 198 regulator-min-microvolt = <725000>; 199 regulator-max-microvolt = <1062500>; 200 regulator-always-on; 201 }; 202 }; 203 }; 204 }; 205 206 smem { 207 compatible = "qcom,smem"; 208 memory-region = <&smem_region>; 209 hwlocks = <&tcsr_mutex 0>; 210 }; 211 212 soc: soc@0 { 213 #address-cells = <2>; 214 #size-cells = <2>; 215 ranges = <0 0 0 0 0x0 0xffffffff>; 216 dma-ranges; 217 compatible = "simple-bus"; 218 219 qusb_phy_1: qusb@59000 { 220 compatible = "qcom,ipq6018-qusb2-phy"; 221 reg = <0x0 0x00059000 0x0 0x180>; 222 #phy-cells = <0>; 223 224 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 225 <&xo>; 226 clock-names = "cfg_ahb", "ref"; 227 228 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 229 status = "disabled"; 230 }; 231 232 ssphy_0: ssphy@78000 { 233 compatible = "qcom,ipq6018-qmp-usb3-phy"; 234 reg = <0x0 0x00078000 0x0 0x1c4>; 235 #address-cells = <2>; 236 #size-cells = <2>; 237 ranges; 238 239 clocks = <&gcc GCC_USB0_AUX_CLK>, 240 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>; 241 clock-names = "aux", "cfg_ahb", "ref"; 242 243 resets = <&gcc GCC_USB0_PHY_BCR>, 244 <&gcc GCC_USB3PHY_0_PHY_BCR>; 245 reset-names = "phy","common"; 246 status = "disabled"; 247 248 usb0_ssphy: phy@78200 { 249 reg = <0x0 0x00078200 0x0 0x130>, /* Tx */ 250 <0x0 0x00078400 0x0 0x200>, /* Rx */ 251 <0x0 0x00078800 0x0 0x1f8>, /* PCS */ 252 <0x0 0x00078600 0x0 0x044>; /* PCS misc */ 253 #phy-cells = <0>; 254 #clock-cells = <0>; 255 clocks = <&gcc GCC_USB0_PIPE_CLK>; 256 clock-names = "pipe0"; 257 clock-output-names = "gcc_usb0_pipe_clk_src"; 258 }; 259 }; 260 261 qusb_phy_0: qusb@79000 { 262 compatible = "qcom,ipq6018-qusb2-phy"; 263 reg = <0x0 0x00079000 0x0 0x180>; 264 #phy-cells = <0>; 265 266 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 267 <&xo>; 268 clock-names = "cfg_ahb", "ref"; 269 270 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 271 status = "disabled"; 272 }; 273 274 pcie_phy: phy@84000 { 275 compatible = "qcom,ipq6018-qmp-pcie-phy"; 276 reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */ 277 status = "disabled"; 278 #address-cells = <2>; 279 #size-cells = <2>; 280 ranges; 281 282 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 283 <&gcc GCC_PCIE0_AHB_CLK>; 284 clock-names = "aux", "cfg_ahb"; 285 286 resets = <&gcc GCC_PCIE0_PHY_BCR>, 287 <&gcc GCC_PCIE0PHY_PHY_BCR>; 288 reset-names = "phy", 289 "common"; 290 291 pcie_phy0: phy@84200 { 292 reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */ 293 <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */ 294 <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */ 295 <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */ 296 #phy-cells = <0>; 297 298 clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 299 clock-names = "pipe0"; 300 clock-output-names = "gcc_pcie0_pipe_clk_src"; 301 #clock-cells = <0>; 302 }; 303 }; 304 305 mdio: mdio@90000 { 306 #address-cells = <1>; 307 #size-cells = <0>; 308 compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio"; 309 reg = <0x0 0x00090000 0x0 0x64>; 310 clocks = <&gcc GCC_MDIO_AHB_CLK>; 311 clock-names = "gcc_mdio_ahb_clk"; 312 status = "disabled"; 313 }; 314 315 qfprom: efuse@a4000 { 316 compatible = "qcom,ipq6018-qfprom", "qcom,qfprom"; 317 reg = <0x0 0x000a4000 0x0 0x2000>; 318 #address-cells = <1>; 319 #size-cells = <1>; 320 }; 321 322 prng: qrng@e3000 { 323 compatible = "qcom,prng-ee"; 324 reg = <0x0 0x000e3000 0x0 0x1000>; 325 clocks = <&gcc GCC_PRNG_AHB_CLK>; 326 clock-names = "core"; 327 }; 328 329 cryptobam: dma-controller@704000 { 330 compatible = "qcom,bam-v1.7.0"; 331 reg = <0x0 0x00704000 0x0 0x20000>; 332 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 334 clock-names = "bam_clk"; 335 #dma-cells = <1>; 336 qcom,ee = <1>; 337 qcom,controlled-remotely; 338 }; 339 340 crypto: crypto@73a000 { 341 compatible = "qcom,crypto-v5.1"; 342 reg = <0x0 0x0073a000 0x0 0x6000>; 343 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 344 <&gcc GCC_CRYPTO_AXI_CLK>, 345 <&gcc GCC_CRYPTO_CLK>; 346 clock-names = "iface", "bus", "core"; 347 dmas = <&cryptobam 2>, <&cryptobam 3>; 348 dma-names = "rx", "tx"; 349 }; 350 351 tlmm: pinctrl@1000000 { 352 compatible = "qcom,ipq6018-pinctrl"; 353 reg = <0x0 0x01000000 0x0 0x300000>; 354 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 355 gpio-controller; 356 #gpio-cells = <2>; 357 gpio-ranges = <&tlmm 0 0 80>; 358 interrupt-controller; 359 #interrupt-cells = <2>; 360 361 serial_3_pins: serial3-state { 362 pins = "gpio44", "gpio45"; 363 function = "blsp2_uart"; 364 drive-strength = <8>; 365 bias-pull-down; 366 }; 367 368 qpic_pins: qpic-state { 369 pins = "gpio1", "gpio3", "gpio4", 370 "gpio5", "gpio6", "gpio7", 371 "gpio8", "gpio10", "gpio11", 372 "gpio12", "gpio13", "gpio14", 373 "gpio15", "gpio17"; 374 function = "qpic_pad"; 375 drive-strength = <8>; 376 bias-disable; 377 }; 378 }; 379 380 gcc: gcc@1800000 { 381 compatible = "qcom,gcc-ipq6018"; 382 reg = <0x0 0x01800000 0x0 0x80000>; 383 clocks = <&xo>, <&sleep_clk>; 384 clock-names = "xo", "sleep_clk"; 385 #clock-cells = <1>; 386 #reset-cells = <1>; 387 }; 388 389 tcsr_mutex: hwlock@1905000 { 390 compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex"; 391 reg = <0x0 0x01905000 0x0 0x1000>; 392 #hwlock-cells = <1>; 393 }; 394 395 tcsr: syscon@1937000 { 396 compatible = "qcom,tcsr-ipq6018", "syscon"; 397 reg = <0x0 0x01937000 0x0 0x21000>; 398 }; 399 400 usb2: usb@70f8800 { 401 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; 402 reg = <0x0 0x070f8800 0x0 0x400>; 403 #address-cells = <2>; 404 #size-cells = <2>; 405 ranges; 406 clocks = <&gcc GCC_USB1_MASTER_CLK>, 407 <&gcc GCC_USB1_SLEEP_CLK>, 408 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 409 clock-names = "core", 410 "sleep", 411 "mock_utmi"; 412 413 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, 414 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 415 assigned-clock-rates = <133330000>, 416 <24000000>; 417 resets = <&gcc GCC_USB1_BCR>; 418 status = "disabled"; 419 420 dwc_1: usb@7000000 { 421 compatible = "snps,dwc3"; 422 reg = <0x0 0x07000000 0x0 0xcd00>; 423 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 424 phys = <&qusb_phy_1>; 425 phy-names = "usb2-phy"; 426 tx-fifo-resize; 427 snps,is-utmi-l1-suspend; 428 snps,hird-threshold = /bits/ 8 <0x0>; 429 snps,dis_u2_susphy_quirk; 430 snps,dis_u3_susphy_quirk; 431 dr_mode = "host"; 432 }; 433 }; 434 435 blsp_dma: dma-controller@7884000 { 436 compatible = "qcom,bam-v1.7.0"; 437 reg = <0x0 0x07884000 0x0 0x2b000>; 438 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 440 clock-names = "bam_clk"; 441 #dma-cells = <1>; 442 qcom,ee = <0>; 443 }; 444 445 blsp1_uart3: serial@78b1000 { 446 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 447 reg = <0x0 0x078b1000 0x0 0x200>; 448 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 450 <&gcc GCC_BLSP1_AHB_CLK>; 451 clock-names = "core", "iface"; 452 status = "disabled"; 453 }; 454 455 blsp1_spi1: spi@78b5000 { 456 compatible = "qcom,spi-qup-v2.2.1"; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 reg = <0x0 0x078b5000 0x0 0x600>; 460 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 461 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 462 <&gcc GCC_BLSP1_AHB_CLK>; 463 clock-names = "core", "iface"; 464 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 465 dma-names = "tx", "rx"; 466 status = "disabled"; 467 }; 468 469 blsp1_spi2: spi@78b6000 { 470 compatible = "qcom,spi-qup-v2.2.1"; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 reg = <0x0 0x078b6000 0x0 0x600>; 474 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 475 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 476 <&gcc GCC_BLSP1_AHB_CLK>; 477 clock-names = "core", "iface"; 478 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 479 dma-names = "tx", "rx"; 480 status = "disabled"; 481 }; 482 483 blsp1_i2c2: i2c@78b6000 { 484 compatible = "qcom,i2c-qup-v2.2.1"; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 reg = <0x0 0x078b6000 0x0 0x600>; 488 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 490 <&gcc GCC_BLSP1_AHB_CLK>; 491 clock-names = "core", "iface"; 492 clock-frequency = <400000>; 493 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 494 dma-names = "tx", "rx"; 495 status = "disabled"; 496 }; 497 498 blsp1_i2c3: i2c@78b7000 { 499 compatible = "qcom,i2c-qup-v2.2.1"; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 reg = <0x0 0x078b7000 0x0 0x600>; 503 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 505 <&gcc GCC_BLSP1_AHB_CLK>; 506 clock-names = "core", "iface"; 507 clock-frequency = <400000>; 508 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 509 dma-names = "tx", "rx"; 510 status = "disabled"; 511 }; 512 513 qpic_bam: dma-controller@7984000 { 514 compatible = "qcom,bam-v1.7.0"; 515 reg = <0x0 0x07984000 0x0 0x1a000>; 516 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&gcc GCC_QPIC_AHB_CLK>; 518 clock-names = "bam_clk"; 519 #dma-cells = <1>; 520 qcom,ee = <0>; 521 status = "disabled"; 522 }; 523 524 qpic_nand: nand-controller@79b0000 { 525 compatible = "qcom,ipq6018-nand"; 526 reg = <0x0 0x079b0000 0x0 0x10000>; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 clocks = <&gcc GCC_QPIC_CLK>, 530 <&gcc GCC_QPIC_AHB_CLK>; 531 clock-names = "core", "aon"; 532 533 dmas = <&qpic_bam 0>, 534 <&qpic_bam 1>, 535 <&qpic_bam 2>; 536 dma-names = "tx", "rx", "cmd"; 537 pinctrl-0 = <&qpic_pins>; 538 pinctrl-names = "default"; 539 status = "disabled"; 540 }; 541 542 usb3: usb@8af8800 { 543 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; 544 reg = <0x0 0x08af8800 0x0 0x400>; 545 #address-cells = <2>; 546 #size-cells = <2>; 547 ranges; 548 549 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 550 <&gcc GCC_USB0_MASTER_CLK>, 551 <&gcc GCC_USB0_SLEEP_CLK>, 552 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 553 clock-names = "cfg_noc", 554 "core", 555 "sleep", 556 "mock_utmi"; 557 558 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 559 <&gcc GCC_USB0_MASTER_CLK>, 560 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 561 assigned-clock-rates = <133330000>, 562 <133330000>, 563 <20000000>; 564 565 resets = <&gcc GCC_USB0_BCR>; 566 status = "disabled"; 567 568 dwc_0: usb@8a00000 { 569 compatible = "snps,dwc3"; 570 reg = <0x0 0x08a00000 0x0 0xcd00>; 571 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 572 phys = <&qusb_phy_0>, <&usb0_ssphy>; 573 phy-names = "usb2-phy", "usb3-phy"; 574 clocks = <&xo>; 575 clock-names = "ref"; 576 tx-fifo-resize; 577 snps,is-utmi-l1-suspend; 578 snps,hird-threshold = /bits/ 8 <0x0>; 579 snps,dis_u2_susphy_quirk; 580 snps,dis_u3_susphy_quirk; 581 dr_mode = "host"; 582 }; 583 }; 584 585 intc: interrupt-controller@b000000 { 586 compatible = "qcom,msm-qgic2"; 587 #address-cells = <2>; 588 #size-cells = <2>; 589 interrupt-controller; 590 #interrupt-cells = <3>; 591 reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ 592 <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ 593 <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ 594 <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ 595 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 596 ranges = <0 0 0 0xb00a000 0 0xffd>; 597 598 v2m@0 { 599 compatible = "arm,gic-v2m-frame"; 600 msi-controller; 601 reg = <0x0 0x0 0x0 0xffd>; 602 }; 603 }; 604 605 watchdog@b017000 { 606 compatible = "qcom,kpss-wdt"; 607 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 608 reg = <0x0 0x0b017000 0x0 0x40>; 609 clocks = <&sleep_clk>; 610 timeout-sec = <10>; 611 }; 612 613 apcs_glb: mailbox@b111000 { 614 compatible = "qcom,ipq6018-apcs-apps-global"; 615 reg = <0x0 0x0b111000 0x0 0x1000>; 616 #clock-cells = <1>; 617 clocks = <&a53pll>, <&xo>; 618 clock-names = "pll", "xo"; 619 #mbox-cells = <1>; 620 }; 621 622 a53pll: clock@b116000 { 623 compatible = "qcom,ipq6018-a53pll"; 624 reg = <0x0 0x0b116000 0x0 0x40>; 625 #clock-cells = <0>; 626 clocks = <&xo>; 627 clock-names = "xo"; 628 }; 629 630 timer@b120000 { 631 #address-cells = <1>; 632 #size-cells = <1>; 633 ranges = <0 0 0 0x10000000>; 634 compatible = "arm,armv7-timer-mem"; 635 reg = <0x0 0x0b120000 0x0 0x1000>; 636 637 frame@b120000 { 638 frame-number = <0>; 639 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 641 reg = <0x0b121000 0x1000>, 642 <0x0b122000 0x1000>; 643 }; 644 645 frame@b123000 { 646 frame-number = <1>; 647 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 648 reg = <0x0b123000 0x1000>; 649 status = "disabled"; 650 }; 651 652 frame@b124000 { 653 frame-number = <2>; 654 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 655 reg = <0x0b124000 0x1000>; 656 status = "disabled"; 657 }; 658 659 frame@b125000 { 660 frame-number = <3>; 661 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 662 reg = <0x0b125000 0x1000>; 663 status = "disabled"; 664 }; 665 666 frame@b126000 { 667 frame-number = <4>; 668 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 669 reg = <0x0b126000 0x1000>; 670 status = "disabled"; 671 }; 672 673 frame@b127000 { 674 frame-number = <5>; 675 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 676 reg = <0x0b127000 0x1000>; 677 status = "disabled"; 678 }; 679 680 frame@b128000 { 681 frame-number = <6>; 682 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 683 reg = <0x0b128000 0x1000>; 684 status = "disabled"; 685 }; 686 }; 687 688 q6v5_wcss: remoteproc@cd00000 { 689 compatible = "qcom,ipq6018-wcss-pil"; 690 reg = <0x0 0x0cd00000 0x0 0x4040>, 691 <0x0 0x004ab000 0x0 0x20>; 692 reg-names = "qdsp6", 693 "rmb"; 694 interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, 695 <&wcss_smp2p_in 0 0>, 696 <&wcss_smp2p_in 1 0>, 697 <&wcss_smp2p_in 2 0>, 698 <&wcss_smp2p_in 3 0>; 699 interrupt-names = "wdog", 700 "fatal", 701 "ready", 702 "handover", 703 "stop-ack"; 704 705 resets = <&gcc GCC_WCSSAON_RESET>, 706 <&gcc GCC_WCSS_BCR>, 707 <&gcc GCC_WCSS_Q6_BCR>; 708 709 reset-names = "wcss_aon_reset", 710 "wcss_reset", 711 "wcss_q6_reset"; 712 713 clocks = <&gcc GCC_PRNG_AHB_CLK>; 714 clock-names = "prng"; 715 716 qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>; 717 718 qcom,smem-states = <&wcss_smp2p_out 0>, 719 <&wcss_smp2p_out 1>; 720 qcom,smem-state-names = "shutdown", 721 "stop"; 722 723 memory-region = <&q6_region>; 724 725 glink-edge { 726 interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>; 727 label = "rtr"; 728 qcom,remote-pid = <1>; 729 mboxes = <&apcs_glb 8>; 730 731 qrtr_requests { 732 qcom,glink-channels = "IPCRTR"; 733 }; 734 }; 735 }; 736 737 pcie0: pci@20000000 { 738 compatible = "qcom,pcie-ipq6018"; 739 reg = <0x0 0x20000000 0x0 0xf1d>, 740 <0x0 0x20000f20 0x0 0xa8>, 741 <0x0 0x20001000 0x0 0x1000>, 742 <0x0 0x80000 0x0 0x4000>, 743 <0x0 0x20100000 0x0 0x1000>; 744 reg-names = "dbi", "elbi", "atu", "parf", "config"; 745 746 device_type = "pci"; 747 linux,pci-domain = <0>; 748 bus-range = <0x00 0xff>; 749 num-lanes = <1>; 750 max-link-speed = <3>; 751 #address-cells = <3>; 752 #size-cells = <2>; 753 754 phys = <&pcie_phy0>; 755 phy-names = "pciephy"; 756 757 ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>, 758 <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>; 759 760 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 761 interrupt-names = "msi"; 762 763 #interrupt-cells = <1>; 764 interrupt-map-mask = <0 0 0 0x7>; 765 interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 766 <0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 767 <0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 768 <0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 769 770 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 771 <&gcc GCC_PCIE0_AXI_M_CLK>, 772 <&gcc GCC_PCIE0_AXI_S_CLK>, 773 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 774 <&gcc PCIE0_RCHNG_CLK>; 775 clock-names = "iface", 776 "axi_m", 777 "axi_s", 778 "axi_bridge", 779 "rchng"; 780 781 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 782 <&gcc GCC_PCIE0_SLEEP_ARES>, 783 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 784 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 785 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 786 <&gcc GCC_PCIE0_AHB_ARES>, 787 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, 788 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; 789 reset-names = "pipe", 790 "sleep", 791 "sticky", 792 "axi_m", 793 "axi_s", 794 "ahb", 795 "axi_m_sticky", 796 "axi_s_sticky"; 797 798 status = "disabled"; 799 }; 800 }; 801 802 timer { 803 compatible = "arm,armv8-timer"; 804 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 805 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 806 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 807 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 808 }; 809 810 wcss: wcss-smp2p { 811 compatible = "qcom,smp2p"; 812 qcom,smem = <435>, <428>; 813 814 interrupt-parent = <&intc>; 815 interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>; 816 817 mboxes = <&apcs_glb 9>; 818 819 qcom,local-pid = <0>; 820 qcom,remote-pid = <1>; 821 822 wcss_smp2p_out: master-kernel { 823 qcom,entry-name = "master-kernel"; 824 #qcom,smem-state-cells = <1>; 825 }; 826 827 wcss_smp2p_in: slave-kernel { 828 qcom,entry-name = "slave-kernel"; 829 interrupt-controller; 830 #interrupt-cells = <2>; 831 }; 832 }; 833}; 834