16694aee0SLars Povlsen// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 26694aee0SLars Povlsen/* 36694aee0SLars Povlsen * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. 46694aee0SLars Povlsen */ 56694aee0SLars Povlsen 66694aee0SLars Povlsen#include <dt-bindings/gpio/gpio.h> 76694aee0SLars Povlsen#include <dt-bindings/interrupt-controller/arm-gic.h> 845145406SLars Povlsen#include <dt-bindings/clock/microchip,sparx5.h> 96694aee0SLars Povlsen 106694aee0SLars Povlsen/ { 116694aee0SLars Povlsen compatible = "microchip,sparx5"; 126694aee0SLars Povlsen interrupt-parent = <&gic>; 136694aee0SLars Povlsen #address-cells = <2>; 146694aee0SLars Povlsen #size-cells = <1>; 156694aee0SLars Povlsen 166694aee0SLars Povlsen aliases { 1708ee16e9SLars Povlsen spi0 = &spi0; 186694aee0SLars Povlsen serial0 = &uart0; 196694aee0SLars Povlsen serial1 = &uart1; 206694aee0SLars Povlsen }; 216694aee0SLars Povlsen 226694aee0SLars Povlsen chosen { 236694aee0SLars Povlsen stdout-path = "serial0:115200n8"; 246694aee0SLars Povlsen }; 256694aee0SLars Povlsen 266694aee0SLars Povlsen cpus { 276694aee0SLars Povlsen #address-cells = <2>; 286694aee0SLars Povlsen #size-cells = <0>; 296694aee0SLars Povlsen cpu-map { 306694aee0SLars Povlsen cluster0 { 316694aee0SLars Povlsen core0 { 326694aee0SLars Povlsen cpu = <&cpu0>; 336694aee0SLars Povlsen }; 346694aee0SLars Povlsen core1 { 356694aee0SLars Povlsen cpu = <&cpu1>; 366694aee0SLars Povlsen }; 376694aee0SLars Povlsen }; 386694aee0SLars Povlsen }; 396694aee0SLars Povlsen cpu0: cpu@0 { 406694aee0SLars Povlsen compatible = "arm,cortex-a53"; 416694aee0SLars Povlsen device_type = "cpu"; 426694aee0SLars Povlsen reg = <0x0 0x0>; 436694aee0SLars Povlsen enable-method = "psci"; 446694aee0SLars Povlsen next-level-cache = <&L2_0>; 456694aee0SLars Povlsen }; 466694aee0SLars Povlsen cpu1: cpu@1 { 476694aee0SLars Povlsen compatible = "arm,cortex-a53"; 486694aee0SLars Povlsen device_type = "cpu"; 496694aee0SLars Povlsen reg = <0x0 0x1>; 506694aee0SLars Povlsen enable-method = "psci"; 516694aee0SLars Povlsen next-level-cache = <&L2_0>; 526694aee0SLars Povlsen }; 536694aee0SLars Povlsen L2_0: l2-cache0 { 546694aee0SLars Povlsen compatible = "cache"; 556694aee0SLars Povlsen }; 566694aee0SLars Povlsen }; 576694aee0SLars Povlsen 586694aee0SLars Povlsen arm-pmu { 596694aee0SLars Povlsen compatible = "arm,cortex-a53-pmu"; 606694aee0SLars Povlsen interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 616694aee0SLars Povlsen interrupt-affinity = <&cpu0>, <&cpu1>; 626694aee0SLars Povlsen }; 636694aee0SLars Povlsen 646694aee0SLars Povlsen psci { 656694aee0SLars Povlsen compatible = "arm,psci-0.2"; 666694aee0SLars Povlsen method = "smc"; 676694aee0SLars Povlsen }; 686694aee0SLars Povlsen 696694aee0SLars Povlsen timer { 706694aee0SLars Povlsen compatible = "arm,armv8-timer"; 716694aee0SLars Povlsen interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 726694aee0SLars Povlsen <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 736694aee0SLars Povlsen <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 746694aee0SLars Povlsen <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 756694aee0SLars Povlsen }; 766694aee0SLars Povlsen 77e4e06a50SLars Povlsen lcpll_clk: lcpll-clk { 78e4e06a50SLars Povlsen compatible = "fixed-clock"; 79e4e06a50SLars Povlsen #clock-cells = <0>; 80e4e06a50SLars Povlsen clock-frequency = <2500000000>; 81e4e06a50SLars Povlsen }; 82e4e06a50SLars Povlsen 83e4e06a50SLars Povlsen clks: clock-controller@61110000c { 84e4e06a50SLars Povlsen compatible = "microchip,sparx5-dpll"; 85e4e06a50SLars Povlsen #clock-cells = <1>; 86e4e06a50SLars Povlsen clocks = <&lcpll_clk>; 87e4e06a50SLars Povlsen reg = <0x6 0x1110000c 0x24>; 88e4e06a50SLars Povlsen }; 89e4e06a50SLars Povlsen 906694aee0SLars Povlsen ahb_clk: ahb-clk { 916694aee0SLars Povlsen compatible = "fixed-clock"; 926694aee0SLars Povlsen #clock-cells = <0>; 936694aee0SLars Povlsen clock-frequency = <250000000>; 946694aee0SLars Povlsen }; 95e4e06a50SLars Povlsen 966694aee0SLars Povlsen sys_clk: sys-clk { 976694aee0SLars Povlsen compatible = "fixed-clock"; 986694aee0SLars Povlsen #clock-cells = <0>; 996694aee0SLars Povlsen clock-frequency = <625000000>; 1006694aee0SLars Povlsen }; 1016694aee0SLars Povlsen 1026694aee0SLars Povlsen axi: axi@600000000 { 1036694aee0SLars Povlsen compatible = "simple-bus"; 1046694aee0SLars Povlsen #address-cells = <2>; 1056694aee0SLars Povlsen #size-cells = <1>; 1066694aee0SLars Povlsen ranges; 1076694aee0SLars Povlsen 1086694aee0SLars Povlsen gic: interrupt-controller@600300000 { 1096694aee0SLars Povlsen compatible = "arm,gic-v3"; 1106694aee0SLars Povlsen #interrupt-cells = <3>; 1116694aee0SLars Povlsen #address-cells = <2>; 1126694aee0SLars Povlsen #size-cells = <2>; 1136694aee0SLars Povlsen interrupt-controller; 1146694aee0SLars Povlsen reg = <0x6 0x00300000 0x10000>, /* GIC Dist */ 1156694aee0SLars Povlsen <0x6 0x00340000 0xc0000>, /* GICR */ 1166694aee0SLars Povlsen <0x6 0x00200000 0x2000>, /* GICC */ 1176694aee0SLars Povlsen <0x6 0x00210000 0x2000>, /* GICV */ 1186694aee0SLars Povlsen <0x6 0x00220000 0x2000>; /* GICH */ 1196694aee0SLars Povlsen interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1206694aee0SLars Povlsen }; 1216694aee0SLars Povlsen 12208ee16e9SLars Povlsen cpu_ctrl: syscon@600000000 { 12308ee16e9SLars Povlsen compatible = "microchip,sparx5-cpu-syscon", "syscon", 12408ee16e9SLars Povlsen "simple-mfd"; 12508ee16e9SLars Povlsen reg = <0x6 0x00000000 0xd0>; 12608ee16e9SLars Povlsen mux: mux-controller { 12708ee16e9SLars Povlsen compatible = "mmio-mux"; 12808ee16e9SLars Povlsen #mux-control-cells = <0>; 12908ee16e9SLars Povlsen /* 13008ee16e9SLars Povlsen * SI_OWNER and SI2_OWNER in GENERAL_CTRL 13108ee16e9SLars Povlsen * SPI: value 9 - (SIMC,SIBM) = 0b1001 13208ee16e9SLars Povlsen * SPI2: value 6 - (SIBM,SIMC) = 0b0110 13308ee16e9SLars Povlsen */ 13408ee16e9SLars Povlsen mux-reg-masks = <0x88 0xf0>; 13508ee16e9SLars Povlsen }; 13608ee16e9SLars Povlsen }; 13708ee16e9SLars Povlsen 138d0f482bbSSteen Hegelund reset: reset-controller@611010008 { 139d0f482bbSSteen Hegelund compatible = "microchip,sparx5-switch-reset"; 1405ef399aaSLars Povlsen reg = <0x6 0x11010008 0x4>; 141d0f482bbSSteen Hegelund reg-names = "gcb"; 142d0f482bbSSteen Hegelund #reset-cells = <1>; 143d0f482bbSSteen Hegelund cpu-syscon = <&cpu_ctrl>; 1445ef399aaSLars Povlsen }; 1455ef399aaSLars Povlsen 1466694aee0SLars Povlsen uart0: serial@600100000 { 14714bc6703SLars Povlsen pinctrl-0 = <&uart_pins>; 14814bc6703SLars Povlsen pinctrl-names = "default"; 1496694aee0SLars Povlsen compatible = "ns16550a"; 1506694aee0SLars Povlsen reg = <0x6 0x00100000 0x20>; 1516694aee0SLars Povlsen clocks = <&ahb_clk>; 1526694aee0SLars Povlsen reg-io-width = <4>; 1536694aee0SLars Povlsen reg-shift = <2>; 1546694aee0SLars Povlsen interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1556694aee0SLars Povlsen 1566694aee0SLars Povlsen status = "disabled"; 1576694aee0SLars Povlsen }; 1586694aee0SLars Povlsen 1596694aee0SLars Povlsen uart1: serial@600102000 { 16014bc6703SLars Povlsen pinctrl-0 = <&uart2_pins>; 16114bc6703SLars Povlsen pinctrl-names = "default"; 1626694aee0SLars Povlsen compatible = "ns16550a"; 1636694aee0SLars Povlsen reg = <0x6 0x00102000 0x20>; 1646694aee0SLars Povlsen clocks = <&ahb_clk>; 1656694aee0SLars Povlsen reg-io-width = <4>; 1666694aee0SLars Povlsen reg-shift = <2>; 1676694aee0SLars Povlsen interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1686694aee0SLars Povlsen 1696694aee0SLars Povlsen status = "disabled"; 1706694aee0SLars Povlsen }; 1716694aee0SLars Povlsen 17208ee16e9SLars Povlsen spi0: spi@600104000 { 17308ee16e9SLars Povlsen #address-cells = <1>; 17408ee16e9SLars Povlsen #size-cells = <0>; 17508ee16e9SLars Povlsen compatible = "microchip,sparx5-spi"; 17608ee16e9SLars Povlsen reg = <0x6 0x00104000 0x40>; 17708ee16e9SLars Povlsen num-cs = <16>; 17808ee16e9SLars Povlsen reg-io-width = <4>; 17908ee16e9SLars Povlsen reg-shift = <2>; 18008ee16e9SLars Povlsen clocks = <&ahb_clk>; 18108ee16e9SLars Povlsen interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 18208ee16e9SLars Povlsen status = "disabled"; 18308ee16e9SLars Povlsen }; 18408ee16e9SLars Povlsen 1856694aee0SLars Povlsen timer1: timer@600105000 { 1866694aee0SLars Povlsen compatible = "snps,dw-apb-timer"; 1876694aee0SLars Povlsen reg = <0x6 0x00105000 0x1000>; 1886694aee0SLars Povlsen clocks = <&ahb_clk>; 1896694aee0SLars Povlsen clock-names = "timer"; 1906694aee0SLars Povlsen interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1916694aee0SLars Povlsen }; 1926694aee0SLars Povlsen 19345145406SLars Povlsen sdhci0: mmc@600800000 { 19445145406SLars Povlsen compatible = "microchip,dw-sparx5-sdhci"; 19545145406SLars Povlsen status = "disabled"; 19645145406SLars Povlsen reg = <0x6 0x00800000 0x1000>; 19745145406SLars Povlsen pinctrl-0 = <&emmc_pins>; 19845145406SLars Povlsen pinctrl-names = "default"; 19945145406SLars Povlsen clocks = <&clks CLK_ID_AUX1>; 20045145406SLars Povlsen clock-names = "core"; 20145145406SLars Povlsen assigned-clocks = <&clks CLK_ID_AUX1>; 20245145406SLars Povlsen assigned-clock-rates = <800000000>; 20345145406SLars Povlsen interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 20445145406SLars Povlsen bus-width = <8>; 20545145406SLars Povlsen }; 20645145406SLars Povlsen 20714bc6703SLars Povlsen gpio: pinctrl@6110101e0 { 20814bc6703SLars Povlsen compatible = "microchip,sparx5-pinctrl"; 20914bc6703SLars Povlsen reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>; 21014bc6703SLars Povlsen gpio-controller; 21114bc6703SLars Povlsen #gpio-cells = <2>; 21214bc6703SLars Povlsen gpio-ranges = <&gpio 0 0 64>; 21314bc6703SLars Povlsen interrupt-controller; 21414bc6703SLars Povlsen interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 21514bc6703SLars Povlsen #interrupt-cells = <2>; 21614bc6703SLars Povlsen 2175df50128SLars Povlsen cs1_pins: cs1-pins { 2185df50128SLars Povlsen pins = "GPIO_16"; 2195df50128SLars Povlsen function = "si"; 2205df50128SLars Povlsen }; 2215df50128SLars Povlsen 2225df50128SLars Povlsen cs2_pins: cs2-pins { 2235df50128SLars Povlsen pins = "GPIO_17"; 2245df50128SLars Povlsen function = "si"; 2255df50128SLars Povlsen }; 2265df50128SLars Povlsen 2275df50128SLars Povlsen cs3_pins: cs3-pins { 2285df50128SLars Povlsen pins = "GPIO_18"; 2295df50128SLars Povlsen function = "si"; 2305df50128SLars Povlsen }; 2315df50128SLars Povlsen 2325df50128SLars Povlsen si2_pins: si2-pins { 2335df50128SLars Povlsen pins = "GPIO_39", "GPIO_40", "GPIO_41"; 2345df50128SLars Povlsen function = "si2"; 2355df50128SLars Povlsen }; 2365df50128SLars Povlsen 2377e1f91cbSLars Povlsen sgpio0_pins: sgpio-pins { 2387e1f91cbSLars Povlsen pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; 2397e1f91cbSLars Povlsen function = "sg0"; 2407e1f91cbSLars Povlsen }; 2417e1f91cbSLars Povlsen 2427e1f91cbSLars Povlsen sgpio1_pins: sgpio1-pins { 2437e1f91cbSLars Povlsen pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13"; 2447e1f91cbSLars Povlsen function = "sg1"; 2457e1f91cbSLars Povlsen }; 2467e1f91cbSLars Povlsen 2477e1f91cbSLars Povlsen sgpio2_pins: sgpio2-pins { 2487e1f91cbSLars Povlsen pins = "GPIO_30", "GPIO_31", "GPIO_32", 2497e1f91cbSLars Povlsen "GPIO_33"; 2507e1f91cbSLars Povlsen function = "sg2"; 2517e1f91cbSLars Povlsen }; 2527e1f91cbSLars Povlsen 25314bc6703SLars Povlsen uart_pins: uart-pins { 25414bc6703SLars Povlsen pins = "GPIO_10", "GPIO_11"; 25514bc6703SLars Povlsen function = "uart"; 25614bc6703SLars Povlsen }; 25714bc6703SLars Povlsen 25814bc6703SLars Povlsen uart2_pins: uart2-pins { 25914bc6703SLars Povlsen pins = "GPIO_26", "GPIO_27"; 26014bc6703SLars Povlsen function = "uart2"; 26114bc6703SLars Povlsen }; 262623910f4SLars Povlsen 263623910f4SLars Povlsen i2c_pins: i2c-pins { 264623910f4SLars Povlsen pins = "GPIO_14", "GPIO_15"; 265623910f4SLars Povlsen function = "twi"; 266623910f4SLars Povlsen }; 267623910f4SLars Povlsen 268623910f4SLars Povlsen i2c2_pins: i2c2-pins { 269623910f4SLars Povlsen pins = "GPIO_28", "GPIO_29"; 270623910f4SLars Povlsen function = "twi2"; 271623910f4SLars Povlsen }; 27245145406SLars Povlsen 27345145406SLars Povlsen emmc_pins: emmc-pins { 27445145406SLars Povlsen pins = "GPIO_34", "GPIO_35", "GPIO_36", 27545145406SLars Povlsen "GPIO_37", "GPIO_38", "GPIO_39", 27645145406SLars Povlsen "GPIO_40", "GPIO_41", "GPIO_42", 27745145406SLars Povlsen "GPIO_43", "GPIO_44", "GPIO_45", 27845145406SLars Povlsen "GPIO_46", "GPIO_47"; 27945145406SLars Povlsen function = "emmc"; 28045145406SLars Povlsen }; 281d0f482bbSSteen Hegelund 282d0f482bbSSteen Hegelund miim1_pins: miim1-pins { 283d0f482bbSSteen Hegelund pins = "GPIO_56", "GPIO_57"; 284d0f482bbSSteen Hegelund function = "miim"; 285d0f482bbSSteen Hegelund }; 286d0f482bbSSteen Hegelund 287d0f482bbSSteen Hegelund miim2_pins: miim2-pins { 288d0f482bbSSteen Hegelund pins = "GPIO_58", "GPIO_59"; 289d0f482bbSSteen Hegelund function = "miim"; 290d0f482bbSSteen Hegelund }; 291d0f482bbSSteen Hegelund 292d0f482bbSSteen Hegelund miim3_pins: miim3-pins { 293d0f482bbSSteen Hegelund pins = "GPIO_52", "GPIO_53"; 294d0f482bbSSteen Hegelund function = "miim"; 295d0f482bbSSteen Hegelund }; 296623910f4SLars Povlsen }; 297623910f4SLars Povlsen 2987e1f91cbSLars Povlsen sgpio0: gpio@61101036c { 2997e1f91cbSLars Povlsen #address-cells = <1>; 3007e1f91cbSLars Povlsen #size-cells = <0>; 3017e1f91cbSLars Povlsen compatible = "microchip,sparx5-sgpio"; 3027e1f91cbSLars Povlsen status = "disabled"; 3037e1f91cbSLars Povlsen clocks = <&sys_clk>; 3047e1f91cbSLars Povlsen pinctrl-0 = <&sgpio0_pins>; 3057e1f91cbSLars Povlsen pinctrl-names = "default"; 306d0f482bbSSteen Hegelund resets = <&reset 0>; 307d0f482bbSSteen Hegelund reset-names = "switch"; 3087e1f91cbSLars Povlsen reg = <0x6 0x1101036c 0x100>; 3097e1f91cbSLars Povlsen sgpio_in0: gpio@0 { 3107e1f91cbSLars Povlsen compatible = "microchip,sparx5-sgpio-bank"; 3117e1f91cbSLars Povlsen reg = <0>; 3127e1f91cbSLars Povlsen gpio-controller; 3137e1f91cbSLars Povlsen #gpio-cells = <3>; 3147e1f91cbSLars Povlsen ngpios = <96>; 315d0f482bbSSteen Hegelund interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 316d0f482bbSSteen Hegelund interrupt-controller; 317d0f482bbSSteen Hegelund #interrupt-cells = <3>; 3187e1f91cbSLars Povlsen }; 3197e1f91cbSLars Povlsen sgpio_out0: gpio@1 { 3207e1f91cbSLars Povlsen compatible = "microchip,sparx5-sgpio-bank"; 3217e1f91cbSLars Povlsen reg = <1>; 3227e1f91cbSLars Povlsen gpio-controller; 3237e1f91cbSLars Povlsen #gpio-cells = <3>; 3247e1f91cbSLars Povlsen ngpios = <96>; 3257e1f91cbSLars Povlsen }; 3267e1f91cbSLars Povlsen }; 3277e1f91cbSLars Povlsen 3287e1f91cbSLars Povlsen sgpio1: gpio@611010484 { 3297e1f91cbSLars Povlsen #address-cells = <1>; 3307e1f91cbSLars Povlsen #size-cells = <0>; 3317e1f91cbSLars Povlsen compatible = "microchip,sparx5-sgpio"; 3327e1f91cbSLars Povlsen status = "disabled"; 3337e1f91cbSLars Povlsen clocks = <&sys_clk>; 3347e1f91cbSLars Povlsen pinctrl-0 = <&sgpio1_pins>; 3357e1f91cbSLars Povlsen pinctrl-names = "default"; 336d0f482bbSSteen Hegelund resets = <&reset 0>; 337d0f482bbSSteen Hegelund reset-names = "switch"; 3387e1f91cbSLars Povlsen reg = <0x6 0x11010484 0x100>; 3397e1f91cbSLars Povlsen sgpio_in1: gpio@0 { 3407e1f91cbSLars Povlsen compatible = "microchip,sparx5-sgpio-bank"; 3417e1f91cbSLars Povlsen reg = <0>; 3427e1f91cbSLars Povlsen gpio-controller; 3437e1f91cbSLars Povlsen #gpio-cells = <3>; 3447e1f91cbSLars Povlsen ngpios = <96>; 345d0f482bbSSteen Hegelund interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 346d0f482bbSSteen Hegelund interrupt-controller; 347d0f482bbSSteen Hegelund #interrupt-cells = <3>; 3487e1f91cbSLars Povlsen }; 3497e1f91cbSLars Povlsen sgpio_out1: gpio@1 { 3507e1f91cbSLars Povlsen compatible = "microchip,sparx5-sgpio-bank"; 3517e1f91cbSLars Povlsen reg = <1>; 3527e1f91cbSLars Povlsen gpio-controller; 3537e1f91cbSLars Povlsen #gpio-cells = <3>; 3547e1f91cbSLars Povlsen ngpios = <96>; 3557e1f91cbSLars Povlsen }; 3567e1f91cbSLars Povlsen }; 3577e1f91cbSLars Povlsen 3587e1f91cbSLars Povlsen sgpio2: gpio@61101059c { 3597e1f91cbSLars Povlsen #address-cells = <1>; 3607e1f91cbSLars Povlsen #size-cells = <0>; 3617e1f91cbSLars Povlsen compatible = "microchip,sparx5-sgpio"; 3627e1f91cbSLars Povlsen status = "disabled"; 3637e1f91cbSLars Povlsen clocks = <&sys_clk>; 3647e1f91cbSLars Povlsen pinctrl-0 = <&sgpio2_pins>; 3657e1f91cbSLars Povlsen pinctrl-names = "default"; 366d0f482bbSSteen Hegelund resets = <&reset 0>; 367d0f482bbSSteen Hegelund reset-names = "switch"; 3687e1f91cbSLars Povlsen reg = <0x6 0x1101059c 0x100>; 3697e1f91cbSLars Povlsen sgpio_in2: gpio@0 { 3707e1f91cbSLars Povlsen reg = <0>; 3717e1f91cbSLars Povlsen compatible = "microchip,sparx5-sgpio-bank"; 3727e1f91cbSLars Povlsen gpio-controller; 3737e1f91cbSLars Povlsen #gpio-cells = <3>; 3747e1f91cbSLars Povlsen ngpios = <96>; 375d0f482bbSSteen Hegelund interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 376d0f482bbSSteen Hegelund interrupt-controller; 377d0f482bbSSteen Hegelund #interrupt-cells = <3>; 3787e1f91cbSLars Povlsen }; 3797e1f91cbSLars Povlsen sgpio_out2: gpio@1 { 3807e1f91cbSLars Povlsen compatible = "microchip,sparx5-sgpio-bank"; 3817e1f91cbSLars Povlsen reg = <1>; 3827e1f91cbSLars Povlsen gpio-controller; 3837e1f91cbSLars Povlsen #gpio-cells = <3>; 3847e1f91cbSLars Povlsen ngpios = <96>; 3857e1f91cbSLars Povlsen }; 3867e1f91cbSLars Povlsen }; 3877e1f91cbSLars Povlsen 388623910f4SLars Povlsen i2c0: i2c@600101000 { 389623910f4SLars Povlsen compatible = "snps,designware-i2c"; 390623910f4SLars Povlsen status = "disabled"; 391623910f4SLars Povlsen pinctrl-0 = <&i2c_pins>; 392623910f4SLars Povlsen pinctrl-names = "default"; 393623910f4SLars Povlsen reg = <0x6 0x00101000 0x100>; 394623910f4SLars Povlsen #address-cells = <1>; 395623910f4SLars Povlsen #size-cells = <0>; 396623910f4SLars Povlsen interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 397623910f4SLars Povlsen i2c-sda-hold-time-ns = <300>; 398623910f4SLars Povlsen clock-frequency = <100000>; 399623910f4SLars Povlsen clocks = <&ahb_clk>; 400623910f4SLars Povlsen }; 401623910f4SLars Povlsen 402623910f4SLars Povlsen i2c1: i2c@600103000 { 403623910f4SLars Povlsen compatible = "snps,designware-i2c"; 404623910f4SLars Povlsen status = "disabled"; 405623910f4SLars Povlsen pinctrl-0 = <&i2c2_pins>; 406623910f4SLars Povlsen pinctrl-names = "default"; 407623910f4SLars Povlsen reg = <0x6 0x00103000 0x100>; 408623910f4SLars Povlsen #address-cells = <1>; 409623910f4SLars Povlsen #size-cells = <0>; 410623910f4SLars Povlsen interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 411623910f4SLars Povlsen i2c-sda-hold-time-ns = <300>; 412623910f4SLars Povlsen clock-frequency = <100000>; 413623910f4SLars Povlsen clocks = <&ahb_clk>; 41414bc6703SLars Povlsen }; 415d14f6a1aSLars Povlsen 416d14f6a1aSLars Povlsen tmon0: tmon@610508110 { 417d14f6a1aSLars Povlsen compatible = "microchip,sparx5-temp"; 418d14f6a1aSLars Povlsen reg = <0x6 0x10508110 0xc>; 419d14f6a1aSLars Povlsen #thermal-sensor-cells = <0>; 420d14f6a1aSLars Povlsen clocks = <&ahb_clk>; 421d14f6a1aSLars Povlsen }; 422d0f482bbSSteen Hegelund 423d0f482bbSSteen Hegelund mdio0: mdio@6110102b0 { 424d0f482bbSSteen Hegelund compatible = "mscc,ocelot-miim"; 425d0f482bbSSteen Hegelund status = "disabled"; 426d0f482bbSSteen Hegelund #address-cells = <1>; 427d0f482bbSSteen Hegelund #size-cells = <0>; 428d0f482bbSSteen Hegelund reg = <0x6 0x110102b0 0x24>; 429d0f482bbSSteen Hegelund }; 430d0f482bbSSteen Hegelund 431d0f482bbSSteen Hegelund mdio1: mdio@6110102d4 { 432d0f482bbSSteen Hegelund compatible = "mscc,ocelot-miim"; 433d0f482bbSSteen Hegelund status = "disabled"; 434d0f482bbSSteen Hegelund pinctrl-0 = <&miim1_pins>; 435d0f482bbSSteen Hegelund pinctrl-names = "default"; 436d0f482bbSSteen Hegelund #address-cells = <1>; 437d0f482bbSSteen Hegelund #size-cells = <0>; 438d0f482bbSSteen Hegelund reg = <0x6 0x110102d4 0x24>; 439d0f482bbSSteen Hegelund }; 440d0f482bbSSteen Hegelund 441d0f482bbSSteen Hegelund mdio2: mdio@6110102f8 { 442d0f482bbSSteen Hegelund compatible = "mscc,ocelot-miim"; 443d0f482bbSSteen Hegelund status = "disabled"; 444d0f482bbSSteen Hegelund pinctrl-0 = <&miim2_pins>; 445d0f482bbSSteen Hegelund pinctrl-names = "default"; 446d0f482bbSSteen Hegelund #address-cells = <1>; 447d0f482bbSSteen Hegelund #size-cells = <0>; 448d0f482bbSSteen Hegelund reg = <0x6 0x110102d4 0x24>; 449d0f482bbSSteen Hegelund }; 450d0f482bbSSteen Hegelund 451d0f482bbSSteen Hegelund mdio3: mdio@61101031c { 452d0f482bbSSteen Hegelund compatible = "mscc,ocelot-miim"; 453d0f482bbSSteen Hegelund status = "disabled"; 454d0f482bbSSteen Hegelund pinctrl-0 = <&miim3_pins>; 455d0f482bbSSteen Hegelund pinctrl-names = "default"; 456d0f482bbSSteen Hegelund #address-cells = <1>; 457d0f482bbSSteen Hegelund #size-cells = <0>; 458d0f482bbSSteen Hegelund reg = <0x6 0x1101031c 0x24>; 459d0f482bbSSteen Hegelund }; 460d0f482bbSSteen Hegelund 461d0f482bbSSteen Hegelund serdes: serdes@10808000 { 462d0f482bbSSteen Hegelund compatible = "microchip,sparx5-serdes"; 463d0f482bbSSteen Hegelund #phy-cells = <1>; 464d0f482bbSSteen Hegelund clocks = <&sys_clk>; 465d0f482bbSSteen Hegelund reg = <0x6 0x10808000 0x5d0000>; 466d0f482bbSSteen Hegelund }; 467d0f482bbSSteen Hegelund 468d0f482bbSSteen Hegelund switch: switch@0x600000000 { 469d0f482bbSSteen Hegelund compatible = "microchip,sparx5-switch"; 470d0f482bbSSteen Hegelund reg = <0x6 0 0x401000>, 471d0f482bbSSteen Hegelund <0x6 0x10004000 0x7fc000>, 472d0f482bbSSteen Hegelund <0x6 0x11010000 0xaf0000>; 473d0f482bbSSteen Hegelund reg-names = "cpu", "dev", "gcb"; 474*6015fb90SHoratiu Vultur interrupt-names = "xtr", "fdma", "ptp"; 475920c293aSSteen Hegelund interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 476*6015fb90SHoratiu Vultur <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 477*6015fb90SHoratiu Vultur <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 478d0f482bbSSteen Hegelund resets = <&reset 0>; 479d0f482bbSSteen Hegelund reset-names = "switch"; 480d0f482bbSSteen Hegelund }; 4816694aee0SLars Povlsen }; 4826694aee0SLars Povlsen}; 483