16694aee0SLars Povlsen// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 26694aee0SLars Povlsen/* 36694aee0SLars Povlsen * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. 46694aee0SLars Povlsen */ 56694aee0SLars Povlsen 66694aee0SLars Povlsen#include <dt-bindings/gpio/gpio.h> 76694aee0SLars Povlsen#include <dt-bindings/interrupt-controller/arm-gic.h> 845145406SLars Povlsen#include <dt-bindings/clock/microchip,sparx5.h> 96694aee0SLars Povlsen 106694aee0SLars Povlsen/ { 116694aee0SLars Povlsen compatible = "microchip,sparx5"; 126694aee0SLars Povlsen interrupt-parent = <&gic>; 136694aee0SLars Povlsen #address-cells = <2>; 146694aee0SLars Povlsen #size-cells = <1>; 156694aee0SLars Povlsen 166694aee0SLars Povlsen aliases { 1708ee16e9SLars Povlsen spi0 = &spi0; 186694aee0SLars Povlsen serial0 = &uart0; 196694aee0SLars Povlsen serial1 = &uart1; 206694aee0SLars Povlsen }; 216694aee0SLars Povlsen 226694aee0SLars Povlsen chosen { 236694aee0SLars Povlsen stdout-path = "serial0:115200n8"; 246694aee0SLars Povlsen }; 256694aee0SLars Povlsen 266694aee0SLars Povlsen cpus { 276694aee0SLars Povlsen #address-cells = <2>; 286694aee0SLars Povlsen #size-cells = <0>; 296694aee0SLars Povlsen cpu-map { 306694aee0SLars Povlsen cluster0 { 316694aee0SLars Povlsen core0 { 326694aee0SLars Povlsen cpu = <&cpu0>; 336694aee0SLars Povlsen }; 346694aee0SLars Povlsen core1 { 356694aee0SLars Povlsen cpu = <&cpu1>; 366694aee0SLars Povlsen }; 376694aee0SLars Povlsen }; 386694aee0SLars Povlsen }; 396694aee0SLars Povlsen cpu0: cpu@0 { 406694aee0SLars Povlsen compatible = "arm,cortex-a53"; 416694aee0SLars Povlsen device_type = "cpu"; 426694aee0SLars Povlsen reg = <0x0 0x0>; 436694aee0SLars Povlsen enable-method = "psci"; 446694aee0SLars Povlsen next-level-cache = <&L2_0>; 456694aee0SLars Povlsen }; 466694aee0SLars Povlsen cpu1: cpu@1 { 476694aee0SLars Povlsen compatible = "arm,cortex-a53"; 486694aee0SLars Povlsen device_type = "cpu"; 496694aee0SLars Povlsen reg = <0x0 0x1>; 506694aee0SLars Povlsen enable-method = "psci"; 516694aee0SLars Povlsen next-level-cache = <&L2_0>; 526694aee0SLars Povlsen }; 536694aee0SLars Povlsen L2_0: l2-cache0 { 546694aee0SLars Povlsen compatible = "cache"; 556694aee0SLars Povlsen }; 566694aee0SLars Povlsen }; 576694aee0SLars Povlsen 586694aee0SLars Povlsen arm-pmu { 596694aee0SLars Povlsen compatible = "arm,cortex-a53-pmu"; 606694aee0SLars Povlsen interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 616694aee0SLars Povlsen interrupt-affinity = <&cpu0>, <&cpu1>; 626694aee0SLars Povlsen }; 636694aee0SLars Povlsen 646694aee0SLars Povlsen psci { 656694aee0SLars Povlsen compatible = "arm,psci-0.2"; 666694aee0SLars Povlsen method = "smc"; 676694aee0SLars Povlsen }; 686694aee0SLars Povlsen 696694aee0SLars Povlsen timer { 706694aee0SLars Povlsen compatible = "arm,armv8-timer"; 716694aee0SLars Povlsen interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 726694aee0SLars Povlsen <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 736694aee0SLars Povlsen <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 746694aee0SLars Povlsen <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 756694aee0SLars Povlsen }; 766694aee0SLars Povlsen 77e4e06a50SLars Povlsen lcpll_clk: lcpll-clk { 78e4e06a50SLars Povlsen compatible = "fixed-clock"; 79e4e06a50SLars Povlsen #clock-cells = <0>; 80e4e06a50SLars Povlsen clock-frequency = <2500000000>; 81e4e06a50SLars Povlsen }; 82e4e06a50SLars Povlsen 83e4e06a50SLars Povlsen clks: clock-controller@61110000c { 84e4e06a50SLars Povlsen compatible = "microchip,sparx5-dpll"; 85e4e06a50SLars Povlsen #clock-cells = <1>; 86e4e06a50SLars Povlsen clocks = <&lcpll_clk>; 87e4e06a50SLars Povlsen reg = <0x6 0x1110000c 0x24>; 88e4e06a50SLars Povlsen }; 89e4e06a50SLars Povlsen 906694aee0SLars Povlsen ahb_clk: ahb-clk { 916694aee0SLars Povlsen compatible = "fixed-clock"; 926694aee0SLars Povlsen #clock-cells = <0>; 936694aee0SLars Povlsen clock-frequency = <250000000>; 946694aee0SLars Povlsen }; 95e4e06a50SLars Povlsen 966694aee0SLars Povlsen sys_clk: sys-clk { 976694aee0SLars Povlsen compatible = "fixed-clock"; 986694aee0SLars Povlsen #clock-cells = <0>; 996694aee0SLars Povlsen clock-frequency = <625000000>; 1006694aee0SLars Povlsen }; 1016694aee0SLars Povlsen 1026694aee0SLars Povlsen axi: axi@600000000 { 1036694aee0SLars Povlsen compatible = "simple-bus"; 1046694aee0SLars Povlsen #address-cells = <2>; 1056694aee0SLars Povlsen #size-cells = <1>; 1066694aee0SLars Povlsen ranges; 1076694aee0SLars Povlsen 1086694aee0SLars Povlsen gic: interrupt-controller@600300000 { 1096694aee0SLars Povlsen compatible = "arm,gic-v3"; 1106694aee0SLars Povlsen #interrupt-cells = <3>; 1116694aee0SLars Povlsen #address-cells = <2>; 1126694aee0SLars Povlsen #size-cells = <2>; 1136694aee0SLars Povlsen interrupt-controller; 1146694aee0SLars Povlsen reg = <0x6 0x00300000 0x10000>, /* GIC Dist */ 1156694aee0SLars Povlsen <0x6 0x00340000 0xc0000>, /* GICR */ 1166694aee0SLars Povlsen <0x6 0x00200000 0x2000>, /* GICC */ 1176694aee0SLars Povlsen <0x6 0x00210000 0x2000>, /* GICV */ 1186694aee0SLars Povlsen <0x6 0x00220000 0x2000>; /* GICH */ 1196694aee0SLars Povlsen interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1206694aee0SLars Povlsen }; 1216694aee0SLars Povlsen 12208ee16e9SLars Povlsen cpu_ctrl: syscon@600000000 { 12308ee16e9SLars Povlsen compatible = "microchip,sparx5-cpu-syscon", "syscon", 12408ee16e9SLars Povlsen "simple-mfd"; 12508ee16e9SLars Povlsen reg = <0x6 0x00000000 0xd0>; 12608ee16e9SLars Povlsen mux: mux-controller { 12708ee16e9SLars Povlsen compatible = "mmio-mux"; 12808ee16e9SLars Povlsen #mux-control-cells = <0>; 12908ee16e9SLars Povlsen /* 13008ee16e9SLars Povlsen * SI_OWNER and SI2_OWNER in GENERAL_CTRL 13108ee16e9SLars Povlsen * SPI: value 9 - (SIMC,SIBM) = 0b1001 13208ee16e9SLars Povlsen * SPI2: value 6 - (SIBM,SIMC) = 0b0110 13308ee16e9SLars Povlsen */ 13408ee16e9SLars Povlsen mux-reg-masks = <0x88 0xf0>; 13508ee16e9SLars Povlsen }; 13608ee16e9SLars Povlsen }; 13708ee16e9SLars Povlsen 1386694aee0SLars Povlsen uart0: serial@600100000 { 13914bc6703SLars Povlsen pinctrl-0 = <&uart_pins>; 14014bc6703SLars Povlsen pinctrl-names = "default"; 1416694aee0SLars Povlsen compatible = "ns16550a"; 1426694aee0SLars Povlsen reg = <0x6 0x00100000 0x20>; 1436694aee0SLars Povlsen clocks = <&ahb_clk>; 1446694aee0SLars Povlsen reg-io-width = <4>; 1456694aee0SLars Povlsen reg-shift = <2>; 1466694aee0SLars Povlsen interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1476694aee0SLars Povlsen 1486694aee0SLars Povlsen status = "disabled"; 1496694aee0SLars Povlsen }; 1506694aee0SLars Povlsen 1516694aee0SLars Povlsen uart1: serial@600102000 { 15214bc6703SLars Povlsen pinctrl-0 = <&uart2_pins>; 15314bc6703SLars Povlsen pinctrl-names = "default"; 1546694aee0SLars Povlsen compatible = "ns16550a"; 1556694aee0SLars Povlsen reg = <0x6 0x00102000 0x20>; 1566694aee0SLars Povlsen clocks = <&ahb_clk>; 1576694aee0SLars Povlsen reg-io-width = <4>; 1586694aee0SLars Povlsen reg-shift = <2>; 1596694aee0SLars Povlsen interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1606694aee0SLars Povlsen 1616694aee0SLars Povlsen status = "disabled"; 1626694aee0SLars Povlsen }; 1636694aee0SLars Povlsen 16408ee16e9SLars Povlsen spi0: spi@600104000 { 16508ee16e9SLars Povlsen #address-cells = <1>; 16608ee16e9SLars Povlsen #size-cells = <0>; 16708ee16e9SLars Povlsen compatible = "microchip,sparx5-spi"; 16808ee16e9SLars Povlsen reg = <0x6 0x00104000 0x40>; 16908ee16e9SLars Povlsen num-cs = <16>; 17008ee16e9SLars Povlsen reg-io-width = <4>; 17108ee16e9SLars Povlsen reg-shift = <2>; 17208ee16e9SLars Povlsen clocks = <&ahb_clk>; 17308ee16e9SLars Povlsen interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 17408ee16e9SLars Povlsen status = "disabled"; 17508ee16e9SLars Povlsen }; 17608ee16e9SLars Povlsen 1776694aee0SLars Povlsen timer1: timer@600105000 { 1786694aee0SLars Povlsen compatible = "snps,dw-apb-timer"; 1796694aee0SLars Povlsen reg = <0x6 0x00105000 0x1000>; 1806694aee0SLars Povlsen clocks = <&ahb_clk>; 1816694aee0SLars Povlsen clock-names = "timer"; 1826694aee0SLars Povlsen interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1836694aee0SLars Povlsen }; 1846694aee0SLars Povlsen 18545145406SLars Povlsen sdhci0: mmc@600800000 { 18645145406SLars Povlsen compatible = "microchip,dw-sparx5-sdhci"; 18745145406SLars Povlsen status = "disabled"; 18845145406SLars Povlsen reg = <0x6 0x00800000 0x1000>; 18945145406SLars Povlsen pinctrl-0 = <&emmc_pins>; 19045145406SLars Povlsen pinctrl-names = "default"; 19145145406SLars Povlsen clocks = <&clks CLK_ID_AUX1>; 19245145406SLars Povlsen clock-names = "core"; 19345145406SLars Povlsen assigned-clocks = <&clks CLK_ID_AUX1>; 19445145406SLars Povlsen assigned-clock-rates = <800000000>; 19545145406SLars Povlsen interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 19645145406SLars Povlsen bus-width = <8>; 19745145406SLars Povlsen }; 19845145406SLars Povlsen 19914bc6703SLars Povlsen gpio: pinctrl@6110101e0 { 20014bc6703SLars Povlsen compatible = "microchip,sparx5-pinctrl"; 20114bc6703SLars Povlsen reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>; 20214bc6703SLars Povlsen gpio-controller; 20314bc6703SLars Povlsen #gpio-cells = <2>; 20414bc6703SLars Povlsen gpio-ranges = <&gpio 0 0 64>; 20514bc6703SLars Povlsen interrupt-controller; 20614bc6703SLars Povlsen interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 20714bc6703SLars Povlsen #interrupt-cells = <2>; 20814bc6703SLars Povlsen 2095df50128SLars Povlsen cs1_pins: cs1-pins { 2105df50128SLars Povlsen pins = "GPIO_16"; 2115df50128SLars Povlsen function = "si"; 2125df50128SLars Povlsen }; 2135df50128SLars Povlsen 2145df50128SLars Povlsen cs2_pins: cs2-pins { 2155df50128SLars Povlsen pins = "GPIO_17"; 2165df50128SLars Povlsen function = "si"; 2175df50128SLars Povlsen }; 2185df50128SLars Povlsen 2195df50128SLars Povlsen cs3_pins: cs3-pins { 2205df50128SLars Povlsen pins = "GPIO_18"; 2215df50128SLars Povlsen function = "si"; 2225df50128SLars Povlsen }; 2235df50128SLars Povlsen 2245df50128SLars Povlsen si2_pins: si2-pins { 2255df50128SLars Povlsen pins = "GPIO_39", "GPIO_40", "GPIO_41"; 2265df50128SLars Povlsen function = "si2"; 2275df50128SLars Povlsen }; 2285df50128SLars Povlsen 22914bc6703SLars Povlsen uart_pins: uart-pins { 23014bc6703SLars Povlsen pins = "GPIO_10", "GPIO_11"; 23114bc6703SLars Povlsen function = "uart"; 23214bc6703SLars Povlsen }; 23314bc6703SLars Povlsen 23414bc6703SLars Povlsen uart2_pins: uart2-pins { 23514bc6703SLars Povlsen pins = "GPIO_26", "GPIO_27"; 23614bc6703SLars Povlsen function = "uart2"; 23714bc6703SLars Povlsen }; 238623910f4SLars Povlsen 239623910f4SLars Povlsen i2c_pins: i2c-pins { 240623910f4SLars Povlsen pins = "GPIO_14", "GPIO_15"; 241623910f4SLars Povlsen function = "twi"; 242623910f4SLars Povlsen }; 243623910f4SLars Povlsen 244623910f4SLars Povlsen i2c2_pins: i2c2-pins { 245623910f4SLars Povlsen pins = "GPIO_28", "GPIO_29"; 246623910f4SLars Povlsen function = "twi2"; 247623910f4SLars Povlsen }; 24845145406SLars Povlsen 24945145406SLars Povlsen emmc_pins: emmc-pins { 25045145406SLars Povlsen pins = "GPIO_34", "GPIO_35", "GPIO_36", 25145145406SLars Povlsen "GPIO_37", "GPIO_38", "GPIO_39", 25245145406SLars Povlsen "GPIO_40", "GPIO_41", "GPIO_42", 25345145406SLars Povlsen "GPIO_43", "GPIO_44", "GPIO_45", 25445145406SLars Povlsen "GPIO_46", "GPIO_47"; 25545145406SLars Povlsen function = "emmc"; 25645145406SLars Povlsen }; 257623910f4SLars Povlsen }; 258623910f4SLars Povlsen 259623910f4SLars Povlsen i2c0: i2c@600101000 { 260623910f4SLars Povlsen compatible = "snps,designware-i2c"; 261623910f4SLars Povlsen status = "disabled"; 262623910f4SLars Povlsen pinctrl-0 = <&i2c_pins>; 263623910f4SLars Povlsen pinctrl-names = "default"; 264623910f4SLars Povlsen reg = <0x6 0x00101000 0x100>; 265623910f4SLars Povlsen #address-cells = <1>; 266623910f4SLars Povlsen #size-cells = <0>; 267623910f4SLars Povlsen interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 268623910f4SLars Povlsen i2c-sda-hold-time-ns = <300>; 269623910f4SLars Povlsen clock-frequency = <100000>; 270623910f4SLars Povlsen clocks = <&ahb_clk>; 271623910f4SLars Povlsen }; 272623910f4SLars Povlsen 273623910f4SLars Povlsen i2c1: i2c@600103000 { 274623910f4SLars Povlsen compatible = "snps,designware-i2c"; 275623910f4SLars Povlsen status = "disabled"; 276623910f4SLars Povlsen pinctrl-0 = <&i2c2_pins>; 277623910f4SLars Povlsen pinctrl-names = "default"; 278623910f4SLars Povlsen reg = <0x6 0x00103000 0x100>; 279623910f4SLars Povlsen #address-cells = <1>; 280623910f4SLars Povlsen #size-cells = <0>; 281623910f4SLars Povlsen interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 282623910f4SLars Povlsen i2c-sda-hold-time-ns = <300>; 283623910f4SLars Povlsen clock-frequency = <100000>; 284623910f4SLars Povlsen clocks = <&ahb_clk>; 28514bc6703SLars Povlsen }; 286d14f6a1aSLars Povlsen 287d14f6a1aSLars Povlsen tmon0: tmon@610508110 { 288d14f6a1aSLars Povlsen compatible = "microchip,sparx5-temp"; 289d14f6a1aSLars Povlsen reg = <0x6 0x10508110 0xc>; 290d14f6a1aSLars Povlsen #thermal-sensor-cells = <0>; 291d14f6a1aSLars Povlsen clocks = <&ahb_clk>; 292d14f6a1aSLars Povlsen }; 2936694aee0SLars Povlsen }; 2946694aee0SLars Povlsen}; 295