1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6/dts-v1/; 7#include "mt8192.dtsi" 8#include "mt6359.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/spmi/spmi.h> 11 12/ { 13 aliases { 14 serial0 = &uart0; 15 }; 16 17 chosen { 18 stdout-path = "serial0:115200n8"; 19 }; 20 21 memory@40000000 { 22 device_type = "memory"; 23 reg = <0 0x40000000 0 0x80000000>; 24 }; 25 26 pp1000_dpbrdg: regulator-1v0-dpbrdg { 27 compatible = "regulator-fixed"; 28 regulator-name = "pp1000_dpbrdg"; 29 pinctrl-names = "default"; 30 pinctrl-0 = <&pp1000_dpbrdg_en_pins>; 31 regulator-min-microvolt = <1000000>; 32 regulator-max-microvolt = <1000000>; 33 enable-active-high; 34 regulator-boot-on; 35 gpio = <&pio 19 GPIO_ACTIVE_HIGH>; 36 vin-supply = <&mt6359_vs2_buck_reg>; 37 }; 38 39 pp1000_mipibrdg: regulator-1v0-mipibrdg { 40 compatible = "regulator-fixed"; 41 regulator-name = "pp1000_mipibrdg"; 42 pinctrl-names = "default"; 43 pinctrl-0 = <&pp1000_mipibrdg_en_pins>; 44 regulator-min-microvolt = <1000000>; 45 regulator-max-microvolt = <1000000>; 46 enable-active-high; 47 regulator-boot-on; 48 gpio = <&pio 129 GPIO_ACTIVE_HIGH>; 49 vin-supply = <&mt6359_vs2_buck_reg>; 50 }; 51 52 pp1800_dpbrdg: regulator-1v8-dpbrdg { 53 compatible = "regulator-fixed"; 54 regulator-name = "pp1800_dpbrdg"; 55 pinctrl-names = "default"; 56 pinctrl-0 = <&pp1800_dpbrdg_en_pins>; 57 enable-active-high; 58 regulator-boot-on; 59 gpio = <&pio 126 GPIO_ACTIVE_HIGH>; 60 vin-supply = <&mt6359_vio18_ldo_reg>; 61 }; 62 63 /* system wide LDO 1.8V power rail */ 64 pp1800_ldo_g: regulator-1v8-g { 65 compatible = "regulator-fixed"; 66 regulator-name = "pp1800_ldo_g"; 67 regulator-always-on; 68 regulator-boot-on; 69 regulator-min-microvolt = <1800000>; 70 regulator-max-microvolt = <1800000>; 71 vin-supply = <&pp3300_g>; 72 }; 73 74 pp1800_mipibrdg: regulator-1v8-mipibrdg { 75 compatible = "regulator-fixed"; 76 regulator-name = "pp1800_mipibrdg"; 77 pinctrl-names = "default"; 78 pinctrl-0 = <&pp1800_mipibrdg_en_pins>; 79 enable-active-high; 80 regulator-boot-on; 81 gpio = <&pio 128 GPIO_ACTIVE_HIGH>; 82 vin-supply = <&mt6359_vio18_ldo_reg>; 83 }; 84 85 pp3300_dpbrdg: regulator-3v3-dpbrdg { 86 compatible = "regulator-fixed"; 87 regulator-name = "pp3300_dpbrdg"; 88 pinctrl-names = "default"; 89 pinctrl-0 = <&pp3300_dpbrdg_en_pins>; 90 enable-active-high; 91 regulator-boot-on; 92 gpio = <&pio 26 GPIO_ACTIVE_HIGH>; 93 vin-supply = <&pp3300_g>; 94 }; 95 96 /* system wide switching 3.3V power rail */ 97 pp3300_g: regulator-3v3-g { 98 compatible = "regulator-fixed"; 99 regulator-name = "pp3300_g"; 100 regulator-always-on; 101 regulator-boot-on; 102 regulator-min-microvolt = <3300000>; 103 regulator-max-microvolt = <3300000>; 104 vin-supply = <&ppvar_sys>; 105 }; 106 107 /* system wide LDO 3.3V power rail */ 108 pp3300_ldo_z: regulator-3v3-z { 109 compatible = "regulator-fixed"; 110 regulator-name = "pp3300_ldo_z"; 111 regulator-always-on; 112 regulator-boot-on; 113 regulator-min-microvolt = <3300000>; 114 regulator-max-microvolt = <3300000>; 115 vin-supply = <&ppvar_sys>; 116 }; 117 118 pp3300_mipibrdg: regulator-3v3-mipibrdg { 119 compatible = "regulator-fixed"; 120 regulator-name = "pp3300_mipibrdg"; 121 pinctrl-names = "default"; 122 pinctrl-0 = <&pp3300_mipibrdg_en_pins>; 123 enable-active-high; 124 regulator-boot-on; 125 gpio = <&pio 127 GPIO_ACTIVE_HIGH>; 126 vin-supply = <&pp3300_g>; 127 }; 128 129 /* separately switched 3.3V power rail */ 130 pp3300_u: regulator-3v3-u { 131 compatible = "regulator-fixed"; 132 regulator-name = "pp3300_u"; 133 regulator-always-on; 134 regulator-boot-on; 135 regulator-min-microvolt = <3300000>; 136 regulator-max-microvolt = <3300000>; 137 /* enable pin wired to GPIO controlled by EC */ 138 vin-supply = <&pp3300_g>; 139 }; 140 141 pp3300_wlan: regulator-3v3-wlan { 142 compatible = "regulator-fixed"; 143 regulator-name = "pp3300_wlan"; 144 regulator-always-on; 145 regulator-boot-on; 146 regulator-min-microvolt = <3300000>; 147 regulator-max-microvolt = <3300000>; 148 pinctrl-names = "default"; 149 pinctrl-0 = <&pp3300_wlan_pins>; 150 enable-active-high; 151 gpio = <&pio 143 GPIO_ACTIVE_HIGH>; 152 }; 153 154 /* system wide switching 5.0V power rail */ 155 pp5000_a: regulator-5v0-a { 156 compatible = "regulator-fixed"; 157 regulator-name = "pp5000_a"; 158 regulator-always-on; 159 regulator-boot-on; 160 regulator-min-microvolt = <5000000>; 161 regulator-max-microvolt = <5000000>; 162 vin-supply = <&ppvar_sys>; 163 }; 164 165 /* system wide semi-regulated power rail from battery or USB */ 166 ppvar_sys: regulator-var-sys { 167 compatible = "regulator-fixed"; 168 regulator-name = "ppvar_sys"; 169 regulator-always-on; 170 regulator-boot-on; 171 }; 172 173 reserved_memory: reserved-memory { 174 #address-cells = <2>; 175 #size-cells = <2>; 176 ranges; 177 178 scp_mem_reserved: scp@50000000 { 179 compatible = "shared-dma-pool"; 180 reg = <0 0x50000000 0 0x2900000>; 181 no-map; 182 }; 183 184 wifi_restricted_dma_region: wifi@c0000000 { 185 compatible = "restricted-dma-pool"; 186 reg = <0 0xc0000000 0 0x4000000>; 187 }; 188 }; 189}; 190 191&i2c0 { 192 status = "okay"; 193 194 clock-frequency = <400000>; 195 pinctrl-names = "default"; 196 pinctrl-0 = <&i2c0_pins>; 197 198 touchscreen: touchscreen@10 { 199 reg = <0x10>; 200 interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>; 201 pinctrl-names = "default"; 202 pinctrl-0 = <&touchscreen_pins>; 203 }; 204}; 205 206&i2c1 { 207 status = "okay"; 208 209 clock-frequency = <400000>; 210 pinctrl-names = "default"; 211 pinctrl-0 = <&i2c1_pins>; 212}; 213 214&i2c2 { 215 status = "okay"; 216 217 clock-frequency = <400000>; 218 clock-stretch-ns = <12600>; 219 pinctrl-names = "default"; 220 pinctrl-0 = <&i2c2_pins>; 221 222 trackpad@15 { 223 compatible = "elan,ekth3000"; 224 reg = <0x15>; 225 interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; 226 pinctrl-names = "default"; 227 pinctrl-0 = <&trackpad_pins>; 228 vcc-supply = <&pp3300_u>; 229 wakeup-source; 230 }; 231}; 232 233&i2c3 { 234 status = "okay"; 235 236 clock-frequency = <400000>; 237 pinctrl-names = "default"; 238 pinctrl-0 = <&i2c3_pins>; 239}; 240 241&i2c7 { 242 status = "okay"; 243 244 clock-frequency = <400000>; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&i2c7_pins>; 247}; 248 249&mmc0 { 250 status = "okay"; 251 252 pinctrl-names = "default", "state_uhs"; 253 pinctrl-0 = <&mmc0_default_pins>; 254 pinctrl-1 = <&mmc0_uhs_pins>; 255 bus-width = <8>; 256 max-frequency = <200000000>; 257 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 258 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 259 cap-mmc-highspeed; 260 mmc-hs200-1_8v; 261 mmc-hs400-1_8v; 262 supports-cqe; 263 cap-mmc-hw-reset; 264 mmc-hs400-enhanced-strobe; 265 hs400-ds-delay = <0x12814>; 266 no-sdio; 267 no-sd; 268 non-removable; 269}; 270 271&mmc1 { 272 status = "okay"; 273 274 pinctrl-names = "default", "state_uhs"; 275 pinctrl-0 = <&mmc1_default_pins>; 276 pinctrl-1 = <&mmc1_uhs_pins>; 277 bus-width = <4>; 278 max-frequency = <200000000>; 279 cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>; 280 vmmc-supply = <&mt6360_ldo5_reg>; 281 vqmmc-supply = <&mt6360_ldo3_reg>; 282 cap-sd-highspeed; 283 sd-uhs-sdr50; 284 sd-uhs-sdr104; 285 no-sdio; 286 no-mmc; 287}; 288 289/* for CORE */ 290&mt6359_vgpu11_buck_reg { 291 regulator-always-on; 292}; 293 294&mt6359_vgpu11_sshub_buck_reg { 295 regulator-always-on; 296 regulator-min-microvolt = <575000>; 297 regulator-max-microvolt = <575000>; 298}; 299 300&mt6359_vrf12_ldo_reg { 301 regulator-always-on; 302}; 303 304&mt6359_vufs_ldo_reg { 305 regulator-always-on; 306}; 307 308&mt6359codec { 309 mediatek,dmic-mode = <1>; /* one-wire */ 310 mediatek,mic-type-0 = <2>; /* DMIC */ 311 mediatek,mic-type-2 = <2>; /* DMIC */ 312}; 313 314&nor_flash { 315 status = "okay"; 316 317 pinctrl-names = "default"; 318 pinctrl-0 = <&nor_flash_pins>; 319 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 320 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>; 321 322 flash@0 { 323 compatible = "winbond,w25q64jwm", "jedec,spi-nor"; 324 reg = <0>; 325 spi-max-frequency = <52000000>; 326 spi-rx-bus-width = <2>; 327 spi-tx-bus-width = <2>; 328 }; 329}; 330 331&pcie { 332 pinctrl-names = "default"; 333 pinctrl-0 = <&pcie_pins>; 334 335 pcie0: pcie@0,0 { 336 device_type = "pci"; 337 reg = <0x0000 0 0 0 0>; 338 num-lanes = <1>; 339 bus-range = <0x1 0x1>; 340 341 #address-cells = <3>; 342 #size-cells = <2>; 343 ranges; 344 345 wifi: wifi@0,0 { 346 reg = <0x10000 0 0 0 0x100000>, 347 <0x10000 0 0x100000 0 0x100000>; 348 memory-region = <&wifi_restricted_dma_region>; 349 }; 350 }; 351}; 352 353&pio { 354 /* 220 lines */ 355 gpio-line-names = "I2S_DP_LRCK", 356 "IS_DP_BCLK", 357 "I2S_DP_MCLK", 358 "I2S_DP_DATAOUT", 359 "SAR0_INT_ODL", 360 "EC_AP_INT_ODL", 361 "EDPBRDG_INT_ODL", 362 "DPBRDG_INT_ODL", 363 "DPBRDG_PWREN", 364 "DPBRDG_RST_ODL", 365 "I2S_HP_MCLK", 366 "I2S_HP_BCK", 367 "I2S_HP_LRCK", 368 "I2S_HP_DATAIN", 369 /* 370 * AP_FLASH_WP_L is crossystem ABI. Schematics 371 * call it AP_FLASH_WP_ODL. 372 */ 373 "AP_FLASH_WP_L", 374 "TRACKPAD_INT_ODL", 375 "EC_AP_HPD_OD", 376 "SD_CD_ODL", 377 "HP_INT_ODL_ALC", 378 "EN_PP1000_DPBRDG", 379 "AP_GPIO20", 380 "TOUCH_INT_L_1V8", 381 "UART_BT_WAKE_ODL", 382 "AP_GPIO23", 383 "AP_SPI_FLASH_CS_L", 384 "AP_SPI_FLASH_CLK", 385 "EN_PP3300_DPBRDG_DX", 386 "AP_SPI_FLASH_MOSI", 387 "AP_SPI_FLASH_MISO", 388 "I2S_HP_DATAOUT", 389 "AP_GPIO30", 390 "I2S_SPKR_MCLK", 391 "I2S_SPKR_BCLK", 392 "I2S_SPKR_LRCK", 393 "I2S_SPKR_DATAIN", 394 "I2S_SPKR_DATAOUT", 395 "AP_SPI_H1_TPM_CLK", 396 "AP_SPI_H1_TPM_CS_L", 397 "AP_SPI_H1_TPM_MISO", 398 "AP_SPI_H1_TPM_MOSI", 399 "BL_PWM", 400 "EDPBRDG_PWREN", 401 "EDPBRDG_RST_ODL", 402 "EN_PP3300_HUB", 403 "HUB_RST_L", 404 "", 405 "", 406 "", 407 "", 408 "", 409 "", 410 "SD_CLK", 411 "SD_CMD", 412 "SD_DATA3", 413 "SD_DATA0", 414 "SD_DATA2", 415 "SD_DATA1", 416 "", 417 "", 418 "", 419 "", 420 "", 421 "", 422 "PCIE_WAKE_ODL", 423 "PCIE_RST_L", 424 "PCIE_CLKREQ_ODL", 425 "", 426 "", 427 "", 428 "", 429 "", 430 "", 431 "", 432 "", 433 "", 434 "", 435 "", 436 "", 437 "", 438 "", 439 "", 440 "", 441 "", 442 "", 443 "", 444 "", 445 "", 446 "", 447 "", 448 "SPMI_SCL", 449 "SPMI_SDA", 450 "AP_GOOD", 451 "UART_DBG_TX_AP_RX", 452 "UART_AP_TX_DBG_RX", 453 "UART_AP_TX_BT_RX", 454 "UART_BT_TX_AP_RX", 455 "MIPI_DPI_D0_R", 456 "MIPI_DPI_D1_R", 457 "MIPI_DPI_D2_R", 458 "MIPI_DPI_D3_R", 459 "MIPI_DPI_D4_R", 460 "MIPI_DPI_D5_R", 461 "MIPI_DPI_D6_R", 462 "MIPI_DPI_D7_R", 463 "MIPI_DPI_D8_R", 464 "MIPI_DPI_D9_R", 465 "MIPI_DPI_D10_R", 466 "", 467 "", 468 "MIPI_DPI_DE_R", 469 "MIPI_DPI_D11_R", 470 "MIPI_DPI_VSYNC_R", 471 "MIPI_DPI_CLK_R", 472 "MIPI_DPI_HSYNC_R", 473 "PCM_BT_DATAIN", 474 "PCM_BT_SYNC", 475 "PCM_BT_DATAOUT", 476 "PCM_BT_CLK", 477 "AP_I2C_AUDIO_SCL", 478 "AP_I2C_AUDIO_SDA", 479 "SCP_I2C_SCL", 480 "SCP_I2C_SDA", 481 "AP_I2C_WLAN_SCL", 482 "AP_I2C_WLAN_SDA", 483 "AP_I2C_DPBRDG_SCL", 484 "AP_I2C_DPBRDG_SDA", 485 "EN_PP1800_DPBRDG_DX", 486 "EN_PP3300_EDP_DX", 487 "EN_PP1800_EDPBRDG_DX", 488 "EN_PP1000_EDPBRDG", 489 "SCP_JTAG0_TDO", 490 "SCP_JTAG0_TDI", 491 "SCP_JTAG0_TMS", 492 "SCP_JTAG0_TCK", 493 "SCP_JTAG0_TRSTN", 494 "EN_PP3000_VMC_PMU", 495 "EN_PP3300_DISPLAY_DX", 496 "TOUCH_RST_L_1V8", 497 "TOUCH_REPORT_DISABLE", 498 "", 499 "", 500 "AP_I2C_TRACKPAD_SCL_1V8", 501 "AP_I2C_TRACKPAD_SDA_1V8", 502 "EN_PP3300_WLAN", 503 "BT_KILL_L", 504 "WIFI_KILL_L", 505 "SET_VMC_VOLT_AT_1V8", 506 "EN_SPK", 507 "AP_WARM_RST_REQ", 508 "", 509 "", 510 "EN_PP3000_SD_S3", 511 "AP_EDP_BKLTEN", 512 "", 513 "", 514 "", 515 "AP_SPI_EC_CLK", 516 "AP_SPI_EC_CS_L", 517 "AP_SPI_EC_MISO", 518 "AP_SPI_EC_MOSI", 519 "AP_I2C_EDPBRDG_SCL", 520 "AP_I2C_EDPBRDG_SDA", 521 "MT6315_PROC_INT", 522 "MT6315_GPU_INT", 523 "UART_SERVO_TX_SCP_RX", 524 "UART_SCP_TX_SERVO_RX", 525 "BT_RTS_AP_CTS", 526 "AP_RTS_BT_CTS", 527 "UART_AP_WAKE_BT_ODL", 528 "WLAN_ALERT_ODL", 529 "EC_IN_RW_ODL", 530 "H1_AP_INT_ODL", 531 "", 532 "", 533 "", 534 "", 535 "", 536 "", 537 "", 538 "", 539 "", 540 "", 541 "", 542 "MSDC0_CMD", 543 "MSDC0_DAT0", 544 "MSDC0_DAT2", 545 "MSDC0_DAT4", 546 "MSDC0_DAT6", 547 "MSDC0_DAT1", 548 "MSDC0_DAT5", 549 "MSDC0_DAT7", 550 "MSDC0_DSL", 551 "MSDC0_CLK", 552 "MSDC0_DAT3", 553 "MSDC0_RST_L", 554 "SCP_VREQ_VAO", 555 "AUD_DAT_MOSI2", 556 "AUD_NLE_MOSI1", 557 "AUD_NLE_MOSI0", 558 "AUD_DAT_MISO2", 559 "AP_I2C_SAR_SDA", 560 "AP_I2C_SAR_SCL", 561 "AP_I2C_PWR_SCL", 562 "AP_I2C_PWR_SDA", 563 "AP_I2C_TS_SCL_1V8", 564 "AP_I2C_TS_SDA_1V8", 565 "SRCLKENA0", 566 "SRCLKENA1", 567 "AP_EC_WATCHDOG_L", 568 "PWRAP_SPI0_MI", 569 "PWRAP_SPI0_CSN", 570 "PWRAP_SPI0_MO", 571 "PWRAP_SPI0_CK", 572 "AP_RTC_CLK32K", 573 "AUD_CLK_MOSI", 574 "AUD_SYNC_MOSI", 575 "AUD_DAT_MOSI0", 576 "AUD_DAT_MOSI1", 577 "AUD_DAT_MISO0", 578 "AUD_DAT_MISO1"; 579 580 cr50_int: cr50-irq-default-pins { 581 pins-gsc-ap-int-odl { 582 pinmux = <PINMUX_GPIO171__FUNC_GPIO171>; 583 input-enable; 584 }; 585 }; 586 587 cros_ec_int: cros-ec-irq-default-pins { 588 pins-ec-ap-int-odl { 589 pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; 590 input-enable; 591 bias-pull-up; 592 }; 593 }; 594 595 i2c0_pins: i2c0-default-pins { 596 pins-bus { 597 pinmux = <PINMUX_GPIO204__FUNC_SCL0>, 598 <PINMUX_GPIO205__FUNC_SDA0>; 599 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 600 drive-strength-microamp = <1000>; 601 }; 602 }; 603 604 i2c1_pins: i2c1-default-pins { 605 pins-bus { 606 pinmux = <PINMUX_GPIO118__FUNC_SCL1>, 607 <PINMUX_GPIO119__FUNC_SDA1>; 608 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 609 drive-strength-microamp = <1000>; 610 }; 611 }; 612 613 i2c2_pins: i2c2-default-pins { 614 pins-bus { 615 pinmux = <PINMUX_GPIO141__FUNC_SCL2>, 616 <PINMUX_GPIO142__FUNC_SDA2>; 617 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 618 }; 619 }; 620 621 i2c3_pins: i2c3-default-pins { 622 pins-bus { 623 pinmux = <PINMUX_GPIO160__FUNC_SCL3>, 624 <PINMUX_GPIO161__FUNC_SDA3>; 625 bias-disable; 626 drive-strength-microamp = <1000>; 627 }; 628 }; 629 630 i2c7_pins: i2c7-default-pins { 631 pins-bus { 632 pinmux = <PINMUX_GPIO124__FUNC_SCL7>, 633 <PINMUX_GPIO125__FUNC_SDA7>; 634 bias-disable; 635 drive-strength-microamp = <1000>; 636 }; 637 }; 638 639 mmc0_default_pins: mmc0-default-pins { 640 pins-cmd-dat { 641 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 642 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 643 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 644 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 645 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 646 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 647 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 648 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 649 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 650 input-enable; 651 drive-strength = <8>; 652 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 653 }; 654 655 pins-clk { 656 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 657 drive-strength = <8>; 658 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 659 }; 660 661 pins-rst { 662 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 663 drive-strength = <8>; 664 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 665 }; 666 }; 667 668 mmc0_uhs_pins: mmc0-uhs-pins { 669 pins-cmd-dat { 670 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 671 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 672 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 673 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 674 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 675 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 676 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 677 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 678 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 679 input-enable; 680 drive-strength = <10>; 681 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 682 }; 683 684 pins-clk { 685 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 686 drive-strength = <10>; 687 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 688 }; 689 690 pins-rst { 691 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 692 drive-strength = <8>; 693 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 694 }; 695 696 pins-ds { 697 pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>; 698 drive-strength = <10>; 699 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 700 }; 701 }; 702 703 mmc1_default_pins: mmc1-default-pins { 704 pins-cmd-dat { 705 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 706 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 707 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 708 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 709 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 710 input-enable; 711 drive-strength = <8>; 712 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 713 }; 714 715 pins-clk { 716 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 717 drive-strength = <8>; 718 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 719 }; 720 721 pins-insert { 722 pinmux = <PINMUX_GPIO17__FUNC_GPIO17>; 723 input-enable; 724 bias-pull-up; 725 }; 726 }; 727 728 mmc1_uhs_pins: mmc1-uhs-pins { 729 pins-cmd-dat { 730 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 731 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 732 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 733 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 734 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 735 input-enable; 736 drive-strength = <8>; 737 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 738 }; 739 740 pins-clk { 741 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 742 input-enable; 743 drive-strength = <8>; 744 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 745 }; 746 }; 747 748 nor_flash_pins: nor-flash-default-pins { 749 pins-cs-io1 { 750 pinmux = <PINMUX_GPIO24__FUNC_SPINOR_CS>, 751 <PINMUX_GPIO28__FUNC_SPINOR_IO1>; 752 input-enable; 753 bias-pull-up; 754 drive-strength = <10>; 755 }; 756 757 pins-io0 { 758 pinmux = <PINMUX_GPIO27__FUNC_SPINOR_IO0>; 759 bias-pull-up; 760 drive-strength = <10>; 761 }; 762 763 pins-clk { 764 pinmux = <PINMUX_GPIO25__FUNC_SPINOR_CK>; 765 input-enable; 766 bias-pull-up; 767 drive-strength = <10>; 768 }; 769 }; 770 771 pcie_pins: pcie-default-pins { 772 pins-pcie-wake { 773 pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>; 774 bias-pull-up; 775 }; 776 777 pins-pcie-pereset { 778 pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>; 779 }; 780 781 pins-pcie-clkreq { 782 pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>; 783 bias-pull-up; 784 }; 785 786 pins-wifi-kill { 787 pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */ 788 output-high; 789 }; 790 }; 791 792 pp1000_dpbrdg_en_pins: pp1000-dpbrdg-en-pins { 793 pins-en { 794 pinmux = <PINMUX_GPIO19__FUNC_GPIO19>; 795 output-low; 796 }; 797 }; 798 799 pp1000_mipibrdg_en_pins: pp1000-mipibrdg-en-pins { 800 pins-en { 801 pinmux = <PINMUX_GPIO129__FUNC_GPIO129>; 802 output-low; 803 }; 804 }; 805 806 pp1800_dpbrdg_en_pins: pp1800-dpbrdg-en-pins { 807 pins-en { 808 pinmux = <PINMUX_GPIO126__FUNC_GPIO126>; 809 output-low; 810 }; 811 }; 812 813 pp1800_mipibrdg_en_pins: pp1800-mipibrd-en-pins { 814 pins-en { 815 pinmux = <PINMUX_GPIO128__FUNC_GPIO128>; 816 output-low; 817 }; 818 }; 819 820 pp3300_dpbrdg_en_pins: pp3300-dpbrdg-en-pins { 821 pins-en { 822 pinmux = <PINMUX_GPIO26__FUNC_GPIO26>; 823 output-low; 824 }; 825 }; 826 827 pp3300_mipibrdg_en_pins: pp3300-mipibrdg-en-pins { 828 pins-en { 829 pinmux = <PINMUX_GPIO127__FUNC_GPIO127>; 830 output-low; 831 }; 832 }; 833 834 pp3300_wlan_pins: pp3300-wlan-pins { 835 pins-pcie-en-pp3300-wlan { 836 pinmux = <PINMUX_GPIO143__FUNC_GPIO143>; 837 output-high; 838 }; 839 }; 840 841 scp_pins: scp-pins { 842 pins-vreq-vao { 843 pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>; 844 }; 845 }; 846 847 spi1_pins: spi1-default-pins { 848 pins-cs-mosi-clk { 849 pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, 850 <PINMUX_GPIO159__FUNC_SPI1_A_MO>, 851 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; 852 bias-disable; 853 }; 854 855 pins-miso { 856 pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; 857 bias-pull-down; 858 }; 859 }; 860 861 spi5_pins: spi5-default-pins { 862 pins-bus { 863 pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>, 864 <PINMUX_GPIO37__FUNC_GPIO37>, 865 <PINMUX_GPIO39__FUNC_SPI5_A_MO>, 866 <PINMUX_GPIO36__FUNC_SPI5_A_CLK>; 867 bias-disable; 868 }; 869 }; 870 871 trackpad_pins: trackpad-default-pins { 872 pins-int-n { 873 pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; 874 input-enable; 875 bias-pull-up = <MTK_PUPD_SET_R1R0_11>; 876 }; 877 }; 878 879 touchscreen_pins: touchscreen-default-pins { 880 pins-irq { 881 pinmux = <PINMUX_GPIO21__FUNC_GPIO21>; 882 input-enable; 883 bias-pull-up; 884 }; 885 886 pins-reset { 887 pinmux = <PINMUX_GPIO137__FUNC_GPIO137>; 888 output-high; 889 }; 890 891 pins-report-sw { 892 pinmux = <PINMUX_GPIO138__FUNC_GPIO138>; 893 output-low; 894 }; 895 }; 896}; 897 898&pmic { 899 interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>; 900}; 901 902&scp { 903 status = "okay"; 904 905 firmware-name = "mediatek/mt8192/scp.img"; 906 memory-region = <&scp_mem_reserved>; 907 pinctrl-names = "default"; 908 pinctrl-0 = <&scp_pins>; 909 910 cros-ec { 911 compatible = "google,cros-ec-rpmsg"; 912 mediatek,rpmsg-name = "cros-ec-rpmsg"; 913 }; 914}; 915 916&spi1 { 917 status = "okay"; 918 919 mediatek,pad-select = <0>; 920 pinctrl-names = "default"; 921 pinctrl-0 = <&spi1_pins>; 922 923 cros_ec: ec@0 { 924 compatible = "google,cros-ec-spi"; 925 reg = <0>; 926 interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; 927 spi-max-frequency = <3000000>; 928 pinctrl-names = "default"; 929 pinctrl-0 = <&cros_ec_int>; 930 931 #address-cells = <1>; 932 #size-cells = <0>; 933 934 base_detection: cbas { 935 compatible = "google,cros-cbas"; 936 }; 937 938 cros_ec_pwm: pwm { 939 compatible = "google,cros-ec-pwm"; 940 #pwm-cells = <1>; 941 942 status = "disabled"; 943 }; 944 945 i2c_tunnel: i2c-tunnel { 946 compatible = "google,cros-ec-i2c-tunnel"; 947 google,remote-bus = <0>; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 }; 951 952 mt6360_ldo3_reg: regulator@0 { 953 compatible = "google,cros-ec-regulator"; 954 reg = <0>; 955 regulator-min-microvolt = <1800000>; 956 regulator-max-microvolt = <3300000>; 957 }; 958 959 mt6360_ldo5_reg: regulator@1 { 960 compatible = "google,cros-ec-regulator"; 961 reg = <1>; 962 regulator-min-microvolt = <3300000>; 963 regulator-max-microvolt = <3300000>; 964 }; 965 966 typec { 967 compatible = "google,cros-ec-typec"; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 971 usb_c0: connector@0 { 972 compatible = "usb-c-connector"; 973 reg = <0>; 974 label = "left"; 975 power-role = "dual"; 976 data-role = "host"; 977 try-power-role = "source"; 978 }; 979 980 usb_c1: connector@1 { 981 compatible = "usb-c-connector"; 982 reg = <1>; 983 label = "right"; 984 power-role = "dual"; 985 data-role = "host"; 986 try-power-role = "source"; 987 }; 988 }; 989 }; 990}; 991 992&spi5 { 993 status = "okay"; 994 995 cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>; 996 mediatek,pad-select = <0>; 997 pinctrl-names = "default"; 998 pinctrl-0 = <&spi5_pins>; 999 1000 cr50@0 { 1001 compatible = "google,cr50"; 1002 reg = <0>; 1003 interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>; 1004 spi-max-frequency = <1000000>; 1005 pinctrl-names = "default"; 1006 pinctrl-0 = <&cr50_int>; 1007 }; 1008}; 1009 1010&spmi { 1011 #address-cells = <2>; 1012 #size-cells = <0>; 1013 1014 mt6315_6: pmic@6 { 1015 compatible = "mediatek,mt6315-regulator"; 1016 reg = <0x6 SPMI_USID>; 1017 1018 regulators { 1019 mt6315_6_vbuck1: vbuck1 { 1020 regulator-compatible = "vbuck1"; 1021 regulator-name = "Vbcpu"; 1022 regulator-min-microvolt = <300000>; 1023 regulator-max-microvolt = <1193750>; 1024 regulator-enable-ramp-delay = <256>; 1025 regulator-allowed-modes = <0 1 2>; 1026 regulator-always-on; 1027 }; 1028 1029 mt6315_6_vbuck3: vbuck3 { 1030 regulator-compatible = "vbuck3"; 1031 regulator-name = "Vlcpu"; 1032 regulator-min-microvolt = <300000>; 1033 regulator-max-microvolt = <1193750>; 1034 regulator-enable-ramp-delay = <256>; 1035 regulator-allowed-modes = <0 1 2>; 1036 regulator-always-on; 1037 }; 1038 }; 1039 }; 1040 1041 mt6315_7: pmic@7 { 1042 compatible = "mediatek,mt6315-regulator"; 1043 reg = <0x7 SPMI_USID>; 1044 1045 regulators { 1046 mt6315_7_vbuck1: vbuck1 { 1047 regulator-compatible = "vbuck1"; 1048 regulator-name = "Vgpu"; 1049 regulator-min-microvolt = <606250>; 1050 regulator-max-microvolt = <1193750>; 1051 regulator-enable-ramp-delay = <256>; 1052 regulator-allowed-modes = <0 1 2>; 1053 }; 1054 }; 1055 }; 1056}; 1057 1058&uart0 { 1059 status = "okay"; 1060}; 1061 1062&xhci { 1063 status = "okay"; 1064 1065 wakeup-source; 1066 vusb33-supply = <&pp3300_g>; 1067 vbus-supply = <&pp5000_a>; 1068}; 1069 1070#include <arm/cros-ec-keyboard.dtsi> 1071#include <arm/cros-ec-sbs.dtsi> 1072