1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6/dts-v1/; 7#include "mt8192.dtsi" 8#include "mt6359.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/spmi/spmi.h> 11 12/ { 13 aliases { 14 i2c0 = &i2c0; 15 i2c1 = &i2c1; 16 i2c2 = &i2c2; 17 i2c3 = &i2c3; 18 i2c7 = &i2c7; 19 mmc0 = &mmc0; 20 mmc1 = &mmc1; 21 serial0 = &uart0; 22 }; 23 24 chosen { 25 stdout-path = "serial0:115200n8"; 26 }; 27 28 memory@40000000 { 29 device_type = "memory"; 30 reg = <0 0x40000000 0 0x80000000>; 31 }; 32 33 backlight_lcd0: backlight-lcd0 { 34 compatible = "pwm-backlight"; 35 pwms = <&pwm0 0 500000>; 36 power-supply = <&ppvar_sys>; 37 enable-gpios = <&pio 152 0>; 38 brightness-levels = <0 1023>; 39 num-interpolated-steps = <1023>; 40 default-brightness-level = <576>; 41 }; 42 43 dmic_codec: dmic-codec { 44 compatible = "dmic-codec"; 45 num-channels = <2>; 46 wakeup-delay-ms = <50>; 47 }; 48 49 pp1000_dpbrdg: regulator-1v0-dpbrdg { 50 compatible = "regulator-fixed"; 51 regulator-name = "pp1000_dpbrdg"; 52 pinctrl-names = "default"; 53 pinctrl-0 = <&pp1000_dpbrdg_en_pins>; 54 regulator-min-microvolt = <1000000>; 55 regulator-max-microvolt = <1000000>; 56 enable-active-high; 57 regulator-boot-on; 58 gpio = <&pio 19 GPIO_ACTIVE_HIGH>; 59 vin-supply = <&mt6359_vs2_buck_reg>; 60 }; 61 62 pp1000_mipibrdg: regulator-1v0-mipibrdg { 63 compatible = "regulator-fixed"; 64 regulator-name = "pp1000_mipibrdg"; 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pp1000_mipibrdg_en_pins>; 67 regulator-min-microvolt = <1000000>; 68 regulator-max-microvolt = <1000000>; 69 enable-active-high; 70 regulator-boot-on; 71 gpio = <&pio 129 GPIO_ACTIVE_HIGH>; 72 vin-supply = <&mt6359_vs2_buck_reg>; 73 }; 74 75 pp1800_dpbrdg: regulator-1v8-dpbrdg { 76 compatible = "regulator-fixed"; 77 regulator-name = "pp1800_dpbrdg"; 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pp1800_dpbrdg_en_pins>; 80 enable-active-high; 81 regulator-boot-on; 82 gpio = <&pio 126 GPIO_ACTIVE_HIGH>; 83 vin-supply = <&mt6359_vio18_ldo_reg>; 84 }; 85 86 /* system wide LDO 1.8V power rail */ 87 pp1800_ldo_g: regulator-1v8-g { 88 compatible = "regulator-fixed"; 89 regulator-name = "pp1800_ldo_g"; 90 regulator-always-on; 91 regulator-boot-on; 92 regulator-min-microvolt = <1800000>; 93 regulator-max-microvolt = <1800000>; 94 vin-supply = <&pp3300_g>; 95 }; 96 97 pp1800_mipibrdg: regulator-1v8-mipibrdg { 98 compatible = "regulator-fixed"; 99 regulator-name = "pp1800_mipibrdg"; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&pp1800_mipibrdg_en_pins>; 102 enable-active-high; 103 regulator-boot-on; 104 gpio = <&pio 128 GPIO_ACTIVE_HIGH>; 105 vin-supply = <&mt6359_vio18_ldo_reg>; 106 }; 107 108 pp3300_dpbrdg: regulator-3v3-dpbrdg { 109 compatible = "regulator-fixed"; 110 regulator-name = "pp3300_dpbrdg"; 111 pinctrl-names = "default"; 112 pinctrl-0 = <&pp3300_dpbrdg_en_pins>; 113 enable-active-high; 114 regulator-boot-on; 115 gpio = <&pio 26 GPIO_ACTIVE_HIGH>; 116 vin-supply = <&pp3300_g>; 117 }; 118 119 /* system wide switching 3.3V power rail */ 120 pp3300_g: regulator-3v3-g { 121 compatible = "regulator-fixed"; 122 regulator-name = "pp3300_g"; 123 regulator-always-on; 124 regulator-boot-on; 125 regulator-min-microvolt = <3300000>; 126 regulator-max-microvolt = <3300000>; 127 vin-supply = <&ppvar_sys>; 128 }; 129 130 /* system wide LDO 3.3V power rail */ 131 pp3300_ldo_z: regulator-3v3-z { 132 compatible = "regulator-fixed"; 133 regulator-name = "pp3300_ldo_z"; 134 regulator-always-on; 135 regulator-boot-on; 136 regulator-min-microvolt = <3300000>; 137 regulator-max-microvolt = <3300000>; 138 vin-supply = <&ppvar_sys>; 139 }; 140 141 pp3300_mipibrdg: regulator-3v3-mipibrdg { 142 compatible = "regulator-fixed"; 143 regulator-name = "pp3300_mipibrdg"; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pp3300_mipibrdg_en_pins>; 146 enable-active-high; 147 regulator-boot-on; 148 gpio = <&pio 127 GPIO_ACTIVE_HIGH>; 149 vin-supply = <&pp3300_g>; 150 }; 151 152 /* separately switched 3.3V power rail */ 153 pp3300_u: regulator-3v3-u { 154 compatible = "regulator-fixed"; 155 regulator-name = "pp3300_u"; 156 regulator-always-on; 157 regulator-boot-on; 158 regulator-min-microvolt = <3300000>; 159 regulator-max-microvolt = <3300000>; 160 /* enable pin wired to GPIO controlled by EC */ 161 vin-supply = <&pp3300_g>; 162 }; 163 164 pp3300_wlan: regulator-3v3-wlan { 165 compatible = "regulator-fixed"; 166 regulator-name = "pp3300_wlan"; 167 regulator-always-on; 168 regulator-boot-on; 169 regulator-min-microvolt = <3300000>; 170 regulator-max-microvolt = <3300000>; 171 pinctrl-names = "default"; 172 pinctrl-0 = <&pp3300_wlan_pins>; 173 enable-active-high; 174 gpio = <&pio 143 GPIO_ACTIVE_HIGH>; 175 }; 176 177 /* system wide switching 5.0V power rail */ 178 pp5000_a: regulator-5v0-a { 179 compatible = "regulator-fixed"; 180 regulator-name = "pp5000_a"; 181 regulator-always-on; 182 regulator-boot-on; 183 regulator-min-microvolt = <5000000>; 184 regulator-max-microvolt = <5000000>; 185 vin-supply = <&ppvar_sys>; 186 }; 187 188 /* system wide semi-regulated power rail from battery or USB */ 189 ppvar_sys: regulator-var-sys { 190 compatible = "regulator-fixed"; 191 regulator-name = "ppvar_sys"; 192 regulator-always-on; 193 regulator-boot-on; 194 }; 195 196 reserved_memory: reserved-memory { 197 #address-cells = <2>; 198 #size-cells = <2>; 199 ranges; 200 201 scp_mem_reserved: scp@50000000 { 202 compatible = "shared-dma-pool"; 203 reg = <0 0x50000000 0 0x2900000>; 204 no-map; 205 }; 206 207 wifi_restricted_dma_region: wifi@c0000000 { 208 compatible = "restricted-dma-pool"; 209 reg = <0 0xc0000000 0 0x4000000>; 210 }; 211 }; 212 213 sound: sound { 214 mediatek,platform = <&afe>; 215 pinctrl-names = "aud_clk_mosi_off", 216 "aud_clk_mosi_on", 217 "aud_dat_mosi_off", 218 "aud_dat_mosi_on", 219 "aud_dat_miso_off", 220 "aud_dat_miso_on", 221 "vow_dat_miso_off", 222 "vow_dat_miso_on", 223 "vow_clk_miso_off", 224 "vow_clk_miso_on", 225 "aud_nle_mosi_off", 226 "aud_nle_mosi_on", 227 "aud_dat_miso2_off", 228 "aud_dat_miso2_on", 229 "aud_gpio_i2s3_off", 230 "aud_gpio_i2s3_on", 231 "aud_gpio_i2s8_off", 232 "aud_gpio_i2s8_on", 233 "aud_gpio_i2s9_off", 234 "aud_gpio_i2s9_on", 235 "aud_dat_mosi_ch34_off", 236 "aud_dat_mosi_ch34_on", 237 "aud_dat_miso_ch34_off", 238 "aud_dat_miso_ch34_on", 239 "aud_gpio_tdm_off", 240 "aud_gpio_tdm_on"; 241 pinctrl-0 = <&aud_clk_mosi_off_pins>; 242 pinctrl-1 = <&aud_clk_mosi_on_pins>; 243 pinctrl-2 = <&aud_dat_mosi_off_pins>; 244 pinctrl-3 = <&aud_dat_mosi_on_pins>; 245 pinctrl-4 = <&aud_dat_miso_off_pins>; 246 pinctrl-5 = <&aud_dat_miso_on_pins>; 247 pinctrl-6 = <&vow_dat_miso_off_pins>; 248 pinctrl-7 = <&vow_dat_miso_on_pins>; 249 pinctrl-8 = <&vow_clk_miso_off_pins>; 250 pinctrl-9 = <&vow_clk_miso_on_pins>; 251 pinctrl-10 = <&aud_nle_mosi_off_pins>; 252 pinctrl-11 = <&aud_nle_mosi_on_pins>; 253 pinctrl-12 = <&aud_dat_miso2_off_pins>; 254 pinctrl-13 = <&aud_dat_miso2_on_pins>; 255 pinctrl-14 = <&aud_gpio_i2s3_off_pins>; 256 pinctrl-15 = <&aud_gpio_i2s3_on_pins>; 257 pinctrl-16 = <&aud_gpio_i2s8_off_pins>; 258 pinctrl-17 = <&aud_gpio_i2s8_on_pins>; 259 pinctrl-18 = <&aud_gpio_i2s9_off_pins>; 260 pinctrl-19 = <&aud_gpio_i2s9_on_pins>; 261 pinctrl-20 = <&aud_dat_mosi_ch34_off_pins>; 262 pinctrl-21 = <&aud_dat_mosi_ch34_on_pins>; 263 pinctrl-22 = <&aud_dat_miso_ch34_off_pins>; 264 pinctrl-23 = <&aud_dat_miso_ch34_on_pins>; 265 pinctrl-24 = <&aud_gpio_tdm_off_pins>; 266 pinctrl-25 = <&aud_gpio_tdm_on_pins>; 267 }; 268}; 269 270&dsi0 { 271 status = "okay"; 272}; 273 274&dsi_out { 275 remote-endpoint = <&anx7625_in>; 276}; 277 278&i2c0 { 279 status = "okay"; 280 281 clock-frequency = <400000>; 282 pinctrl-names = "default"; 283 pinctrl-0 = <&i2c0_pins>; 284 285 touchscreen: touchscreen@10 { 286 reg = <0x10>; 287 interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&touchscreen_pins>; 290 }; 291}; 292 293&i2c1 { 294 status = "okay"; 295 296 clock-frequency = <400000>; 297 pinctrl-names = "default"; 298 pinctrl-0 = <&i2c1_pins>; 299}; 300 301&i2c2 { 302 status = "okay"; 303 304 clock-frequency = <400000>; 305 clock-stretch-ns = <12600>; 306 pinctrl-names = "default"; 307 pinctrl-0 = <&i2c2_pins>; 308 309 trackpad@15 { 310 compatible = "elan,ekth3000"; 311 reg = <0x15>; 312 interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&trackpad_pins>; 315 vcc-supply = <&pp3300_u>; 316 wakeup-source; 317 }; 318}; 319 320&i2c3 { 321 status = "okay"; 322 323 clock-frequency = <400000>; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&i2c3_pins>; 326 327 anx_bridge: anx7625@58 { 328 compatible = "analogix,anx7625"; 329 reg = <0x58>; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&anx7625_pins>; 332 enable-gpios = <&pio 41 GPIO_ACTIVE_HIGH>; 333 reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; 334 vdd10-supply = <&pp1000_mipibrdg>; 335 vdd18-supply = <&pp1800_mipibrdg>; 336 vdd33-supply = <&pp3300_mipibrdg>; 337 338 ports { 339 #address-cells = <1>; 340 #size-cells = <0>; 341 342 port@0 { 343 reg = <0>; 344 345 anx7625_in: endpoint { 346 remote-endpoint = <&dsi_out>; 347 }; 348 }; 349 350 port@1 { 351 reg = <1>; 352 353 anx7625_out: endpoint { 354 remote-endpoint = <&panel_in>; 355 }; 356 }; 357 }; 358 359 aux-bus { 360 panel: panel { 361 compatible = "edp-panel"; 362 power-supply = <&pp3300_mipibrdg>; 363 backlight = <&backlight_lcd0>; 364 365 port { 366 panel_in: endpoint { 367 remote-endpoint = <&anx7625_out>; 368 }; 369 }; 370 }; 371 }; 372 }; 373}; 374 375&i2c7 { 376 status = "okay"; 377 378 clock-frequency = <400000>; 379 pinctrl-names = "default"; 380 pinctrl-0 = <&i2c7_pins>; 381}; 382 383&mipi_tx0 { 384 status = "okay"; 385}; 386 387&mmc0 { 388 status = "okay"; 389 390 pinctrl-names = "default", "state_uhs"; 391 pinctrl-0 = <&mmc0_default_pins>; 392 pinctrl-1 = <&mmc0_uhs_pins>; 393 bus-width = <8>; 394 max-frequency = <200000000>; 395 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 396 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 397 cap-mmc-highspeed; 398 mmc-hs200-1_8v; 399 mmc-hs400-1_8v; 400 supports-cqe; 401 cap-mmc-hw-reset; 402 mmc-hs400-enhanced-strobe; 403 hs400-ds-delay = <0x12814>; 404 no-sdio; 405 no-sd; 406 non-removable; 407}; 408 409&mmc1 { 410 status = "okay"; 411 412 pinctrl-names = "default", "state_uhs"; 413 pinctrl-0 = <&mmc1_default_pins>; 414 pinctrl-1 = <&mmc1_uhs_pins>; 415 bus-width = <4>; 416 max-frequency = <200000000>; 417 cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>; 418 vmmc-supply = <&mt6360_ldo5_reg>; 419 vqmmc-supply = <&mt6360_ldo3_reg>; 420 cap-sd-highspeed; 421 sd-uhs-sdr50; 422 sd-uhs-sdr104; 423 no-sdio; 424 no-mmc; 425}; 426 427/* for CORE */ 428&mt6359_vgpu11_buck_reg { 429 regulator-always-on; 430}; 431 432&mt6359_vgpu11_sshub_buck_reg { 433 regulator-always-on; 434 regulator-min-microvolt = <575000>; 435 regulator-max-microvolt = <575000>; 436}; 437 438&mt6359_vrf12_ldo_reg { 439 regulator-always-on; 440}; 441 442&mt6359_vufs_ldo_reg { 443 regulator-always-on; 444}; 445 446&mt6359codec { 447 mediatek,dmic-mode = <1>; /* one-wire */ 448 mediatek,mic-type-0 = <2>; /* DMIC */ 449 mediatek,mic-type-2 = <2>; /* DMIC */ 450}; 451 452&nor_flash { 453 status = "okay"; 454 455 pinctrl-names = "default"; 456 pinctrl-0 = <&nor_flash_pins>; 457 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 458 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>; 459 460 flash@0 { 461 compatible = "winbond,w25q64jwm", "jedec,spi-nor"; 462 reg = <0>; 463 spi-max-frequency = <52000000>; 464 spi-rx-bus-width = <2>; 465 spi-tx-bus-width = <2>; 466 }; 467}; 468 469&pcie { 470 pinctrl-names = "default"; 471 pinctrl-0 = <&pcie_pins>; 472 473 pcie0: pcie@0,0 { 474 device_type = "pci"; 475 reg = <0x0000 0 0 0 0>; 476 num-lanes = <1>; 477 bus-range = <0x1 0x1>; 478 479 #address-cells = <3>; 480 #size-cells = <2>; 481 ranges; 482 483 wifi: wifi@0,0 { 484 reg = <0x10000 0 0 0 0x100000>, 485 <0x10000 0 0x100000 0 0x100000>; 486 memory-region = <&wifi_restricted_dma_region>; 487 }; 488 }; 489}; 490 491&pio { 492 /* 220 lines */ 493 gpio-line-names = "I2S_DP_LRCK", 494 "IS_DP_BCLK", 495 "I2S_DP_MCLK", 496 "I2S_DP_DATAOUT", 497 "SAR0_INT_ODL", 498 "EC_AP_INT_ODL", 499 "EDPBRDG_INT_ODL", 500 "DPBRDG_INT_ODL", 501 "DPBRDG_PWREN", 502 "DPBRDG_RST_ODL", 503 "I2S_HP_MCLK", 504 "I2S_HP_BCK", 505 "I2S_HP_LRCK", 506 "I2S_HP_DATAIN", 507 /* 508 * AP_FLASH_WP_L is crossystem ABI. Schematics 509 * call it AP_FLASH_WP_ODL. 510 */ 511 "AP_FLASH_WP_L", 512 "TRACKPAD_INT_ODL", 513 "EC_AP_HPD_OD", 514 "SD_CD_ODL", 515 "HP_INT_ODL_ALC", 516 "EN_PP1000_DPBRDG", 517 "AP_GPIO20", 518 "TOUCH_INT_L_1V8", 519 "UART_BT_WAKE_ODL", 520 "AP_GPIO23", 521 "AP_SPI_FLASH_CS_L", 522 "AP_SPI_FLASH_CLK", 523 "EN_PP3300_DPBRDG_DX", 524 "AP_SPI_FLASH_MOSI", 525 "AP_SPI_FLASH_MISO", 526 "I2S_HP_DATAOUT", 527 "AP_GPIO30", 528 "I2S_SPKR_MCLK", 529 "I2S_SPKR_BCLK", 530 "I2S_SPKR_LRCK", 531 "I2S_SPKR_DATAIN", 532 "I2S_SPKR_DATAOUT", 533 "AP_SPI_H1_TPM_CLK", 534 "AP_SPI_H1_TPM_CS_L", 535 "AP_SPI_H1_TPM_MISO", 536 "AP_SPI_H1_TPM_MOSI", 537 "BL_PWM", 538 "EDPBRDG_PWREN", 539 "EDPBRDG_RST_ODL", 540 "EN_PP3300_HUB", 541 "HUB_RST_L", 542 "", 543 "", 544 "", 545 "", 546 "", 547 "", 548 "SD_CLK", 549 "SD_CMD", 550 "SD_DATA3", 551 "SD_DATA0", 552 "SD_DATA2", 553 "SD_DATA1", 554 "", 555 "", 556 "", 557 "", 558 "", 559 "", 560 "PCIE_WAKE_ODL", 561 "PCIE_RST_L", 562 "PCIE_CLKREQ_ODL", 563 "", 564 "", 565 "", 566 "", 567 "", 568 "", 569 "", 570 "", 571 "", 572 "", 573 "", 574 "", 575 "", 576 "", 577 "", 578 "", 579 "", 580 "", 581 "", 582 "", 583 "", 584 "", 585 "", 586 "SPMI_SCL", 587 "SPMI_SDA", 588 "AP_GOOD", 589 "UART_DBG_TX_AP_RX", 590 "UART_AP_TX_DBG_RX", 591 "UART_AP_TX_BT_RX", 592 "UART_BT_TX_AP_RX", 593 "MIPI_DPI_D0_R", 594 "MIPI_DPI_D1_R", 595 "MIPI_DPI_D2_R", 596 "MIPI_DPI_D3_R", 597 "MIPI_DPI_D4_R", 598 "MIPI_DPI_D5_R", 599 "MIPI_DPI_D6_R", 600 "MIPI_DPI_D7_R", 601 "MIPI_DPI_D8_R", 602 "MIPI_DPI_D9_R", 603 "MIPI_DPI_D10_R", 604 "", 605 "", 606 "MIPI_DPI_DE_R", 607 "MIPI_DPI_D11_R", 608 "MIPI_DPI_VSYNC_R", 609 "MIPI_DPI_CLK_R", 610 "MIPI_DPI_HSYNC_R", 611 "PCM_BT_DATAIN", 612 "PCM_BT_SYNC", 613 "PCM_BT_DATAOUT", 614 "PCM_BT_CLK", 615 "AP_I2C_AUDIO_SCL", 616 "AP_I2C_AUDIO_SDA", 617 "SCP_I2C_SCL", 618 "SCP_I2C_SDA", 619 "AP_I2C_WLAN_SCL", 620 "AP_I2C_WLAN_SDA", 621 "AP_I2C_DPBRDG_SCL", 622 "AP_I2C_DPBRDG_SDA", 623 "EN_PP1800_DPBRDG_DX", 624 "EN_PP3300_EDP_DX", 625 "EN_PP1800_EDPBRDG_DX", 626 "EN_PP1000_EDPBRDG", 627 "SCP_JTAG0_TDO", 628 "SCP_JTAG0_TDI", 629 "SCP_JTAG0_TMS", 630 "SCP_JTAG0_TCK", 631 "SCP_JTAG0_TRSTN", 632 "EN_PP3000_VMC_PMU", 633 "EN_PP3300_DISPLAY_DX", 634 "TOUCH_RST_L_1V8", 635 "TOUCH_REPORT_DISABLE", 636 "", 637 "", 638 "AP_I2C_TRACKPAD_SCL_1V8", 639 "AP_I2C_TRACKPAD_SDA_1V8", 640 "EN_PP3300_WLAN", 641 "BT_KILL_L", 642 "WIFI_KILL_L", 643 "SET_VMC_VOLT_AT_1V8", 644 "EN_SPK", 645 "AP_WARM_RST_REQ", 646 "", 647 "", 648 "EN_PP3000_SD_S3", 649 "AP_EDP_BKLTEN", 650 "", 651 "", 652 "", 653 "AP_SPI_EC_CLK", 654 "AP_SPI_EC_CS_L", 655 "AP_SPI_EC_MISO", 656 "AP_SPI_EC_MOSI", 657 "AP_I2C_EDPBRDG_SCL", 658 "AP_I2C_EDPBRDG_SDA", 659 "MT6315_PROC_INT", 660 "MT6315_GPU_INT", 661 "UART_SERVO_TX_SCP_RX", 662 "UART_SCP_TX_SERVO_RX", 663 "BT_RTS_AP_CTS", 664 "AP_RTS_BT_CTS", 665 "UART_AP_WAKE_BT_ODL", 666 "WLAN_ALERT_ODL", 667 "EC_IN_RW_ODL", 668 "H1_AP_INT_ODL", 669 "", 670 "", 671 "", 672 "", 673 "", 674 "", 675 "", 676 "", 677 "", 678 "", 679 "", 680 "MSDC0_CMD", 681 "MSDC0_DAT0", 682 "MSDC0_DAT2", 683 "MSDC0_DAT4", 684 "MSDC0_DAT6", 685 "MSDC0_DAT1", 686 "MSDC0_DAT5", 687 "MSDC0_DAT7", 688 "MSDC0_DSL", 689 "MSDC0_CLK", 690 "MSDC0_DAT3", 691 "MSDC0_RST_L", 692 "SCP_VREQ_VAO", 693 "AUD_DAT_MOSI2", 694 "AUD_NLE_MOSI1", 695 "AUD_NLE_MOSI0", 696 "AUD_DAT_MISO2", 697 "AP_I2C_SAR_SDA", 698 "AP_I2C_SAR_SCL", 699 "AP_I2C_PWR_SCL", 700 "AP_I2C_PWR_SDA", 701 "AP_I2C_TS_SCL_1V8", 702 "AP_I2C_TS_SDA_1V8", 703 "SRCLKENA0", 704 "SRCLKENA1", 705 "AP_EC_WATCHDOG_L", 706 "PWRAP_SPI0_MI", 707 "PWRAP_SPI0_CSN", 708 "PWRAP_SPI0_MO", 709 "PWRAP_SPI0_CK", 710 "AP_RTC_CLK32K", 711 "AUD_CLK_MOSI", 712 "AUD_SYNC_MOSI", 713 "AUD_DAT_MOSI0", 714 "AUD_DAT_MOSI1", 715 "AUD_DAT_MISO0", 716 "AUD_DAT_MISO1"; 717 718 anx7625_pins: anx7625-default-pins { 719 pins-out { 720 pinmux = <PINMUX_GPIO41__FUNC_GPIO41>, 721 <PINMUX_GPIO42__FUNC_GPIO42>; 722 output-low; 723 }; 724 725 pins-in { 726 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 727 input-enable; 728 bias-pull-up; 729 }; 730 }; 731 732 aud_clk_mosi_off_pins: aud-clk-mosi-off-pins { 733 pins-mosi-off { 734 pinmux = <PINMUX_GPIO214__FUNC_GPIO214>, 735 <PINMUX_GPIO215__FUNC_GPIO215>; 736 }; 737 }; 738 739 aud_clk_mosi_on_pins: aud-clk-mosi-on-pins { 740 pins-mosi-on { 741 pinmux = <PINMUX_GPIO214__FUNC_AUD_CLK_MOSI>, 742 <PINMUX_GPIO215__FUNC_AUD_SYNC_MOSI>; 743 drive-strength = <10>; 744 }; 745 }; 746 747 aud_dat_miso_ch34_off_pins: aud-dat-miso-ch34-off-pins { 748 pins-miso-off { 749 pinmux = <PINMUX_GPIO199__FUNC_GPIO199>; 750 }; 751 }; 752 753 aud_dat_miso_ch34_on_pins: aud-dat-miso-ch34-on-pins { 754 pins-miso-on { 755 pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>; 756 }; 757 }; 758 759 aud_dat_miso_off_pins: aud-dat-miso-off-pins { 760 pins-miso-off { 761 pinmux = <PINMUX_GPIO218__FUNC_GPIO218>, 762 <PINMUX_GPIO219__FUNC_GPIO219>; 763 }; 764 }; 765 766 aud_dat_miso_on_pins: aud-dat-miso-on-pins { 767 pins-miso-on { 768 pinmux = <PINMUX_GPIO218__FUNC_AUD_DAT_MISO0>, 769 <PINMUX_GPIO219__FUNC_AUD_DAT_MISO1>; 770 drive-strength = <10>; 771 }; 772 }; 773 774 aud_dat_miso2_off_pins: aud-dat-miso2-off-pins { 775 pins-miso-off { 776 pinmux = <PINMUX_GPIO199__FUNC_GPIO199>; 777 }; 778 }; 779 780 aud_dat_miso2_on_pins: aud-dat-miso2-on-pins { 781 pins-miso-on { 782 pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>; 783 }; 784 }; 785 786 aud_dat_mosi_ch34_off_pins: aud-dat-mosi-ch34-off-pins { 787 pins-mosi-off { 788 pinmux = <PINMUX_GPIO196__FUNC_GPIO196>; 789 }; 790 }; 791 792 aud_dat_mosi_ch34_on_pins: aud-dat-mosi-ch34-on-pins { 793 pins-mosi-on { 794 pinmux = <PINMUX_GPIO196__FUNC_AUD_DAT_MOSI2>; 795 }; 796 }; 797 798 aud_dat_mosi_off_pins: aud-dat-mosi-off-pins { 799 pins-mosi-off { 800 pinmux = <PINMUX_GPIO216__FUNC_GPIO216>, 801 <PINMUX_GPIO217__FUNC_GPIO217>; 802 }; 803 }; 804 805 aud_dat_mosi_on_pins: aud-dat-mosi-on-pins { 806 pins-mosi-on { 807 pinmux = <PINMUX_GPIO216__FUNC_AUD_DAT_MOSI0>, 808 <PINMUX_GPIO217__FUNC_AUD_DAT_MOSI1>; 809 drive-strength = <10>; 810 }; 811 }; 812 813 aud_gpio_i2s3_off_pins: aud-gpio-i2s3-off-pins { 814 pins-i2s3-off { 815 pinmux = <PINMUX_GPIO32__FUNC_GPIO32>, 816 <PINMUX_GPIO33__FUNC_GPIO33>, 817 <PINMUX_GPIO35__FUNC_GPIO35>; 818 }; 819 }; 820 821 aud_gpio_i2s3_on_pins: aud-gpio-i2s3-on-pins { 822 pins-i2s3-on { 823 pinmux = <PINMUX_GPIO32__FUNC_I2S3_BCK>, 824 <PINMUX_GPIO33__FUNC_I2S3_LRCK>, 825 <PINMUX_GPIO35__FUNC_I2S3_DO>; 826 }; 827 }; 828 829 aud_gpio_i2s8_off_pins: aud-gpio-i2s8-off-pins { 830 pins-i2s8-off { 831 pinmux = <PINMUX_GPIO10__FUNC_GPIO10>, 832 <PINMUX_GPIO11__FUNC_GPIO11>, 833 <PINMUX_GPIO12__FUNC_GPIO12>, 834 <PINMUX_GPIO13__FUNC_GPIO13>; 835 }; 836 }; 837 838 aud_gpio_i2s8_on_pins: aud-gpio-i2s8-on-pins { 839 pins-i2s8-on { 840 pinmux = <PINMUX_GPIO10__FUNC_I2S8_MCK>, 841 <PINMUX_GPIO11__FUNC_I2S8_BCK>, 842 <PINMUX_GPIO12__FUNC_I2S8_LRCK>, 843 <PINMUX_GPIO13__FUNC_I2S8_DI>; 844 }; 845 }; 846 847 aud_gpio_i2s9_off_pins: aud-gpio-i2s9-off-pins { 848 pins-i2s9-off { 849 pinmux = <PINMUX_GPIO29__FUNC_GPIO29>; 850 }; 851 }; 852 853 aud_gpio_i2s9_on_pins: aud-gpio-i2s9-on-pins { 854 pins-i2s9-on { 855 pinmux = <PINMUX_GPIO29__FUNC_I2S9_DO>; 856 }; 857 }; 858 859 aud_gpio_tdm_off_pins: aud-gpio-tdm-off-pins { 860 pins-tdm-off { 861 pinmux = <PINMUX_GPIO0__FUNC_GPIO0>, 862 <PINMUX_GPIO1__FUNC_GPIO1>, 863 <PINMUX_GPIO2__FUNC_GPIO2>, 864 <PINMUX_GPIO3__FUNC_GPIO3>; 865 }; 866 }; 867 868 aud_gpio_tdm_on_pins: aud-gpio-tdm-on-pins { 869 pins-tdm-on { 870 pinmux = <PINMUX_GPIO0__FUNC_TDM_LRCK>, 871 <PINMUX_GPIO1__FUNC_TDM_BCK>, 872 <PINMUX_GPIO2__FUNC_TDM_MCK>, 873 <PINMUX_GPIO3__FUNC_TDM_DATA0>; 874 }; 875 }; 876 877 aud_nle_mosi_off_pins: aud-nle-mosi-off-pins { 878 pins-nle-mosi-off { 879 pinmux = <PINMUX_GPIO197__FUNC_GPIO197>, 880 <PINMUX_GPIO198__FUNC_GPIO198>; 881 }; 882 }; 883 884 aud_nle_mosi_on_pins: aud-nle-mosi-on-pins { 885 pins-nle-mosi-on { 886 pinmux = <PINMUX_GPIO197__FUNC_AUD_NLE_MOSI1>, 887 <PINMUX_GPIO198__FUNC_AUD_NLE_MOSI0>; 888 }; 889 }; 890 891 cr50_int: cr50-irq-default-pins { 892 pins-gsc-ap-int-odl { 893 pinmux = <PINMUX_GPIO171__FUNC_GPIO171>; 894 input-enable; 895 }; 896 }; 897 898 cros_ec_int: cros-ec-irq-default-pins { 899 pins-ec-ap-int-odl { 900 pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; 901 input-enable; 902 bias-pull-up; 903 }; 904 }; 905 906 i2c0_pins: i2c0-default-pins { 907 pins-bus { 908 pinmux = <PINMUX_GPIO204__FUNC_SCL0>, 909 <PINMUX_GPIO205__FUNC_SDA0>; 910 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 911 drive-strength-microamp = <1000>; 912 }; 913 }; 914 915 i2c1_pins: i2c1-default-pins { 916 pins-bus { 917 pinmux = <PINMUX_GPIO118__FUNC_SCL1>, 918 <PINMUX_GPIO119__FUNC_SDA1>; 919 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 920 drive-strength-microamp = <1000>; 921 }; 922 }; 923 924 i2c2_pins: i2c2-default-pins { 925 pins-bus { 926 pinmux = <PINMUX_GPIO141__FUNC_SCL2>, 927 <PINMUX_GPIO142__FUNC_SDA2>; 928 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 929 }; 930 }; 931 932 i2c3_pins: i2c3-default-pins { 933 pins-bus { 934 pinmux = <PINMUX_GPIO160__FUNC_SCL3>, 935 <PINMUX_GPIO161__FUNC_SDA3>; 936 bias-disable; 937 drive-strength-microamp = <1000>; 938 }; 939 }; 940 941 i2c7_pins: i2c7-default-pins { 942 pins-bus { 943 pinmux = <PINMUX_GPIO124__FUNC_SCL7>, 944 <PINMUX_GPIO125__FUNC_SDA7>; 945 bias-disable; 946 drive-strength-microamp = <1000>; 947 }; 948 }; 949 950 mmc0_default_pins: mmc0-default-pins { 951 pins-cmd-dat { 952 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 953 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 954 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 955 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 956 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 957 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 958 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 959 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 960 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 961 input-enable; 962 drive-strength = <8>; 963 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 964 }; 965 966 pins-clk { 967 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 968 drive-strength = <8>; 969 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 970 }; 971 972 pins-rst { 973 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 974 drive-strength = <8>; 975 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 976 }; 977 }; 978 979 mmc0_uhs_pins: mmc0-uhs-pins { 980 pins-cmd-dat { 981 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 982 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 983 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 984 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 985 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 986 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 987 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 988 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 989 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 990 input-enable; 991 drive-strength = <10>; 992 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 993 }; 994 995 pins-clk { 996 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 997 drive-strength = <10>; 998 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 999 }; 1000 1001 pins-rst { 1002 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 1003 drive-strength = <8>; 1004 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 1005 }; 1006 1007 pins-ds { 1008 pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>; 1009 drive-strength = <10>; 1010 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1011 }; 1012 }; 1013 1014 mmc1_default_pins: mmc1-default-pins { 1015 pins-cmd-dat { 1016 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 1017 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 1018 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 1019 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 1020 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 1021 input-enable; 1022 drive-strength = <8>; 1023 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1024 }; 1025 1026 pins-clk { 1027 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 1028 drive-strength = <8>; 1029 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1030 }; 1031 1032 pins-insert { 1033 pinmux = <PINMUX_GPIO17__FUNC_GPIO17>; 1034 input-enable; 1035 bias-pull-up; 1036 }; 1037 }; 1038 1039 mmc1_uhs_pins: mmc1-uhs-pins { 1040 pins-cmd-dat { 1041 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 1042 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 1043 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 1044 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 1045 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 1046 input-enable; 1047 drive-strength = <8>; 1048 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1049 }; 1050 1051 pins-clk { 1052 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 1053 input-enable; 1054 drive-strength = <8>; 1055 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1056 }; 1057 }; 1058 1059 nor_flash_pins: nor-flash-default-pins { 1060 pins-cs-io1 { 1061 pinmux = <PINMUX_GPIO24__FUNC_SPINOR_CS>, 1062 <PINMUX_GPIO28__FUNC_SPINOR_IO1>; 1063 input-enable; 1064 bias-pull-up; 1065 drive-strength = <10>; 1066 }; 1067 1068 pins-io0 { 1069 pinmux = <PINMUX_GPIO27__FUNC_SPINOR_IO0>; 1070 bias-pull-up; 1071 drive-strength = <10>; 1072 }; 1073 1074 pins-clk { 1075 pinmux = <PINMUX_GPIO25__FUNC_SPINOR_CK>; 1076 input-enable; 1077 bias-pull-up; 1078 drive-strength = <10>; 1079 }; 1080 }; 1081 1082 pcie_pins: pcie-default-pins { 1083 pins-pcie-wake { 1084 pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>; 1085 bias-pull-up; 1086 }; 1087 1088 pins-pcie-pereset { 1089 pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>; 1090 }; 1091 1092 pins-pcie-clkreq { 1093 pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>; 1094 bias-pull-up; 1095 }; 1096 1097 pins-wifi-kill { 1098 pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */ 1099 output-high; 1100 }; 1101 }; 1102 1103 pp1000_dpbrdg_en_pins: pp1000-dpbrdg-en-pins { 1104 pins-en { 1105 pinmux = <PINMUX_GPIO19__FUNC_GPIO19>; 1106 output-low; 1107 }; 1108 }; 1109 1110 pp1000_mipibrdg_en_pins: pp1000-mipibrdg-en-pins { 1111 pins-en { 1112 pinmux = <PINMUX_GPIO129__FUNC_GPIO129>; 1113 output-low; 1114 }; 1115 }; 1116 1117 pp1800_dpbrdg_en_pins: pp1800-dpbrdg-en-pins { 1118 pins-en { 1119 pinmux = <PINMUX_GPIO126__FUNC_GPIO126>; 1120 output-low; 1121 }; 1122 }; 1123 1124 pp1800_mipibrdg_en_pins: pp1800-mipibrd-en-pins { 1125 pins-en { 1126 pinmux = <PINMUX_GPIO128__FUNC_GPIO128>; 1127 output-low; 1128 }; 1129 }; 1130 1131 pp3300_dpbrdg_en_pins: pp3300-dpbrdg-en-pins { 1132 pins-en { 1133 pinmux = <PINMUX_GPIO26__FUNC_GPIO26>; 1134 output-low; 1135 }; 1136 }; 1137 1138 pp3300_mipibrdg_en_pins: pp3300-mipibrdg-en-pins { 1139 pins-en { 1140 pinmux = <PINMUX_GPIO127__FUNC_GPIO127>; 1141 output-low; 1142 }; 1143 }; 1144 1145 pp3300_wlan_pins: pp3300-wlan-pins { 1146 pins-pcie-en-pp3300-wlan { 1147 pinmux = <PINMUX_GPIO143__FUNC_GPIO143>; 1148 output-high; 1149 }; 1150 }; 1151 1152 pwm0_pins: pwm0-default-pins { 1153 pins-pwm { 1154 pinmux = <PINMUX_GPIO40__FUNC_DISP_PWM>; 1155 }; 1156 1157 pins-inhibit { 1158 pinmux = <PINMUX_GPIO152__FUNC_GPIO152>; 1159 output-high; 1160 }; 1161 }; 1162 1163 scp_pins: scp-pins { 1164 pins-vreq-vao { 1165 pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>; 1166 }; 1167 }; 1168 1169 spi1_pins: spi1-default-pins { 1170 pins-cs-mosi-clk { 1171 pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, 1172 <PINMUX_GPIO159__FUNC_SPI1_A_MO>, 1173 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; 1174 bias-disable; 1175 }; 1176 1177 pins-miso { 1178 pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; 1179 bias-pull-down; 1180 }; 1181 }; 1182 1183 spi5_pins: spi5-default-pins { 1184 pins-bus { 1185 pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>, 1186 <PINMUX_GPIO37__FUNC_GPIO37>, 1187 <PINMUX_GPIO39__FUNC_SPI5_A_MO>, 1188 <PINMUX_GPIO36__FUNC_SPI5_A_CLK>; 1189 bias-disable; 1190 }; 1191 }; 1192 1193 trackpad_pins: trackpad-default-pins { 1194 pins-int-n { 1195 pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; 1196 input-enable; 1197 bias-pull-up = <MTK_PUPD_SET_R1R0_11>; 1198 }; 1199 }; 1200 1201 touchscreen_pins: touchscreen-default-pins { 1202 pins-irq { 1203 pinmux = <PINMUX_GPIO21__FUNC_GPIO21>; 1204 input-enable; 1205 bias-pull-up; 1206 }; 1207 1208 pins-reset { 1209 pinmux = <PINMUX_GPIO137__FUNC_GPIO137>; 1210 output-high; 1211 }; 1212 1213 pins-report-sw { 1214 pinmux = <PINMUX_GPIO138__FUNC_GPIO138>; 1215 output-low; 1216 }; 1217 }; 1218 1219 vow_clk_miso_off_pins: vow-clk-miso-off-pins { 1220 pins-miso-off { 1221 pinmux = <PINMUX_GPIO219__FUNC_GPIO219>; 1222 }; 1223 }; 1224 1225 vow_clk_miso_on_pins: vow-clk-miso-on-pins { 1226 pins-miso-on { 1227 pinmux = <PINMUX_GPIO219__FUNC_VOW_CLK_MISO>; 1228 }; 1229 }; 1230 1231 vow_dat_miso_off_pins: vow-dat-miso-off-pins { 1232 pins-miso-off { 1233 pinmux = <PINMUX_GPIO218__FUNC_GPIO218>; 1234 }; 1235 }; 1236 1237 vow_dat_miso_on_pins: vow-dat-miso-on-pins { 1238 pins-miso-on { 1239 pinmux = <PINMUX_GPIO218__FUNC_VOW_DAT_MISO>; 1240 }; 1241 }; 1242}; 1243 1244&pmic { 1245 interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>; 1246}; 1247 1248&pwm0 { 1249 status = "okay"; 1250 1251 pinctrl-names = "default"; 1252 pinctrl-0 = <&pwm0_pins>; 1253}; 1254 1255&scp { 1256 status = "okay"; 1257 1258 firmware-name = "mediatek/mt8192/scp.img"; 1259 memory-region = <&scp_mem_reserved>; 1260 pinctrl-names = "default"; 1261 pinctrl-0 = <&scp_pins>; 1262 1263 cros-ec { 1264 compatible = "google,cros-ec-rpmsg"; 1265 mediatek,rpmsg-name = "cros-ec-rpmsg"; 1266 }; 1267}; 1268 1269&spi1 { 1270 status = "okay"; 1271 1272 mediatek,pad-select = <0>; 1273 pinctrl-names = "default"; 1274 pinctrl-0 = <&spi1_pins>; 1275 1276 cros_ec: ec@0 { 1277 compatible = "google,cros-ec-spi"; 1278 reg = <0>; 1279 interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; 1280 spi-max-frequency = <3000000>; 1281 pinctrl-names = "default"; 1282 pinctrl-0 = <&cros_ec_int>; 1283 1284 #address-cells = <1>; 1285 #size-cells = <0>; 1286 1287 base_detection: cbas { 1288 compatible = "google,cros-cbas"; 1289 }; 1290 1291 cros_ec_pwm: pwm { 1292 compatible = "google,cros-ec-pwm"; 1293 #pwm-cells = <1>; 1294 1295 status = "disabled"; 1296 }; 1297 1298 i2c_tunnel: i2c-tunnel { 1299 compatible = "google,cros-ec-i2c-tunnel"; 1300 google,remote-bus = <0>; 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 }; 1304 1305 mt6360_ldo3_reg: regulator@0 { 1306 compatible = "google,cros-ec-regulator"; 1307 reg = <0>; 1308 regulator-min-microvolt = <1800000>; 1309 regulator-max-microvolt = <3300000>; 1310 }; 1311 1312 mt6360_ldo5_reg: regulator@1 { 1313 compatible = "google,cros-ec-regulator"; 1314 reg = <1>; 1315 regulator-min-microvolt = <3300000>; 1316 regulator-max-microvolt = <3300000>; 1317 }; 1318 1319 typec { 1320 compatible = "google,cros-ec-typec"; 1321 #address-cells = <1>; 1322 #size-cells = <0>; 1323 1324 usb_c0: connector@0 { 1325 compatible = "usb-c-connector"; 1326 reg = <0>; 1327 label = "left"; 1328 power-role = "dual"; 1329 data-role = "host"; 1330 try-power-role = "source"; 1331 }; 1332 1333 usb_c1: connector@1 { 1334 compatible = "usb-c-connector"; 1335 reg = <1>; 1336 label = "right"; 1337 power-role = "dual"; 1338 data-role = "host"; 1339 try-power-role = "source"; 1340 }; 1341 }; 1342 }; 1343}; 1344 1345&spi5 { 1346 status = "okay"; 1347 1348 cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>; 1349 mediatek,pad-select = <0>; 1350 pinctrl-names = "default"; 1351 pinctrl-0 = <&spi5_pins>; 1352 1353 cr50@0 { 1354 compatible = "google,cr50"; 1355 reg = <0>; 1356 interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>; 1357 spi-max-frequency = <1000000>; 1358 pinctrl-names = "default"; 1359 pinctrl-0 = <&cr50_int>; 1360 }; 1361}; 1362 1363&spmi { 1364 #address-cells = <2>; 1365 #size-cells = <0>; 1366 1367 mt6315_6: pmic@6 { 1368 compatible = "mediatek,mt6315-regulator"; 1369 reg = <0x6 SPMI_USID>; 1370 1371 regulators { 1372 mt6315_6_vbuck1: vbuck1 { 1373 regulator-compatible = "vbuck1"; 1374 regulator-name = "Vbcpu"; 1375 regulator-min-microvolt = <300000>; 1376 regulator-max-microvolt = <1193750>; 1377 regulator-enable-ramp-delay = <256>; 1378 regulator-allowed-modes = <0 1 2>; 1379 regulator-always-on; 1380 }; 1381 1382 mt6315_6_vbuck3: vbuck3 { 1383 regulator-compatible = "vbuck3"; 1384 regulator-name = "Vlcpu"; 1385 regulator-min-microvolt = <300000>; 1386 regulator-max-microvolt = <1193750>; 1387 regulator-enable-ramp-delay = <256>; 1388 regulator-allowed-modes = <0 1 2>; 1389 regulator-always-on; 1390 }; 1391 }; 1392 }; 1393 1394 mt6315_7: pmic@7 { 1395 compatible = "mediatek,mt6315-regulator"; 1396 reg = <0x7 SPMI_USID>; 1397 1398 regulators { 1399 mt6315_7_vbuck1: vbuck1 { 1400 regulator-compatible = "vbuck1"; 1401 regulator-name = "Vgpu"; 1402 regulator-min-microvolt = <606250>; 1403 regulator-max-microvolt = <1193750>; 1404 regulator-enable-ramp-delay = <256>; 1405 regulator-allowed-modes = <0 1 2>; 1406 }; 1407 }; 1408 }; 1409}; 1410 1411&uart0 { 1412 status = "okay"; 1413}; 1414 1415&xhci { 1416 status = "okay"; 1417 1418 wakeup-source; 1419 vusb33-supply = <&pp3300_g>; 1420 vbus-supply = <&pp5000_a>; 1421}; 1422 1423#include <arm/cros-ec-keyboard.dtsi> 1424#include <arm/cros-ec-sbs.dtsi> 1425