1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6/dts-v1/; 7#include "mt8192.dtsi" 8#include "mt6359.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/spmi/spmi.h> 11 12/ { 13 aliases { 14 serial0 = &uart0; 15 }; 16 17 chosen { 18 stdout-path = "serial0:115200n8"; 19 }; 20 21 memory@40000000 { 22 device_type = "memory"; 23 reg = <0 0x40000000 0 0x80000000>; 24 }; 25 26 /* system wide LDO 1.8V power rail */ 27 pp1800_ldo_g: regulator-1v8-g { 28 compatible = "regulator-fixed"; 29 regulator-name = "pp1800_ldo_g"; 30 regulator-always-on; 31 regulator-boot-on; 32 regulator-min-microvolt = <1800000>; 33 regulator-max-microvolt = <1800000>; 34 vin-supply = <&pp3300_g>; 35 }; 36 37 /* system wide switching 3.3V power rail */ 38 pp3300_g: regulator-3v3-g { 39 compatible = "regulator-fixed"; 40 regulator-name = "pp3300_g"; 41 regulator-always-on; 42 regulator-boot-on; 43 regulator-min-microvolt = <3300000>; 44 regulator-max-microvolt = <3300000>; 45 vin-supply = <&ppvar_sys>; 46 }; 47 48 /* system wide LDO 3.3V power rail */ 49 pp3300_ldo_z: regulator-3v3-z { 50 compatible = "regulator-fixed"; 51 regulator-name = "pp3300_ldo_z"; 52 regulator-always-on; 53 regulator-boot-on; 54 regulator-min-microvolt = <3300000>; 55 regulator-max-microvolt = <3300000>; 56 vin-supply = <&ppvar_sys>; 57 }; 58 59 /* separately switched 3.3V power rail */ 60 pp3300_u: regulator-3v3-u { 61 compatible = "regulator-fixed"; 62 regulator-name = "pp3300_u"; 63 regulator-always-on; 64 regulator-boot-on; 65 regulator-min-microvolt = <3300000>; 66 regulator-max-microvolt = <3300000>; 67 /* enable pin wired to GPIO controlled by EC */ 68 vin-supply = <&pp3300_g>; 69 }; 70 71 pp3300_wlan: regulator-3v3-wlan { 72 compatible = "regulator-fixed"; 73 regulator-name = "pp3300_wlan"; 74 regulator-always-on; 75 regulator-boot-on; 76 regulator-min-microvolt = <3300000>; 77 regulator-max-microvolt = <3300000>; 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pp3300_wlan_pins>; 80 enable-active-high; 81 gpio = <&pio 143 GPIO_ACTIVE_HIGH>; 82 }; 83 84 /* system wide switching 5.0V power rail */ 85 pp5000_a: regulator-5v0-a { 86 compatible = "regulator-fixed"; 87 regulator-name = "pp5000_a"; 88 regulator-always-on; 89 regulator-boot-on; 90 regulator-min-microvolt = <5000000>; 91 regulator-max-microvolt = <5000000>; 92 vin-supply = <&ppvar_sys>; 93 }; 94 95 /* system wide semi-regulated power rail from battery or USB */ 96 ppvar_sys: regulator-var-sys { 97 compatible = "regulator-fixed"; 98 regulator-name = "ppvar_sys"; 99 regulator-always-on; 100 regulator-boot-on; 101 }; 102 103 reserved_memory: reserved-memory { 104 #address-cells = <2>; 105 #size-cells = <2>; 106 ranges; 107 108 scp_mem_reserved: scp@50000000 { 109 compatible = "shared-dma-pool"; 110 reg = <0 0x50000000 0 0x2900000>; 111 no-map; 112 }; 113 114 wifi_restricted_dma_region: wifi@c0000000 { 115 compatible = "restricted-dma-pool"; 116 reg = <0 0xc0000000 0 0x4000000>; 117 }; 118 }; 119}; 120 121&i2c0 { 122 status = "okay"; 123 124 clock-frequency = <400000>; 125 pinctrl-names = "default"; 126 pinctrl-0 = <&i2c0_pins>; 127 128 touchscreen: touchscreen@10 { 129 reg = <0x10>; 130 interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>; 131 pinctrl-names = "default"; 132 pinctrl-0 = <&touchscreen_pins>; 133 }; 134}; 135 136&i2c1 { 137 status = "okay"; 138 139 clock-frequency = <400000>; 140 pinctrl-names = "default"; 141 pinctrl-0 = <&i2c1_pins>; 142}; 143 144&i2c2 { 145 status = "okay"; 146 147 clock-frequency = <400000>; 148 clock-stretch-ns = <12600>; 149 pinctrl-names = "default"; 150 pinctrl-0 = <&i2c2_pins>; 151 152 trackpad@15 { 153 compatible = "elan,ekth3000"; 154 reg = <0x15>; 155 interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; 156 pinctrl-names = "default"; 157 pinctrl-0 = <&trackpad_pins>; 158 vcc-supply = <&pp3300_u>; 159 wakeup-source; 160 }; 161}; 162 163&i2c3 { 164 status = "okay"; 165 166 clock-frequency = <400000>; 167 pinctrl-names = "default"; 168 pinctrl-0 = <&i2c3_pins>; 169}; 170 171&i2c7 { 172 status = "okay"; 173 174 clock-frequency = <400000>; 175 pinctrl-names = "default"; 176 pinctrl-0 = <&i2c7_pins>; 177}; 178 179&mmc0 { 180 status = "okay"; 181 182 pinctrl-names = "default", "state_uhs"; 183 pinctrl-0 = <&mmc0_default_pins>; 184 pinctrl-1 = <&mmc0_uhs_pins>; 185 bus-width = <8>; 186 max-frequency = <200000000>; 187 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 188 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 189 cap-mmc-highspeed; 190 mmc-hs200-1_8v; 191 mmc-hs400-1_8v; 192 supports-cqe; 193 cap-mmc-hw-reset; 194 mmc-hs400-enhanced-strobe; 195 hs400-ds-delay = <0x12814>; 196 no-sdio; 197 no-sd; 198 non-removable; 199}; 200 201&mmc1 { 202 status = "okay"; 203 204 pinctrl-names = "default", "state_uhs"; 205 pinctrl-0 = <&mmc1_default_pins>; 206 pinctrl-1 = <&mmc1_uhs_pins>; 207 bus-width = <4>; 208 max-frequency = <200000000>; 209 cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>; 210 vmmc-supply = <&mt6360_ldo5_reg>; 211 vqmmc-supply = <&mt6360_ldo3_reg>; 212 cap-sd-highspeed; 213 sd-uhs-sdr50; 214 sd-uhs-sdr104; 215 no-sdio; 216 no-mmc; 217}; 218 219/* for CORE */ 220&mt6359_vgpu11_buck_reg { 221 regulator-always-on; 222}; 223 224&mt6359_vgpu11_sshub_buck_reg { 225 regulator-always-on; 226 regulator-min-microvolt = <575000>; 227 regulator-max-microvolt = <575000>; 228}; 229 230&mt6359_vrf12_ldo_reg { 231 regulator-always-on; 232}; 233 234&mt6359_vufs_ldo_reg { 235 regulator-always-on; 236}; 237 238&mt6359codec { 239 mediatek,dmic-mode = <1>; /* one-wire */ 240 mediatek,mic-type-0 = <2>; /* DMIC */ 241 mediatek,mic-type-2 = <2>; /* DMIC */ 242}; 243 244&pcie { 245 pinctrl-names = "default"; 246 pinctrl-0 = <&pcie_pins>; 247 248 pcie0: pcie@0,0 { 249 device_type = "pci"; 250 reg = <0x0000 0 0 0 0>; 251 num-lanes = <1>; 252 bus-range = <0x1 0x1>; 253 254 #address-cells = <3>; 255 #size-cells = <2>; 256 ranges; 257 258 wifi: wifi@0,0 { 259 reg = <0x10000 0 0 0 0x100000>, 260 <0x10000 0 0x100000 0 0x100000>; 261 memory-region = <&wifi_restricted_dma_region>; 262 }; 263 }; 264}; 265 266&pio { 267 /* 220 lines */ 268 gpio-line-names = "I2S_DP_LRCK", 269 "IS_DP_BCLK", 270 "I2S_DP_MCLK", 271 "I2S_DP_DATAOUT", 272 "SAR0_INT_ODL", 273 "EC_AP_INT_ODL", 274 "EDPBRDG_INT_ODL", 275 "DPBRDG_INT_ODL", 276 "DPBRDG_PWREN", 277 "DPBRDG_RST_ODL", 278 "I2S_HP_MCLK", 279 "I2S_HP_BCK", 280 "I2S_HP_LRCK", 281 "I2S_HP_DATAIN", 282 /* 283 * AP_FLASH_WP_L is crossystem ABI. Schematics 284 * call it AP_FLASH_WP_ODL. 285 */ 286 "AP_FLASH_WP_L", 287 "TRACKPAD_INT_ODL", 288 "EC_AP_HPD_OD", 289 "SD_CD_ODL", 290 "HP_INT_ODL_ALC", 291 "EN_PP1000_DPBRDG", 292 "AP_GPIO20", 293 "TOUCH_INT_L_1V8", 294 "UART_BT_WAKE_ODL", 295 "AP_GPIO23", 296 "AP_SPI_FLASH_CS_L", 297 "AP_SPI_FLASH_CLK", 298 "EN_PP3300_DPBRDG_DX", 299 "AP_SPI_FLASH_MOSI", 300 "AP_SPI_FLASH_MISO", 301 "I2S_HP_DATAOUT", 302 "AP_GPIO30", 303 "I2S_SPKR_MCLK", 304 "I2S_SPKR_BCLK", 305 "I2S_SPKR_LRCK", 306 "I2S_SPKR_DATAIN", 307 "I2S_SPKR_DATAOUT", 308 "AP_SPI_H1_TPM_CLK", 309 "AP_SPI_H1_TPM_CS_L", 310 "AP_SPI_H1_TPM_MISO", 311 "AP_SPI_H1_TPM_MOSI", 312 "BL_PWM", 313 "EDPBRDG_PWREN", 314 "EDPBRDG_RST_ODL", 315 "EN_PP3300_HUB", 316 "HUB_RST_L", 317 "", 318 "", 319 "", 320 "", 321 "", 322 "", 323 "SD_CLK", 324 "SD_CMD", 325 "SD_DATA3", 326 "SD_DATA0", 327 "SD_DATA2", 328 "SD_DATA1", 329 "", 330 "", 331 "", 332 "", 333 "", 334 "", 335 "PCIE_WAKE_ODL", 336 "PCIE_RST_L", 337 "PCIE_CLKREQ_ODL", 338 "", 339 "", 340 "", 341 "", 342 "", 343 "", 344 "", 345 "", 346 "", 347 "", 348 "", 349 "", 350 "", 351 "", 352 "", 353 "", 354 "", 355 "", 356 "", 357 "", 358 "", 359 "", 360 "", 361 "SPMI_SCL", 362 "SPMI_SDA", 363 "AP_GOOD", 364 "UART_DBG_TX_AP_RX", 365 "UART_AP_TX_DBG_RX", 366 "UART_AP_TX_BT_RX", 367 "UART_BT_TX_AP_RX", 368 "MIPI_DPI_D0_R", 369 "MIPI_DPI_D1_R", 370 "MIPI_DPI_D2_R", 371 "MIPI_DPI_D3_R", 372 "MIPI_DPI_D4_R", 373 "MIPI_DPI_D5_R", 374 "MIPI_DPI_D6_R", 375 "MIPI_DPI_D7_R", 376 "MIPI_DPI_D8_R", 377 "MIPI_DPI_D9_R", 378 "MIPI_DPI_D10_R", 379 "", 380 "", 381 "MIPI_DPI_DE_R", 382 "MIPI_DPI_D11_R", 383 "MIPI_DPI_VSYNC_R", 384 "MIPI_DPI_CLK_R", 385 "MIPI_DPI_HSYNC_R", 386 "PCM_BT_DATAIN", 387 "PCM_BT_SYNC", 388 "PCM_BT_DATAOUT", 389 "PCM_BT_CLK", 390 "AP_I2C_AUDIO_SCL", 391 "AP_I2C_AUDIO_SDA", 392 "SCP_I2C_SCL", 393 "SCP_I2C_SDA", 394 "AP_I2C_WLAN_SCL", 395 "AP_I2C_WLAN_SDA", 396 "AP_I2C_DPBRDG_SCL", 397 "AP_I2C_DPBRDG_SDA", 398 "EN_PP1800_DPBRDG_DX", 399 "EN_PP3300_EDP_DX", 400 "EN_PP1800_EDPBRDG_DX", 401 "EN_PP1000_EDPBRDG", 402 "SCP_JTAG0_TDO", 403 "SCP_JTAG0_TDI", 404 "SCP_JTAG0_TMS", 405 "SCP_JTAG0_TCK", 406 "SCP_JTAG0_TRSTN", 407 "EN_PP3000_VMC_PMU", 408 "EN_PP3300_DISPLAY_DX", 409 "TOUCH_RST_L_1V8", 410 "TOUCH_REPORT_DISABLE", 411 "", 412 "", 413 "AP_I2C_TRACKPAD_SCL_1V8", 414 "AP_I2C_TRACKPAD_SDA_1V8", 415 "EN_PP3300_WLAN", 416 "BT_KILL_L", 417 "WIFI_KILL_L", 418 "SET_VMC_VOLT_AT_1V8", 419 "EN_SPK", 420 "AP_WARM_RST_REQ", 421 "", 422 "", 423 "EN_PP3000_SD_S3", 424 "AP_EDP_BKLTEN", 425 "", 426 "", 427 "", 428 "AP_SPI_EC_CLK", 429 "AP_SPI_EC_CS_L", 430 "AP_SPI_EC_MISO", 431 "AP_SPI_EC_MOSI", 432 "AP_I2C_EDPBRDG_SCL", 433 "AP_I2C_EDPBRDG_SDA", 434 "MT6315_PROC_INT", 435 "MT6315_GPU_INT", 436 "UART_SERVO_TX_SCP_RX", 437 "UART_SCP_TX_SERVO_RX", 438 "BT_RTS_AP_CTS", 439 "AP_RTS_BT_CTS", 440 "UART_AP_WAKE_BT_ODL", 441 "WLAN_ALERT_ODL", 442 "EC_IN_RW_ODL", 443 "H1_AP_INT_ODL", 444 "", 445 "", 446 "", 447 "", 448 "", 449 "", 450 "", 451 "", 452 "", 453 "", 454 "", 455 "MSDC0_CMD", 456 "MSDC0_DAT0", 457 "MSDC0_DAT2", 458 "MSDC0_DAT4", 459 "MSDC0_DAT6", 460 "MSDC0_DAT1", 461 "MSDC0_DAT5", 462 "MSDC0_DAT7", 463 "MSDC0_DSL", 464 "MSDC0_CLK", 465 "MSDC0_DAT3", 466 "MSDC0_RST_L", 467 "SCP_VREQ_VAO", 468 "AUD_DAT_MOSI2", 469 "AUD_NLE_MOSI1", 470 "AUD_NLE_MOSI0", 471 "AUD_DAT_MISO2", 472 "AP_I2C_SAR_SDA", 473 "AP_I2C_SAR_SCL", 474 "AP_I2C_PWR_SCL", 475 "AP_I2C_PWR_SDA", 476 "AP_I2C_TS_SCL_1V8", 477 "AP_I2C_TS_SDA_1V8", 478 "SRCLKENA0", 479 "SRCLKENA1", 480 "AP_EC_WATCHDOG_L", 481 "PWRAP_SPI0_MI", 482 "PWRAP_SPI0_CSN", 483 "PWRAP_SPI0_MO", 484 "PWRAP_SPI0_CK", 485 "AP_RTC_CLK32K", 486 "AUD_CLK_MOSI", 487 "AUD_SYNC_MOSI", 488 "AUD_DAT_MOSI0", 489 "AUD_DAT_MOSI1", 490 "AUD_DAT_MISO0", 491 "AUD_DAT_MISO1"; 492 493 cr50_int: cr50-irq-default-pins { 494 pins-gsc-ap-int-odl { 495 pinmux = <PINMUX_GPIO171__FUNC_GPIO171>; 496 input-enable; 497 }; 498 }; 499 500 cros_ec_int: cros-ec-irq-default-pins { 501 pins-ec-ap-int-odl { 502 pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; 503 input-enable; 504 bias-pull-up; 505 }; 506 }; 507 508 i2c0_pins: i2c0-default-pins { 509 pins-bus { 510 pinmux = <PINMUX_GPIO204__FUNC_SCL0>, 511 <PINMUX_GPIO205__FUNC_SDA0>; 512 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 513 drive-strength-microamp = <1000>; 514 }; 515 }; 516 517 i2c1_pins: i2c1-default-pins { 518 pins-bus { 519 pinmux = <PINMUX_GPIO118__FUNC_SCL1>, 520 <PINMUX_GPIO119__FUNC_SDA1>; 521 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 522 drive-strength-microamp = <1000>; 523 }; 524 }; 525 526 i2c2_pins: i2c2-default-pins { 527 pins-bus { 528 pinmux = <PINMUX_GPIO141__FUNC_SCL2>, 529 <PINMUX_GPIO142__FUNC_SDA2>; 530 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 531 }; 532 }; 533 534 i2c3_pins: i2c3-default-pins { 535 pins-bus { 536 pinmux = <PINMUX_GPIO160__FUNC_SCL3>, 537 <PINMUX_GPIO161__FUNC_SDA3>; 538 bias-disable; 539 drive-strength-microamp = <1000>; 540 }; 541 }; 542 543 i2c7_pins: i2c7-default-pins { 544 pins-bus { 545 pinmux = <PINMUX_GPIO124__FUNC_SCL7>, 546 <PINMUX_GPIO125__FUNC_SDA7>; 547 bias-disable; 548 drive-strength-microamp = <1000>; 549 }; 550 }; 551 552 mmc0_default_pins: mmc0-default-pins { 553 pins-cmd-dat { 554 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 555 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 556 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 557 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 558 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 559 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 560 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 561 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 562 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 563 input-enable; 564 drive-strength = <8>; 565 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 566 }; 567 568 pins-clk { 569 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 570 drive-strength = <8>; 571 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 572 }; 573 574 pins-rst { 575 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 576 drive-strength = <8>; 577 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 578 }; 579 }; 580 581 mmc0_uhs_pins: mmc0-uhs-pins { 582 pins-cmd-dat { 583 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 584 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 585 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 586 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 587 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 588 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 589 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 590 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 591 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 592 input-enable; 593 drive-strength = <10>; 594 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 595 }; 596 597 pins-clk { 598 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 599 drive-strength = <10>; 600 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 601 }; 602 603 pins-rst { 604 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 605 drive-strength = <8>; 606 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 607 }; 608 609 pins-ds { 610 pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>; 611 drive-strength = <10>; 612 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 613 }; 614 }; 615 616 mmc1_default_pins: mmc1-default-pins { 617 pins-cmd-dat { 618 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 619 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 620 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 621 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 622 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 623 input-enable; 624 drive-strength = <8>; 625 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 626 }; 627 628 pins-clk { 629 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 630 drive-strength = <8>; 631 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 632 }; 633 634 pins-insert { 635 pinmux = <PINMUX_GPIO17__FUNC_GPIO17>; 636 input-enable; 637 bias-pull-up; 638 }; 639 }; 640 641 mmc1_uhs_pins: mmc1-uhs-pins { 642 pins-cmd-dat { 643 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 644 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 645 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 646 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 647 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 648 input-enable; 649 drive-strength = <8>; 650 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 651 }; 652 653 pins-clk { 654 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 655 input-enable; 656 drive-strength = <8>; 657 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 658 }; 659 }; 660 661 pcie_pins: pcie-default-pins { 662 pins-pcie-wake { 663 pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>; 664 bias-pull-up; 665 }; 666 667 pins-pcie-pereset { 668 pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>; 669 }; 670 671 pins-pcie-clkreq { 672 pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>; 673 bias-pull-up; 674 }; 675 676 pins-wifi-kill { 677 pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */ 678 output-high; 679 }; 680 }; 681 682 pp3300_wlan_pins: pp3300-wlan-pins { 683 pins-pcie-en-pp3300-wlan { 684 pinmux = <PINMUX_GPIO143__FUNC_GPIO143>; 685 output-high; 686 }; 687 }; 688 689 scp_pins: scp-pins { 690 pins-vreq-vao { 691 pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>; 692 }; 693 }; 694 695 spi1_pins: spi1-default-pins { 696 pins-cs-mosi-clk { 697 pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, 698 <PINMUX_GPIO159__FUNC_SPI1_A_MO>, 699 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; 700 bias-disable; 701 }; 702 703 pins-miso { 704 pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; 705 bias-pull-down; 706 }; 707 }; 708 709 spi5_pins: spi5-default-pins { 710 pins-bus { 711 pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>, 712 <PINMUX_GPIO37__FUNC_GPIO37>, 713 <PINMUX_GPIO39__FUNC_SPI5_A_MO>, 714 <PINMUX_GPIO36__FUNC_SPI5_A_CLK>; 715 bias-disable; 716 }; 717 }; 718 719 trackpad_pins: trackpad-default-pins { 720 pins-int-n { 721 pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; 722 input-enable; 723 bias-pull-up = <MTK_PUPD_SET_R1R0_11>; 724 }; 725 }; 726 727 touchscreen_pins: touchscreen-default-pins { 728 pins-irq { 729 pinmux = <PINMUX_GPIO21__FUNC_GPIO21>; 730 input-enable; 731 bias-pull-up; 732 }; 733 734 pins-reset { 735 pinmux = <PINMUX_GPIO137__FUNC_GPIO137>; 736 output-high; 737 }; 738 739 pins-report-sw { 740 pinmux = <PINMUX_GPIO138__FUNC_GPIO138>; 741 output-low; 742 }; 743 }; 744}; 745 746&pmic { 747 interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>; 748}; 749 750&scp { 751 status = "okay"; 752 753 firmware-name = "mediatek/mt8192/scp.img"; 754 memory-region = <&scp_mem_reserved>; 755 pinctrl-names = "default"; 756 pinctrl-0 = <&scp_pins>; 757 758 cros-ec { 759 compatible = "google,cros-ec-rpmsg"; 760 mediatek,rpmsg-name = "cros-ec-rpmsg"; 761 }; 762}; 763 764&spi1 { 765 status = "okay"; 766 767 mediatek,pad-select = <0>; 768 pinctrl-names = "default"; 769 pinctrl-0 = <&spi1_pins>; 770 771 cros_ec: ec@0 { 772 compatible = "google,cros-ec-spi"; 773 reg = <0>; 774 interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; 775 spi-max-frequency = <3000000>; 776 pinctrl-names = "default"; 777 pinctrl-0 = <&cros_ec_int>; 778 779 #address-cells = <1>; 780 #size-cells = <0>; 781 782 base_detection: cbas { 783 compatible = "google,cros-cbas"; 784 }; 785 786 cros_ec_pwm: pwm { 787 compatible = "google,cros-ec-pwm"; 788 #pwm-cells = <1>; 789 790 status = "disabled"; 791 }; 792 793 i2c_tunnel: i2c-tunnel { 794 compatible = "google,cros-ec-i2c-tunnel"; 795 google,remote-bus = <0>; 796 #address-cells = <1>; 797 #size-cells = <0>; 798 }; 799 800 mt6360_ldo3_reg: regulator@0 { 801 compatible = "google,cros-ec-regulator"; 802 reg = <0>; 803 regulator-min-microvolt = <1800000>; 804 regulator-max-microvolt = <3300000>; 805 }; 806 807 mt6360_ldo5_reg: regulator@1 { 808 compatible = "google,cros-ec-regulator"; 809 reg = <1>; 810 regulator-min-microvolt = <3300000>; 811 regulator-max-microvolt = <3300000>; 812 }; 813 814 typec { 815 compatible = "google,cros-ec-typec"; 816 #address-cells = <1>; 817 #size-cells = <0>; 818 819 usb_c0: connector@0 { 820 compatible = "usb-c-connector"; 821 reg = <0>; 822 label = "left"; 823 power-role = "dual"; 824 data-role = "host"; 825 try-power-role = "source"; 826 }; 827 828 usb_c1: connector@1 { 829 compatible = "usb-c-connector"; 830 reg = <1>; 831 label = "right"; 832 power-role = "dual"; 833 data-role = "host"; 834 try-power-role = "source"; 835 }; 836 }; 837 }; 838}; 839 840&spi5 { 841 status = "okay"; 842 843 cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>; 844 mediatek,pad-select = <0>; 845 pinctrl-names = "default"; 846 pinctrl-0 = <&spi5_pins>; 847 848 cr50@0 { 849 compatible = "google,cr50"; 850 reg = <0>; 851 interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>; 852 spi-max-frequency = <1000000>; 853 pinctrl-names = "default"; 854 pinctrl-0 = <&cr50_int>; 855 }; 856}; 857 858&spmi { 859 #address-cells = <2>; 860 #size-cells = <0>; 861 862 mt6315_6: pmic@6 { 863 compatible = "mediatek,mt6315-regulator"; 864 reg = <0x6 SPMI_USID>; 865 866 regulators { 867 mt6315_6_vbuck1: vbuck1 { 868 regulator-compatible = "vbuck1"; 869 regulator-name = "Vbcpu"; 870 regulator-min-microvolt = <300000>; 871 regulator-max-microvolt = <1193750>; 872 regulator-enable-ramp-delay = <256>; 873 regulator-allowed-modes = <0 1 2>; 874 regulator-always-on; 875 }; 876 877 mt6315_6_vbuck3: vbuck3 { 878 regulator-compatible = "vbuck3"; 879 regulator-name = "Vlcpu"; 880 regulator-min-microvolt = <300000>; 881 regulator-max-microvolt = <1193750>; 882 regulator-enable-ramp-delay = <256>; 883 regulator-allowed-modes = <0 1 2>; 884 regulator-always-on; 885 }; 886 }; 887 }; 888 889 mt6315_7: pmic@7 { 890 compatible = "mediatek,mt6315-regulator"; 891 reg = <0x7 SPMI_USID>; 892 893 regulators { 894 mt6315_7_vbuck1: vbuck1 { 895 regulator-compatible = "vbuck1"; 896 regulator-name = "Vgpu"; 897 regulator-min-microvolt = <606250>; 898 regulator-max-microvolt = <1193750>; 899 regulator-enable-ramp-delay = <256>; 900 regulator-allowed-modes = <0 1 2>; 901 }; 902 }; 903 }; 904}; 905 906&uart0 { 907 status = "okay"; 908}; 909 910&xhci { 911 status = "okay"; 912 913 wakeup-source; 914 vusb33-supply = <&pp3300_g>; 915 vbus-supply = <&pp5000_a>; 916}; 917 918#include <arm/cros-ec-keyboard.dtsi> 919#include <arm/cros-ec-sbs.dtsi> 920