1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6/dts-v1/; 7#include "mt8192.dtsi" 8#include "mt6359.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/spmi/spmi.h> 11 12/ { 13 aliases { 14 i2c0 = &i2c0; 15 i2c1 = &i2c1; 16 i2c2 = &i2c2; 17 i2c3 = &i2c3; 18 i2c7 = &i2c7; 19 mmc0 = &mmc0; 20 mmc1 = &mmc1; 21 serial0 = &uart0; 22 }; 23 24 chosen { 25 stdout-path = "serial0:115200n8"; 26 }; 27 28 memory@40000000 { 29 device_type = "memory"; 30 reg = <0 0x40000000 0 0x80000000>; 31 }; 32 33 backlight_lcd0: backlight-lcd0 { 34 compatible = "pwm-backlight"; 35 pwms = <&pwm0 0 500000>; 36 power-supply = <&ppvar_sys>; 37 enable-gpios = <&pio 152 0>; 38 brightness-levels = <0 1023>; 39 num-interpolated-steps = <1023>; 40 default-brightness-level = <576>; 41 }; 42 43 dmic_codec: dmic-codec { 44 compatible = "dmic-codec"; 45 num-channels = <2>; 46 wakeup-delay-ms = <50>; 47 }; 48 49 pp1000_dpbrdg: regulator-1v0-dpbrdg { 50 compatible = "regulator-fixed"; 51 regulator-name = "pp1000_dpbrdg"; 52 pinctrl-names = "default"; 53 pinctrl-0 = <&pp1000_dpbrdg_en_pins>; 54 regulator-min-microvolt = <1000000>; 55 regulator-max-microvolt = <1000000>; 56 enable-active-high; 57 regulator-boot-on; 58 gpio = <&pio 19 GPIO_ACTIVE_HIGH>; 59 vin-supply = <&mt6359_vs2_buck_reg>; 60 }; 61 62 pp1000_mipibrdg: regulator-1v0-mipibrdg { 63 compatible = "regulator-fixed"; 64 regulator-name = "pp1000_mipibrdg"; 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pp1000_mipibrdg_en_pins>; 67 regulator-min-microvolt = <1000000>; 68 regulator-max-microvolt = <1000000>; 69 enable-active-high; 70 regulator-boot-on; 71 gpio = <&pio 129 GPIO_ACTIVE_HIGH>; 72 vin-supply = <&mt6359_vs2_buck_reg>; 73 }; 74 75 pp1800_dpbrdg: regulator-1v8-dpbrdg { 76 compatible = "regulator-fixed"; 77 regulator-name = "pp1800_dpbrdg"; 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pp1800_dpbrdg_en_pins>; 80 enable-active-high; 81 regulator-boot-on; 82 gpio = <&pio 126 GPIO_ACTIVE_HIGH>; 83 vin-supply = <&mt6359_vio18_ldo_reg>; 84 }; 85 86 /* system wide LDO 1.8V power rail */ 87 pp1800_ldo_g: regulator-1v8-g { 88 compatible = "regulator-fixed"; 89 regulator-name = "pp1800_ldo_g"; 90 regulator-always-on; 91 regulator-boot-on; 92 regulator-min-microvolt = <1800000>; 93 regulator-max-microvolt = <1800000>; 94 vin-supply = <&pp3300_g>; 95 }; 96 97 pp1800_mipibrdg: regulator-1v8-mipibrdg { 98 compatible = "regulator-fixed"; 99 regulator-name = "pp1800_mipibrdg"; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&pp1800_mipibrdg_en_pins>; 102 enable-active-high; 103 regulator-boot-on; 104 gpio = <&pio 128 GPIO_ACTIVE_HIGH>; 105 vin-supply = <&mt6359_vio18_ldo_reg>; 106 }; 107 108 pp3300_dpbrdg: regulator-3v3-dpbrdg { 109 compatible = "regulator-fixed"; 110 regulator-name = "pp3300_dpbrdg"; 111 pinctrl-names = "default"; 112 pinctrl-0 = <&pp3300_dpbrdg_en_pins>; 113 enable-active-high; 114 regulator-boot-on; 115 gpio = <&pio 26 GPIO_ACTIVE_HIGH>; 116 vin-supply = <&pp3300_g>; 117 }; 118 119 /* system wide switching 3.3V power rail */ 120 pp3300_g: regulator-3v3-g { 121 compatible = "regulator-fixed"; 122 regulator-name = "pp3300_g"; 123 regulator-always-on; 124 regulator-boot-on; 125 regulator-min-microvolt = <3300000>; 126 regulator-max-microvolt = <3300000>; 127 vin-supply = <&ppvar_sys>; 128 }; 129 130 /* system wide LDO 3.3V power rail */ 131 pp3300_ldo_z: regulator-3v3-z { 132 compatible = "regulator-fixed"; 133 regulator-name = "pp3300_ldo_z"; 134 regulator-always-on; 135 regulator-boot-on; 136 regulator-min-microvolt = <3300000>; 137 regulator-max-microvolt = <3300000>; 138 vin-supply = <&ppvar_sys>; 139 }; 140 141 pp3300_mipibrdg: regulator-3v3-mipibrdg { 142 compatible = "regulator-fixed"; 143 regulator-name = "pp3300_mipibrdg"; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pp3300_mipibrdg_en_pins>; 146 enable-active-high; 147 regulator-boot-on; 148 gpio = <&pio 127 GPIO_ACTIVE_HIGH>; 149 vin-supply = <&pp3300_g>; 150 off-on-delay-us = <500000>; 151 }; 152 153 /* separately switched 3.3V power rail */ 154 pp3300_u: regulator-3v3-u { 155 compatible = "regulator-fixed"; 156 regulator-name = "pp3300_u"; 157 regulator-always-on; 158 regulator-boot-on; 159 regulator-min-microvolt = <3300000>; 160 regulator-max-microvolt = <3300000>; 161 /* enable pin wired to GPIO controlled by EC */ 162 vin-supply = <&pp3300_g>; 163 }; 164 165 pp3300_wlan: regulator-3v3-wlan { 166 compatible = "regulator-fixed"; 167 regulator-name = "pp3300_wlan"; 168 regulator-always-on; 169 regulator-boot-on; 170 regulator-min-microvolt = <3300000>; 171 regulator-max-microvolt = <3300000>; 172 pinctrl-names = "default"; 173 pinctrl-0 = <&pp3300_wlan_pins>; 174 enable-active-high; 175 gpio = <&pio 143 GPIO_ACTIVE_HIGH>; 176 }; 177 178 /* system wide switching 5.0V power rail */ 179 pp5000_a: regulator-5v0-a { 180 compatible = "regulator-fixed"; 181 regulator-name = "pp5000_a"; 182 regulator-always-on; 183 regulator-boot-on; 184 regulator-min-microvolt = <5000000>; 185 regulator-max-microvolt = <5000000>; 186 vin-supply = <&ppvar_sys>; 187 }; 188 189 /* system wide semi-regulated power rail from battery or USB */ 190 ppvar_sys: regulator-var-sys { 191 compatible = "regulator-fixed"; 192 regulator-name = "ppvar_sys"; 193 regulator-always-on; 194 regulator-boot-on; 195 }; 196 197 reserved_memory: reserved-memory { 198 #address-cells = <2>; 199 #size-cells = <2>; 200 ranges; 201 202 scp_mem_reserved: scp@50000000 { 203 compatible = "shared-dma-pool"; 204 reg = <0 0x50000000 0 0x2900000>; 205 no-map; 206 }; 207 208 wifi_restricted_dma_region: wifi@c0000000 { 209 compatible = "restricted-dma-pool"; 210 reg = <0 0xc0000000 0 0x4000000>; 211 }; 212 }; 213 214 sound: sound { 215 mediatek,platform = <&afe>; 216 pinctrl-names = "aud_clk_mosi_off", 217 "aud_clk_mosi_on", 218 "aud_dat_mosi_off", 219 "aud_dat_mosi_on", 220 "aud_dat_miso_off", 221 "aud_dat_miso_on", 222 "vow_dat_miso_off", 223 "vow_dat_miso_on", 224 "vow_clk_miso_off", 225 "vow_clk_miso_on", 226 "aud_nle_mosi_off", 227 "aud_nle_mosi_on", 228 "aud_dat_miso2_off", 229 "aud_dat_miso2_on", 230 "aud_gpio_i2s3_off", 231 "aud_gpio_i2s3_on", 232 "aud_gpio_i2s8_off", 233 "aud_gpio_i2s8_on", 234 "aud_gpio_i2s9_off", 235 "aud_gpio_i2s9_on", 236 "aud_dat_mosi_ch34_off", 237 "aud_dat_mosi_ch34_on", 238 "aud_dat_miso_ch34_off", 239 "aud_dat_miso_ch34_on", 240 "aud_gpio_tdm_off", 241 "aud_gpio_tdm_on"; 242 pinctrl-0 = <&aud_clk_mosi_off_pins>; 243 pinctrl-1 = <&aud_clk_mosi_on_pins>; 244 pinctrl-2 = <&aud_dat_mosi_off_pins>; 245 pinctrl-3 = <&aud_dat_mosi_on_pins>; 246 pinctrl-4 = <&aud_dat_miso_off_pins>; 247 pinctrl-5 = <&aud_dat_miso_on_pins>; 248 pinctrl-6 = <&vow_dat_miso_off_pins>; 249 pinctrl-7 = <&vow_dat_miso_on_pins>; 250 pinctrl-8 = <&vow_clk_miso_off_pins>; 251 pinctrl-9 = <&vow_clk_miso_on_pins>; 252 pinctrl-10 = <&aud_nle_mosi_off_pins>; 253 pinctrl-11 = <&aud_nle_mosi_on_pins>; 254 pinctrl-12 = <&aud_dat_miso2_off_pins>; 255 pinctrl-13 = <&aud_dat_miso2_on_pins>; 256 pinctrl-14 = <&aud_gpio_i2s3_off_pins>; 257 pinctrl-15 = <&aud_gpio_i2s3_on_pins>; 258 pinctrl-16 = <&aud_gpio_i2s8_off_pins>; 259 pinctrl-17 = <&aud_gpio_i2s8_on_pins>; 260 pinctrl-18 = <&aud_gpio_i2s9_off_pins>; 261 pinctrl-19 = <&aud_gpio_i2s9_on_pins>; 262 pinctrl-20 = <&aud_dat_mosi_ch34_off_pins>; 263 pinctrl-21 = <&aud_dat_mosi_ch34_on_pins>; 264 pinctrl-22 = <&aud_dat_miso_ch34_off_pins>; 265 pinctrl-23 = <&aud_dat_miso_ch34_on_pins>; 266 pinctrl-24 = <&aud_gpio_tdm_off_pins>; 267 pinctrl-25 = <&aud_gpio_tdm_on_pins>; 268 }; 269}; 270 271&dsi0 { 272 status = "okay"; 273}; 274 275&dsi_out { 276 remote-endpoint = <&anx7625_in>; 277}; 278 279&gic { 280 mediatek,broken-save-restore-fw; 281}; 282 283&gpu { 284 mali-supply = <&mt6315_7_vbuck1>; 285 status = "okay"; 286}; 287 288&i2c0 { 289 status = "okay"; 290 291 clock-frequency = <400000>; 292 pinctrl-names = "default"; 293 pinctrl-0 = <&i2c0_pins>; 294 295 touchscreen: touchscreen@10 { 296 reg = <0x10>; 297 interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&touchscreen_pins>; 300 }; 301}; 302 303&i2c1 { 304 status = "okay"; 305 306 clock-frequency = <400000>; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&i2c1_pins>; 309}; 310 311&i2c2 { 312 status = "okay"; 313 314 clock-frequency = <400000>; 315 clock-stretch-ns = <12600>; 316 pinctrl-names = "default"; 317 pinctrl-0 = <&i2c2_pins>; 318 319 trackpad@15 { 320 compatible = "elan,ekth3000"; 321 reg = <0x15>; 322 interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; 323 pinctrl-names = "default"; 324 pinctrl-0 = <&trackpad_pins>; 325 vcc-supply = <&pp3300_u>; 326 wakeup-source; 327 }; 328}; 329 330&i2c3 { 331 status = "okay"; 332 333 clock-frequency = <400000>; 334 pinctrl-names = "default"; 335 pinctrl-0 = <&i2c3_pins>; 336 337 anx_bridge: anx7625@58 { 338 compatible = "analogix,anx7625"; 339 reg = <0x58>; 340 pinctrl-names = "default"; 341 pinctrl-0 = <&anx7625_pins>; 342 enable-gpios = <&pio 41 GPIO_ACTIVE_HIGH>; 343 reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; 344 vdd10-supply = <&pp1000_mipibrdg>; 345 vdd18-supply = <&pp1800_mipibrdg>; 346 vdd33-supply = <&pp3300_mipibrdg>; 347 348 ports { 349 #address-cells = <1>; 350 #size-cells = <0>; 351 352 port@0 { 353 reg = <0>; 354 355 anx7625_in: endpoint { 356 remote-endpoint = <&dsi_out>; 357 }; 358 }; 359 360 port@1 { 361 reg = <1>; 362 363 anx7625_out: endpoint { 364 remote-endpoint = <&panel_in>; 365 }; 366 }; 367 }; 368 369 aux-bus { 370 panel: panel { 371 compatible = "edp-panel"; 372 power-supply = <&pp3300_mipibrdg>; 373 backlight = <&backlight_lcd0>; 374 375 port { 376 panel_in: endpoint { 377 remote-endpoint = <&anx7625_out>; 378 }; 379 }; 380 }; 381 }; 382 }; 383}; 384 385&i2c7 { 386 status = "okay"; 387 388 clock-frequency = <400000>; 389 pinctrl-names = "default"; 390 pinctrl-0 = <&i2c7_pins>; 391}; 392 393&mfg0 { 394 domain-supply = <&mt6315_7_vbuck1>; 395}; 396 397&mfg1 { 398 domain-supply = <&mt6359_vsram_others_ldo_reg>; 399}; 400 401&mipi_tx0 { 402 status = "okay"; 403}; 404 405&mmc0 { 406 status = "okay"; 407 408 pinctrl-names = "default", "state_uhs"; 409 pinctrl-0 = <&mmc0_default_pins>; 410 pinctrl-1 = <&mmc0_uhs_pins>; 411 bus-width = <8>; 412 max-frequency = <200000000>; 413 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 414 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 415 cap-mmc-highspeed; 416 mmc-hs200-1_8v; 417 mmc-hs400-1_8v; 418 supports-cqe; 419 cap-mmc-hw-reset; 420 mmc-hs400-enhanced-strobe; 421 hs400-ds-delay = <0x12814>; 422 no-sdio; 423 no-sd; 424 non-removable; 425}; 426 427&mmc1 { 428 status = "okay"; 429 430 pinctrl-names = "default", "state_uhs"; 431 pinctrl-0 = <&mmc1_default_pins>; 432 pinctrl-1 = <&mmc1_uhs_pins>; 433 bus-width = <4>; 434 max-frequency = <200000000>; 435 cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>; 436 vmmc-supply = <&mt6360_ldo5_reg>; 437 vqmmc-supply = <&mt6360_ldo3_reg>; 438 cap-sd-highspeed; 439 sd-uhs-sdr50; 440 sd-uhs-sdr104; 441 no-sdio; 442 no-mmc; 443}; 444 445/* for CORE */ 446&mt6359_vgpu11_buck_reg { 447 regulator-always-on; 448}; 449 450&mt6359_vgpu11_sshub_buck_reg { 451 regulator-always-on; 452 regulator-min-microvolt = <575000>; 453 regulator-max-microvolt = <575000>; 454}; 455 456&mt6359_vrf12_ldo_reg { 457 regulator-always-on; 458}; 459 460&mt6359_vsram_others_ldo_reg { 461 regulator-min-microvolt = <750000>; 462 regulator-max-microvolt = <800000>; 463 regulator-coupled-with = <&mt6315_7_vbuck1>; 464 regulator-coupled-max-spread = <10000>; 465}; 466 467&mt6359_vufs_ldo_reg { 468 regulator-always-on; 469}; 470 471&mt6359codec { 472 mediatek,dmic-mode = <1>; /* one-wire */ 473 mediatek,mic-type-0 = <2>; /* DMIC */ 474 mediatek,mic-type-2 = <2>; /* DMIC */ 475}; 476 477&nor_flash { 478 status = "okay"; 479 480 pinctrl-names = "default"; 481 pinctrl-0 = <&nor_flash_pins>; 482 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 483 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>; 484 485 flash@0 { 486 compatible = "winbond,w25q64jwm", "jedec,spi-nor"; 487 reg = <0>; 488 spi-max-frequency = <52000000>; 489 spi-rx-bus-width = <2>; 490 spi-tx-bus-width = <2>; 491 }; 492}; 493 494&pcie { 495 pinctrl-names = "default"; 496 pinctrl-0 = <&pcie_pins>; 497 498 pcie0: pcie@0,0 { 499 device_type = "pci"; 500 reg = <0x0000 0 0 0 0>; 501 num-lanes = <1>; 502 bus-range = <0x1 0x1>; 503 504 #address-cells = <3>; 505 #size-cells = <2>; 506 ranges; 507 508 wifi: wifi@0,0 { 509 reg = <0x10000 0 0 0 0x100000>, 510 <0x10000 0 0x100000 0 0x100000>; 511 memory-region = <&wifi_restricted_dma_region>; 512 }; 513 }; 514}; 515 516&pio { 517 /* 220 lines */ 518 gpio-line-names = "I2S_DP_LRCK", 519 "IS_DP_BCLK", 520 "I2S_DP_MCLK", 521 "I2S_DP_DATAOUT", 522 "SAR0_INT_ODL", 523 "EC_AP_INT_ODL", 524 "EDPBRDG_INT_ODL", 525 "DPBRDG_INT_ODL", 526 "DPBRDG_PWREN", 527 "DPBRDG_RST_ODL", 528 "I2S_HP_MCLK", 529 "I2S_HP_BCK", 530 "I2S_HP_LRCK", 531 "I2S_HP_DATAIN", 532 /* 533 * AP_FLASH_WP_L is crossystem ABI. Schematics 534 * call it AP_FLASH_WP_ODL. 535 */ 536 "AP_FLASH_WP_L", 537 "TRACKPAD_INT_ODL", 538 "EC_AP_HPD_OD", 539 "SD_CD_ODL", 540 "HP_INT_ODL_ALC", 541 "EN_PP1000_DPBRDG", 542 "AP_GPIO20", 543 "TOUCH_INT_L_1V8", 544 "UART_BT_WAKE_ODL", 545 "AP_GPIO23", 546 "AP_SPI_FLASH_CS_L", 547 "AP_SPI_FLASH_CLK", 548 "EN_PP3300_DPBRDG_DX", 549 "AP_SPI_FLASH_MOSI", 550 "AP_SPI_FLASH_MISO", 551 "I2S_HP_DATAOUT", 552 "AP_GPIO30", 553 "I2S_SPKR_MCLK", 554 "I2S_SPKR_BCLK", 555 "I2S_SPKR_LRCK", 556 "I2S_SPKR_DATAIN", 557 "I2S_SPKR_DATAOUT", 558 "AP_SPI_H1_TPM_CLK", 559 "AP_SPI_H1_TPM_CS_L", 560 "AP_SPI_H1_TPM_MISO", 561 "AP_SPI_H1_TPM_MOSI", 562 "BL_PWM", 563 "EDPBRDG_PWREN", 564 "EDPBRDG_RST_ODL", 565 "EN_PP3300_HUB", 566 "HUB_RST_L", 567 "", 568 "", 569 "", 570 "", 571 "", 572 "", 573 "SD_CLK", 574 "SD_CMD", 575 "SD_DATA3", 576 "SD_DATA0", 577 "SD_DATA2", 578 "SD_DATA1", 579 "", 580 "", 581 "", 582 "", 583 "", 584 "", 585 "PCIE_WAKE_ODL", 586 "PCIE_RST_L", 587 "PCIE_CLKREQ_ODL", 588 "", 589 "", 590 "", 591 "", 592 "", 593 "", 594 "", 595 "", 596 "", 597 "", 598 "", 599 "", 600 "", 601 "", 602 "", 603 "", 604 "", 605 "", 606 "", 607 "", 608 "", 609 "", 610 "", 611 "SPMI_SCL", 612 "SPMI_SDA", 613 "AP_GOOD", 614 "UART_DBG_TX_AP_RX", 615 "UART_AP_TX_DBG_RX", 616 "UART_AP_TX_BT_RX", 617 "UART_BT_TX_AP_RX", 618 "MIPI_DPI_D0_R", 619 "MIPI_DPI_D1_R", 620 "MIPI_DPI_D2_R", 621 "MIPI_DPI_D3_R", 622 "MIPI_DPI_D4_R", 623 "MIPI_DPI_D5_R", 624 "MIPI_DPI_D6_R", 625 "MIPI_DPI_D7_R", 626 "MIPI_DPI_D8_R", 627 "MIPI_DPI_D9_R", 628 "MIPI_DPI_D10_R", 629 "", 630 "", 631 "MIPI_DPI_DE_R", 632 "MIPI_DPI_D11_R", 633 "MIPI_DPI_VSYNC_R", 634 "MIPI_DPI_CLK_R", 635 "MIPI_DPI_HSYNC_R", 636 "PCM_BT_DATAIN", 637 "PCM_BT_SYNC", 638 "PCM_BT_DATAOUT", 639 "PCM_BT_CLK", 640 "AP_I2C_AUDIO_SCL", 641 "AP_I2C_AUDIO_SDA", 642 "SCP_I2C_SCL", 643 "SCP_I2C_SDA", 644 "AP_I2C_WLAN_SCL", 645 "AP_I2C_WLAN_SDA", 646 "AP_I2C_DPBRDG_SCL", 647 "AP_I2C_DPBRDG_SDA", 648 "EN_PP1800_DPBRDG_DX", 649 "EN_PP3300_EDP_DX", 650 "EN_PP1800_EDPBRDG_DX", 651 "EN_PP1000_EDPBRDG", 652 "SCP_JTAG0_TDO", 653 "SCP_JTAG0_TDI", 654 "SCP_JTAG0_TMS", 655 "SCP_JTAG0_TCK", 656 "SCP_JTAG0_TRSTN", 657 "EN_PP3000_VMC_PMU", 658 "EN_PP3300_DISPLAY_DX", 659 "TOUCH_RST_L_1V8", 660 "TOUCH_REPORT_DISABLE", 661 "", 662 "", 663 "AP_I2C_TRACKPAD_SCL_1V8", 664 "AP_I2C_TRACKPAD_SDA_1V8", 665 "EN_PP3300_WLAN", 666 "BT_KILL_L", 667 "WIFI_KILL_L", 668 "SET_VMC_VOLT_AT_1V8", 669 "EN_SPK", 670 "AP_WARM_RST_REQ", 671 "", 672 "", 673 "EN_PP3000_SD_S3", 674 "AP_EDP_BKLTEN", 675 "", 676 "", 677 "", 678 "AP_SPI_EC_CLK", 679 "AP_SPI_EC_CS_L", 680 "AP_SPI_EC_MISO", 681 "AP_SPI_EC_MOSI", 682 "AP_I2C_EDPBRDG_SCL", 683 "AP_I2C_EDPBRDG_SDA", 684 "MT6315_PROC_INT", 685 "MT6315_GPU_INT", 686 "UART_SERVO_TX_SCP_RX", 687 "UART_SCP_TX_SERVO_RX", 688 "BT_RTS_AP_CTS", 689 "AP_RTS_BT_CTS", 690 "UART_AP_WAKE_BT_ODL", 691 "WLAN_ALERT_ODL", 692 "EC_IN_RW_ODL", 693 "H1_AP_INT_ODL", 694 "", 695 "", 696 "", 697 "", 698 "", 699 "", 700 "", 701 "", 702 "", 703 "", 704 "", 705 "MSDC0_CMD", 706 "MSDC0_DAT0", 707 "MSDC0_DAT2", 708 "MSDC0_DAT4", 709 "MSDC0_DAT6", 710 "MSDC0_DAT1", 711 "MSDC0_DAT5", 712 "MSDC0_DAT7", 713 "MSDC0_DSL", 714 "MSDC0_CLK", 715 "MSDC0_DAT3", 716 "MSDC0_RST_L", 717 "SCP_VREQ_VAO", 718 "AUD_DAT_MOSI2", 719 "AUD_NLE_MOSI1", 720 "AUD_NLE_MOSI0", 721 "AUD_DAT_MISO2", 722 "AP_I2C_SAR_SDA", 723 "AP_I2C_SAR_SCL", 724 "AP_I2C_PWR_SCL", 725 "AP_I2C_PWR_SDA", 726 "AP_I2C_TS_SCL_1V8", 727 "AP_I2C_TS_SDA_1V8", 728 "SRCLKENA0", 729 "SRCLKENA1", 730 "AP_EC_WATCHDOG_L", 731 "PWRAP_SPI0_MI", 732 "PWRAP_SPI0_CSN", 733 "PWRAP_SPI0_MO", 734 "PWRAP_SPI0_CK", 735 "AP_RTC_CLK32K", 736 "AUD_CLK_MOSI", 737 "AUD_SYNC_MOSI", 738 "AUD_DAT_MOSI0", 739 "AUD_DAT_MOSI1", 740 "AUD_DAT_MISO0", 741 "AUD_DAT_MISO1"; 742 743 anx7625_pins: anx7625-default-pins { 744 pins-out { 745 pinmux = <PINMUX_GPIO41__FUNC_GPIO41>, 746 <PINMUX_GPIO42__FUNC_GPIO42>; 747 output-low; 748 }; 749 750 pins-in { 751 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 752 input-enable; 753 bias-pull-up; 754 }; 755 }; 756 757 aud_clk_mosi_off_pins: aud-clk-mosi-off-pins { 758 pins-mosi-off { 759 pinmux = <PINMUX_GPIO214__FUNC_GPIO214>, 760 <PINMUX_GPIO215__FUNC_GPIO215>; 761 }; 762 }; 763 764 aud_clk_mosi_on_pins: aud-clk-mosi-on-pins { 765 pins-mosi-on { 766 pinmux = <PINMUX_GPIO214__FUNC_AUD_CLK_MOSI>, 767 <PINMUX_GPIO215__FUNC_AUD_SYNC_MOSI>; 768 drive-strength = <10>; 769 }; 770 }; 771 772 aud_dat_miso_ch34_off_pins: aud-dat-miso-ch34-off-pins { 773 pins-miso-off { 774 pinmux = <PINMUX_GPIO199__FUNC_GPIO199>; 775 }; 776 }; 777 778 aud_dat_miso_ch34_on_pins: aud-dat-miso-ch34-on-pins { 779 pins-miso-on { 780 pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>; 781 }; 782 }; 783 784 aud_dat_miso_off_pins: aud-dat-miso-off-pins { 785 pins-miso-off { 786 pinmux = <PINMUX_GPIO218__FUNC_GPIO218>, 787 <PINMUX_GPIO219__FUNC_GPIO219>; 788 }; 789 }; 790 791 aud_dat_miso_on_pins: aud-dat-miso-on-pins { 792 pins-miso-on { 793 pinmux = <PINMUX_GPIO218__FUNC_AUD_DAT_MISO0>, 794 <PINMUX_GPIO219__FUNC_AUD_DAT_MISO1>; 795 drive-strength = <10>; 796 }; 797 }; 798 799 aud_dat_miso2_off_pins: aud-dat-miso2-off-pins { 800 pins-miso-off { 801 pinmux = <PINMUX_GPIO199__FUNC_GPIO199>; 802 }; 803 }; 804 805 aud_dat_miso2_on_pins: aud-dat-miso2-on-pins { 806 pins-miso-on { 807 pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>; 808 }; 809 }; 810 811 aud_dat_mosi_ch34_off_pins: aud-dat-mosi-ch34-off-pins { 812 pins-mosi-off { 813 pinmux = <PINMUX_GPIO196__FUNC_GPIO196>; 814 }; 815 }; 816 817 aud_dat_mosi_ch34_on_pins: aud-dat-mosi-ch34-on-pins { 818 pins-mosi-on { 819 pinmux = <PINMUX_GPIO196__FUNC_AUD_DAT_MOSI2>; 820 }; 821 }; 822 823 aud_dat_mosi_off_pins: aud-dat-mosi-off-pins { 824 pins-mosi-off { 825 pinmux = <PINMUX_GPIO216__FUNC_GPIO216>, 826 <PINMUX_GPIO217__FUNC_GPIO217>; 827 }; 828 }; 829 830 aud_dat_mosi_on_pins: aud-dat-mosi-on-pins { 831 pins-mosi-on { 832 pinmux = <PINMUX_GPIO216__FUNC_AUD_DAT_MOSI0>, 833 <PINMUX_GPIO217__FUNC_AUD_DAT_MOSI1>; 834 drive-strength = <10>; 835 }; 836 }; 837 838 aud_gpio_i2s3_off_pins: aud-gpio-i2s3-off-pins { 839 pins-i2s3-off { 840 pinmux = <PINMUX_GPIO32__FUNC_GPIO32>, 841 <PINMUX_GPIO33__FUNC_GPIO33>, 842 <PINMUX_GPIO35__FUNC_GPIO35>; 843 }; 844 }; 845 846 aud_gpio_i2s3_on_pins: aud-gpio-i2s3-on-pins { 847 pins-i2s3-on { 848 pinmux = <PINMUX_GPIO32__FUNC_I2S3_BCK>, 849 <PINMUX_GPIO33__FUNC_I2S3_LRCK>, 850 <PINMUX_GPIO35__FUNC_I2S3_DO>; 851 }; 852 }; 853 854 aud_gpio_i2s8_off_pins: aud-gpio-i2s8-off-pins { 855 pins-i2s8-off { 856 pinmux = <PINMUX_GPIO10__FUNC_GPIO10>, 857 <PINMUX_GPIO11__FUNC_GPIO11>, 858 <PINMUX_GPIO12__FUNC_GPIO12>, 859 <PINMUX_GPIO13__FUNC_GPIO13>; 860 }; 861 }; 862 863 aud_gpio_i2s8_on_pins: aud-gpio-i2s8-on-pins { 864 pins-i2s8-on { 865 pinmux = <PINMUX_GPIO10__FUNC_I2S8_MCK>, 866 <PINMUX_GPIO11__FUNC_I2S8_BCK>, 867 <PINMUX_GPIO12__FUNC_I2S8_LRCK>, 868 <PINMUX_GPIO13__FUNC_I2S8_DI>; 869 }; 870 }; 871 872 aud_gpio_i2s9_off_pins: aud-gpio-i2s9-off-pins { 873 pins-i2s9-off { 874 pinmux = <PINMUX_GPIO29__FUNC_GPIO29>; 875 }; 876 }; 877 878 aud_gpio_i2s9_on_pins: aud-gpio-i2s9-on-pins { 879 pins-i2s9-on { 880 pinmux = <PINMUX_GPIO29__FUNC_I2S9_DO>; 881 }; 882 }; 883 884 aud_gpio_tdm_off_pins: aud-gpio-tdm-off-pins { 885 pins-tdm-off { 886 pinmux = <PINMUX_GPIO0__FUNC_GPIO0>, 887 <PINMUX_GPIO1__FUNC_GPIO1>, 888 <PINMUX_GPIO2__FUNC_GPIO2>, 889 <PINMUX_GPIO3__FUNC_GPIO3>; 890 }; 891 }; 892 893 aud_gpio_tdm_on_pins: aud-gpio-tdm-on-pins { 894 pins-tdm-on { 895 pinmux = <PINMUX_GPIO0__FUNC_TDM_LRCK>, 896 <PINMUX_GPIO1__FUNC_TDM_BCK>, 897 <PINMUX_GPIO2__FUNC_TDM_MCK>, 898 <PINMUX_GPIO3__FUNC_TDM_DATA0>; 899 }; 900 }; 901 902 aud_nle_mosi_off_pins: aud-nle-mosi-off-pins { 903 pins-nle-mosi-off { 904 pinmux = <PINMUX_GPIO197__FUNC_GPIO197>, 905 <PINMUX_GPIO198__FUNC_GPIO198>; 906 }; 907 }; 908 909 aud_nle_mosi_on_pins: aud-nle-mosi-on-pins { 910 pins-nle-mosi-on { 911 pinmux = <PINMUX_GPIO197__FUNC_AUD_NLE_MOSI1>, 912 <PINMUX_GPIO198__FUNC_AUD_NLE_MOSI0>; 913 }; 914 }; 915 916 cr50_int: cr50-irq-default-pins { 917 pins-gsc-ap-int-odl { 918 pinmux = <PINMUX_GPIO171__FUNC_GPIO171>; 919 input-enable; 920 }; 921 }; 922 923 cros_ec_int: cros-ec-irq-default-pins { 924 pins-ec-ap-int-odl { 925 pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; 926 input-enable; 927 bias-pull-up; 928 }; 929 }; 930 931 i2c0_pins: i2c0-default-pins { 932 pins-bus { 933 pinmux = <PINMUX_GPIO204__FUNC_SCL0>, 934 <PINMUX_GPIO205__FUNC_SDA0>; 935 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 936 drive-strength-microamp = <1000>; 937 }; 938 }; 939 940 i2c1_pins: i2c1-default-pins { 941 pins-bus { 942 pinmux = <PINMUX_GPIO118__FUNC_SCL1>, 943 <PINMUX_GPIO119__FUNC_SDA1>; 944 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 945 drive-strength-microamp = <1000>; 946 }; 947 }; 948 949 i2c2_pins: i2c2-default-pins { 950 pins-bus { 951 pinmux = <PINMUX_GPIO141__FUNC_SCL2>, 952 <PINMUX_GPIO142__FUNC_SDA2>; 953 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 954 }; 955 }; 956 957 i2c3_pins: i2c3-default-pins { 958 pins-bus { 959 pinmux = <PINMUX_GPIO160__FUNC_SCL3>, 960 <PINMUX_GPIO161__FUNC_SDA3>; 961 bias-disable; 962 drive-strength-microamp = <1000>; 963 }; 964 }; 965 966 i2c7_pins: i2c7-default-pins { 967 pins-bus { 968 pinmux = <PINMUX_GPIO124__FUNC_SCL7>, 969 <PINMUX_GPIO125__FUNC_SDA7>; 970 bias-disable; 971 drive-strength-microamp = <1000>; 972 }; 973 }; 974 975 mmc0_default_pins: mmc0-default-pins { 976 pins-cmd-dat { 977 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 978 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 979 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 980 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 981 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 982 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 983 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 984 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 985 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 986 input-enable; 987 drive-strength = <8>; 988 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 989 }; 990 991 pins-clk { 992 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 993 drive-strength = <8>; 994 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 995 }; 996 997 pins-rst { 998 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 999 drive-strength = <8>; 1000 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 1001 }; 1002 }; 1003 1004 mmc0_uhs_pins: mmc0-uhs-pins { 1005 pins-cmd-dat { 1006 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 1007 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 1008 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 1009 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 1010 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 1011 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 1012 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 1013 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 1014 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 1015 input-enable; 1016 drive-strength = <10>; 1017 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1018 }; 1019 1020 pins-clk { 1021 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 1022 drive-strength = <10>; 1023 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1024 }; 1025 1026 pins-rst { 1027 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 1028 drive-strength = <8>; 1029 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 1030 }; 1031 1032 pins-ds { 1033 pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>; 1034 drive-strength = <10>; 1035 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1036 }; 1037 }; 1038 1039 mmc1_default_pins: mmc1-default-pins { 1040 pins-cmd-dat { 1041 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 1042 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 1043 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 1044 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 1045 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 1046 input-enable; 1047 drive-strength = <8>; 1048 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1049 }; 1050 1051 pins-clk { 1052 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 1053 drive-strength = <8>; 1054 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1055 }; 1056 1057 pins-insert { 1058 pinmux = <PINMUX_GPIO17__FUNC_GPIO17>; 1059 input-enable; 1060 bias-pull-up; 1061 }; 1062 }; 1063 1064 mmc1_uhs_pins: mmc1-uhs-pins { 1065 pins-cmd-dat { 1066 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 1067 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 1068 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 1069 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 1070 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 1071 input-enable; 1072 drive-strength = <8>; 1073 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1074 }; 1075 1076 pins-clk { 1077 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 1078 input-enable; 1079 drive-strength = <8>; 1080 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1081 }; 1082 }; 1083 1084 nor_flash_pins: nor-flash-default-pins { 1085 pins-cs-io1 { 1086 pinmux = <PINMUX_GPIO24__FUNC_SPINOR_CS>, 1087 <PINMUX_GPIO28__FUNC_SPINOR_IO1>; 1088 input-enable; 1089 bias-pull-up; 1090 drive-strength = <10>; 1091 }; 1092 1093 pins-io0 { 1094 pinmux = <PINMUX_GPIO27__FUNC_SPINOR_IO0>; 1095 bias-pull-up; 1096 drive-strength = <10>; 1097 }; 1098 1099 pins-clk { 1100 pinmux = <PINMUX_GPIO25__FUNC_SPINOR_CK>; 1101 input-enable; 1102 bias-pull-up; 1103 drive-strength = <10>; 1104 }; 1105 }; 1106 1107 pcie_pins: pcie-default-pins { 1108 pins-pcie-wake { 1109 pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>; 1110 bias-pull-up; 1111 }; 1112 1113 pins-pcie-pereset { 1114 pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>; 1115 }; 1116 1117 pins-pcie-clkreq { 1118 pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>; 1119 bias-pull-up; 1120 }; 1121 1122 pins-wifi-kill { 1123 pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */ 1124 output-high; 1125 }; 1126 }; 1127 1128 pp1000_dpbrdg_en_pins: pp1000-dpbrdg-en-pins { 1129 pins-en { 1130 pinmux = <PINMUX_GPIO19__FUNC_GPIO19>; 1131 output-low; 1132 }; 1133 }; 1134 1135 pp1000_mipibrdg_en_pins: pp1000-mipibrdg-en-pins { 1136 pins-en { 1137 pinmux = <PINMUX_GPIO129__FUNC_GPIO129>; 1138 output-low; 1139 }; 1140 }; 1141 1142 pp1800_dpbrdg_en_pins: pp1800-dpbrdg-en-pins { 1143 pins-en { 1144 pinmux = <PINMUX_GPIO126__FUNC_GPIO126>; 1145 output-low; 1146 }; 1147 }; 1148 1149 pp1800_mipibrdg_en_pins: pp1800-mipibrd-en-pins { 1150 pins-en { 1151 pinmux = <PINMUX_GPIO128__FUNC_GPIO128>; 1152 output-low; 1153 }; 1154 }; 1155 1156 pp3300_dpbrdg_en_pins: pp3300-dpbrdg-en-pins { 1157 pins-en { 1158 pinmux = <PINMUX_GPIO26__FUNC_GPIO26>; 1159 output-low; 1160 }; 1161 }; 1162 1163 pp3300_mipibrdg_en_pins: pp3300-mipibrdg-en-pins { 1164 pins-en { 1165 pinmux = <PINMUX_GPIO127__FUNC_GPIO127>; 1166 output-low; 1167 }; 1168 }; 1169 1170 pp3300_wlan_pins: pp3300-wlan-pins { 1171 pins-pcie-en-pp3300-wlan { 1172 pinmux = <PINMUX_GPIO143__FUNC_GPIO143>; 1173 output-high; 1174 }; 1175 }; 1176 1177 pwm0_pins: pwm0-default-pins { 1178 pins-pwm { 1179 pinmux = <PINMUX_GPIO40__FUNC_DISP_PWM>; 1180 }; 1181 1182 pins-inhibit { 1183 pinmux = <PINMUX_GPIO152__FUNC_GPIO152>; 1184 output-high; 1185 }; 1186 }; 1187 1188 scp_pins: scp-pins { 1189 pins-vreq-vao { 1190 pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>; 1191 }; 1192 }; 1193 1194 spi1_pins: spi1-default-pins { 1195 pins-cs-mosi-clk { 1196 pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, 1197 <PINMUX_GPIO159__FUNC_SPI1_A_MO>, 1198 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; 1199 bias-disable; 1200 }; 1201 1202 pins-miso { 1203 pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; 1204 bias-pull-down; 1205 }; 1206 }; 1207 1208 spi5_pins: spi5-default-pins { 1209 pins-bus { 1210 pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>, 1211 <PINMUX_GPIO37__FUNC_GPIO37>, 1212 <PINMUX_GPIO39__FUNC_SPI5_A_MO>, 1213 <PINMUX_GPIO36__FUNC_SPI5_A_CLK>; 1214 bias-disable; 1215 }; 1216 }; 1217 1218 trackpad_pins: trackpad-default-pins { 1219 pins-int-n { 1220 pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; 1221 input-enable; 1222 bias-pull-up = <MTK_PUPD_SET_R1R0_11>; 1223 }; 1224 }; 1225 1226 touchscreen_pins: touchscreen-default-pins { 1227 pins-irq { 1228 pinmux = <PINMUX_GPIO21__FUNC_GPIO21>; 1229 input-enable; 1230 bias-pull-up; 1231 }; 1232 1233 pins-reset { 1234 pinmux = <PINMUX_GPIO137__FUNC_GPIO137>; 1235 output-high; 1236 }; 1237 1238 pins-report-sw { 1239 pinmux = <PINMUX_GPIO138__FUNC_GPIO138>; 1240 output-low; 1241 }; 1242 }; 1243 1244 vow_clk_miso_off_pins: vow-clk-miso-off-pins { 1245 pins-miso-off { 1246 pinmux = <PINMUX_GPIO219__FUNC_GPIO219>; 1247 }; 1248 }; 1249 1250 vow_clk_miso_on_pins: vow-clk-miso-on-pins { 1251 pins-miso-on { 1252 pinmux = <PINMUX_GPIO219__FUNC_VOW_CLK_MISO>; 1253 }; 1254 }; 1255 1256 vow_dat_miso_off_pins: vow-dat-miso-off-pins { 1257 pins-miso-off { 1258 pinmux = <PINMUX_GPIO218__FUNC_GPIO218>; 1259 }; 1260 }; 1261 1262 vow_dat_miso_on_pins: vow-dat-miso-on-pins { 1263 pins-miso-on { 1264 pinmux = <PINMUX_GPIO218__FUNC_VOW_DAT_MISO>; 1265 }; 1266 }; 1267}; 1268 1269&pmic { 1270 interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>; 1271}; 1272 1273&pwm0 { 1274 status = "okay"; 1275 1276 pinctrl-names = "default"; 1277 pinctrl-0 = <&pwm0_pins>; 1278}; 1279 1280&scp { 1281 status = "okay"; 1282 1283 firmware-name = "mediatek/mt8192/scp.img"; 1284 memory-region = <&scp_mem_reserved>; 1285 pinctrl-names = "default"; 1286 pinctrl-0 = <&scp_pins>; 1287 1288 cros-ec { 1289 compatible = "google,cros-ec-rpmsg"; 1290 mediatek,rpmsg-name = "cros-ec-rpmsg"; 1291 }; 1292}; 1293 1294&spi1 { 1295 status = "okay"; 1296 1297 mediatek,pad-select = <0>; 1298 pinctrl-names = "default"; 1299 pinctrl-0 = <&spi1_pins>; 1300 1301 cros_ec: ec@0 { 1302 compatible = "google,cros-ec-spi"; 1303 reg = <0>; 1304 interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; 1305 spi-max-frequency = <3000000>; 1306 pinctrl-names = "default"; 1307 pinctrl-0 = <&cros_ec_int>; 1308 1309 #address-cells = <1>; 1310 #size-cells = <0>; 1311 1312 cros_ec_pwm: pwm { 1313 compatible = "google,cros-ec-pwm"; 1314 #pwm-cells = <1>; 1315 1316 status = "disabled"; 1317 }; 1318 1319 i2c_tunnel: i2c-tunnel { 1320 compatible = "google,cros-ec-i2c-tunnel"; 1321 google,remote-bus = <0>; 1322 #address-cells = <1>; 1323 #size-cells = <0>; 1324 }; 1325 1326 mt6360_ldo3_reg: regulator@0 { 1327 compatible = "google,cros-ec-regulator"; 1328 reg = <0>; 1329 regulator-min-microvolt = <1800000>; 1330 regulator-max-microvolt = <3300000>; 1331 }; 1332 1333 mt6360_ldo5_reg: regulator@1 { 1334 compatible = "google,cros-ec-regulator"; 1335 reg = <1>; 1336 regulator-min-microvolt = <3300000>; 1337 regulator-max-microvolt = <3300000>; 1338 }; 1339 1340 typec { 1341 compatible = "google,cros-ec-typec"; 1342 #address-cells = <1>; 1343 #size-cells = <0>; 1344 1345 usb_c0: connector@0 { 1346 compatible = "usb-c-connector"; 1347 reg = <0>; 1348 label = "left"; 1349 power-role = "dual"; 1350 data-role = "host"; 1351 try-power-role = "source"; 1352 }; 1353 1354 usb_c1: connector@1 { 1355 compatible = "usb-c-connector"; 1356 reg = <1>; 1357 label = "right"; 1358 power-role = "dual"; 1359 data-role = "host"; 1360 try-power-role = "source"; 1361 }; 1362 }; 1363 }; 1364}; 1365 1366&spi5 { 1367 status = "okay"; 1368 1369 cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>; 1370 mediatek,pad-select = <0>; 1371 pinctrl-names = "default"; 1372 pinctrl-0 = <&spi5_pins>; 1373 1374 cr50@0 { 1375 compatible = "google,cr50"; 1376 reg = <0>; 1377 interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>; 1378 spi-max-frequency = <1000000>; 1379 pinctrl-names = "default"; 1380 pinctrl-0 = <&cr50_int>; 1381 }; 1382}; 1383 1384&spmi { 1385 #address-cells = <2>; 1386 #size-cells = <0>; 1387 1388 mt6315_6: pmic@6 { 1389 compatible = "mediatek,mt6315-regulator"; 1390 reg = <0x6 SPMI_USID>; 1391 1392 regulators { 1393 mt6315_6_vbuck1: vbuck1 { 1394 regulator-compatible = "vbuck1"; 1395 regulator-name = "Vbcpu"; 1396 regulator-min-microvolt = <400000>; 1397 regulator-max-microvolt = <1193750>; 1398 regulator-enable-ramp-delay = <256>; 1399 regulator-allowed-modes = <0 1 2>; 1400 regulator-always-on; 1401 }; 1402 1403 mt6315_6_vbuck3: vbuck3 { 1404 regulator-compatible = "vbuck3"; 1405 regulator-name = "Vlcpu"; 1406 regulator-min-microvolt = <400000>; 1407 regulator-max-microvolt = <1193750>; 1408 regulator-enable-ramp-delay = <256>; 1409 regulator-allowed-modes = <0 1 2>; 1410 regulator-always-on; 1411 }; 1412 }; 1413 }; 1414 1415 mt6315_7: pmic@7 { 1416 compatible = "mediatek,mt6315-regulator"; 1417 reg = <0x7 SPMI_USID>; 1418 1419 regulators { 1420 mt6315_7_vbuck1: vbuck1 { 1421 regulator-compatible = "vbuck1"; 1422 regulator-name = "Vgpu"; 1423 regulator-min-microvolt = <400000>; 1424 regulator-max-microvolt = <800000>; 1425 regulator-enable-ramp-delay = <256>; 1426 regulator-allowed-modes = <0 1 2>; 1427 regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>; 1428 regulator-coupled-max-spread = <10000>; 1429 }; 1430 }; 1431 }; 1432}; 1433 1434&uart0 { 1435 status = "okay"; 1436}; 1437 1438&xhci { 1439 status = "okay"; 1440 1441 wakeup-source; 1442 vusb33-supply = <&pp3300_g>; 1443 vbus-supply = <&pp5000_a>; 1444}; 1445 1446#include <arm/cros-ec-keyboard.dtsi> 1447#include <arm/cros-ec-sbs.dtsi> 1448