1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2020 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6/dts-v1/;
7#include "mt8192.dtsi"
8#include <dt-bindings/gpio/gpio.h>
9
10/ {
11	aliases {
12		serial0 = &uart0;
13	};
14
15	chosen {
16		stdout-path = "serial0:115200n8";
17	};
18
19	memory@40000000 {
20		device_type = "memory";
21		reg = <0 0x40000000 0 0x80000000>;
22	};
23
24	/* system wide LDO 1.8V power rail */
25	pp1800_ldo_g: regulator-1v8-g {
26		compatible = "regulator-fixed";
27		regulator-name = "pp1800_ldo_g";
28		regulator-always-on;
29		regulator-boot-on;
30		regulator-min-microvolt = <1800000>;
31		regulator-max-microvolt = <1800000>;
32		vin-supply = <&pp3300_g>;
33	};
34
35	/* system wide switching 3.3V power rail */
36	pp3300_g: regulator-3v3-g {
37		compatible = "regulator-fixed";
38		regulator-name = "pp3300_g";
39		regulator-always-on;
40		regulator-boot-on;
41		regulator-min-microvolt = <3300000>;
42		regulator-max-microvolt = <3300000>;
43		vin-supply = <&ppvar_sys>;
44	};
45
46	/* system wide LDO 3.3V power rail */
47	pp3300_ldo_z: regulator-3v3-z {
48		compatible = "regulator-fixed";
49		regulator-name = "pp3300_ldo_z";
50		regulator-always-on;
51		regulator-boot-on;
52		regulator-min-microvolt = <3300000>;
53		regulator-max-microvolt = <3300000>;
54		vin-supply = <&ppvar_sys>;
55	};
56
57	/* separately switched 3.3V power rail */
58	pp3300_u: regulator-3v3-u {
59		compatible = "regulator-fixed";
60		regulator-name = "pp3300_u";
61		regulator-always-on;
62		regulator-boot-on;
63		regulator-min-microvolt = <3300000>;
64		regulator-max-microvolt = <3300000>;
65		/* enable pin wired to GPIO controlled by EC */
66		vin-supply = <&pp3300_g>;
67	};
68
69	/* system wide switching 5.0V power rail */
70	pp5000_a: regulator-5v0-a {
71		compatible = "regulator-fixed";
72		regulator-name = "pp5000_a";
73		regulator-always-on;
74		regulator-boot-on;
75		regulator-min-microvolt = <5000000>;
76		regulator-max-microvolt = <5000000>;
77		vin-supply = <&ppvar_sys>;
78	};
79
80	/* system wide semi-regulated power rail from battery or USB */
81	ppvar_sys: regulator-var-sys {
82		compatible = "regulator-fixed";
83		regulator-name = "ppvar_sys";
84		regulator-always-on;
85		regulator-boot-on;
86	};
87};
88
89&i2c0 {
90	status = "okay";
91
92	clock-frequency = <400000>;
93	pinctrl-names = "default";
94	pinctrl-0 = <&i2c0_pins>;
95};
96
97&i2c1 {
98	status = "okay";
99
100	clock-frequency = <400000>;
101	pinctrl-names = "default";
102	pinctrl-0 = <&i2c1_pins>;
103};
104
105&i2c2 {
106	status = "okay";
107
108	clock-frequency = <400000>;
109	clock-stretch-ns = <12600>;
110	pinctrl-names = "default";
111	pinctrl-0 = <&i2c2_pins>;
112};
113
114&i2c3 {
115	status = "okay";
116
117	clock-frequency = <400000>;
118	pinctrl-names = "default";
119	pinctrl-0 = <&i2c3_pins>;
120};
121
122&i2c7 {
123	status = "okay";
124
125	clock-frequency = <400000>;
126	pinctrl-names = "default";
127	pinctrl-0 = <&i2c7_pins>;
128};
129
130&pio {
131	/* 220 lines */
132	gpio-line-names = "I2S_DP_LRCK",
133			  "IS_DP_BCLK",
134			  "I2S_DP_MCLK",
135			  "I2S_DP_DATAOUT",
136			  "SAR0_INT_ODL",
137			  "EC_AP_INT_ODL",
138			  "EDPBRDG_INT_ODL",
139			  "DPBRDG_INT_ODL",
140			  "DPBRDG_PWREN",
141			  "DPBRDG_RST_ODL",
142			  "I2S_HP_MCLK",
143			  "I2S_HP_BCK",
144			  "I2S_HP_LRCK",
145			  "I2S_HP_DATAIN",
146			  /*
147			   * AP_FLASH_WP_L is crossystem ABI. Schematics
148			   * call it AP_FLASH_WP_ODL.
149			   */
150			  "AP_FLASH_WP_L",
151			  "TRACKPAD_INT_ODL",
152			  "EC_AP_HPD_OD",
153			  "SD_CD_ODL",
154			  "HP_INT_ODL_ALC",
155			  "EN_PP1000_DPBRDG",
156			  "AP_GPIO20",
157			  "TOUCH_INT_L_1V8",
158			  "UART_BT_WAKE_ODL",
159			  "AP_GPIO23",
160			  "AP_SPI_FLASH_CS_L",
161			  "AP_SPI_FLASH_CLK",
162			  "EN_PP3300_DPBRDG_DX",
163			  "AP_SPI_FLASH_MOSI",
164			  "AP_SPI_FLASH_MISO",
165			  "I2S_HP_DATAOUT",
166			  "AP_GPIO30",
167			  "I2S_SPKR_MCLK",
168			  "I2S_SPKR_BCLK",
169			  "I2S_SPKR_LRCK",
170			  "I2S_SPKR_DATAIN",
171			  "I2S_SPKR_DATAOUT",
172			  "AP_SPI_H1_TPM_CLK",
173			  "AP_SPI_H1_TPM_CS_L",
174			  "AP_SPI_H1_TPM_MISO",
175			  "AP_SPI_H1_TPM_MOSI",
176			  "BL_PWM",
177			  "EDPBRDG_PWREN",
178			  "EDPBRDG_RST_ODL",
179			  "EN_PP3300_HUB",
180			  "HUB_RST_L",
181			  "",
182			  "",
183			  "",
184			  "",
185			  "",
186			  "",
187			  "SD_CLK",
188			  "SD_CMD",
189			  "SD_DATA3",
190			  "SD_DATA0",
191			  "SD_DATA2",
192			  "SD_DATA1",
193			  "",
194			  "",
195			  "",
196			  "",
197			  "",
198			  "",
199			  "PCIE_WAKE_ODL",
200			  "PCIE_RST_L",
201			  "PCIE_CLKREQ_ODL",
202			  "",
203			  "",
204			  "",
205			  "",
206			  "",
207			  "",
208			  "",
209			  "",
210			  "",
211			  "",
212			  "",
213			  "",
214			  "",
215			  "",
216			  "",
217			  "",
218			  "",
219			  "",
220			  "",
221			  "",
222			  "",
223			  "",
224			  "",
225			  "SPMI_SCL",
226			  "SPMI_SDA",
227			  "AP_GOOD",
228			  "UART_DBG_TX_AP_RX",
229			  "UART_AP_TX_DBG_RX",
230			  "UART_AP_TX_BT_RX",
231			  "UART_BT_TX_AP_RX",
232			  "MIPI_DPI_D0_R",
233			  "MIPI_DPI_D1_R",
234			  "MIPI_DPI_D2_R",
235			  "MIPI_DPI_D3_R",
236			  "MIPI_DPI_D4_R",
237			  "MIPI_DPI_D5_R",
238			  "MIPI_DPI_D6_R",
239			  "MIPI_DPI_D7_R",
240			  "MIPI_DPI_D8_R",
241			  "MIPI_DPI_D9_R",
242			  "MIPI_DPI_D10_R",
243			  "",
244			  "",
245			  "MIPI_DPI_DE_R",
246			  "MIPI_DPI_D11_R",
247			  "MIPI_DPI_VSYNC_R",
248			  "MIPI_DPI_CLK_R",
249			  "MIPI_DPI_HSYNC_R",
250			  "PCM_BT_DATAIN",
251			  "PCM_BT_SYNC",
252			  "PCM_BT_DATAOUT",
253			  "PCM_BT_CLK",
254			  "AP_I2C_AUDIO_SCL",
255			  "AP_I2C_AUDIO_SDA",
256			  "SCP_I2C_SCL",
257			  "SCP_I2C_SDA",
258			  "AP_I2C_WLAN_SCL",
259			  "AP_I2C_WLAN_SDA",
260			  "AP_I2C_DPBRDG_SCL",
261			  "AP_I2C_DPBRDG_SDA",
262			  "EN_PP1800_DPBRDG_DX",
263			  "EN_PP3300_EDP_DX",
264			  "EN_PP1800_EDPBRDG_DX",
265			  "EN_PP1000_EDPBRDG",
266			  "SCP_JTAG0_TDO",
267			  "SCP_JTAG0_TDI",
268			  "SCP_JTAG0_TMS",
269			  "SCP_JTAG0_TCK",
270			  "SCP_JTAG0_TRSTN",
271			  "EN_PP3000_VMC_PMU",
272			  "EN_PP3300_DISPLAY_DX",
273			  "TOUCH_RST_L_1V8",
274			  "TOUCH_REPORT_DISABLE",
275			  "",
276			  "",
277			  "AP_I2C_TRACKPAD_SCL_1V8",
278			  "AP_I2C_TRACKPAD_SDA_1V8",
279			  "EN_PP3300_WLAN",
280			  "BT_KILL_L",
281			  "WIFI_KILL_L",
282			  "SET_VMC_VOLT_AT_1V8",
283			  "EN_SPK",
284			  "AP_WARM_RST_REQ",
285			  "",
286			  "",
287			  "EN_PP3000_SD_S3",
288			  "AP_EDP_BKLTEN",
289			  "",
290			  "",
291			  "",
292			  "AP_SPI_EC_CLK",
293			  "AP_SPI_EC_CS_L",
294			  "AP_SPI_EC_MISO",
295			  "AP_SPI_EC_MOSI",
296			  "AP_I2C_EDPBRDG_SCL",
297			  "AP_I2C_EDPBRDG_SDA",
298			  "MT6315_PROC_INT",
299			  "MT6315_GPU_INT",
300			  "UART_SERVO_TX_SCP_RX",
301			  "UART_SCP_TX_SERVO_RX",
302			  "BT_RTS_AP_CTS",
303			  "AP_RTS_BT_CTS",
304			  "UART_AP_WAKE_BT_ODL",
305			  "WLAN_ALERT_ODL",
306			  "EC_IN_RW_ODL",
307			  "H1_AP_INT_ODL",
308			  "",
309			  "",
310			  "",
311			  "",
312			  "",
313			  "",
314			  "",
315			  "",
316			  "",
317			  "",
318			  "",
319			  "MSDC0_CMD",
320			  "MSDC0_DAT0",
321			  "MSDC0_DAT2",
322			  "MSDC0_DAT4",
323			  "MSDC0_DAT6",
324			  "MSDC0_DAT1",
325			  "MSDC0_DAT5",
326			  "MSDC0_DAT7",
327			  "MSDC0_DSL",
328			  "MSDC0_CLK",
329			  "MSDC0_DAT3",
330			  "MSDC0_RST_L",
331			  "SCP_VREQ_VAO",
332			  "AUD_DAT_MOSI2",
333			  "AUD_NLE_MOSI1",
334			  "AUD_NLE_MOSI0",
335			  "AUD_DAT_MISO2",
336			  "AP_I2C_SAR_SDA",
337			  "AP_I2C_SAR_SCL",
338			  "AP_I2C_PWR_SCL",
339			  "AP_I2C_PWR_SDA",
340			  "AP_I2C_TS_SCL_1V8",
341			  "AP_I2C_TS_SDA_1V8",
342			  "SRCLKENA0",
343			  "SRCLKENA1",
344			  "AP_EC_WATCHDOG_L",
345			  "PWRAP_SPI0_MI",
346			  "PWRAP_SPI0_CSN",
347			  "PWRAP_SPI0_MO",
348			  "PWRAP_SPI0_CK",
349			  "AP_RTC_CLK32K",
350			  "AUD_CLK_MOSI",
351			  "AUD_SYNC_MOSI",
352			  "AUD_DAT_MOSI0",
353			  "AUD_DAT_MOSI1",
354			  "AUD_DAT_MISO0",
355			  "AUD_DAT_MISO1";
356
357	cr50_int: cr50-irq-default-pins {
358		pins-gsc-ap-int-odl {
359			pinmux = <PINMUX_GPIO171__FUNC_GPIO171>;
360			input-enable;
361		};
362	};
363
364	cros_ec_int: cros-ec-irq-default-pins {
365		pins-ec-ap-int-odl {
366			pinmux = <PINMUX_GPIO5__FUNC_GPIO5>;
367			input-enable;
368			bias-pull-up;
369		};
370	};
371
372	i2c0_pins: i2c0-default-pins {
373		pins-bus {
374			pinmux = <PINMUX_GPIO204__FUNC_SCL0>,
375				 <PINMUX_GPIO205__FUNC_SDA0>;
376			bias-pull-up = <MTK_PULL_SET_RSEL_011>;
377			drive-strength-microamp = <1000>;
378		};
379	};
380
381	i2c1_pins: i2c1-default-pins {
382		pins-bus {
383			pinmux = <PINMUX_GPIO118__FUNC_SCL1>,
384				 <PINMUX_GPIO119__FUNC_SDA1>;
385			bias-pull-up = <MTK_PULL_SET_RSEL_011>;
386			drive-strength-microamp = <1000>;
387		};
388	};
389
390	i2c2_pins: i2c2-default-pins {
391		pins-bus {
392			pinmux = <PINMUX_GPIO141__FUNC_SCL2>,
393				 <PINMUX_GPIO142__FUNC_SDA2>;
394			bias-pull-up = <MTK_PULL_SET_RSEL_011>;
395		};
396	};
397
398	i2c3_pins: i2c3-default-pins {
399		pins-bus {
400			pinmux = <PINMUX_GPIO160__FUNC_SCL3>,
401				 <PINMUX_GPIO161__FUNC_SDA3>;
402			bias-disable;
403			drive-strength-microamp = <1000>;
404		};
405	};
406
407	i2c7_pins: i2c7-default-pins {
408		pins-bus {
409			pinmux = <PINMUX_GPIO124__FUNC_SCL7>,
410				 <PINMUX_GPIO125__FUNC_SDA7>;
411			bias-disable;
412			drive-strength-microamp = <1000>;
413		};
414	};
415
416	spi1_pins: spi1-default-pins {
417		pins-cs-mosi-clk {
418			pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>,
419				 <PINMUX_GPIO159__FUNC_SPI1_A_MO>,
420				 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>;
421			bias-disable;
422		};
423
424		pins-miso {
425			pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>;
426			bias-pull-down;
427		};
428	};
429
430	spi5_pins: spi5-default-pins {
431		pins-bus {
432			pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>,
433				 <PINMUX_GPIO37__FUNC_GPIO37>,
434				 <PINMUX_GPIO39__FUNC_SPI5_A_MO>,
435				 <PINMUX_GPIO36__FUNC_SPI5_A_CLK>;
436			bias-disable;
437		};
438	};
439};
440
441&spi1 {
442	status = "okay";
443
444	mediatek,pad-select = <0>;
445	pinctrl-names = "default";
446	pinctrl-0 = <&spi1_pins>;
447
448	cros_ec: ec@0 {
449		compatible = "google,cros-ec-spi";
450		reg = <0>;
451		interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>;
452		spi-max-frequency = <3000000>;
453		pinctrl-names = "default";
454		pinctrl-0 = <&cros_ec_int>;
455
456		#address-cells = <1>;
457		#size-cells = <0>;
458
459		base_detection: cbas {
460			compatible = "google,cros-cbas";
461		};
462
463		cros_ec_pwm: pwm {
464			compatible = "google,cros-ec-pwm";
465			#pwm-cells = <1>;
466
467			status = "disabled";
468		};
469
470		i2c_tunnel: i2c-tunnel {
471			compatible = "google,cros-ec-i2c-tunnel";
472			google,remote-bus = <0>;
473			#address-cells = <1>;
474			#size-cells = <0>;
475		};
476
477		mt6360_ldo3_reg: regulator@0 {
478			compatible = "google,cros-ec-regulator";
479			reg = <0>;
480			regulator-min-microvolt = <1800000>;
481			regulator-max-microvolt = <3300000>;
482		};
483
484		mt6360_ldo5_reg: regulator@1 {
485			compatible = "google,cros-ec-regulator";
486			reg = <1>;
487			regulator-min-microvolt = <3300000>;
488			regulator-max-microvolt = <3300000>;
489		};
490
491		typec {
492			compatible = "google,cros-ec-typec";
493			#address-cells = <1>;
494			#size-cells = <0>;
495
496			usb_c0: connector@0 {
497				compatible = "usb-c-connector";
498				reg = <0>;
499				label = "left";
500				power-role = "dual";
501				data-role = "host";
502				try-power-role = "source";
503			};
504
505			usb_c1: connector@1 {
506				compatible = "usb-c-connector";
507				reg = <1>;
508				label = "right";
509				power-role = "dual";
510				data-role = "host";
511				try-power-role = "source";
512			};
513		};
514	};
515};
516
517&spi5 {
518	status = "okay";
519
520	cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>;
521	mediatek,pad-select = <0>;
522	pinctrl-names = "default";
523	pinctrl-0 = <&spi5_pins>;
524
525	cr50@0 {
526		compatible = "google,cr50";
527		reg = <0>;
528		interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>;
529		spi-max-frequency = <1000000>;
530		pinctrl-names = "default";
531		pinctrl-0 = <&cr50_int>;
532	};
533};
534
535&uart0 {
536	status = "okay";
537};
538
539#include <arm/cros-ec-keyboard.dtsi>
540#include <arm/cros-ec-sbs.dtsi>
541