1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6/dts-v1/; 7#include "mt8192.dtsi" 8#include "mt6359.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/spmi/spmi.h> 11 12/ { 13 aliases { 14 serial0 = &uart0; 15 }; 16 17 chosen { 18 stdout-path = "serial0:115200n8"; 19 }; 20 21 memory@40000000 { 22 device_type = "memory"; 23 reg = <0 0x40000000 0 0x80000000>; 24 }; 25 26 backlight_lcd0: backlight-lcd0 { 27 compatible = "pwm-backlight"; 28 pwms = <&pwm0 0 500000>; 29 power-supply = <&ppvar_sys>; 30 enable-gpios = <&pio 152 0>; 31 brightness-levels = <0 1023>; 32 num-interpolated-steps = <1023>; 33 default-brightness-level = <576>; 34 }; 35 36 pp1000_dpbrdg: regulator-1v0-dpbrdg { 37 compatible = "regulator-fixed"; 38 regulator-name = "pp1000_dpbrdg"; 39 pinctrl-names = "default"; 40 pinctrl-0 = <&pp1000_dpbrdg_en_pins>; 41 regulator-min-microvolt = <1000000>; 42 regulator-max-microvolt = <1000000>; 43 enable-active-high; 44 regulator-boot-on; 45 gpio = <&pio 19 GPIO_ACTIVE_HIGH>; 46 vin-supply = <&mt6359_vs2_buck_reg>; 47 }; 48 49 pp1000_mipibrdg: regulator-1v0-mipibrdg { 50 compatible = "regulator-fixed"; 51 regulator-name = "pp1000_mipibrdg"; 52 pinctrl-names = "default"; 53 pinctrl-0 = <&pp1000_mipibrdg_en_pins>; 54 regulator-min-microvolt = <1000000>; 55 regulator-max-microvolt = <1000000>; 56 enable-active-high; 57 regulator-boot-on; 58 gpio = <&pio 129 GPIO_ACTIVE_HIGH>; 59 vin-supply = <&mt6359_vs2_buck_reg>; 60 }; 61 62 pp1800_dpbrdg: regulator-1v8-dpbrdg { 63 compatible = "regulator-fixed"; 64 regulator-name = "pp1800_dpbrdg"; 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pp1800_dpbrdg_en_pins>; 67 enable-active-high; 68 regulator-boot-on; 69 gpio = <&pio 126 GPIO_ACTIVE_HIGH>; 70 vin-supply = <&mt6359_vio18_ldo_reg>; 71 }; 72 73 /* system wide LDO 1.8V power rail */ 74 pp1800_ldo_g: regulator-1v8-g { 75 compatible = "regulator-fixed"; 76 regulator-name = "pp1800_ldo_g"; 77 regulator-always-on; 78 regulator-boot-on; 79 regulator-min-microvolt = <1800000>; 80 regulator-max-microvolt = <1800000>; 81 vin-supply = <&pp3300_g>; 82 }; 83 84 pp1800_mipibrdg: regulator-1v8-mipibrdg { 85 compatible = "regulator-fixed"; 86 regulator-name = "pp1800_mipibrdg"; 87 pinctrl-names = "default"; 88 pinctrl-0 = <&pp1800_mipibrdg_en_pins>; 89 enable-active-high; 90 regulator-boot-on; 91 gpio = <&pio 128 GPIO_ACTIVE_HIGH>; 92 vin-supply = <&mt6359_vio18_ldo_reg>; 93 }; 94 95 pp3300_dpbrdg: regulator-3v3-dpbrdg { 96 compatible = "regulator-fixed"; 97 regulator-name = "pp3300_dpbrdg"; 98 pinctrl-names = "default"; 99 pinctrl-0 = <&pp3300_dpbrdg_en_pins>; 100 enable-active-high; 101 regulator-boot-on; 102 gpio = <&pio 26 GPIO_ACTIVE_HIGH>; 103 vin-supply = <&pp3300_g>; 104 }; 105 106 /* system wide switching 3.3V power rail */ 107 pp3300_g: regulator-3v3-g { 108 compatible = "regulator-fixed"; 109 regulator-name = "pp3300_g"; 110 regulator-always-on; 111 regulator-boot-on; 112 regulator-min-microvolt = <3300000>; 113 regulator-max-microvolt = <3300000>; 114 vin-supply = <&ppvar_sys>; 115 }; 116 117 /* system wide LDO 3.3V power rail */ 118 pp3300_ldo_z: regulator-3v3-z { 119 compatible = "regulator-fixed"; 120 regulator-name = "pp3300_ldo_z"; 121 regulator-always-on; 122 regulator-boot-on; 123 regulator-min-microvolt = <3300000>; 124 regulator-max-microvolt = <3300000>; 125 vin-supply = <&ppvar_sys>; 126 }; 127 128 pp3300_mipibrdg: regulator-3v3-mipibrdg { 129 compatible = "regulator-fixed"; 130 regulator-name = "pp3300_mipibrdg"; 131 pinctrl-names = "default"; 132 pinctrl-0 = <&pp3300_mipibrdg_en_pins>; 133 enable-active-high; 134 regulator-boot-on; 135 gpio = <&pio 127 GPIO_ACTIVE_HIGH>; 136 vin-supply = <&pp3300_g>; 137 }; 138 139 /* separately switched 3.3V power rail */ 140 pp3300_u: regulator-3v3-u { 141 compatible = "regulator-fixed"; 142 regulator-name = "pp3300_u"; 143 regulator-always-on; 144 regulator-boot-on; 145 regulator-min-microvolt = <3300000>; 146 regulator-max-microvolt = <3300000>; 147 /* enable pin wired to GPIO controlled by EC */ 148 vin-supply = <&pp3300_g>; 149 }; 150 151 pp3300_wlan: regulator-3v3-wlan { 152 compatible = "regulator-fixed"; 153 regulator-name = "pp3300_wlan"; 154 regulator-always-on; 155 regulator-boot-on; 156 regulator-min-microvolt = <3300000>; 157 regulator-max-microvolt = <3300000>; 158 pinctrl-names = "default"; 159 pinctrl-0 = <&pp3300_wlan_pins>; 160 enable-active-high; 161 gpio = <&pio 143 GPIO_ACTIVE_HIGH>; 162 }; 163 164 /* system wide switching 5.0V power rail */ 165 pp5000_a: regulator-5v0-a { 166 compatible = "regulator-fixed"; 167 regulator-name = "pp5000_a"; 168 regulator-always-on; 169 regulator-boot-on; 170 regulator-min-microvolt = <5000000>; 171 regulator-max-microvolt = <5000000>; 172 vin-supply = <&ppvar_sys>; 173 }; 174 175 /* system wide semi-regulated power rail from battery or USB */ 176 ppvar_sys: regulator-var-sys { 177 compatible = "regulator-fixed"; 178 regulator-name = "ppvar_sys"; 179 regulator-always-on; 180 regulator-boot-on; 181 }; 182 183 reserved_memory: reserved-memory { 184 #address-cells = <2>; 185 #size-cells = <2>; 186 ranges; 187 188 scp_mem_reserved: scp@50000000 { 189 compatible = "shared-dma-pool"; 190 reg = <0 0x50000000 0 0x2900000>; 191 no-map; 192 }; 193 194 wifi_restricted_dma_region: wifi@c0000000 { 195 compatible = "restricted-dma-pool"; 196 reg = <0 0xc0000000 0 0x4000000>; 197 }; 198 }; 199}; 200 201&dsi0 { 202 status = "okay"; 203}; 204 205&dsi_out { 206 remote-endpoint = <&anx7625_in>; 207}; 208 209&i2c0 { 210 status = "okay"; 211 212 clock-frequency = <400000>; 213 pinctrl-names = "default"; 214 pinctrl-0 = <&i2c0_pins>; 215 216 touchscreen: touchscreen@10 { 217 reg = <0x10>; 218 interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>; 219 pinctrl-names = "default"; 220 pinctrl-0 = <&touchscreen_pins>; 221 }; 222}; 223 224&i2c1 { 225 status = "okay"; 226 227 clock-frequency = <400000>; 228 pinctrl-names = "default"; 229 pinctrl-0 = <&i2c1_pins>; 230}; 231 232&i2c2 { 233 status = "okay"; 234 235 clock-frequency = <400000>; 236 clock-stretch-ns = <12600>; 237 pinctrl-names = "default"; 238 pinctrl-0 = <&i2c2_pins>; 239 240 trackpad@15 { 241 compatible = "elan,ekth3000"; 242 reg = <0x15>; 243 interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; 244 pinctrl-names = "default"; 245 pinctrl-0 = <&trackpad_pins>; 246 vcc-supply = <&pp3300_u>; 247 wakeup-source; 248 }; 249}; 250 251&i2c3 { 252 status = "okay"; 253 254 clock-frequency = <400000>; 255 pinctrl-names = "default"; 256 pinctrl-0 = <&i2c3_pins>; 257 258 anx_bridge: anx7625@58 { 259 compatible = "analogix,anx7625"; 260 reg = <0x58>; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&anx7625_pins>; 263 enable-gpios = <&pio 41 GPIO_ACTIVE_HIGH>; 264 reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; 265 vdd10-supply = <&pp1000_mipibrdg>; 266 vdd18-supply = <&pp1800_mipibrdg>; 267 vdd33-supply = <&pp3300_mipibrdg>; 268 269 ports { 270 #address-cells = <1>; 271 #size-cells = <0>; 272 273 port@0 { 274 reg = <0>; 275 276 anx7625_in: endpoint { 277 remote-endpoint = <&dsi_out>; 278 }; 279 }; 280 281 port@1 { 282 reg = <1>; 283 284 anx7625_out: endpoint { 285 remote-endpoint = <&panel_in>; 286 }; 287 }; 288 }; 289 290 aux-bus { 291 panel: panel { 292 compatible = "edp-panel"; 293 power-supply = <&pp3300_mipibrdg>; 294 backlight = <&backlight_lcd0>; 295 296 port { 297 panel_in: endpoint { 298 remote-endpoint = <&anx7625_out>; 299 }; 300 }; 301 }; 302 }; 303 }; 304}; 305 306&i2c7 { 307 status = "okay"; 308 309 clock-frequency = <400000>; 310 pinctrl-names = "default"; 311 pinctrl-0 = <&i2c7_pins>; 312}; 313 314&mipi_tx0 { 315 status = "okay"; 316}; 317 318&mmc0 { 319 status = "okay"; 320 321 pinctrl-names = "default", "state_uhs"; 322 pinctrl-0 = <&mmc0_default_pins>; 323 pinctrl-1 = <&mmc0_uhs_pins>; 324 bus-width = <8>; 325 max-frequency = <200000000>; 326 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 327 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 328 cap-mmc-highspeed; 329 mmc-hs200-1_8v; 330 mmc-hs400-1_8v; 331 supports-cqe; 332 cap-mmc-hw-reset; 333 mmc-hs400-enhanced-strobe; 334 hs400-ds-delay = <0x12814>; 335 no-sdio; 336 no-sd; 337 non-removable; 338}; 339 340&mmc1 { 341 status = "okay"; 342 343 pinctrl-names = "default", "state_uhs"; 344 pinctrl-0 = <&mmc1_default_pins>; 345 pinctrl-1 = <&mmc1_uhs_pins>; 346 bus-width = <4>; 347 max-frequency = <200000000>; 348 cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>; 349 vmmc-supply = <&mt6360_ldo5_reg>; 350 vqmmc-supply = <&mt6360_ldo3_reg>; 351 cap-sd-highspeed; 352 sd-uhs-sdr50; 353 sd-uhs-sdr104; 354 no-sdio; 355 no-mmc; 356}; 357 358/* for CORE */ 359&mt6359_vgpu11_buck_reg { 360 regulator-always-on; 361}; 362 363&mt6359_vgpu11_sshub_buck_reg { 364 regulator-always-on; 365 regulator-min-microvolt = <575000>; 366 regulator-max-microvolt = <575000>; 367}; 368 369&mt6359_vrf12_ldo_reg { 370 regulator-always-on; 371}; 372 373&mt6359_vufs_ldo_reg { 374 regulator-always-on; 375}; 376 377&mt6359codec { 378 mediatek,dmic-mode = <1>; /* one-wire */ 379 mediatek,mic-type-0 = <2>; /* DMIC */ 380 mediatek,mic-type-2 = <2>; /* DMIC */ 381}; 382 383&nor_flash { 384 status = "okay"; 385 386 pinctrl-names = "default"; 387 pinctrl-0 = <&nor_flash_pins>; 388 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 389 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>; 390 391 flash@0 { 392 compatible = "winbond,w25q64jwm", "jedec,spi-nor"; 393 reg = <0>; 394 spi-max-frequency = <52000000>; 395 spi-rx-bus-width = <2>; 396 spi-tx-bus-width = <2>; 397 }; 398}; 399 400&pcie { 401 pinctrl-names = "default"; 402 pinctrl-0 = <&pcie_pins>; 403 404 pcie0: pcie@0,0 { 405 device_type = "pci"; 406 reg = <0x0000 0 0 0 0>; 407 num-lanes = <1>; 408 bus-range = <0x1 0x1>; 409 410 #address-cells = <3>; 411 #size-cells = <2>; 412 ranges; 413 414 wifi: wifi@0,0 { 415 reg = <0x10000 0 0 0 0x100000>, 416 <0x10000 0 0x100000 0 0x100000>; 417 memory-region = <&wifi_restricted_dma_region>; 418 }; 419 }; 420}; 421 422&pio { 423 /* 220 lines */ 424 gpio-line-names = "I2S_DP_LRCK", 425 "IS_DP_BCLK", 426 "I2S_DP_MCLK", 427 "I2S_DP_DATAOUT", 428 "SAR0_INT_ODL", 429 "EC_AP_INT_ODL", 430 "EDPBRDG_INT_ODL", 431 "DPBRDG_INT_ODL", 432 "DPBRDG_PWREN", 433 "DPBRDG_RST_ODL", 434 "I2S_HP_MCLK", 435 "I2S_HP_BCK", 436 "I2S_HP_LRCK", 437 "I2S_HP_DATAIN", 438 /* 439 * AP_FLASH_WP_L is crossystem ABI. Schematics 440 * call it AP_FLASH_WP_ODL. 441 */ 442 "AP_FLASH_WP_L", 443 "TRACKPAD_INT_ODL", 444 "EC_AP_HPD_OD", 445 "SD_CD_ODL", 446 "HP_INT_ODL_ALC", 447 "EN_PP1000_DPBRDG", 448 "AP_GPIO20", 449 "TOUCH_INT_L_1V8", 450 "UART_BT_WAKE_ODL", 451 "AP_GPIO23", 452 "AP_SPI_FLASH_CS_L", 453 "AP_SPI_FLASH_CLK", 454 "EN_PP3300_DPBRDG_DX", 455 "AP_SPI_FLASH_MOSI", 456 "AP_SPI_FLASH_MISO", 457 "I2S_HP_DATAOUT", 458 "AP_GPIO30", 459 "I2S_SPKR_MCLK", 460 "I2S_SPKR_BCLK", 461 "I2S_SPKR_LRCK", 462 "I2S_SPKR_DATAIN", 463 "I2S_SPKR_DATAOUT", 464 "AP_SPI_H1_TPM_CLK", 465 "AP_SPI_H1_TPM_CS_L", 466 "AP_SPI_H1_TPM_MISO", 467 "AP_SPI_H1_TPM_MOSI", 468 "BL_PWM", 469 "EDPBRDG_PWREN", 470 "EDPBRDG_RST_ODL", 471 "EN_PP3300_HUB", 472 "HUB_RST_L", 473 "", 474 "", 475 "", 476 "", 477 "", 478 "", 479 "SD_CLK", 480 "SD_CMD", 481 "SD_DATA3", 482 "SD_DATA0", 483 "SD_DATA2", 484 "SD_DATA1", 485 "", 486 "", 487 "", 488 "", 489 "", 490 "", 491 "PCIE_WAKE_ODL", 492 "PCIE_RST_L", 493 "PCIE_CLKREQ_ODL", 494 "", 495 "", 496 "", 497 "", 498 "", 499 "", 500 "", 501 "", 502 "", 503 "", 504 "", 505 "", 506 "", 507 "", 508 "", 509 "", 510 "", 511 "", 512 "", 513 "", 514 "", 515 "", 516 "", 517 "SPMI_SCL", 518 "SPMI_SDA", 519 "AP_GOOD", 520 "UART_DBG_TX_AP_RX", 521 "UART_AP_TX_DBG_RX", 522 "UART_AP_TX_BT_RX", 523 "UART_BT_TX_AP_RX", 524 "MIPI_DPI_D0_R", 525 "MIPI_DPI_D1_R", 526 "MIPI_DPI_D2_R", 527 "MIPI_DPI_D3_R", 528 "MIPI_DPI_D4_R", 529 "MIPI_DPI_D5_R", 530 "MIPI_DPI_D6_R", 531 "MIPI_DPI_D7_R", 532 "MIPI_DPI_D8_R", 533 "MIPI_DPI_D9_R", 534 "MIPI_DPI_D10_R", 535 "", 536 "", 537 "MIPI_DPI_DE_R", 538 "MIPI_DPI_D11_R", 539 "MIPI_DPI_VSYNC_R", 540 "MIPI_DPI_CLK_R", 541 "MIPI_DPI_HSYNC_R", 542 "PCM_BT_DATAIN", 543 "PCM_BT_SYNC", 544 "PCM_BT_DATAOUT", 545 "PCM_BT_CLK", 546 "AP_I2C_AUDIO_SCL", 547 "AP_I2C_AUDIO_SDA", 548 "SCP_I2C_SCL", 549 "SCP_I2C_SDA", 550 "AP_I2C_WLAN_SCL", 551 "AP_I2C_WLAN_SDA", 552 "AP_I2C_DPBRDG_SCL", 553 "AP_I2C_DPBRDG_SDA", 554 "EN_PP1800_DPBRDG_DX", 555 "EN_PP3300_EDP_DX", 556 "EN_PP1800_EDPBRDG_DX", 557 "EN_PP1000_EDPBRDG", 558 "SCP_JTAG0_TDO", 559 "SCP_JTAG0_TDI", 560 "SCP_JTAG0_TMS", 561 "SCP_JTAG0_TCK", 562 "SCP_JTAG0_TRSTN", 563 "EN_PP3000_VMC_PMU", 564 "EN_PP3300_DISPLAY_DX", 565 "TOUCH_RST_L_1V8", 566 "TOUCH_REPORT_DISABLE", 567 "", 568 "", 569 "AP_I2C_TRACKPAD_SCL_1V8", 570 "AP_I2C_TRACKPAD_SDA_1V8", 571 "EN_PP3300_WLAN", 572 "BT_KILL_L", 573 "WIFI_KILL_L", 574 "SET_VMC_VOLT_AT_1V8", 575 "EN_SPK", 576 "AP_WARM_RST_REQ", 577 "", 578 "", 579 "EN_PP3000_SD_S3", 580 "AP_EDP_BKLTEN", 581 "", 582 "", 583 "", 584 "AP_SPI_EC_CLK", 585 "AP_SPI_EC_CS_L", 586 "AP_SPI_EC_MISO", 587 "AP_SPI_EC_MOSI", 588 "AP_I2C_EDPBRDG_SCL", 589 "AP_I2C_EDPBRDG_SDA", 590 "MT6315_PROC_INT", 591 "MT6315_GPU_INT", 592 "UART_SERVO_TX_SCP_RX", 593 "UART_SCP_TX_SERVO_RX", 594 "BT_RTS_AP_CTS", 595 "AP_RTS_BT_CTS", 596 "UART_AP_WAKE_BT_ODL", 597 "WLAN_ALERT_ODL", 598 "EC_IN_RW_ODL", 599 "H1_AP_INT_ODL", 600 "", 601 "", 602 "", 603 "", 604 "", 605 "", 606 "", 607 "", 608 "", 609 "", 610 "", 611 "MSDC0_CMD", 612 "MSDC0_DAT0", 613 "MSDC0_DAT2", 614 "MSDC0_DAT4", 615 "MSDC0_DAT6", 616 "MSDC0_DAT1", 617 "MSDC0_DAT5", 618 "MSDC0_DAT7", 619 "MSDC0_DSL", 620 "MSDC0_CLK", 621 "MSDC0_DAT3", 622 "MSDC0_RST_L", 623 "SCP_VREQ_VAO", 624 "AUD_DAT_MOSI2", 625 "AUD_NLE_MOSI1", 626 "AUD_NLE_MOSI0", 627 "AUD_DAT_MISO2", 628 "AP_I2C_SAR_SDA", 629 "AP_I2C_SAR_SCL", 630 "AP_I2C_PWR_SCL", 631 "AP_I2C_PWR_SDA", 632 "AP_I2C_TS_SCL_1V8", 633 "AP_I2C_TS_SDA_1V8", 634 "SRCLKENA0", 635 "SRCLKENA1", 636 "AP_EC_WATCHDOG_L", 637 "PWRAP_SPI0_MI", 638 "PWRAP_SPI0_CSN", 639 "PWRAP_SPI0_MO", 640 "PWRAP_SPI0_CK", 641 "AP_RTC_CLK32K", 642 "AUD_CLK_MOSI", 643 "AUD_SYNC_MOSI", 644 "AUD_DAT_MOSI0", 645 "AUD_DAT_MOSI1", 646 "AUD_DAT_MISO0", 647 "AUD_DAT_MISO1"; 648 649 anx7625_pins: anx7625-default-pins { 650 pins-out { 651 pinmux = <PINMUX_GPIO41__FUNC_GPIO41>, 652 <PINMUX_GPIO42__FUNC_GPIO42>; 653 output-low; 654 }; 655 656 pins-in { 657 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 658 input-enable; 659 bias-pull-up; 660 }; 661 }; 662 663 cr50_int: cr50-irq-default-pins { 664 pins-gsc-ap-int-odl { 665 pinmux = <PINMUX_GPIO171__FUNC_GPIO171>; 666 input-enable; 667 }; 668 }; 669 670 cros_ec_int: cros-ec-irq-default-pins { 671 pins-ec-ap-int-odl { 672 pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; 673 input-enable; 674 bias-pull-up; 675 }; 676 }; 677 678 i2c0_pins: i2c0-default-pins { 679 pins-bus { 680 pinmux = <PINMUX_GPIO204__FUNC_SCL0>, 681 <PINMUX_GPIO205__FUNC_SDA0>; 682 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 683 drive-strength-microamp = <1000>; 684 }; 685 }; 686 687 i2c1_pins: i2c1-default-pins { 688 pins-bus { 689 pinmux = <PINMUX_GPIO118__FUNC_SCL1>, 690 <PINMUX_GPIO119__FUNC_SDA1>; 691 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 692 drive-strength-microamp = <1000>; 693 }; 694 }; 695 696 i2c2_pins: i2c2-default-pins { 697 pins-bus { 698 pinmux = <PINMUX_GPIO141__FUNC_SCL2>, 699 <PINMUX_GPIO142__FUNC_SDA2>; 700 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 701 }; 702 }; 703 704 i2c3_pins: i2c3-default-pins { 705 pins-bus { 706 pinmux = <PINMUX_GPIO160__FUNC_SCL3>, 707 <PINMUX_GPIO161__FUNC_SDA3>; 708 bias-disable; 709 drive-strength-microamp = <1000>; 710 }; 711 }; 712 713 i2c7_pins: i2c7-default-pins { 714 pins-bus { 715 pinmux = <PINMUX_GPIO124__FUNC_SCL7>, 716 <PINMUX_GPIO125__FUNC_SDA7>; 717 bias-disable; 718 drive-strength-microamp = <1000>; 719 }; 720 }; 721 722 mmc0_default_pins: mmc0-default-pins { 723 pins-cmd-dat { 724 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 725 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 726 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 727 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 728 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 729 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 730 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 731 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 732 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 733 input-enable; 734 drive-strength = <8>; 735 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 736 }; 737 738 pins-clk { 739 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 740 drive-strength = <8>; 741 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 742 }; 743 744 pins-rst { 745 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 746 drive-strength = <8>; 747 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 748 }; 749 }; 750 751 mmc0_uhs_pins: mmc0-uhs-pins { 752 pins-cmd-dat { 753 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 754 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 755 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 756 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 757 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 758 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 759 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 760 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 761 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 762 input-enable; 763 drive-strength = <10>; 764 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 765 }; 766 767 pins-clk { 768 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 769 drive-strength = <10>; 770 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 771 }; 772 773 pins-rst { 774 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 775 drive-strength = <8>; 776 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 777 }; 778 779 pins-ds { 780 pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>; 781 drive-strength = <10>; 782 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 783 }; 784 }; 785 786 mmc1_default_pins: mmc1-default-pins { 787 pins-cmd-dat { 788 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 789 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 790 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 791 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 792 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 793 input-enable; 794 drive-strength = <8>; 795 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 796 }; 797 798 pins-clk { 799 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 800 drive-strength = <8>; 801 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 802 }; 803 804 pins-insert { 805 pinmux = <PINMUX_GPIO17__FUNC_GPIO17>; 806 input-enable; 807 bias-pull-up; 808 }; 809 }; 810 811 mmc1_uhs_pins: mmc1-uhs-pins { 812 pins-cmd-dat { 813 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 814 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 815 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 816 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 817 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 818 input-enable; 819 drive-strength = <8>; 820 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 821 }; 822 823 pins-clk { 824 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 825 input-enable; 826 drive-strength = <8>; 827 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 828 }; 829 }; 830 831 nor_flash_pins: nor-flash-default-pins { 832 pins-cs-io1 { 833 pinmux = <PINMUX_GPIO24__FUNC_SPINOR_CS>, 834 <PINMUX_GPIO28__FUNC_SPINOR_IO1>; 835 input-enable; 836 bias-pull-up; 837 drive-strength = <10>; 838 }; 839 840 pins-io0 { 841 pinmux = <PINMUX_GPIO27__FUNC_SPINOR_IO0>; 842 bias-pull-up; 843 drive-strength = <10>; 844 }; 845 846 pins-clk { 847 pinmux = <PINMUX_GPIO25__FUNC_SPINOR_CK>; 848 input-enable; 849 bias-pull-up; 850 drive-strength = <10>; 851 }; 852 }; 853 854 pcie_pins: pcie-default-pins { 855 pins-pcie-wake { 856 pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>; 857 bias-pull-up; 858 }; 859 860 pins-pcie-pereset { 861 pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>; 862 }; 863 864 pins-pcie-clkreq { 865 pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>; 866 bias-pull-up; 867 }; 868 869 pins-wifi-kill { 870 pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */ 871 output-high; 872 }; 873 }; 874 875 pp1000_dpbrdg_en_pins: pp1000-dpbrdg-en-pins { 876 pins-en { 877 pinmux = <PINMUX_GPIO19__FUNC_GPIO19>; 878 output-low; 879 }; 880 }; 881 882 pp1000_mipibrdg_en_pins: pp1000-mipibrdg-en-pins { 883 pins-en { 884 pinmux = <PINMUX_GPIO129__FUNC_GPIO129>; 885 output-low; 886 }; 887 }; 888 889 pp1800_dpbrdg_en_pins: pp1800-dpbrdg-en-pins { 890 pins-en { 891 pinmux = <PINMUX_GPIO126__FUNC_GPIO126>; 892 output-low; 893 }; 894 }; 895 896 pp1800_mipibrdg_en_pins: pp1800-mipibrd-en-pins { 897 pins-en { 898 pinmux = <PINMUX_GPIO128__FUNC_GPIO128>; 899 output-low; 900 }; 901 }; 902 903 pp3300_dpbrdg_en_pins: pp3300-dpbrdg-en-pins { 904 pins-en { 905 pinmux = <PINMUX_GPIO26__FUNC_GPIO26>; 906 output-low; 907 }; 908 }; 909 910 pp3300_mipibrdg_en_pins: pp3300-mipibrdg-en-pins { 911 pins-en { 912 pinmux = <PINMUX_GPIO127__FUNC_GPIO127>; 913 output-low; 914 }; 915 }; 916 917 pp3300_wlan_pins: pp3300-wlan-pins { 918 pins-pcie-en-pp3300-wlan { 919 pinmux = <PINMUX_GPIO143__FUNC_GPIO143>; 920 output-high; 921 }; 922 }; 923 924 pwm0_pins: pwm0-default-pins { 925 pins-pwm { 926 pinmux = <PINMUX_GPIO40__FUNC_DISP_PWM>; 927 }; 928 929 pins-inhibit { 930 pinmux = <PINMUX_GPIO152__FUNC_GPIO152>; 931 output-high; 932 }; 933 }; 934 935 scp_pins: scp-pins { 936 pins-vreq-vao { 937 pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>; 938 }; 939 }; 940 941 spi1_pins: spi1-default-pins { 942 pins-cs-mosi-clk { 943 pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, 944 <PINMUX_GPIO159__FUNC_SPI1_A_MO>, 945 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; 946 bias-disable; 947 }; 948 949 pins-miso { 950 pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; 951 bias-pull-down; 952 }; 953 }; 954 955 spi5_pins: spi5-default-pins { 956 pins-bus { 957 pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>, 958 <PINMUX_GPIO37__FUNC_GPIO37>, 959 <PINMUX_GPIO39__FUNC_SPI5_A_MO>, 960 <PINMUX_GPIO36__FUNC_SPI5_A_CLK>; 961 bias-disable; 962 }; 963 }; 964 965 trackpad_pins: trackpad-default-pins { 966 pins-int-n { 967 pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; 968 input-enable; 969 bias-pull-up = <MTK_PUPD_SET_R1R0_11>; 970 }; 971 }; 972 973 touchscreen_pins: touchscreen-default-pins { 974 pins-irq { 975 pinmux = <PINMUX_GPIO21__FUNC_GPIO21>; 976 input-enable; 977 bias-pull-up; 978 }; 979 980 pins-reset { 981 pinmux = <PINMUX_GPIO137__FUNC_GPIO137>; 982 output-high; 983 }; 984 985 pins-report-sw { 986 pinmux = <PINMUX_GPIO138__FUNC_GPIO138>; 987 output-low; 988 }; 989 }; 990}; 991 992&pmic { 993 interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>; 994}; 995 996&pwm0 { 997 status = "okay"; 998 999 pinctrl-names = "default"; 1000 pinctrl-0 = <&pwm0_pins>; 1001}; 1002 1003&scp { 1004 status = "okay"; 1005 1006 firmware-name = "mediatek/mt8192/scp.img"; 1007 memory-region = <&scp_mem_reserved>; 1008 pinctrl-names = "default"; 1009 pinctrl-0 = <&scp_pins>; 1010 1011 cros-ec { 1012 compatible = "google,cros-ec-rpmsg"; 1013 mediatek,rpmsg-name = "cros-ec-rpmsg"; 1014 }; 1015}; 1016 1017&spi1 { 1018 status = "okay"; 1019 1020 mediatek,pad-select = <0>; 1021 pinctrl-names = "default"; 1022 pinctrl-0 = <&spi1_pins>; 1023 1024 cros_ec: ec@0 { 1025 compatible = "google,cros-ec-spi"; 1026 reg = <0>; 1027 interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; 1028 spi-max-frequency = <3000000>; 1029 pinctrl-names = "default"; 1030 pinctrl-0 = <&cros_ec_int>; 1031 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 1035 base_detection: cbas { 1036 compatible = "google,cros-cbas"; 1037 }; 1038 1039 cros_ec_pwm: pwm { 1040 compatible = "google,cros-ec-pwm"; 1041 #pwm-cells = <1>; 1042 1043 status = "disabled"; 1044 }; 1045 1046 i2c_tunnel: i2c-tunnel { 1047 compatible = "google,cros-ec-i2c-tunnel"; 1048 google,remote-bus = <0>; 1049 #address-cells = <1>; 1050 #size-cells = <0>; 1051 }; 1052 1053 mt6360_ldo3_reg: regulator@0 { 1054 compatible = "google,cros-ec-regulator"; 1055 reg = <0>; 1056 regulator-min-microvolt = <1800000>; 1057 regulator-max-microvolt = <3300000>; 1058 }; 1059 1060 mt6360_ldo5_reg: regulator@1 { 1061 compatible = "google,cros-ec-regulator"; 1062 reg = <1>; 1063 regulator-min-microvolt = <3300000>; 1064 regulator-max-microvolt = <3300000>; 1065 }; 1066 1067 typec { 1068 compatible = "google,cros-ec-typec"; 1069 #address-cells = <1>; 1070 #size-cells = <0>; 1071 1072 usb_c0: connector@0 { 1073 compatible = "usb-c-connector"; 1074 reg = <0>; 1075 label = "left"; 1076 power-role = "dual"; 1077 data-role = "host"; 1078 try-power-role = "source"; 1079 }; 1080 1081 usb_c1: connector@1 { 1082 compatible = "usb-c-connector"; 1083 reg = <1>; 1084 label = "right"; 1085 power-role = "dual"; 1086 data-role = "host"; 1087 try-power-role = "source"; 1088 }; 1089 }; 1090 }; 1091}; 1092 1093&spi5 { 1094 status = "okay"; 1095 1096 cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>; 1097 mediatek,pad-select = <0>; 1098 pinctrl-names = "default"; 1099 pinctrl-0 = <&spi5_pins>; 1100 1101 cr50@0 { 1102 compatible = "google,cr50"; 1103 reg = <0>; 1104 interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>; 1105 spi-max-frequency = <1000000>; 1106 pinctrl-names = "default"; 1107 pinctrl-0 = <&cr50_int>; 1108 }; 1109}; 1110 1111&spmi { 1112 #address-cells = <2>; 1113 #size-cells = <0>; 1114 1115 mt6315_6: pmic@6 { 1116 compatible = "mediatek,mt6315-regulator"; 1117 reg = <0x6 SPMI_USID>; 1118 1119 regulators { 1120 mt6315_6_vbuck1: vbuck1 { 1121 regulator-compatible = "vbuck1"; 1122 regulator-name = "Vbcpu"; 1123 regulator-min-microvolt = <300000>; 1124 regulator-max-microvolt = <1193750>; 1125 regulator-enable-ramp-delay = <256>; 1126 regulator-allowed-modes = <0 1 2>; 1127 regulator-always-on; 1128 }; 1129 1130 mt6315_6_vbuck3: vbuck3 { 1131 regulator-compatible = "vbuck3"; 1132 regulator-name = "Vlcpu"; 1133 regulator-min-microvolt = <300000>; 1134 regulator-max-microvolt = <1193750>; 1135 regulator-enable-ramp-delay = <256>; 1136 regulator-allowed-modes = <0 1 2>; 1137 regulator-always-on; 1138 }; 1139 }; 1140 }; 1141 1142 mt6315_7: pmic@7 { 1143 compatible = "mediatek,mt6315-regulator"; 1144 reg = <0x7 SPMI_USID>; 1145 1146 regulators { 1147 mt6315_7_vbuck1: vbuck1 { 1148 regulator-compatible = "vbuck1"; 1149 regulator-name = "Vgpu"; 1150 regulator-min-microvolt = <606250>; 1151 regulator-max-microvolt = <1193750>; 1152 regulator-enable-ramp-delay = <256>; 1153 regulator-allowed-modes = <0 1 2>; 1154 }; 1155 }; 1156 }; 1157}; 1158 1159&uart0 { 1160 status = "okay"; 1161}; 1162 1163&xhci { 1164 status = "okay"; 1165 1166 wakeup-source; 1167 vusb33-supply = <&pp3300_g>; 1168 vbus-supply = <&pp5000_a>; 1169}; 1170 1171#include <arm/cros-ec-keyboard.dtsi> 1172#include <arm/cros-ec-sbs.dtsi> 1173