1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6/dts-v1/; 7#include "mt8192.dtsi" 8#include "mt6359.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/spmi/spmi.h> 11 12/ { 13 aliases { 14 i2c0 = &i2c0; 15 i2c1 = &i2c1; 16 i2c2 = &i2c2; 17 i2c3 = &i2c3; 18 i2c7 = &i2c7; 19 mmc0 = &mmc0; 20 mmc1 = &mmc1; 21 serial0 = &uart0; 22 }; 23 24 chosen { 25 stdout-path = "serial0:115200n8"; 26 }; 27 28 memory@40000000 { 29 device_type = "memory"; 30 reg = <0 0x40000000 0 0x80000000>; 31 }; 32 33 backlight_lcd0: backlight-lcd0 { 34 compatible = "pwm-backlight"; 35 pwms = <&pwm0 0 500000>; 36 power-supply = <&ppvar_sys>; 37 enable-gpios = <&pio 152 0>; 38 brightness-levels = <0 1023>; 39 num-interpolated-steps = <1023>; 40 default-brightness-level = <576>; 41 }; 42 43 dmic_codec: dmic-codec { 44 compatible = "dmic-codec"; 45 num-channels = <2>; 46 wakeup-delay-ms = <50>; 47 }; 48 49 pp1000_dpbrdg: regulator-1v0-dpbrdg { 50 compatible = "regulator-fixed"; 51 regulator-name = "pp1000_dpbrdg"; 52 pinctrl-names = "default"; 53 pinctrl-0 = <&pp1000_dpbrdg_en_pins>; 54 regulator-min-microvolt = <1000000>; 55 regulator-max-microvolt = <1000000>; 56 enable-active-high; 57 regulator-boot-on; 58 gpio = <&pio 19 GPIO_ACTIVE_HIGH>; 59 vin-supply = <&mt6359_vs2_buck_reg>; 60 }; 61 62 pp1000_mipibrdg: regulator-1v0-mipibrdg { 63 compatible = "regulator-fixed"; 64 regulator-name = "pp1000_mipibrdg"; 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pp1000_mipibrdg_en_pins>; 67 regulator-min-microvolt = <1000000>; 68 regulator-max-microvolt = <1000000>; 69 enable-active-high; 70 regulator-boot-on; 71 gpio = <&pio 129 GPIO_ACTIVE_HIGH>; 72 vin-supply = <&mt6359_vs2_buck_reg>; 73 }; 74 75 pp1800_dpbrdg: regulator-1v8-dpbrdg { 76 compatible = "regulator-fixed"; 77 regulator-name = "pp1800_dpbrdg"; 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pp1800_dpbrdg_en_pins>; 80 enable-active-high; 81 regulator-boot-on; 82 gpio = <&pio 126 GPIO_ACTIVE_HIGH>; 83 vin-supply = <&mt6359_vio18_ldo_reg>; 84 }; 85 86 /* system wide LDO 1.8V power rail */ 87 pp1800_ldo_g: regulator-1v8-g { 88 compatible = "regulator-fixed"; 89 regulator-name = "pp1800_ldo_g"; 90 regulator-always-on; 91 regulator-boot-on; 92 regulator-min-microvolt = <1800000>; 93 regulator-max-microvolt = <1800000>; 94 vin-supply = <&pp3300_g>; 95 }; 96 97 pp1800_mipibrdg: regulator-1v8-mipibrdg { 98 compatible = "regulator-fixed"; 99 regulator-name = "pp1800_mipibrdg"; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&pp1800_mipibrdg_en_pins>; 102 enable-active-high; 103 regulator-boot-on; 104 gpio = <&pio 128 GPIO_ACTIVE_HIGH>; 105 vin-supply = <&mt6359_vio18_ldo_reg>; 106 }; 107 108 pp3300_dpbrdg: regulator-3v3-dpbrdg { 109 compatible = "regulator-fixed"; 110 regulator-name = "pp3300_dpbrdg"; 111 pinctrl-names = "default"; 112 pinctrl-0 = <&pp3300_dpbrdg_en_pins>; 113 enable-active-high; 114 regulator-boot-on; 115 gpio = <&pio 26 GPIO_ACTIVE_HIGH>; 116 vin-supply = <&pp3300_g>; 117 }; 118 119 /* system wide switching 3.3V power rail */ 120 pp3300_g: regulator-3v3-g { 121 compatible = "regulator-fixed"; 122 regulator-name = "pp3300_g"; 123 regulator-always-on; 124 regulator-boot-on; 125 regulator-min-microvolt = <3300000>; 126 regulator-max-microvolt = <3300000>; 127 vin-supply = <&ppvar_sys>; 128 }; 129 130 /* system wide LDO 3.3V power rail */ 131 pp3300_ldo_z: regulator-3v3-z { 132 compatible = "regulator-fixed"; 133 regulator-name = "pp3300_ldo_z"; 134 regulator-always-on; 135 regulator-boot-on; 136 regulator-min-microvolt = <3300000>; 137 regulator-max-microvolt = <3300000>; 138 vin-supply = <&ppvar_sys>; 139 }; 140 141 pp3300_mipibrdg: regulator-3v3-mipibrdg { 142 compatible = "regulator-fixed"; 143 regulator-name = "pp3300_mipibrdg"; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pp3300_mipibrdg_en_pins>; 146 enable-active-high; 147 regulator-boot-on; 148 gpio = <&pio 127 GPIO_ACTIVE_HIGH>; 149 vin-supply = <&pp3300_g>; 150 }; 151 152 /* separately switched 3.3V power rail */ 153 pp3300_u: regulator-3v3-u { 154 compatible = "regulator-fixed"; 155 regulator-name = "pp3300_u"; 156 regulator-always-on; 157 regulator-boot-on; 158 regulator-min-microvolt = <3300000>; 159 regulator-max-microvolt = <3300000>; 160 /* enable pin wired to GPIO controlled by EC */ 161 vin-supply = <&pp3300_g>; 162 }; 163 164 pp3300_wlan: regulator-3v3-wlan { 165 compatible = "regulator-fixed"; 166 regulator-name = "pp3300_wlan"; 167 regulator-always-on; 168 regulator-boot-on; 169 regulator-min-microvolt = <3300000>; 170 regulator-max-microvolt = <3300000>; 171 pinctrl-names = "default"; 172 pinctrl-0 = <&pp3300_wlan_pins>; 173 enable-active-high; 174 gpio = <&pio 143 GPIO_ACTIVE_HIGH>; 175 }; 176 177 /* system wide switching 5.0V power rail */ 178 pp5000_a: regulator-5v0-a { 179 compatible = "regulator-fixed"; 180 regulator-name = "pp5000_a"; 181 regulator-always-on; 182 regulator-boot-on; 183 regulator-min-microvolt = <5000000>; 184 regulator-max-microvolt = <5000000>; 185 vin-supply = <&ppvar_sys>; 186 }; 187 188 /* system wide semi-regulated power rail from battery or USB */ 189 ppvar_sys: regulator-var-sys { 190 compatible = "regulator-fixed"; 191 regulator-name = "ppvar_sys"; 192 regulator-always-on; 193 regulator-boot-on; 194 }; 195 196 reserved_memory: reserved-memory { 197 #address-cells = <2>; 198 #size-cells = <2>; 199 ranges; 200 201 scp_mem_reserved: scp@50000000 { 202 compatible = "shared-dma-pool"; 203 reg = <0 0x50000000 0 0x2900000>; 204 no-map; 205 }; 206 207 wifi_restricted_dma_region: wifi@c0000000 { 208 compatible = "restricted-dma-pool"; 209 reg = <0 0xc0000000 0 0x4000000>; 210 }; 211 }; 212 213 sound: sound { 214 mediatek,platform = <&afe>; 215 pinctrl-names = "aud_clk_mosi_off", 216 "aud_clk_mosi_on", 217 "aud_dat_mosi_off", 218 "aud_dat_mosi_on", 219 "aud_dat_miso_off", 220 "aud_dat_miso_on", 221 "vow_dat_miso_off", 222 "vow_dat_miso_on", 223 "vow_clk_miso_off", 224 "vow_clk_miso_on", 225 "aud_nle_mosi_off", 226 "aud_nle_mosi_on", 227 "aud_dat_miso2_off", 228 "aud_dat_miso2_on", 229 "aud_gpio_i2s3_off", 230 "aud_gpio_i2s3_on", 231 "aud_gpio_i2s8_off", 232 "aud_gpio_i2s8_on", 233 "aud_gpio_i2s9_off", 234 "aud_gpio_i2s9_on", 235 "aud_dat_mosi_ch34_off", 236 "aud_dat_mosi_ch34_on", 237 "aud_dat_miso_ch34_off", 238 "aud_dat_miso_ch34_on", 239 "aud_gpio_tdm_off", 240 "aud_gpio_tdm_on"; 241 pinctrl-0 = <&aud_clk_mosi_off_pins>; 242 pinctrl-1 = <&aud_clk_mosi_on_pins>; 243 pinctrl-2 = <&aud_dat_mosi_off_pins>; 244 pinctrl-3 = <&aud_dat_mosi_on_pins>; 245 pinctrl-4 = <&aud_dat_miso_off_pins>; 246 pinctrl-5 = <&aud_dat_miso_on_pins>; 247 pinctrl-6 = <&vow_dat_miso_off_pins>; 248 pinctrl-7 = <&vow_dat_miso_on_pins>; 249 pinctrl-8 = <&vow_clk_miso_off_pins>; 250 pinctrl-9 = <&vow_clk_miso_on_pins>; 251 pinctrl-10 = <&aud_nle_mosi_off_pins>; 252 pinctrl-11 = <&aud_nle_mosi_on_pins>; 253 pinctrl-12 = <&aud_dat_miso2_off_pins>; 254 pinctrl-13 = <&aud_dat_miso2_on_pins>; 255 pinctrl-14 = <&aud_gpio_i2s3_off_pins>; 256 pinctrl-15 = <&aud_gpio_i2s3_on_pins>; 257 pinctrl-16 = <&aud_gpio_i2s8_off_pins>; 258 pinctrl-17 = <&aud_gpio_i2s8_on_pins>; 259 pinctrl-18 = <&aud_gpio_i2s9_off_pins>; 260 pinctrl-19 = <&aud_gpio_i2s9_on_pins>; 261 pinctrl-20 = <&aud_dat_mosi_ch34_off_pins>; 262 pinctrl-21 = <&aud_dat_mosi_ch34_on_pins>; 263 pinctrl-22 = <&aud_dat_miso_ch34_off_pins>; 264 pinctrl-23 = <&aud_dat_miso_ch34_on_pins>; 265 pinctrl-24 = <&aud_gpio_tdm_off_pins>; 266 pinctrl-25 = <&aud_gpio_tdm_on_pins>; 267 }; 268}; 269 270&dsi0 { 271 status = "okay"; 272}; 273 274&dsi_out { 275 remote-endpoint = <&anx7625_in>; 276}; 277 278&i2c0 { 279 status = "okay"; 280 281 clock-frequency = <400000>; 282 pinctrl-names = "default"; 283 pinctrl-0 = <&i2c0_pins>; 284 285 touchscreen: touchscreen@10 { 286 reg = <0x10>; 287 interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&touchscreen_pins>; 290 }; 291}; 292 293&i2c1 { 294 status = "okay"; 295 296 clock-frequency = <400000>; 297 pinctrl-names = "default"; 298 pinctrl-0 = <&i2c1_pins>; 299}; 300 301&i2c2 { 302 status = "okay"; 303 304 clock-frequency = <400000>; 305 clock-stretch-ns = <12600>; 306 pinctrl-names = "default"; 307 pinctrl-0 = <&i2c2_pins>; 308 309 trackpad@15 { 310 compatible = "elan,ekth3000"; 311 reg = <0x15>; 312 interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&trackpad_pins>; 315 vcc-supply = <&pp3300_u>; 316 wakeup-source; 317 }; 318}; 319 320&i2c3 { 321 status = "okay"; 322 323 clock-frequency = <400000>; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&i2c3_pins>; 326 327 anx_bridge: anx7625@58 { 328 compatible = "analogix,anx7625"; 329 reg = <0x58>; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&anx7625_pins>; 332 enable-gpios = <&pio 41 GPIO_ACTIVE_HIGH>; 333 reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; 334 vdd10-supply = <&pp1000_mipibrdg>; 335 vdd18-supply = <&pp1800_mipibrdg>; 336 vdd33-supply = <&pp3300_mipibrdg>; 337 338 ports { 339 #address-cells = <1>; 340 #size-cells = <0>; 341 342 port@0 { 343 reg = <0>; 344 345 anx7625_in: endpoint { 346 remote-endpoint = <&dsi_out>; 347 }; 348 }; 349 350 port@1 { 351 reg = <1>; 352 353 anx7625_out: endpoint { 354 remote-endpoint = <&panel_in>; 355 }; 356 }; 357 }; 358 359 aux-bus { 360 panel: panel { 361 compatible = "edp-panel"; 362 power-supply = <&pp3300_mipibrdg>; 363 backlight = <&backlight_lcd0>; 364 365 port { 366 panel_in: endpoint { 367 remote-endpoint = <&anx7625_out>; 368 }; 369 }; 370 }; 371 }; 372 }; 373}; 374 375&i2c7 { 376 status = "okay"; 377 378 clock-frequency = <400000>; 379 pinctrl-names = "default"; 380 pinctrl-0 = <&i2c7_pins>; 381}; 382 383&mfg0 { 384 domain-supply = <&mt6315_7_vbuck1>; 385}; 386 387&mipi_tx0 { 388 status = "okay"; 389}; 390 391&mmc0 { 392 status = "okay"; 393 394 pinctrl-names = "default", "state_uhs"; 395 pinctrl-0 = <&mmc0_default_pins>; 396 pinctrl-1 = <&mmc0_uhs_pins>; 397 bus-width = <8>; 398 max-frequency = <200000000>; 399 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 400 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 401 cap-mmc-highspeed; 402 mmc-hs200-1_8v; 403 mmc-hs400-1_8v; 404 supports-cqe; 405 cap-mmc-hw-reset; 406 mmc-hs400-enhanced-strobe; 407 hs400-ds-delay = <0x12814>; 408 no-sdio; 409 no-sd; 410 non-removable; 411}; 412 413&mmc1 { 414 status = "okay"; 415 416 pinctrl-names = "default", "state_uhs"; 417 pinctrl-0 = <&mmc1_default_pins>; 418 pinctrl-1 = <&mmc1_uhs_pins>; 419 bus-width = <4>; 420 max-frequency = <200000000>; 421 cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>; 422 vmmc-supply = <&mt6360_ldo5_reg>; 423 vqmmc-supply = <&mt6360_ldo3_reg>; 424 cap-sd-highspeed; 425 sd-uhs-sdr50; 426 sd-uhs-sdr104; 427 no-sdio; 428 no-mmc; 429}; 430 431/* for CORE */ 432&mt6359_vgpu11_buck_reg { 433 regulator-always-on; 434}; 435 436&mt6359_vgpu11_sshub_buck_reg { 437 regulator-always-on; 438 regulator-min-microvolt = <575000>; 439 regulator-max-microvolt = <575000>; 440}; 441 442&mt6359_vrf12_ldo_reg { 443 regulator-always-on; 444}; 445 446&mt6359_vufs_ldo_reg { 447 regulator-always-on; 448}; 449 450&mt6359codec { 451 mediatek,dmic-mode = <1>; /* one-wire */ 452 mediatek,mic-type-0 = <2>; /* DMIC */ 453 mediatek,mic-type-2 = <2>; /* DMIC */ 454}; 455 456&nor_flash { 457 status = "okay"; 458 459 pinctrl-names = "default"; 460 pinctrl-0 = <&nor_flash_pins>; 461 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 462 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>; 463 464 flash@0 { 465 compatible = "winbond,w25q64jwm", "jedec,spi-nor"; 466 reg = <0>; 467 spi-max-frequency = <52000000>; 468 spi-rx-bus-width = <2>; 469 spi-tx-bus-width = <2>; 470 }; 471}; 472 473&pcie { 474 pinctrl-names = "default"; 475 pinctrl-0 = <&pcie_pins>; 476 477 pcie0: pcie@0,0 { 478 device_type = "pci"; 479 reg = <0x0000 0 0 0 0>; 480 num-lanes = <1>; 481 bus-range = <0x1 0x1>; 482 483 #address-cells = <3>; 484 #size-cells = <2>; 485 ranges; 486 487 wifi: wifi@0,0 { 488 reg = <0x10000 0 0 0 0x100000>, 489 <0x10000 0 0x100000 0 0x100000>; 490 memory-region = <&wifi_restricted_dma_region>; 491 }; 492 }; 493}; 494 495&pio { 496 /* 220 lines */ 497 gpio-line-names = "I2S_DP_LRCK", 498 "IS_DP_BCLK", 499 "I2S_DP_MCLK", 500 "I2S_DP_DATAOUT", 501 "SAR0_INT_ODL", 502 "EC_AP_INT_ODL", 503 "EDPBRDG_INT_ODL", 504 "DPBRDG_INT_ODL", 505 "DPBRDG_PWREN", 506 "DPBRDG_RST_ODL", 507 "I2S_HP_MCLK", 508 "I2S_HP_BCK", 509 "I2S_HP_LRCK", 510 "I2S_HP_DATAIN", 511 /* 512 * AP_FLASH_WP_L is crossystem ABI. Schematics 513 * call it AP_FLASH_WP_ODL. 514 */ 515 "AP_FLASH_WP_L", 516 "TRACKPAD_INT_ODL", 517 "EC_AP_HPD_OD", 518 "SD_CD_ODL", 519 "HP_INT_ODL_ALC", 520 "EN_PP1000_DPBRDG", 521 "AP_GPIO20", 522 "TOUCH_INT_L_1V8", 523 "UART_BT_WAKE_ODL", 524 "AP_GPIO23", 525 "AP_SPI_FLASH_CS_L", 526 "AP_SPI_FLASH_CLK", 527 "EN_PP3300_DPBRDG_DX", 528 "AP_SPI_FLASH_MOSI", 529 "AP_SPI_FLASH_MISO", 530 "I2S_HP_DATAOUT", 531 "AP_GPIO30", 532 "I2S_SPKR_MCLK", 533 "I2S_SPKR_BCLK", 534 "I2S_SPKR_LRCK", 535 "I2S_SPKR_DATAIN", 536 "I2S_SPKR_DATAOUT", 537 "AP_SPI_H1_TPM_CLK", 538 "AP_SPI_H1_TPM_CS_L", 539 "AP_SPI_H1_TPM_MISO", 540 "AP_SPI_H1_TPM_MOSI", 541 "BL_PWM", 542 "EDPBRDG_PWREN", 543 "EDPBRDG_RST_ODL", 544 "EN_PP3300_HUB", 545 "HUB_RST_L", 546 "", 547 "", 548 "", 549 "", 550 "", 551 "", 552 "SD_CLK", 553 "SD_CMD", 554 "SD_DATA3", 555 "SD_DATA0", 556 "SD_DATA2", 557 "SD_DATA1", 558 "", 559 "", 560 "", 561 "", 562 "", 563 "", 564 "PCIE_WAKE_ODL", 565 "PCIE_RST_L", 566 "PCIE_CLKREQ_ODL", 567 "", 568 "", 569 "", 570 "", 571 "", 572 "", 573 "", 574 "", 575 "", 576 "", 577 "", 578 "", 579 "", 580 "", 581 "", 582 "", 583 "", 584 "", 585 "", 586 "", 587 "", 588 "", 589 "", 590 "SPMI_SCL", 591 "SPMI_SDA", 592 "AP_GOOD", 593 "UART_DBG_TX_AP_RX", 594 "UART_AP_TX_DBG_RX", 595 "UART_AP_TX_BT_RX", 596 "UART_BT_TX_AP_RX", 597 "MIPI_DPI_D0_R", 598 "MIPI_DPI_D1_R", 599 "MIPI_DPI_D2_R", 600 "MIPI_DPI_D3_R", 601 "MIPI_DPI_D4_R", 602 "MIPI_DPI_D5_R", 603 "MIPI_DPI_D6_R", 604 "MIPI_DPI_D7_R", 605 "MIPI_DPI_D8_R", 606 "MIPI_DPI_D9_R", 607 "MIPI_DPI_D10_R", 608 "", 609 "", 610 "MIPI_DPI_DE_R", 611 "MIPI_DPI_D11_R", 612 "MIPI_DPI_VSYNC_R", 613 "MIPI_DPI_CLK_R", 614 "MIPI_DPI_HSYNC_R", 615 "PCM_BT_DATAIN", 616 "PCM_BT_SYNC", 617 "PCM_BT_DATAOUT", 618 "PCM_BT_CLK", 619 "AP_I2C_AUDIO_SCL", 620 "AP_I2C_AUDIO_SDA", 621 "SCP_I2C_SCL", 622 "SCP_I2C_SDA", 623 "AP_I2C_WLAN_SCL", 624 "AP_I2C_WLAN_SDA", 625 "AP_I2C_DPBRDG_SCL", 626 "AP_I2C_DPBRDG_SDA", 627 "EN_PP1800_DPBRDG_DX", 628 "EN_PP3300_EDP_DX", 629 "EN_PP1800_EDPBRDG_DX", 630 "EN_PP1000_EDPBRDG", 631 "SCP_JTAG0_TDO", 632 "SCP_JTAG0_TDI", 633 "SCP_JTAG0_TMS", 634 "SCP_JTAG0_TCK", 635 "SCP_JTAG0_TRSTN", 636 "EN_PP3000_VMC_PMU", 637 "EN_PP3300_DISPLAY_DX", 638 "TOUCH_RST_L_1V8", 639 "TOUCH_REPORT_DISABLE", 640 "", 641 "", 642 "AP_I2C_TRACKPAD_SCL_1V8", 643 "AP_I2C_TRACKPAD_SDA_1V8", 644 "EN_PP3300_WLAN", 645 "BT_KILL_L", 646 "WIFI_KILL_L", 647 "SET_VMC_VOLT_AT_1V8", 648 "EN_SPK", 649 "AP_WARM_RST_REQ", 650 "", 651 "", 652 "EN_PP3000_SD_S3", 653 "AP_EDP_BKLTEN", 654 "", 655 "", 656 "", 657 "AP_SPI_EC_CLK", 658 "AP_SPI_EC_CS_L", 659 "AP_SPI_EC_MISO", 660 "AP_SPI_EC_MOSI", 661 "AP_I2C_EDPBRDG_SCL", 662 "AP_I2C_EDPBRDG_SDA", 663 "MT6315_PROC_INT", 664 "MT6315_GPU_INT", 665 "UART_SERVO_TX_SCP_RX", 666 "UART_SCP_TX_SERVO_RX", 667 "BT_RTS_AP_CTS", 668 "AP_RTS_BT_CTS", 669 "UART_AP_WAKE_BT_ODL", 670 "WLAN_ALERT_ODL", 671 "EC_IN_RW_ODL", 672 "H1_AP_INT_ODL", 673 "", 674 "", 675 "", 676 "", 677 "", 678 "", 679 "", 680 "", 681 "", 682 "", 683 "", 684 "MSDC0_CMD", 685 "MSDC0_DAT0", 686 "MSDC0_DAT2", 687 "MSDC0_DAT4", 688 "MSDC0_DAT6", 689 "MSDC0_DAT1", 690 "MSDC0_DAT5", 691 "MSDC0_DAT7", 692 "MSDC0_DSL", 693 "MSDC0_CLK", 694 "MSDC0_DAT3", 695 "MSDC0_RST_L", 696 "SCP_VREQ_VAO", 697 "AUD_DAT_MOSI2", 698 "AUD_NLE_MOSI1", 699 "AUD_NLE_MOSI0", 700 "AUD_DAT_MISO2", 701 "AP_I2C_SAR_SDA", 702 "AP_I2C_SAR_SCL", 703 "AP_I2C_PWR_SCL", 704 "AP_I2C_PWR_SDA", 705 "AP_I2C_TS_SCL_1V8", 706 "AP_I2C_TS_SDA_1V8", 707 "SRCLKENA0", 708 "SRCLKENA1", 709 "AP_EC_WATCHDOG_L", 710 "PWRAP_SPI0_MI", 711 "PWRAP_SPI0_CSN", 712 "PWRAP_SPI0_MO", 713 "PWRAP_SPI0_CK", 714 "AP_RTC_CLK32K", 715 "AUD_CLK_MOSI", 716 "AUD_SYNC_MOSI", 717 "AUD_DAT_MOSI0", 718 "AUD_DAT_MOSI1", 719 "AUD_DAT_MISO0", 720 "AUD_DAT_MISO1"; 721 722 anx7625_pins: anx7625-default-pins { 723 pins-out { 724 pinmux = <PINMUX_GPIO41__FUNC_GPIO41>, 725 <PINMUX_GPIO42__FUNC_GPIO42>; 726 output-low; 727 }; 728 729 pins-in { 730 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 731 input-enable; 732 bias-pull-up; 733 }; 734 }; 735 736 aud_clk_mosi_off_pins: aud-clk-mosi-off-pins { 737 pins-mosi-off { 738 pinmux = <PINMUX_GPIO214__FUNC_GPIO214>, 739 <PINMUX_GPIO215__FUNC_GPIO215>; 740 }; 741 }; 742 743 aud_clk_mosi_on_pins: aud-clk-mosi-on-pins { 744 pins-mosi-on { 745 pinmux = <PINMUX_GPIO214__FUNC_AUD_CLK_MOSI>, 746 <PINMUX_GPIO215__FUNC_AUD_SYNC_MOSI>; 747 drive-strength = <10>; 748 }; 749 }; 750 751 aud_dat_miso_ch34_off_pins: aud-dat-miso-ch34-off-pins { 752 pins-miso-off { 753 pinmux = <PINMUX_GPIO199__FUNC_GPIO199>; 754 }; 755 }; 756 757 aud_dat_miso_ch34_on_pins: aud-dat-miso-ch34-on-pins { 758 pins-miso-on { 759 pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>; 760 }; 761 }; 762 763 aud_dat_miso_off_pins: aud-dat-miso-off-pins { 764 pins-miso-off { 765 pinmux = <PINMUX_GPIO218__FUNC_GPIO218>, 766 <PINMUX_GPIO219__FUNC_GPIO219>; 767 }; 768 }; 769 770 aud_dat_miso_on_pins: aud-dat-miso-on-pins { 771 pins-miso-on { 772 pinmux = <PINMUX_GPIO218__FUNC_AUD_DAT_MISO0>, 773 <PINMUX_GPIO219__FUNC_AUD_DAT_MISO1>; 774 drive-strength = <10>; 775 }; 776 }; 777 778 aud_dat_miso2_off_pins: aud-dat-miso2-off-pins { 779 pins-miso-off { 780 pinmux = <PINMUX_GPIO199__FUNC_GPIO199>; 781 }; 782 }; 783 784 aud_dat_miso2_on_pins: aud-dat-miso2-on-pins { 785 pins-miso-on { 786 pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>; 787 }; 788 }; 789 790 aud_dat_mosi_ch34_off_pins: aud-dat-mosi-ch34-off-pins { 791 pins-mosi-off { 792 pinmux = <PINMUX_GPIO196__FUNC_GPIO196>; 793 }; 794 }; 795 796 aud_dat_mosi_ch34_on_pins: aud-dat-mosi-ch34-on-pins { 797 pins-mosi-on { 798 pinmux = <PINMUX_GPIO196__FUNC_AUD_DAT_MOSI2>; 799 }; 800 }; 801 802 aud_dat_mosi_off_pins: aud-dat-mosi-off-pins { 803 pins-mosi-off { 804 pinmux = <PINMUX_GPIO216__FUNC_GPIO216>, 805 <PINMUX_GPIO217__FUNC_GPIO217>; 806 }; 807 }; 808 809 aud_dat_mosi_on_pins: aud-dat-mosi-on-pins { 810 pins-mosi-on { 811 pinmux = <PINMUX_GPIO216__FUNC_AUD_DAT_MOSI0>, 812 <PINMUX_GPIO217__FUNC_AUD_DAT_MOSI1>; 813 drive-strength = <10>; 814 }; 815 }; 816 817 aud_gpio_i2s3_off_pins: aud-gpio-i2s3-off-pins { 818 pins-i2s3-off { 819 pinmux = <PINMUX_GPIO32__FUNC_GPIO32>, 820 <PINMUX_GPIO33__FUNC_GPIO33>, 821 <PINMUX_GPIO35__FUNC_GPIO35>; 822 }; 823 }; 824 825 aud_gpio_i2s3_on_pins: aud-gpio-i2s3-on-pins { 826 pins-i2s3-on { 827 pinmux = <PINMUX_GPIO32__FUNC_I2S3_BCK>, 828 <PINMUX_GPIO33__FUNC_I2S3_LRCK>, 829 <PINMUX_GPIO35__FUNC_I2S3_DO>; 830 }; 831 }; 832 833 aud_gpio_i2s8_off_pins: aud-gpio-i2s8-off-pins { 834 pins-i2s8-off { 835 pinmux = <PINMUX_GPIO10__FUNC_GPIO10>, 836 <PINMUX_GPIO11__FUNC_GPIO11>, 837 <PINMUX_GPIO12__FUNC_GPIO12>, 838 <PINMUX_GPIO13__FUNC_GPIO13>; 839 }; 840 }; 841 842 aud_gpio_i2s8_on_pins: aud-gpio-i2s8-on-pins { 843 pins-i2s8-on { 844 pinmux = <PINMUX_GPIO10__FUNC_I2S8_MCK>, 845 <PINMUX_GPIO11__FUNC_I2S8_BCK>, 846 <PINMUX_GPIO12__FUNC_I2S8_LRCK>, 847 <PINMUX_GPIO13__FUNC_I2S8_DI>; 848 }; 849 }; 850 851 aud_gpio_i2s9_off_pins: aud-gpio-i2s9-off-pins { 852 pins-i2s9-off { 853 pinmux = <PINMUX_GPIO29__FUNC_GPIO29>; 854 }; 855 }; 856 857 aud_gpio_i2s9_on_pins: aud-gpio-i2s9-on-pins { 858 pins-i2s9-on { 859 pinmux = <PINMUX_GPIO29__FUNC_I2S9_DO>; 860 }; 861 }; 862 863 aud_gpio_tdm_off_pins: aud-gpio-tdm-off-pins { 864 pins-tdm-off { 865 pinmux = <PINMUX_GPIO0__FUNC_GPIO0>, 866 <PINMUX_GPIO1__FUNC_GPIO1>, 867 <PINMUX_GPIO2__FUNC_GPIO2>, 868 <PINMUX_GPIO3__FUNC_GPIO3>; 869 }; 870 }; 871 872 aud_gpio_tdm_on_pins: aud-gpio-tdm-on-pins { 873 pins-tdm-on { 874 pinmux = <PINMUX_GPIO0__FUNC_TDM_LRCK>, 875 <PINMUX_GPIO1__FUNC_TDM_BCK>, 876 <PINMUX_GPIO2__FUNC_TDM_MCK>, 877 <PINMUX_GPIO3__FUNC_TDM_DATA0>; 878 }; 879 }; 880 881 aud_nle_mosi_off_pins: aud-nle-mosi-off-pins { 882 pins-nle-mosi-off { 883 pinmux = <PINMUX_GPIO197__FUNC_GPIO197>, 884 <PINMUX_GPIO198__FUNC_GPIO198>; 885 }; 886 }; 887 888 aud_nle_mosi_on_pins: aud-nle-mosi-on-pins { 889 pins-nle-mosi-on { 890 pinmux = <PINMUX_GPIO197__FUNC_AUD_NLE_MOSI1>, 891 <PINMUX_GPIO198__FUNC_AUD_NLE_MOSI0>; 892 }; 893 }; 894 895 cr50_int: cr50-irq-default-pins { 896 pins-gsc-ap-int-odl { 897 pinmux = <PINMUX_GPIO171__FUNC_GPIO171>; 898 input-enable; 899 }; 900 }; 901 902 cros_ec_int: cros-ec-irq-default-pins { 903 pins-ec-ap-int-odl { 904 pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; 905 input-enable; 906 bias-pull-up; 907 }; 908 }; 909 910 i2c0_pins: i2c0-default-pins { 911 pins-bus { 912 pinmux = <PINMUX_GPIO204__FUNC_SCL0>, 913 <PINMUX_GPIO205__FUNC_SDA0>; 914 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 915 drive-strength-microamp = <1000>; 916 }; 917 }; 918 919 i2c1_pins: i2c1-default-pins { 920 pins-bus { 921 pinmux = <PINMUX_GPIO118__FUNC_SCL1>, 922 <PINMUX_GPIO119__FUNC_SDA1>; 923 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 924 drive-strength-microamp = <1000>; 925 }; 926 }; 927 928 i2c2_pins: i2c2-default-pins { 929 pins-bus { 930 pinmux = <PINMUX_GPIO141__FUNC_SCL2>, 931 <PINMUX_GPIO142__FUNC_SDA2>; 932 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 933 }; 934 }; 935 936 i2c3_pins: i2c3-default-pins { 937 pins-bus { 938 pinmux = <PINMUX_GPIO160__FUNC_SCL3>, 939 <PINMUX_GPIO161__FUNC_SDA3>; 940 bias-disable; 941 drive-strength-microamp = <1000>; 942 }; 943 }; 944 945 i2c7_pins: i2c7-default-pins { 946 pins-bus { 947 pinmux = <PINMUX_GPIO124__FUNC_SCL7>, 948 <PINMUX_GPIO125__FUNC_SDA7>; 949 bias-disable; 950 drive-strength-microamp = <1000>; 951 }; 952 }; 953 954 mmc0_default_pins: mmc0-default-pins { 955 pins-cmd-dat { 956 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 957 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 958 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 959 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 960 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 961 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 962 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 963 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 964 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 965 input-enable; 966 drive-strength = <8>; 967 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 968 }; 969 970 pins-clk { 971 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 972 drive-strength = <8>; 973 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 974 }; 975 976 pins-rst { 977 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 978 drive-strength = <8>; 979 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 980 }; 981 }; 982 983 mmc0_uhs_pins: mmc0-uhs-pins { 984 pins-cmd-dat { 985 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 986 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 987 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 988 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 989 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 990 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 991 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 992 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 993 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 994 input-enable; 995 drive-strength = <10>; 996 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 997 }; 998 999 pins-clk { 1000 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 1001 drive-strength = <10>; 1002 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1003 }; 1004 1005 pins-rst { 1006 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 1007 drive-strength = <8>; 1008 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 1009 }; 1010 1011 pins-ds { 1012 pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>; 1013 drive-strength = <10>; 1014 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1015 }; 1016 }; 1017 1018 mmc1_default_pins: mmc1-default-pins { 1019 pins-cmd-dat { 1020 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 1021 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 1022 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 1023 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 1024 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 1025 input-enable; 1026 drive-strength = <8>; 1027 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1028 }; 1029 1030 pins-clk { 1031 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 1032 drive-strength = <8>; 1033 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1034 }; 1035 1036 pins-insert { 1037 pinmux = <PINMUX_GPIO17__FUNC_GPIO17>; 1038 input-enable; 1039 bias-pull-up; 1040 }; 1041 }; 1042 1043 mmc1_uhs_pins: mmc1-uhs-pins { 1044 pins-cmd-dat { 1045 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 1046 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 1047 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 1048 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 1049 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 1050 input-enable; 1051 drive-strength = <8>; 1052 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1053 }; 1054 1055 pins-clk { 1056 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 1057 input-enable; 1058 drive-strength = <8>; 1059 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1060 }; 1061 }; 1062 1063 nor_flash_pins: nor-flash-default-pins { 1064 pins-cs-io1 { 1065 pinmux = <PINMUX_GPIO24__FUNC_SPINOR_CS>, 1066 <PINMUX_GPIO28__FUNC_SPINOR_IO1>; 1067 input-enable; 1068 bias-pull-up; 1069 drive-strength = <10>; 1070 }; 1071 1072 pins-io0 { 1073 pinmux = <PINMUX_GPIO27__FUNC_SPINOR_IO0>; 1074 bias-pull-up; 1075 drive-strength = <10>; 1076 }; 1077 1078 pins-clk { 1079 pinmux = <PINMUX_GPIO25__FUNC_SPINOR_CK>; 1080 input-enable; 1081 bias-pull-up; 1082 drive-strength = <10>; 1083 }; 1084 }; 1085 1086 pcie_pins: pcie-default-pins { 1087 pins-pcie-wake { 1088 pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>; 1089 bias-pull-up; 1090 }; 1091 1092 pins-pcie-pereset { 1093 pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>; 1094 }; 1095 1096 pins-pcie-clkreq { 1097 pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>; 1098 bias-pull-up; 1099 }; 1100 1101 pins-wifi-kill { 1102 pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */ 1103 output-high; 1104 }; 1105 }; 1106 1107 pp1000_dpbrdg_en_pins: pp1000-dpbrdg-en-pins { 1108 pins-en { 1109 pinmux = <PINMUX_GPIO19__FUNC_GPIO19>; 1110 output-low; 1111 }; 1112 }; 1113 1114 pp1000_mipibrdg_en_pins: pp1000-mipibrdg-en-pins { 1115 pins-en { 1116 pinmux = <PINMUX_GPIO129__FUNC_GPIO129>; 1117 output-low; 1118 }; 1119 }; 1120 1121 pp1800_dpbrdg_en_pins: pp1800-dpbrdg-en-pins { 1122 pins-en { 1123 pinmux = <PINMUX_GPIO126__FUNC_GPIO126>; 1124 output-low; 1125 }; 1126 }; 1127 1128 pp1800_mipibrdg_en_pins: pp1800-mipibrd-en-pins { 1129 pins-en { 1130 pinmux = <PINMUX_GPIO128__FUNC_GPIO128>; 1131 output-low; 1132 }; 1133 }; 1134 1135 pp3300_dpbrdg_en_pins: pp3300-dpbrdg-en-pins { 1136 pins-en { 1137 pinmux = <PINMUX_GPIO26__FUNC_GPIO26>; 1138 output-low; 1139 }; 1140 }; 1141 1142 pp3300_mipibrdg_en_pins: pp3300-mipibrdg-en-pins { 1143 pins-en { 1144 pinmux = <PINMUX_GPIO127__FUNC_GPIO127>; 1145 output-low; 1146 }; 1147 }; 1148 1149 pp3300_wlan_pins: pp3300-wlan-pins { 1150 pins-pcie-en-pp3300-wlan { 1151 pinmux = <PINMUX_GPIO143__FUNC_GPIO143>; 1152 output-high; 1153 }; 1154 }; 1155 1156 pwm0_pins: pwm0-default-pins { 1157 pins-pwm { 1158 pinmux = <PINMUX_GPIO40__FUNC_DISP_PWM>; 1159 }; 1160 1161 pins-inhibit { 1162 pinmux = <PINMUX_GPIO152__FUNC_GPIO152>; 1163 output-high; 1164 }; 1165 }; 1166 1167 scp_pins: scp-pins { 1168 pins-vreq-vao { 1169 pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>; 1170 }; 1171 }; 1172 1173 spi1_pins: spi1-default-pins { 1174 pins-cs-mosi-clk { 1175 pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, 1176 <PINMUX_GPIO159__FUNC_SPI1_A_MO>, 1177 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; 1178 bias-disable; 1179 }; 1180 1181 pins-miso { 1182 pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; 1183 bias-pull-down; 1184 }; 1185 }; 1186 1187 spi5_pins: spi5-default-pins { 1188 pins-bus { 1189 pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>, 1190 <PINMUX_GPIO37__FUNC_GPIO37>, 1191 <PINMUX_GPIO39__FUNC_SPI5_A_MO>, 1192 <PINMUX_GPIO36__FUNC_SPI5_A_CLK>; 1193 bias-disable; 1194 }; 1195 }; 1196 1197 trackpad_pins: trackpad-default-pins { 1198 pins-int-n { 1199 pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; 1200 input-enable; 1201 bias-pull-up = <MTK_PUPD_SET_R1R0_11>; 1202 }; 1203 }; 1204 1205 touchscreen_pins: touchscreen-default-pins { 1206 pins-irq { 1207 pinmux = <PINMUX_GPIO21__FUNC_GPIO21>; 1208 input-enable; 1209 bias-pull-up; 1210 }; 1211 1212 pins-reset { 1213 pinmux = <PINMUX_GPIO137__FUNC_GPIO137>; 1214 output-high; 1215 }; 1216 1217 pins-report-sw { 1218 pinmux = <PINMUX_GPIO138__FUNC_GPIO138>; 1219 output-low; 1220 }; 1221 }; 1222 1223 vow_clk_miso_off_pins: vow-clk-miso-off-pins { 1224 pins-miso-off { 1225 pinmux = <PINMUX_GPIO219__FUNC_GPIO219>; 1226 }; 1227 }; 1228 1229 vow_clk_miso_on_pins: vow-clk-miso-on-pins { 1230 pins-miso-on { 1231 pinmux = <PINMUX_GPIO219__FUNC_VOW_CLK_MISO>; 1232 }; 1233 }; 1234 1235 vow_dat_miso_off_pins: vow-dat-miso-off-pins { 1236 pins-miso-off { 1237 pinmux = <PINMUX_GPIO218__FUNC_GPIO218>; 1238 }; 1239 }; 1240 1241 vow_dat_miso_on_pins: vow-dat-miso-on-pins { 1242 pins-miso-on { 1243 pinmux = <PINMUX_GPIO218__FUNC_VOW_DAT_MISO>; 1244 }; 1245 }; 1246}; 1247 1248&pmic { 1249 interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>; 1250}; 1251 1252&pwm0 { 1253 status = "okay"; 1254 1255 pinctrl-names = "default"; 1256 pinctrl-0 = <&pwm0_pins>; 1257}; 1258 1259&scp { 1260 status = "okay"; 1261 1262 firmware-name = "mediatek/mt8192/scp.img"; 1263 memory-region = <&scp_mem_reserved>; 1264 pinctrl-names = "default"; 1265 pinctrl-0 = <&scp_pins>; 1266 1267 cros-ec { 1268 compatible = "google,cros-ec-rpmsg"; 1269 mediatek,rpmsg-name = "cros-ec-rpmsg"; 1270 }; 1271}; 1272 1273&spi1 { 1274 status = "okay"; 1275 1276 mediatek,pad-select = <0>; 1277 pinctrl-names = "default"; 1278 pinctrl-0 = <&spi1_pins>; 1279 1280 cros_ec: ec@0 { 1281 compatible = "google,cros-ec-spi"; 1282 reg = <0>; 1283 interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; 1284 spi-max-frequency = <3000000>; 1285 pinctrl-names = "default"; 1286 pinctrl-0 = <&cros_ec_int>; 1287 1288 #address-cells = <1>; 1289 #size-cells = <0>; 1290 1291 base_detection: cbas { 1292 compatible = "google,cros-cbas"; 1293 }; 1294 1295 cros_ec_pwm: pwm { 1296 compatible = "google,cros-ec-pwm"; 1297 #pwm-cells = <1>; 1298 1299 status = "disabled"; 1300 }; 1301 1302 i2c_tunnel: i2c-tunnel { 1303 compatible = "google,cros-ec-i2c-tunnel"; 1304 google,remote-bus = <0>; 1305 #address-cells = <1>; 1306 #size-cells = <0>; 1307 }; 1308 1309 mt6360_ldo3_reg: regulator@0 { 1310 compatible = "google,cros-ec-regulator"; 1311 reg = <0>; 1312 regulator-min-microvolt = <1800000>; 1313 regulator-max-microvolt = <3300000>; 1314 }; 1315 1316 mt6360_ldo5_reg: regulator@1 { 1317 compatible = "google,cros-ec-regulator"; 1318 reg = <1>; 1319 regulator-min-microvolt = <3300000>; 1320 regulator-max-microvolt = <3300000>; 1321 }; 1322 1323 typec { 1324 compatible = "google,cros-ec-typec"; 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 1328 usb_c0: connector@0 { 1329 compatible = "usb-c-connector"; 1330 reg = <0>; 1331 label = "left"; 1332 power-role = "dual"; 1333 data-role = "host"; 1334 try-power-role = "source"; 1335 }; 1336 1337 usb_c1: connector@1 { 1338 compatible = "usb-c-connector"; 1339 reg = <1>; 1340 label = "right"; 1341 power-role = "dual"; 1342 data-role = "host"; 1343 try-power-role = "source"; 1344 }; 1345 }; 1346 }; 1347}; 1348 1349&spi5 { 1350 status = "okay"; 1351 1352 cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>; 1353 mediatek,pad-select = <0>; 1354 pinctrl-names = "default"; 1355 pinctrl-0 = <&spi5_pins>; 1356 1357 cr50@0 { 1358 compatible = "google,cr50"; 1359 reg = <0>; 1360 interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>; 1361 spi-max-frequency = <1000000>; 1362 pinctrl-names = "default"; 1363 pinctrl-0 = <&cr50_int>; 1364 }; 1365}; 1366 1367&spmi { 1368 #address-cells = <2>; 1369 #size-cells = <0>; 1370 1371 mt6315_6: pmic@6 { 1372 compatible = "mediatek,mt6315-regulator"; 1373 reg = <0x6 SPMI_USID>; 1374 1375 regulators { 1376 mt6315_6_vbuck1: vbuck1 { 1377 regulator-compatible = "vbuck1"; 1378 regulator-name = "Vbcpu"; 1379 regulator-min-microvolt = <300000>; 1380 regulator-max-microvolt = <1193750>; 1381 regulator-enable-ramp-delay = <256>; 1382 regulator-allowed-modes = <0 1 2>; 1383 regulator-always-on; 1384 }; 1385 1386 mt6315_6_vbuck3: vbuck3 { 1387 regulator-compatible = "vbuck3"; 1388 regulator-name = "Vlcpu"; 1389 regulator-min-microvolt = <300000>; 1390 regulator-max-microvolt = <1193750>; 1391 regulator-enable-ramp-delay = <256>; 1392 regulator-allowed-modes = <0 1 2>; 1393 regulator-always-on; 1394 }; 1395 }; 1396 }; 1397 1398 mt6315_7: pmic@7 { 1399 compatible = "mediatek,mt6315-regulator"; 1400 reg = <0x7 SPMI_USID>; 1401 1402 regulators { 1403 mt6315_7_vbuck1: vbuck1 { 1404 regulator-compatible = "vbuck1"; 1405 regulator-name = "Vgpu"; 1406 regulator-min-microvolt = <606250>; 1407 regulator-max-microvolt = <1193750>; 1408 regulator-enable-ramp-delay = <256>; 1409 regulator-allowed-modes = <0 1 2>; 1410 }; 1411 }; 1412 }; 1413}; 1414 1415&uart0 { 1416 status = "okay"; 1417}; 1418 1419&xhci { 1420 status = "okay"; 1421 1422 wakeup-source; 1423 vusb33-supply = <&pp3300_g>; 1424 vbus-supply = <&pp5000_a>; 1425}; 1426 1427#include <arm/cros-ec-keyboard.dtsi> 1428#include <arm/cros-ec-sbs.dtsi> 1429