1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6/dts-v1/; 7#include "mt8192.dtsi" 8#include "mt6359.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/spmi/spmi.h> 11 12/ { 13 aliases { 14 i2c0 = &i2c0; 15 i2c1 = &i2c1; 16 i2c2 = &i2c2; 17 i2c3 = &i2c3; 18 i2c7 = &i2c7; 19 mmc0 = &mmc0; 20 mmc1 = &mmc1; 21 serial0 = &uart0; 22 }; 23 24 chosen { 25 stdout-path = "serial0:115200n8"; 26 }; 27 28 memory@40000000 { 29 device_type = "memory"; 30 reg = <0 0x40000000 0 0x80000000>; 31 }; 32 33 backlight_lcd0: backlight-lcd0 { 34 compatible = "pwm-backlight"; 35 pwms = <&pwm0 0 500000>; 36 power-supply = <&ppvar_sys>; 37 enable-gpios = <&pio 152 0>; 38 brightness-levels = <0 1023>; 39 num-interpolated-steps = <1023>; 40 default-brightness-level = <576>; 41 }; 42 43 dmic_codec: dmic-codec { 44 compatible = "dmic-codec"; 45 num-channels = <2>; 46 wakeup-delay-ms = <50>; 47 }; 48 49 pp1000_dpbrdg: regulator-1v0-dpbrdg { 50 compatible = "regulator-fixed"; 51 regulator-name = "pp1000_dpbrdg"; 52 pinctrl-names = "default"; 53 pinctrl-0 = <&pp1000_dpbrdg_en_pins>; 54 regulator-min-microvolt = <1000000>; 55 regulator-max-microvolt = <1000000>; 56 enable-active-high; 57 regulator-boot-on; 58 gpio = <&pio 19 GPIO_ACTIVE_HIGH>; 59 vin-supply = <&mt6359_vs2_buck_reg>; 60 }; 61 62 pp1000_mipibrdg: regulator-1v0-mipibrdg { 63 compatible = "regulator-fixed"; 64 regulator-name = "pp1000_mipibrdg"; 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pp1000_mipibrdg_en_pins>; 67 regulator-min-microvolt = <1000000>; 68 regulator-max-microvolt = <1000000>; 69 enable-active-high; 70 regulator-boot-on; 71 gpio = <&pio 129 GPIO_ACTIVE_HIGH>; 72 vin-supply = <&mt6359_vs2_buck_reg>; 73 }; 74 75 pp1800_dpbrdg: regulator-1v8-dpbrdg { 76 compatible = "regulator-fixed"; 77 regulator-name = "pp1800_dpbrdg"; 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pp1800_dpbrdg_en_pins>; 80 enable-active-high; 81 regulator-boot-on; 82 gpio = <&pio 126 GPIO_ACTIVE_HIGH>; 83 vin-supply = <&mt6359_vio18_ldo_reg>; 84 }; 85 86 /* system wide LDO 1.8V power rail */ 87 pp1800_ldo_g: regulator-1v8-g { 88 compatible = "regulator-fixed"; 89 regulator-name = "pp1800_ldo_g"; 90 regulator-always-on; 91 regulator-boot-on; 92 regulator-min-microvolt = <1800000>; 93 regulator-max-microvolt = <1800000>; 94 vin-supply = <&pp3300_g>; 95 }; 96 97 pp1800_mipibrdg: regulator-1v8-mipibrdg { 98 compatible = "regulator-fixed"; 99 regulator-name = "pp1800_mipibrdg"; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&pp1800_mipibrdg_en_pins>; 102 enable-active-high; 103 regulator-boot-on; 104 gpio = <&pio 128 GPIO_ACTIVE_HIGH>; 105 vin-supply = <&mt6359_vio18_ldo_reg>; 106 }; 107 108 pp3300_dpbrdg: regulator-3v3-dpbrdg { 109 compatible = "regulator-fixed"; 110 regulator-name = "pp3300_dpbrdg"; 111 pinctrl-names = "default"; 112 pinctrl-0 = <&pp3300_dpbrdg_en_pins>; 113 enable-active-high; 114 regulator-boot-on; 115 gpio = <&pio 26 GPIO_ACTIVE_HIGH>; 116 vin-supply = <&pp3300_g>; 117 }; 118 119 /* system wide switching 3.3V power rail */ 120 pp3300_g: regulator-3v3-g { 121 compatible = "regulator-fixed"; 122 regulator-name = "pp3300_g"; 123 regulator-always-on; 124 regulator-boot-on; 125 regulator-min-microvolt = <3300000>; 126 regulator-max-microvolt = <3300000>; 127 vin-supply = <&ppvar_sys>; 128 }; 129 130 /* system wide LDO 3.3V power rail */ 131 pp3300_ldo_z: regulator-3v3-z { 132 compatible = "regulator-fixed"; 133 regulator-name = "pp3300_ldo_z"; 134 regulator-always-on; 135 regulator-boot-on; 136 regulator-min-microvolt = <3300000>; 137 regulator-max-microvolt = <3300000>; 138 vin-supply = <&ppvar_sys>; 139 }; 140 141 pp3300_mipibrdg: regulator-3v3-mipibrdg { 142 compatible = "regulator-fixed"; 143 regulator-name = "pp3300_mipibrdg"; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pp3300_mipibrdg_en_pins>; 146 enable-active-high; 147 regulator-boot-on; 148 gpio = <&pio 127 GPIO_ACTIVE_HIGH>; 149 vin-supply = <&pp3300_g>; 150 }; 151 152 /* separately switched 3.3V power rail */ 153 pp3300_u: regulator-3v3-u { 154 compatible = "regulator-fixed"; 155 regulator-name = "pp3300_u"; 156 regulator-always-on; 157 regulator-boot-on; 158 regulator-min-microvolt = <3300000>; 159 regulator-max-microvolt = <3300000>; 160 /* enable pin wired to GPIO controlled by EC */ 161 vin-supply = <&pp3300_g>; 162 }; 163 164 pp3300_wlan: regulator-3v3-wlan { 165 compatible = "regulator-fixed"; 166 regulator-name = "pp3300_wlan"; 167 regulator-always-on; 168 regulator-boot-on; 169 regulator-min-microvolt = <3300000>; 170 regulator-max-microvolt = <3300000>; 171 pinctrl-names = "default"; 172 pinctrl-0 = <&pp3300_wlan_pins>; 173 enable-active-high; 174 gpio = <&pio 143 GPIO_ACTIVE_HIGH>; 175 }; 176 177 /* system wide switching 5.0V power rail */ 178 pp5000_a: regulator-5v0-a { 179 compatible = "regulator-fixed"; 180 regulator-name = "pp5000_a"; 181 regulator-always-on; 182 regulator-boot-on; 183 regulator-min-microvolt = <5000000>; 184 regulator-max-microvolt = <5000000>; 185 vin-supply = <&ppvar_sys>; 186 }; 187 188 /* system wide semi-regulated power rail from battery or USB */ 189 ppvar_sys: regulator-var-sys { 190 compatible = "regulator-fixed"; 191 regulator-name = "ppvar_sys"; 192 regulator-always-on; 193 regulator-boot-on; 194 }; 195 196 reserved_memory: reserved-memory { 197 #address-cells = <2>; 198 #size-cells = <2>; 199 ranges; 200 201 scp_mem_reserved: scp@50000000 { 202 compatible = "shared-dma-pool"; 203 reg = <0 0x50000000 0 0x2900000>; 204 no-map; 205 }; 206 207 wifi_restricted_dma_region: wifi@c0000000 { 208 compatible = "restricted-dma-pool"; 209 reg = <0 0xc0000000 0 0x4000000>; 210 }; 211 }; 212 213 sound: sound { 214 mediatek,platform = <&afe>; 215 pinctrl-names = "aud_clk_mosi_off", 216 "aud_clk_mosi_on", 217 "aud_dat_mosi_off", 218 "aud_dat_mosi_on", 219 "aud_dat_miso_off", 220 "aud_dat_miso_on", 221 "vow_dat_miso_off", 222 "vow_dat_miso_on", 223 "vow_clk_miso_off", 224 "vow_clk_miso_on", 225 "aud_nle_mosi_off", 226 "aud_nle_mosi_on", 227 "aud_dat_miso2_off", 228 "aud_dat_miso2_on", 229 "aud_gpio_i2s3_off", 230 "aud_gpio_i2s3_on", 231 "aud_gpio_i2s8_off", 232 "aud_gpio_i2s8_on", 233 "aud_gpio_i2s9_off", 234 "aud_gpio_i2s9_on", 235 "aud_dat_mosi_ch34_off", 236 "aud_dat_mosi_ch34_on", 237 "aud_dat_miso_ch34_off", 238 "aud_dat_miso_ch34_on", 239 "aud_gpio_tdm_off", 240 "aud_gpio_tdm_on"; 241 pinctrl-0 = <&aud_clk_mosi_off_pins>; 242 pinctrl-1 = <&aud_clk_mosi_on_pins>; 243 pinctrl-2 = <&aud_dat_mosi_off_pins>; 244 pinctrl-3 = <&aud_dat_mosi_on_pins>; 245 pinctrl-4 = <&aud_dat_miso_off_pins>; 246 pinctrl-5 = <&aud_dat_miso_on_pins>; 247 pinctrl-6 = <&vow_dat_miso_off_pins>; 248 pinctrl-7 = <&vow_dat_miso_on_pins>; 249 pinctrl-8 = <&vow_clk_miso_off_pins>; 250 pinctrl-9 = <&vow_clk_miso_on_pins>; 251 pinctrl-10 = <&aud_nle_mosi_off_pins>; 252 pinctrl-11 = <&aud_nle_mosi_on_pins>; 253 pinctrl-12 = <&aud_dat_miso2_off_pins>; 254 pinctrl-13 = <&aud_dat_miso2_on_pins>; 255 pinctrl-14 = <&aud_gpio_i2s3_off_pins>; 256 pinctrl-15 = <&aud_gpio_i2s3_on_pins>; 257 pinctrl-16 = <&aud_gpio_i2s8_off_pins>; 258 pinctrl-17 = <&aud_gpio_i2s8_on_pins>; 259 pinctrl-18 = <&aud_gpio_i2s9_off_pins>; 260 pinctrl-19 = <&aud_gpio_i2s9_on_pins>; 261 pinctrl-20 = <&aud_dat_mosi_ch34_off_pins>; 262 pinctrl-21 = <&aud_dat_mosi_ch34_on_pins>; 263 pinctrl-22 = <&aud_dat_miso_ch34_off_pins>; 264 pinctrl-23 = <&aud_dat_miso_ch34_on_pins>; 265 pinctrl-24 = <&aud_gpio_tdm_off_pins>; 266 pinctrl-25 = <&aud_gpio_tdm_on_pins>; 267 }; 268}; 269 270&dsi0 { 271 status = "okay"; 272}; 273 274&dsi_out { 275 remote-endpoint = <&anx7625_in>; 276}; 277 278&i2c0 { 279 status = "okay"; 280 281 clock-frequency = <400000>; 282 pinctrl-names = "default"; 283 pinctrl-0 = <&i2c0_pins>; 284 285 touchscreen: touchscreen@10 { 286 reg = <0x10>; 287 interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&touchscreen_pins>; 290 }; 291}; 292 293&i2c1 { 294 status = "okay"; 295 296 clock-frequency = <400000>; 297 pinctrl-names = "default"; 298 pinctrl-0 = <&i2c1_pins>; 299}; 300 301&i2c2 { 302 status = "okay"; 303 304 clock-frequency = <400000>; 305 clock-stretch-ns = <12600>; 306 pinctrl-names = "default"; 307 pinctrl-0 = <&i2c2_pins>; 308 309 trackpad@15 { 310 compatible = "elan,ekth3000"; 311 reg = <0x15>; 312 interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&trackpad_pins>; 315 vcc-supply = <&pp3300_u>; 316 wakeup-source; 317 }; 318}; 319 320&i2c3 { 321 status = "okay"; 322 323 clock-frequency = <400000>; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&i2c3_pins>; 326 327 anx_bridge: anx7625@58 { 328 compatible = "analogix,anx7625"; 329 reg = <0x58>; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&anx7625_pins>; 332 enable-gpios = <&pio 41 GPIO_ACTIVE_HIGH>; 333 reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; 334 vdd10-supply = <&pp1000_mipibrdg>; 335 vdd18-supply = <&pp1800_mipibrdg>; 336 vdd33-supply = <&pp3300_mipibrdg>; 337 338 ports { 339 #address-cells = <1>; 340 #size-cells = <0>; 341 342 port@0 { 343 reg = <0>; 344 345 anx7625_in: endpoint { 346 remote-endpoint = <&dsi_out>; 347 }; 348 }; 349 350 port@1 { 351 reg = <1>; 352 353 anx7625_out: endpoint { 354 remote-endpoint = <&panel_in>; 355 }; 356 }; 357 }; 358 359 aux-bus { 360 panel: panel { 361 compatible = "edp-panel"; 362 power-supply = <&pp3300_mipibrdg>; 363 backlight = <&backlight_lcd0>; 364 365 port { 366 panel_in: endpoint { 367 remote-endpoint = <&anx7625_out>; 368 }; 369 }; 370 }; 371 }; 372 }; 373}; 374 375&i2c7 { 376 status = "okay"; 377 378 clock-frequency = <400000>; 379 pinctrl-names = "default"; 380 pinctrl-0 = <&i2c7_pins>; 381}; 382 383&mfg0 { 384 domain-supply = <&mt6315_7_vbuck1>; 385}; 386 387&mfg1 { 388 domain-supply = <&mt6359_vsram_others_ldo_reg>; 389}; 390 391&mipi_tx0 { 392 status = "okay"; 393}; 394 395&mmc0 { 396 status = "okay"; 397 398 pinctrl-names = "default", "state_uhs"; 399 pinctrl-0 = <&mmc0_default_pins>; 400 pinctrl-1 = <&mmc0_uhs_pins>; 401 bus-width = <8>; 402 max-frequency = <200000000>; 403 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 404 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 405 cap-mmc-highspeed; 406 mmc-hs200-1_8v; 407 mmc-hs400-1_8v; 408 supports-cqe; 409 cap-mmc-hw-reset; 410 mmc-hs400-enhanced-strobe; 411 hs400-ds-delay = <0x12814>; 412 no-sdio; 413 no-sd; 414 non-removable; 415}; 416 417&mmc1 { 418 status = "okay"; 419 420 pinctrl-names = "default", "state_uhs"; 421 pinctrl-0 = <&mmc1_default_pins>; 422 pinctrl-1 = <&mmc1_uhs_pins>; 423 bus-width = <4>; 424 max-frequency = <200000000>; 425 cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>; 426 vmmc-supply = <&mt6360_ldo5_reg>; 427 vqmmc-supply = <&mt6360_ldo3_reg>; 428 cap-sd-highspeed; 429 sd-uhs-sdr50; 430 sd-uhs-sdr104; 431 no-sdio; 432 no-mmc; 433}; 434 435/* for CORE */ 436&mt6359_vgpu11_buck_reg { 437 regulator-always-on; 438}; 439 440&mt6359_vgpu11_sshub_buck_reg { 441 regulator-always-on; 442 regulator-min-microvolt = <575000>; 443 regulator-max-microvolt = <575000>; 444}; 445 446&mt6359_vrf12_ldo_reg { 447 regulator-always-on; 448}; 449 450&mt6359_vufs_ldo_reg { 451 regulator-always-on; 452}; 453 454&mt6359codec { 455 mediatek,dmic-mode = <1>; /* one-wire */ 456 mediatek,mic-type-0 = <2>; /* DMIC */ 457 mediatek,mic-type-2 = <2>; /* DMIC */ 458}; 459 460&nor_flash { 461 status = "okay"; 462 463 pinctrl-names = "default"; 464 pinctrl-0 = <&nor_flash_pins>; 465 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 466 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>; 467 468 flash@0 { 469 compatible = "winbond,w25q64jwm", "jedec,spi-nor"; 470 reg = <0>; 471 spi-max-frequency = <52000000>; 472 spi-rx-bus-width = <2>; 473 spi-tx-bus-width = <2>; 474 }; 475}; 476 477&pcie { 478 pinctrl-names = "default"; 479 pinctrl-0 = <&pcie_pins>; 480 481 pcie0: pcie@0,0 { 482 device_type = "pci"; 483 reg = <0x0000 0 0 0 0>; 484 num-lanes = <1>; 485 bus-range = <0x1 0x1>; 486 487 #address-cells = <3>; 488 #size-cells = <2>; 489 ranges; 490 491 wifi: wifi@0,0 { 492 reg = <0x10000 0 0 0 0x100000>, 493 <0x10000 0 0x100000 0 0x100000>; 494 memory-region = <&wifi_restricted_dma_region>; 495 }; 496 }; 497}; 498 499&pio { 500 /* 220 lines */ 501 gpio-line-names = "I2S_DP_LRCK", 502 "IS_DP_BCLK", 503 "I2S_DP_MCLK", 504 "I2S_DP_DATAOUT", 505 "SAR0_INT_ODL", 506 "EC_AP_INT_ODL", 507 "EDPBRDG_INT_ODL", 508 "DPBRDG_INT_ODL", 509 "DPBRDG_PWREN", 510 "DPBRDG_RST_ODL", 511 "I2S_HP_MCLK", 512 "I2S_HP_BCK", 513 "I2S_HP_LRCK", 514 "I2S_HP_DATAIN", 515 /* 516 * AP_FLASH_WP_L is crossystem ABI. Schematics 517 * call it AP_FLASH_WP_ODL. 518 */ 519 "AP_FLASH_WP_L", 520 "TRACKPAD_INT_ODL", 521 "EC_AP_HPD_OD", 522 "SD_CD_ODL", 523 "HP_INT_ODL_ALC", 524 "EN_PP1000_DPBRDG", 525 "AP_GPIO20", 526 "TOUCH_INT_L_1V8", 527 "UART_BT_WAKE_ODL", 528 "AP_GPIO23", 529 "AP_SPI_FLASH_CS_L", 530 "AP_SPI_FLASH_CLK", 531 "EN_PP3300_DPBRDG_DX", 532 "AP_SPI_FLASH_MOSI", 533 "AP_SPI_FLASH_MISO", 534 "I2S_HP_DATAOUT", 535 "AP_GPIO30", 536 "I2S_SPKR_MCLK", 537 "I2S_SPKR_BCLK", 538 "I2S_SPKR_LRCK", 539 "I2S_SPKR_DATAIN", 540 "I2S_SPKR_DATAOUT", 541 "AP_SPI_H1_TPM_CLK", 542 "AP_SPI_H1_TPM_CS_L", 543 "AP_SPI_H1_TPM_MISO", 544 "AP_SPI_H1_TPM_MOSI", 545 "BL_PWM", 546 "EDPBRDG_PWREN", 547 "EDPBRDG_RST_ODL", 548 "EN_PP3300_HUB", 549 "HUB_RST_L", 550 "", 551 "", 552 "", 553 "", 554 "", 555 "", 556 "SD_CLK", 557 "SD_CMD", 558 "SD_DATA3", 559 "SD_DATA0", 560 "SD_DATA2", 561 "SD_DATA1", 562 "", 563 "", 564 "", 565 "", 566 "", 567 "", 568 "PCIE_WAKE_ODL", 569 "PCIE_RST_L", 570 "PCIE_CLKREQ_ODL", 571 "", 572 "", 573 "", 574 "", 575 "", 576 "", 577 "", 578 "", 579 "", 580 "", 581 "", 582 "", 583 "", 584 "", 585 "", 586 "", 587 "", 588 "", 589 "", 590 "", 591 "", 592 "", 593 "", 594 "SPMI_SCL", 595 "SPMI_SDA", 596 "AP_GOOD", 597 "UART_DBG_TX_AP_RX", 598 "UART_AP_TX_DBG_RX", 599 "UART_AP_TX_BT_RX", 600 "UART_BT_TX_AP_RX", 601 "MIPI_DPI_D0_R", 602 "MIPI_DPI_D1_R", 603 "MIPI_DPI_D2_R", 604 "MIPI_DPI_D3_R", 605 "MIPI_DPI_D4_R", 606 "MIPI_DPI_D5_R", 607 "MIPI_DPI_D6_R", 608 "MIPI_DPI_D7_R", 609 "MIPI_DPI_D8_R", 610 "MIPI_DPI_D9_R", 611 "MIPI_DPI_D10_R", 612 "", 613 "", 614 "MIPI_DPI_DE_R", 615 "MIPI_DPI_D11_R", 616 "MIPI_DPI_VSYNC_R", 617 "MIPI_DPI_CLK_R", 618 "MIPI_DPI_HSYNC_R", 619 "PCM_BT_DATAIN", 620 "PCM_BT_SYNC", 621 "PCM_BT_DATAOUT", 622 "PCM_BT_CLK", 623 "AP_I2C_AUDIO_SCL", 624 "AP_I2C_AUDIO_SDA", 625 "SCP_I2C_SCL", 626 "SCP_I2C_SDA", 627 "AP_I2C_WLAN_SCL", 628 "AP_I2C_WLAN_SDA", 629 "AP_I2C_DPBRDG_SCL", 630 "AP_I2C_DPBRDG_SDA", 631 "EN_PP1800_DPBRDG_DX", 632 "EN_PP3300_EDP_DX", 633 "EN_PP1800_EDPBRDG_DX", 634 "EN_PP1000_EDPBRDG", 635 "SCP_JTAG0_TDO", 636 "SCP_JTAG0_TDI", 637 "SCP_JTAG0_TMS", 638 "SCP_JTAG0_TCK", 639 "SCP_JTAG0_TRSTN", 640 "EN_PP3000_VMC_PMU", 641 "EN_PP3300_DISPLAY_DX", 642 "TOUCH_RST_L_1V8", 643 "TOUCH_REPORT_DISABLE", 644 "", 645 "", 646 "AP_I2C_TRACKPAD_SCL_1V8", 647 "AP_I2C_TRACKPAD_SDA_1V8", 648 "EN_PP3300_WLAN", 649 "BT_KILL_L", 650 "WIFI_KILL_L", 651 "SET_VMC_VOLT_AT_1V8", 652 "EN_SPK", 653 "AP_WARM_RST_REQ", 654 "", 655 "", 656 "EN_PP3000_SD_S3", 657 "AP_EDP_BKLTEN", 658 "", 659 "", 660 "", 661 "AP_SPI_EC_CLK", 662 "AP_SPI_EC_CS_L", 663 "AP_SPI_EC_MISO", 664 "AP_SPI_EC_MOSI", 665 "AP_I2C_EDPBRDG_SCL", 666 "AP_I2C_EDPBRDG_SDA", 667 "MT6315_PROC_INT", 668 "MT6315_GPU_INT", 669 "UART_SERVO_TX_SCP_RX", 670 "UART_SCP_TX_SERVO_RX", 671 "BT_RTS_AP_CTS", 672 "AP_RTS_BT_CTS", 673 "UART_AP_WAKE_BT_ODL", 674 "WLAN_ALERT_ODL", 675 "EC_IN_RW_ODL", 676 "H1_AP_INT_ODL", 677 "", 678 "", 679 "", 680 "", 681 "", 682 "", 683 "", 684 "", 685 "", 686 "", 687 "", 688 "MSDC0_CMD", 689 "MSDC0_DAT0", 690 "MSDC0_DAT2", 691 "MSDC0_DAT4", 692 "MSDC0_DAT6", 693 "MSDC0_DAT1", 694 "MSDC0_DAT5", 695 "MSDC0_DAT7", 696 "MSDC0_DSL", 697 "MSDC0_CLK", 698 "MSDC0_DAT3", 699 "MSDC0_RST_L", 700 "SCP_VREQ_VAO", 701 "AUD_DAT_MOSI2", 702 "AUD_NLE_MOSI1", 703 "AUD_NLE_MOSI0", 704 "AUD_DAT_MISO2", 705 "AP_I2C_SAR_SDA", 706 "AP_I2C_SAR_SCL", 707 "AP_I2C_PWR_SCL", 708 "AP_I2C_PWR_SDA", 709 "AP_I2C_TS_SCL_1V8", 710 "AP_I2C_TS_SDA_1V8", 711 "SRCLKENA0", 712 "SRCLKENA1", 713 "AP_EC_WATCHDOG_L", 714 "PWRAP_SPI0_MI", 715 "PWRAP_SPI0_CSN", 716 "PWRAP_SPI0_MO", 717 "PWRAP_SPI0_CK", 718 "AP_RTC_CLK32K", 719 "AUD_CLK_MOSI", 720 "AUD_SYNC_MOSI", 721 "AUD_DAT_MOSI0", 722 "AUD_DAT_MOSI1", 723 "AUD_DAT_MISO0", 724 "AUD_DAT_MISO1"; 725 726 anx7625_pins: anx7625-default-pins { 727 pins-out { 728 pinmux = <PINMUX_GPIO41__FUNC_GPIO41>, 729 <PINMUX_GPIO42__FUNC_GPIO42>; 730 output-low; 731 }; 732 733 pins-in { 734 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 735 input-enable; 736 bias-pull-up; 737 }; 738 }; 739 740 aud_clk_mosi_off_pins: aud-clk-mosi-off-pins { 741 pins-mosi-off { 742 pinmux = <PINMUX_GPIO214__FUNC_GPIO214>, 743 <PINMUX_GPIO215__FUNC_GPIO215>; 744 }; 745 }; 746 747 aud_clk_mosi_on_pins: aud-clk-mosi-on-pins { 748 pins-mosi-on { 749 pinmux = <PINMUX_GPIO214__FUNC_AUD_CLK_MOSI>, 750 <PINMUX_GPIO215__FUNC_AUD_SYNC_MOSI>; 751 drive-strength = <10>; 752 }; 753 }; 754 755 aud_dat_miso_ch34_off_pins: aud-dat-miso-ch34-off-pins { 756 pins-miso-off { 757 pinmux = <PINMUX_GPIO199__FUNC_GPIO199>; 758 }; 759 }; 760 761 aud_dat_miso_ch34_on_pins: aud-dat-miso-ch34-on-pins { 762 pins-miso-on { 763 pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>; 764 }; 765 }; 766 767 aud_dat_miso_off_pins: aud-dat-miso-off-pins { 768 pins-miso-off { 769 pinmux = <PINMUX_GPIO218__FUNC_GPIO218>, 770 <PINMUX_GPIO219__FUNC_GPIO219>; 771 }; 772 }; 773 774 aud_dat_miso_on_pins: aud-dat-miso-on-pins { 775 pins-miso-on { 776 pinmux = <PINMUX_GPIO218__FUNC_AUD_DAT_MISO0>, 777 <PINMUX_GPIO219__FUNC_AUD_DAT_MISO1>; 778 drive-strength = <10>; 779 }; 780 }; 781 782 aud_dat_miso2_off_pins: aud-dat-miso2-off-pins { 783 pins-miso-off { 784 pinmux = <PINMUX_GPIO199__FUNC_GPIO199>; 785 }; 786 }; 787 788 aud_dat_miso2_on_pins: aud-dat-miso2-on-pins { 789 pins-miso-on { 790 pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>; 791 }; 792 }; 793 794 aud_dat_mosi_ch34_off_pins: aud-dat-mosi-ch34-off-pins { 795 pins-mosi-off { 796 pinmux = <PINMUX_GPIO196__FUNC_GPIO196>; 797 }; 798 }; 799 800 aud_dat_mosi_ch34_on_pins: aud-dat-mosi-ch34-on-pins { 801 pins-mosi-on { 802 pinmux = <PINMUX_GPIO196__FUNC_AUD_DAT_MOSI2>; 803 }; 804 }; 805 806 aud_dat_mosi_off_pins: aud-dat-mosi-off-pins { 807 pins-mosi-off { 808 pinmux = <PINMUX_GPIO216__FUNC_GPIO216>, 809 <PINMUX_GPIO217__FUNC_GPIO217>; 810 }; 811 }; 812 813 aud_dat_mosi_on_pins: aud-dat-mosi-on-pins { 814 pins-mosi-on { 815 pinmux = <PINMUX_GPIO216__FUNC_AUD_DAT_MOSI0>, 816 <PINMUX_GPIO217__FUNC_AUD_DAT_MOSI1>; 817 drive-strength = <10>; 818 }; 819 }; 820 821 aud_gpio_i2s3_off_pins: aud-gpio-i2s3-off-pins { 822 pins-i2s3-off { 823 pinmux = <PINMUX_GPIO32__FUNC_GPIO32>, 824 <PINMUX_GPIO33__FUNC_GPIO33>, 825 <PINMUX_GPIO35__FUNC_GPIO35>; 826 }; 827 }; 828 829 aud_gpio_i2s3_on_pins: aud-gpio-i2s3-on-pins { 830 pins-i2s3-on { 831 pinmux = <PINMUX_GPIO32__FUNC_I2S3_BCK>, 832 <PINMUX_GPIO33__FUNC_I2S3_LRCK>, 833 <PINMUX_GPIO35__FUNC_I2S3_DO>; 834 }; 835 }; 836 837 aud_gpio_i2s8_off_pins: aud-gpio-i2s8-off-pins { 838 pins-i2s8-off { 839 pinmux = <PINMUX_GPIO10__FUNC_GPIO10>, 840 <PINMUX_GPIO11__FUNC_GPIO11>, 841 <PINMUX_GPIO12__FUNC_GPIO12>, 842 <PINMUX_GPIO13__FUNC_GPIO13>; 843 }; 844 }; 845 846 aud_gpio_i2s8_on_pins: aud-gpio-i2s8-on-pins { 847 pins-i2s8-on { 848 pinmux = <PINMUX_GPIO10__FUNC_I2S8_MCK>, 849 <PINMUX_GPIO11__FUNC_I2S8_BCK>, 850 <PINMUX_GPIO12__FUNC_I2S8_LRCK>, 851 <PINMUX_GPIO13__FUNC_I2S8_DI>; 852 }; 853 }; 854 855 aud_gpio_i2s9_off_pins: aud-gpio-i2s9-off-pins { 856 pins-i2s9-off { 857 pinmux = <PINMUX_GPIO29__FUNC_GPIO29>; 858 }; 859 }; 860 861 aud_gpio_i2s9_on_pins: aud-gpio-i2s9-on-pins { 862 pins-i2s9-on { 863 pinmux = <PINMUX_GPIO29__FUNC_I2S9_DO>; 864 }; 865 }; 866 867 aud_gpio_tdm_off_pins: aud-gpio-tdm-off-pins { 868 pins-tdm-off { 869 pinmux = <PINMUX_GPIO0__FUNC_GPIO0>, 870 <PINMUX_GPIO1__FUNC_GPIO1>, 871 <PINMUX_GPIO2__FUNC_GPIO2>, 872 <PINMUX_GPIO3__FUNC_GPIO3>; 873 }; 874 }; 875 876 aud_gpio_tdm_on_pins: aud-gpio-tdm-on-pins { 877 pins-tdm-on { 878 pinmux = <PINMUX_GPIO0__FUNC_TDM_LRCK>, 879 <PINMUX_GPIO1__FUNC_TDM_BCK>, 880 <PINMUX_GPIO2__FUNC_TDM_MCK>, 881 <PINMUX_GPIO3__FUNC_TDM_DATA0>; 882 }; 883 }; 884 885 aud_nle_mosi_off_pins: aud-nle-mosi-off-pins { 886 pins-nle-mosi-off { 887 pinmux = <PINMUX_GPIO197__FUNC_GPIO197>, 888 <PINMUX_GPIO198__FUNC_GPIO198>; 889 }; 890 }; 891 892 aud_nle_mosi_on_pins: aud-nle-mosi-on-pins { 893 pins-nle-mosi-on { 894 pinmux = <PINMUX_GPIO197__FUNC_AUD_NLE_MOSI1>, 895 <PINMUX_GPIO198__FUNC_AUD_NLE_MOSI0>; 896 }; 897 }; 898 899 cr50_int: cr50-irq-default-pins { 900 pins-gsc-ap-int-odl { 901 pinmux = <PINMUX_GPIO171__FUNC_GPIO171>; 902 input-enable; 903 }; 904 }; 905 906 cros_ec_int: cros-ec-irq-default-pins { 907 pins-ec-ap-int-odl { 908 pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; 909 input-enable; 910 bias-pull-up; 911 }; 912 }; 913 914 i2c0_pins: i2c0-default-pins { 915 pins-bus { 916 pinmux = <PINMUX_GPIO204__FUNC_SCL0>, 917 <PINMUX_GPIO205__FUNC_SDA0>; 918 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 919 drive-strength-microamp = <1000>; 920 }; 921 }; 922 923 i2c1_pins: i2c1-default-pins { 924 pins-bus { 925 pinmux = <PINMUX_GPIO118__FUNC_SCL1>, 926 <PINMUX_GPIO119__FUNC_SDA1>; 927 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 928 drive-strength-microamp = <1000>; 929 }; 930 }; 931 932 i2c2_pins: i2c2-default-pins { 933 pins-bus { 934 pinmux = <PINMUX_GPIO141__FUNC_SCL2>, 935 <PINMUX_GPIO142__FUNC_SDA2>; 936 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 937 }; 938 }; 939 940 i2c3_pins: i2c3-default-pins { 941 pins-bus { 942 pinmux = <PINMUX_GPIO160__FUNC_SCL3>, 943 <PINMUX_GPIO161__FUNC_SDA3>; 944 bias-disable; 945 drive-strength-microamp = <1000>; 946 }; 947 }; 948 949 i2c7_pins: i2c7-default-pins { 950 pins-bus { 951 pinmux = <PINMUX_GPIO124__FUNC_SCL7>, 952 <PINMUX_GPIO125__FUNC_SDA7>; 953 bias-disable; 954 drive-strength-microamp = <1000>; 955 }; 956 }; 957 958 mmc0_default_pins: mmc0-default-pins { 959 pins-cmd-dat { 960 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 961 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 962 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 963 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 964 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 965 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 966 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 967 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 968 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 969 input-enable; 970 drive-strength = <8>; 971 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 972 }; 973 974 pins-clk { 975 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 976 drive-strength = <8>; 977 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 978 }; 979 980 pins-rst { 981 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 982 drive-strength = <8>; 983 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 984 }; 985 }; 986 987 mmc0_uhs_pins: mmc0-uhs-pins { 988 pins-cmd-dat { 989 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 990 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 991 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 992 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 993 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 994 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 995 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 996 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 997 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 998 input-enable; 999 drive-strength = <10>; 1000 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1001 }; 1002 1003 pins-clk { 1004 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 1005 drive-strength = <10>; 1006 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1007 }; 1008 1009 pins-rst { 1010 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 1011 drive-strength = <8>; 1012 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 1013 }; 1014 1015 pins-ds { 1016 pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>; 1017 drive-strength = <10>; 1018 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1019 }; 1020 }; 1021 1022 mmc1_default_pins: mmc1-default-pins { 1023 pins-cmd-dat { 1024 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 1025 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 1026 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 1027 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 1028 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 1029 input-enable; 1030 drive-strength = <8>; 1031 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1032 }; 1033 1034 pins-clk { 1035 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 1036 drive-strength = <8>; 1037 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1038 }; 1039 1040 pins-insert { 1041 pinmux = <PINMUX_GPIO17__FUNC_GPIO17>; 1042 input-enable; 1043 bias-pull-up; 1044 }; 1045 }; 1046 1047 mmc1_uhs_pins: mmc1-uhs-pins { 1048 pins-cmd-dat { 1049 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 1050 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 1051 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 1052 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 1053 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 1054 input-enable; 1055 drive-strength = <8>; 1056 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1057 }; 1058 1059 pins-clk { 1060 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 1061 input-enable; 1062 drive-strength = <8>; 1063 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1064 }; 1065 }; 1066 1067 nor_flash_pins: nor-flash-default-pins { 1068 pins-cs-io1 { 1069 pinmux = <PINMUX_GPIO24__FUNC_SPINOR_CS>, 1070 <PINMUX_GPIO28__FUNC_SPINOR_IO1>; 1071 input-enable; 1072 bias-pull-up; 1073 drive-strength = <10>; 1074 }; 1075 1076 pins-io0 { 1077 pinmux = <PINMUX_GPIO27__FUNC_SPINOR_IO0>; 1078 bias-pull-up; 1079 drive-strength = <10>; 1080 }; 1081 1082 pins-clk { 1083 pinmux = <PINMUX_GPIO25__FUNC_SPINOR_CK>; 1084 input-enable; 1085 bias-pull-up; 1086 drive-strength = <10>; 1087 }; 1088 }; 1089 1090 pcie_pins: pcie-default-pins { 1091 pins-pcie-wake { 1092 pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>; 1093 bias-pull-up; 1094 }; 1095 1096 pins-pcie-pereset { 1097 pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>; 1098 }; 1099 1100 pins-pcie-clkreq { 1101 pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>; 1102 bias-pull-up; 1103 }; 1104 1105 pins-wifi-kill { 1106 pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */ 1107 output-high; 1108 }; 1109 }; 1110 1111 pp1000_dpbrdg_en_pins: pp1000-dpbrdg-en-pins { 1112 pins-en { 1113 pinmux = <PINMUX_GPIO19__FUNC_GPIO19>; 1114 output-low; 1115 }; 1116 }; 1117 1118 pp1000_mipibrdg_en_pins: pp1000-mipibrdg-en-pins { 1119 pins-en { 1120 pinmux = <PINMUX_GPIO129__FUNC_GPIO129>; 1121 output-low; 1122 }; 1123 }; 1124 1125 pp1800_dpbrdg_en_pins: pp1800-dpbrdg-en-pins { 1126 pins-en { 1127 pinmux = <PINMUX_GPIO126__FUNC_GPIO126>; 1128 output-low; 1129 }; 1130 }; 1131 1132 pp1800_mipibrdg_en_pins: pp1800-mipibrd-en-pins { 1133 pins-en { 1134 pinmux = <PINMUX_GPIO128__FUNC_GPIO128>; 1135 output-low; 1136 }; 1137 }; 1138 1139 pp3300_dpbrdg_en_pins: pp3300-dpbrdg-en-pins { 1140 pins-en { 1141 pinmux = <PINMUX_GPIO26__FUNC_GPIO26>; 1142 output-low; 1143 }; 1144 }; 1145 1146 pp3300_mipibrdg_en_pins: pp3300-mipibrdg-en-pins { 1147 pins-en { 1148 pinmux = <PINMUX_GPIO127__FUNC_GPIO127>; 1149 output-low; 1150 }; 1151 }; 1152 1153 pp3300_wlan_pins: pp3300-wlan-pins { 1154 pins-pcie-en-pp3300-wlan { 1155 pinmux = <PINMUX_GPIO143__FUNC_GPIO143>; 1156 output-high; 1157 }; 1158 }; 1159 1160 pwm0_pins: pwm0-default-pins { 1161 pins-pwm { 1162 pinmux = <PINMUX_GPIO40__FUNC_DISP_PWM>; 1163 }; 1164 1165 pins-inhibit { 1166 pinmux = <PINMUX_GPIO152__FUNC_GPIO152>; 1167 output-high; 1168 }; 1169 }; 1170 1171 scp_pins: scp-pins { 1172 pins-vreq-vao { 1173 pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>; 1174 }; 1175 }; 1176 1177 spi1_pins: spi1-default-pins { 1178 pins-cs-mosi-clk { 1179 pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, 1180 <PINMUX_GPIO159__FUNC_SPI1_A_MO>, 1181 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; 1182 bias-disable; 1183 }; 1184 1185 pins-miso { 1186 pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; 1187 bias-pull-down; 1188 }; 1189 }; 1190 1191 spi5_pins: spi5-default-pins { 1192 pins-bus { 1193 pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>, 1194 <PINMUX_GPIO37__FUNC_GPIO37>, 1195 <PINMUX_GPIO39__FUNC_SPI5_A_MO>, 1196 <PINMUX_GPIO36__FUNC_SPI5_A_CLK>; 1197 bias-disable; 1198 }; 1199 }; 1200 1201 trackpad_pins: trackpad-default-pins { 1202 pins-int-n { 1203 pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; 1204 input-enable; 1205 bias-pull-up = <MTK_PUPD_SET_R1R0_11>; 1206 }; 1207 }; 1208 1209 touchscreen_pins: touchscreen-default-pins { 1210 pins-irq { 1211 pinmux = <PINMUX_GPIO21__FUNC_GPIO21>; 1212 input-enable; 1213 bias-pull-up; 1214 }; 1215 1216 pins-reset { 1217 pinmux = <PINMUX_GPIO137__FUNC_GPIO137>; 1218 output-high; 1219 }; 1220 1221 pins-report-sw { 1222 pinmux = <PINMUX_GPIO138__FUNC_GPIO138>; 1223 output-low; 1224 }; 1225 }; 1226 1227 vow_clk_miso_off_pins: vow-clk-miso-off-pins { 1228 pins-miso-off { 1229 pinmux = <PINMUX_GPIO219__FUNC_GPIO219>; 1230 }; 1231 }; 1232 1233 vow_clk_miso_on_pins: vow-clk-miso-on-pins { 1234 pins-miso-on { 1235 pinmux = <PINMUX_GPIO219__FUNC_VOW_CLK_MISO>; 1236 }; 1237 }; 1238 1239 vow_dat_miso_off_pins: vow-dat-miso-off-pins { 1240 pins-miso-off { 1241 pinmux = <PINMUX_GPIO218__FUNC_GPIO218>; 1242 }; 1243 }; 1244 1245 vow_dat_miso_on_pins: vow-dat-miso-on-pins { 1246 pins-miso-on { 1247 pinmux = <PINMUX_GPIO218__FUNC_VOW_DAT_MISO>; 1248 }; 1249 }; 1250}; 1251 1252&pmic { 1253 interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>; 1254}; 1255 1256&pwm0 { 1257 status = "okay"; 1258 1259 pinctrl-names = "default"; 1260 pinctrl-0 = <&pwm0_pins>; 1261}; 1262 1263&scp { 1264 status = "okay"; 1265 1266 firmware-name = "mediatek/mt8192/scp.img"; 1267 memory-region = <&scp_mem_reserved>; 1268 pinctrl-names = "default"; 1269 pinctrl-0 = <&scp_pins>; 1270 1271 cros-ec { 1272 compatible = "google,cros-ec-rpmsg"; 1273 mediatek,rpmsg-name = "cros-ec-rpmsg"; 1274 }; 1275}; 1276 1277&spi1 { 1278 status = "okay"; 1279 1280 mediatek,pad-select = <0>; 1281 pinctrl-names = "default"; 1282 pinctrl-0 = <&spi1_pins>; 1283 1284 cros_ec: ec@0 { 1285 compatible = "google,cros-ec-spi"; 1286 reg = <0>; 1287 interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; 1288 spi-max-frequency = <3000000>; 1289 pinctrl-names = "default"; 1290 pinctrl-0 = <&cros_ec_int>; 1291 1292 #address-cells = <1>; 1293 #size-cells = <0>; 1294 1295 base_detection: cbas { 1296 compatible = "google,cros-cbas"; 1297 }; 1298 1299 cros_ec_pwm: pwm { 1300 compatible = "google,cros-ec-pwm"; 1301 #pwm-cells = <1>; 1302 1303 status = "disabled"; 1304 }; 1305 1306 i2c_tunnel: i2c-tunnel { 1307 compatible = "google,cros-ec-i2c-tunnel"; 1308 google,remote-bus = <0>; 1309 #address-cells = <1>; 1310 #size-cells = <0>; 1311 }; 1312 1313 mt6360_ldo3_reg: regulator@0 { 1314 compatible = "google,cros-ec-regulator"; 1315 reg = <0>; 1316 regulator-min-microvolt = <1800000>; 1317 regulator-max-microvolt = <3300000>; 1318 }; 1319 1320 mt6360_ldo5_reg: regulator@1 { 1321 compatible = "google,cros-ec-regulator"; 1322 reg = <1>; 1323 regulator-min-microvolt = <3300000>; 1324 regulator-max-microvolt = <3300000>; 1325 }; 1326 1327 typec { 1328 compatible = "google,cros-ec-typec"; 1329 #address-cells = <1>; 1330 #size-cells = <0>; 1331 1332 usb_c0: connector@0 { 1333 compatible = "usb-c-connector"; 1334 reg = <0>; 1335 label = "left"; 1336 power-role = "dual"; 1337 data-role = "host"; 1338 try-power-role = "source"; 1339 }; 1340 1341 usb_c1: connector@1 { 1342 compatible = "usb-c-connector"; 1343 reg = <1>; 1344 label = "right"; 1345 power-role = "dual"; 1346 data-role = "host"; 1347 try-power-role = "source"; 1348 }; 1349 }; 1350 }; 1351}; 1352 1353&spi5 { 1354 status = "okay"; 1355 1356 cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>; 1357 mediatek,pad-select = <0>; 1358 pinctrl-names = "default"; 1359 pinctrl-0 = <&spi5_pins>; 1360 1361 cr50@0 { 1362 compatible = "google,cr50"; 1363 reg = <0>; 1364 interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>; 1365 spi-max-frequency = <1000000>; 1366 pinctrl-names = "default"; 1367 pinctrl-0 = <&cr50_int>; 1368 }; 1369}; 1370 1371&spmi { 1372 #address-cells = <2>; 1373 #size-cells = <0>; 1374 1375 mt6315_6: pmic@6 { 1376 compatible = "mediatek,mt6315-regulator"; 1377 reg = <0x6 SPMI_USID>; 1378 1379 regulators { 1380 mt6315_6_vbuck1: vbuck1 { 1381 regulator-compatible = "vbuck1"; 1382 regulator-name = "Vbcpu"; 1383 regulator-min-microvolt = <300000>; 1384 regulator-max-microvolt = <1193750>; 1385 regulator-enable-ramp-delay = <256>; 1386 regulator-allowed-modes = <0 1 2>; 1387 regulator-always-on; 1388 }; 1389 1390 mt6315_6_vbuck3: vbuck3 { 1391 regulator-compatible = "vbuck3"; 1392 regulator-name = "Vlcpu"; 1393 regulator-min-microvolt = <300000>; 1394 regulator-max-microvolt = <1193750>; 1395 regulator-enable-ramp-delay = <256>; 1396 regulator-allowed-modes = <0 1 2>; 1397 regulator-always-on; 1398 }; 1399 }; 1400 }; 1401 1402 mt6315_7: pmic@7 { 1403 compatible = "mediatek,mt6315-regulator"; 1404 reg = <0x7 SPMI_USID>; 1405 1406 regulators { 1407 mt6315_7_vbuck1: vbuck1 { 1408 regulator-compatible = "vbuck1"; 1409 regulator-name = "Vgpu"; 1410 regulator-min-microvolt = <606250>; 1411 regulator-max-microvolt = <1193750>; 1412 regulator-enable-ramp-delay = <256>; 1413 regulator-allowed-modes = <0 1 2>; 1414 }; 1415 }; 1416 }; 1417}; 1418 1419&uart0 { 1420 status = "okay"; 1421}; 1422 1423&xhci { 1424 status = "okay"; 1425 1426 wakeup-source; 1427 vusb33-supply = <&pp3300_g>; 1428 vbus-supply = <&pp5000_a>; 1429}; 1430 1431#include <arm/cros-ec-keyboard.dtsi> 1432#include <arm/cros-ec-sbs.dtsi> 1433