xref: /openbmc/linux/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi (revision 23e0fff3)

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2020 MediaTek Inc.
 * Author: Seiya Wang <seiya.wang@mediatek.com>
 */
/dts-v1/;
#include "mt8192.dtsi"

/ {
	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0 0x40000000 0 0x80000000>;
	};

	/* system wide LDO 1.8V power rail */
	pp1800_ldo_g: regulator-1v8-g {
		compatible = "regulator-fixed";
		regulator-name = "pp1800_ldo_g";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&pp3300_g>;
	};

	/* system wide switching 3.3V power rail */
	pp3300_g: regulator-3v3-g {
		compatible = "regulator-fixed";
		regulator-name = "pp3300_g";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&ppvar_sys>;
	};

	/* system wide LDO 3.3V power rail */
	pp3300_ldo_z: regulator-3v3-z {
		compatible = "regulator-fixed";
		regulator-name = "pp3300_ldo_z";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&ppvar_sys>;
	};

	/* separately switched 3.3V power rail */
	pp3300_u: regulator-3v3-u {
		compatible = "regulator-fixed";
		regulator-name = "pp3300_u";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		/* enable pin wired to GPIO controlled by EC */
		vin-supply = <&pp3300_g>;
	};

	/* system wide switching 5.0V power rail */
	pp5000_a: regulator-5v0-a {
		compatible = "regulator-fixed";
		regulator-name = "pp5000_a";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&ppvar_sys>;
	};

	/* system wide semi-regulated power rail from battery or USB */
	ppvar_sys: regulator-var-sys {
		compatible = "regulator-fixed";
		regulator-name = "ppvar_sys";
		regulator-always-on;
		regulator-boot-on;
	};
};

&i2c0 {
	status = "okay";

	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
};

&i2c1 {
	status = "okay";

	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
};

&i2c2 {
	status = "okay";

	clock-frequency = <400000>;
	clock-stretch-ns = <12600>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;
};

&i2c3 {
	status = "okay";

	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_pins>;
};

&i2c7 {
	status = "okay";

	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c7_pins>;
};

&pio {
	/* 220 lines */
	gpio-line-names = "I2S_DP_LRCK",
			  "IS_DP_BCLK",
			  "I2S_DP_MCLK",
			  "I2S_DP_DATAOUT",
			  "SAR0_INT_ODL",
			  "EC_AP_INT_ODL",
			  "EDPBRDG_INT_ODL",
			  "DPBRDG_INT_ODL",
			  "DPBRDG_PWREN",
			  "DPBRDG_RST_ODL",
			  "I2S_HP_MCLK",
			  "I2S_HP_BCK",
			  "I2S_HP_LRCK",
			  "I2S_HP_DATAIN",
			  /*
			   * AP_FLASH_WP_L is crossystem ABI. Schematics
			   * call it AP_FLASH_WP_ODL.
			   */
			  "AP_FLASH_WP_L",
			  "TRACKPAD_INT_ODL",
			  "EC_AP_HPD_OD",
			  "SD_CD_ODL",
			  "HP_INT_ODL_ALC",
			  "EN_PP1000_DPBRDG",
			  "AP_GPIO20",
			  "TOUCH_INT_L_1V8",
			  "UART_BT_WAKE_ODL",
			  "AP_GPIO23",
			  "AP_SPI_FLASH_CS_L",
			  "AP_SPI_FLASH_CLK",
			  "EN_PP3300_DPBRDG_DX",
			  "AP_SPI_FLASH_MOSI",
			  "AP_SPI_FLASH_MISO",
			  "I2S_HP_DATAOUT",
			  "AP_GPIO30",
			  "I2S_SPKR_MCLK",
			  "I2S_SPKR_BCLK",
			  "I2S_SPKR_LRCK",
			  "I2S_SPKR_DATAIN",
			  "I2S_SPKR_DATAOUT",
			  "AP_SPI_H1_TPM_CLK",
			  "AP_SPI_H1_TPM_CS_L",
			  "AP_SPI_H1_TPM_MISO",
			  "AP_SPI_H1_TPM_MOSI",
			  "BL_PWM",
			  "EDPBRDG_PWREN",
			  "EDPBRDG_RST_ODL",
			  "EN_PP3300_HUB",
			  "HUB_RST_L",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "SD_CLK",
			  "SD_CMD",
			  "SD_DATA3",
			  "SD_DATA0",
			  "SD_DATA2",
			  "SD_DATA1",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "PCIE_WAKE_ODL",
			  "PCIE_RST_L",
			  "PCIE_CLKREQ_ODL",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "SPMI_SCL",
			  "SPMI_SDA",
			  "AP_GOOD",
			  "UART_DBG_TX_AP_RX",
			  "UART_AP_TX_DBG_RX",
			  "UART_AP_TX_BT_RX",
			  "UART_BT_TX_AP_RX",
			  "MIPI_DPI_D0_R",
			  "MIPI_DPI_D1_R",
			  "MIPI_DPI_D2_R",
			  "MIPI_DPI_D3_R",
			  "MIPI_DPI_D4_R",
			  "MIPI_DPI_D5_R",
			  "MIPI_DPI_D6_R",
			  "MIPI_DPI_D7_R",
			  "MIPI_DPI_D8_R",
			  "MIPI_DPI_D9_R",
			  "MIPI_DPI_D10_R",
			  "",
			  "",
			  "MIPI_DPI_DE_R",
			  "MIPI_DPI_D11_R",
			  "MIPI_DPI_VSYNC_R",
			  "MIPI_DPI_CLK_R",
			  "MIPI_DPI_HSYNC_R",
			  "PCM_BT_DATAIN",
			  "PCM_BT_SYNC",
			  "PCM_BT_DATAOUT",
			  "PCM_BT_CLK",
			  "AP_I2C_AUDIO_SCL",
			  "AP_I2C_AUDIO_SDA",
			  "SCP_I2C_SCL",
			  "SCP_I2C_SDA",
			  "AP_I2C_WLAN_SCL",
			  "AP_I2C_WLAN_SDA",
			  "AP_I2C_DPBRDG_SCL",
			  "AP_I2C_DPBRDG_SDA",
			  "EN_PP1800_DPBRDG_DX",
			  "EN_PP3300_EDP_DX",
			  "EN_PP1800_EDPBRDG_DX",
			  "EN_PP1000_EDPBRDG",
			  "SCP_JTAG0_TDO",
			  "SCP_JTAG0_TDI",
			  "SCP_JTAG0_TMS",
			  "SCP_JTAG0_TCK",
			  "SCP_JTAG0_TRSTN",
			  "EN_PP3000_VMC_PMU",
			  "EN_PP3300_DISPLAY_DX",
			  "TOUCH_RST_L_1V8",
			  "TOUCH_REPORT_DISABLE",
			  "",
			  "",
			  "AP_I2C_TRACKPAD_SCL_1V8",
			  "AP_I2C_TRACKPAD_SDA_1V8",
			  "EN_PP3300_WLAN",
			  "BT_KILL_L",
			  "WIFI_KILL_L",
			  "SET_VMC_VOLT_AT_1V8",
			  "EN_SPK",
			  "AP_WARM_RST_REQ",
			  "",
			  "",
			  "EN_PP3000_SD_S3",
			  "AP_EDP_BKLTEN",
			  "",
			  "",
			  "",
			  "AP_SPI_EC_CLK",
			  "AP_SPI_EC_CS_L",
			  "AP_SPI_EC_MISO",
			  "AP_SPI_EC_MOSI",
			  "AP_I2C_EDPBRDG_SCL",
			  "AP_I2C_EDPBRDG_SDA",
			  "MT6315_PROC_INT",
			  "MT6315_GPU_INT",
			  "UART_SERVO_TX_SCP_RX",
			  "UART_SCP_TX_SERVO_RX",
			  "BT_RTS_AP_CTS",
			  "AP_RTS_BT_CTS",
			  "UART_AP_WAKE_BT_ODL",
			  "WLAN_ALERT_ODL",
			  "EC_IN_RW_ODL",
			  "H1_AP_INT_ODL",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "MSDC0_CMD",
			  "MSDC0_DAT0",
			  "MSDC0_DAT2",
			  "MSDC0_DAT4",
			  "MSDC0_DAT6",
			  "MSDC0_DAT1",
			  "MSDC0_DAT5",
			  "MSDC0_DAT7",
			  "MSDC0_DSL",
			  "MSDC0_CLK",
			  "MSDC0_DAT3",
			  "MSDC0_RST_L",
			  "SCP_VREQ_VAO",
			  "AUD_DAT_MOSI2",
			  "AUD_NLE_MOSI1",
			  "AUD_NLE_MOSI0",
			  "AUD_DAT_MISO2",
			  "AP_I2C_SAR_SDA",
			  "AP_I2C_SAR_SCL",
			  "AP_I2C_PWR_SCL",
			  "AP_I2C_PWR_SDA",
			  "AP_I2C_TS_SCL_1V8",
			  "AP_I2C_TS_SDA_1V8",
			  "SRCLKENA0",
			  "SRCLKENA1",
			  "AP_EC_WATCHDOG_L",
			  "PWRAP_SPI0_MI",
			  "PWRAP_SPI0_CSN",
			  "PWRAP_SPI0_MO",
			  "PWRAP_SPI0_CK",
			  "AP_RTC_CLK32K",
			  "AUD_CLK_MOSI",
			  "AUD_SYNC_MOSI",
			  "AUD_DAT_MOSI0",
			  "AUD_DAT_MOSI1",
			  "AUD_DAT_MISO0",
			  "AUD_DAT_MISO1";

	i2c0_pins: i2c0-default-pins {
		pins-bus {
			pinmux = <PINMUX_GPIO204__FUNC_SCL0>,
				 <PINMUX_GPIO205__FUNC_SDA0>;
			bias-pull-up = <MTK_PULL_SET_RSEL_011>;
			drive-strength-microamp = <1000>;
		};
	};

	i2c1_pins: i2c1-default-pins {
		pins-bus {
			pinmux = <PINMUX_GPIO118__FUNC_SCL1>,
				 <PINMUX_GPIO119__FUNC_SDA1>;
			bias-pull-up = <MTK_PULL_SET_RSEL_011>;
			drive-strength-microamp = <1000>;
		};
	};

	i2c2_pins: i2c2-default-pins {
		pins-bus {
			pinmux = <PINMUX_GPIO141__FUNC_SCL2>,
				 <PINMUX_GPIO142__FUNC_SDA2>;
			bias-pull-up = <MTK_PULL_SET_RSEL_011>;
		};
	};

	i2c3_pins: i2c3-default-pins {
		pins-bus {
			pinmux = <PINMUX_GPIO160__FUNC_SCL3>,
				 <PINMUX_GPIO161__FUNC_SDA3>;
			bias-disable;
			drive-strength-microamp = <1000>;
		};
	};

	i2c7_pins: i2c7-default-pins {
		pins-bus {
			pinmux = <PINMUX_GPIO124__FUNC_SCL7>,
				 <PINMUX_GPIO125__FUNC_SDA7>;
			bias-disable;
			drive-strength-microamp = <1000>;
		};
	};

	spi1_pins: spi1-default-pins {
		pins-cs-mosi-clk {
			pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>,
				 <PINMUX_GPIO159__FUNC_SPI1_A_MO>,
				 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>;
			bias-disable;
		};

		pins-miso {
			pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>;
			bias-pull-down;
		};
	};

	spi5_pins: spi5-default-pins {
		pins-bus {
			pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>,
				 <PINMUX_GPIO37__FUNC_GPIO37>,
				 <PINMUX_GPIO39__FUNC_SPI5_A_MO>,
				 <PINMUX_GPIO36__FUNC_SPI5_A_CLK>;
			bias-disable;
		};
	};
};

&spi1 {
	status = "okay";

	mediatek,pad-select = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_pins>;
};

&spi5 {
	status = "okay";

	cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>;
	mediatek,pad-select = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&spi5_pins>;
};

&uart0 {
	status = "okay";
};