1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include "mt8183.dtsi" 11#include "mt6358.dtsi" 12 13/ { 14 aliases { 15 serial0 = &uart0; 16 }; 17 18 chosen { 19 stdout-path = "serial0:115200n8"; 20 }; 21 22 backlight_lcd0: backlight_lcd0 { 23 compatible = "pwm-backlight"; 24 pwms = <&pwm0 0 500000>; 25 power-supply = <&bl_pp5000>; 26 enable-gpios = <&pio 176 0>; 27 brightness-levels = <0 1023>; 28 num-interpolated-steps = <1023>; 29 default-brightness-level = <576>; 30 status = "okay"; 31 }; 32 33 memory@40000000 { 34 device_type = "memory"; 35 reg = <0 0x40000000 0 0x80000000>; 36 }; 37 38 clk32k: oscillator1 { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <32768>; 42 clock-output-names = "clk32k"; 43 }; 44 45 it6505_pp18_reg: regulator0 { 46 compatible = "regulator-fixed"; 47 regulator-name = "it6505_pp18"; 48 regulator-min-microvolt = <1800000>; 49 regulator-max-microvolt = <1800000>; 50 gpio = <&pio 178 0>; 51 enable-active-high; 52 }; 53 54 lcd_pp3300: regulator1 { 55 compatible = "regulator-fixed"; 56 regulator-name = "lcd_pp3300"; 57 regulator-min-microvolt = <3300000>; 58 regulator-max-microvolt = <3300000>; 59 regulator-always-on; 60 regulator-boot-on; 61 }; 62 63 bl_pp5000: regulator2 { 64 compatible = "regulator-fixed"; 65 regulator-name = "bl_pp5000"; 66 regulator-min-microvolt = <5000000>; 67 regulator-max-microvolt = <5000000>; 68 regulator-always-on; 69 regulator-boot-on; 70 }; 71 72 mmc1_fixed_power: regulator3 { 73 compatible = "regulator-fixed"; 74 regulator-name = "mmc1_power"; 75 regulator-min-microvolt = <3300000>; 76 regulator-max-microvolt = <3300000>; 77 }; 78 79 mmc1_fixed_io: regulator4 { 80 compatible = "regulator-fixed"; 81 regulator-name = "mmc1_io"; 82 regulator-min-microvolt = <1800000>; 83 regulator-max-microvolt = <1800000>; 84 }; 85 86 pp1800_alw: regulator5 { 87 compatible = "regulator-fixed"; 88 regulator-name = "pp1800_alw"; 89 regulator-always-on; 90 regulator-boot-on; 91 regulator-min-microvolt = <1800000>; 92 regulator-max-microvolt = <1800000>; 93 }; 94 95 pp3300_alw: regulator6 { 96 compatible = "regulator-fixed"; 97 regulator-name = "pp3300_alw"; 98 regulator-always-on; 99 regulator-boot-on; 100 regulator-min-microvolt = <3300000>; 101 regulator-max-microvolt = <3300000>; 102 }; 103 104 reserved_memory: reserved-memory { 105 #address-cells = <2>; 106 #size-cells = <2>; 107 ranges; 108 109 scp_mem_reserved: scp_mem_region { 110 compatible = "shared-dma-pool"; 111 reg = <0 0x50000000 0 0x2900000>; 112 no-map; 113 }; 114 }; 115 116 max98357a: codec0 { 117 compatible = "maxim,max98357a"; 118 sdmode-gpios = <&pio 175 0>; 119 }; 120 121 btsco: codec1 { 122 compatible = "linux,bt-sco"; 123 }; 124 125 wifi_pwrseq: wifi-pwrseq { 126 compatible = "mmc-pwrseq-simple"; 127 pinctrl-names = "default"; 128 pinctrl-0 = <&wifi_pins_pwrseq>; 129 130 /* Toggle WIFI_ENABLE to reset the chip. */ 131 reset-gpios = <&pio 119 1>; 132 }; 133 134 wifi_wakeup: wifi-wakeup { 135 compatible = "gpio-keys"; 136 pinctrl-names = "default"; 137 pinctrl-0 = <&wifi_pins_wakeup>; 138 139 wowlan { 140 label = "Wake on WiFi"; 141 gpios = <&pio 113 GPIO_ACTIVE_HIGH>; 142 linux,code = <KEY_WAKEUP>; 143 wakeup-source; 144 }; 145 }; 146 147 tboard_thermistor1: thermal-sensor1 { 148 compatible = "generic-adc-thermal"; 149 #thermal-sensor-cells = <0>; 150 io-channels = <&auxadc 0>; 151 io-channel-names = "sensor-channel"; 152 temperature-lookup-table = < (-5000) 4241 153 0 4063 154 5000 3856 155 10000 3621 156 15000 3364 157 20000 3091 158 25000 2810 159 30000 2526 160 35000 2247 161 40000 1982 162 45000 1734 163 50000 1507 164 55000 1305 165 60000 1122 166 65000 964 167 70000 827 168 75000 710 169 80000 606 170 85000 519 171 90000 445 172 95000 382 173 100000 330 174 105000 284 175 110000 245 176 115000 213 177 120000 183 178 125000 161>; 179 }; 180 181 tboard_thermistor2: thermal-sensor2 { 182 compatible = "generic-adc-thermal"; 183 #thermal-sensor-cells = <0>; 184 io-channels = <&auxadc 1>; 185 io-channel-names = "sensor-channel"; 186 temperature-lookup-table = < (-5000) 4241 187 0 4063 188 5000 3856 189 10000 3621 190 15000 3364 191 20000 3091 192 25000 2810 193 30000 2526 194 35000 2247 195 40000 1982 196 45000 1734 197 50000 1507 198 55000 1305 199 60000 1122 200 65000 964 201 70000 827 202 75000 710 203 80000 606 204 85000 519 205 90000 445 206 95000 382 207 100000 330 208 105000 284 209 110000 245 210 115000 213 211 120000 183 212 125000 161>; 213 }; 214}; 215 216&auxadc { 217 status = "okay"; 218}; 219 220&cpu0 { 221 proc-supply = <&mt6358_vproc12_reg>; 222}; 223 224&cpu1 { 225 proc-supply = <&mt6358_vproc12_reg>; 226}; 227 228&cpu2 { 229 proc-supply = <&mt6358_vproc12_reg>; 230}; 231 232&cpu3 { 233 proc-supply = <&mt6358_vproc12_reg>; 234}; 235 236&cpu4 { 237 proc-supply = <&mt6358_vproc11_reg>; 238}; 239 240&cpu5 { 241 proc-supply = <&mt6358_vproc11_reg>; 242}; 243 244&cpu6 { 245 proc-supply = <&mt6358_vproc11_reg>; 246}; 247 248&cpu7 { 249 proc-supply = <&mt6358_vproc11_reg>; 250}; 251 252&i2c0 { 253 pinctrl-names = "default"; 254 pinctrl-0 = <&i2c0_pins>; 255 status = "okay"; 256 clock-frequency = <400000>; 257 #address-cells = <1>; 258 #size-cells = <0>; 259}; 260 261&i2c1 { 262 pinctrl-names = "default"; 263 pinctrl-0 = <&i2c1_pins>; 264 status = "okay"; 265 clock-frequency = <100000>; 266}; 267 268&i2c3 { 269 pinctrl-names = "default"; 270 pinctrl-0 = <&i2c3_pins>; 271 status = "okay"; 272 clock-frequency = <100000>; 273 #address-cells = <1>; 274 #size-cells = <0>; 275}; 276 277&i2c5 { 278 pinctrl-names = "default"; 279 pinctrl-0 = <&i2c5_pins>; 280 status = "okay"; 281 clock-frequency = <100000>; 282 #address-cells = <1>; 283 #size-cells = <0>; 284}; 285 286&i2c6 { 287 pinctrl-names = "default"; 288 pinctrl-0 = <&i2c6_pins>; 289 status = "okay"; 290 clock-frequency = <100000>; 291}; 292 293&mmc0 { 294 status = "okay"; 295 pinctrl-names = "default", "state_uhs"; 296 pinctrl-0 = <&mmc0_pins_default>; 297 pinctrl-1 = <&mmc0_pins_uhs>; 298 bus-width = <8>; 299 max-frequency = <200000000>; 300 cap-mmc-highspeed; 301 mmc-hs200-1_8v; 302 mmc-hs400-1_8v; 303 cap-mmc-hw-reset; 304 no-sdio; 305 no-sd; 306 hs400-ds-delay = <0x12814>; 307 vmmc-supply = <&mt6358_vemc_reg>; 308 vqmmc-supply = <&mt6358_vio18_reg>; 309 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; 310 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; 311 non-removable; 312}; 313 314&mmc1 { 315 status = "okay"; 316 pinctrl-names = "default", "state_uhs"; 317 pinctrl-0 = <&mmc1_pins_default>; 318 pinctrl-1 = <&mmc1_pins_uhs>; 319 vmmc-supply = <&mmc1_fixed_power>; 320 vqmmc-supply = <&mmc1_fixed_io>; 321 mmc-pwrseq = <&wifi_pwrseq>; 322 bus-width = <4>; 323 max-frequency = <200000000>; 324 drv-type = <2>; 325 cap-sd-highspeed; 326 sd-uhs-sdr50; 327 sd-uhs-sdr104; 328 keep-power-in-suspend; 329 enable-sdio-wakeup; 330 cap-sdio-irq; 331 non-removable; 332 no-mmc; 333 no-sd; 334 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>; 335 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 339 qca_wifi: qca-wifi@1 { 340 compatible = "qcom,ath10k"; 341 reg = <1>; 342 }; 343}; 344 345&mt6358_vdram2_reg { 346 regulator-always-on; 347}; 348 349&mt6358codec { 350 Avdd-supply = <&mt6358_vaud28_reg>; 351}; 352 353&mt6358_vsim1_reg { 354 regulator-min-microvolt = <2700000>; 355 regulator-max-microvolt = <2700000>; 356}; 357 358&mt6358_vsim2_reg { 359 regulator-min-microvolt = <2700000>; 360 regulator-max-microvolt = <2700000>; 361}; 362 363&pio { 364 bt_pins: bt-pins { 365 pins_bt_en { 366 pinmux = <PINMUX_GPIO120__FUNC_GPIO120>; 367 output-low; 368 }; 369 }; 370 371 ec_ap_int_odl: ec_ap_int_odl { 372 pins1 { 373 pinmux = <PINMUX_GPIO151__FUNC_GPIO151>; 374 input-enable; 375 bias-pull-up; 376 }; 377 }; 378 379 h1_int_od_l: h1_int_od_l { 380 pins1 { 381 pinmux = <PINMUX_GPIO153__FUNC_GPIO153>; 382 input-enable; 383 }; 384 }; 385 386 i2c0_pins: i2c0 { 387 pins_bus { 388 pinmux = <PINMUX_GPIO82__FUNC_SDA0>, 389 <PINMUX_GPIO83__FUNC_SCL0>; 390 mediatek,pull-up-adv = <3>; 391 mediatek,drive-strength-adv = <00>; 392 }; 393 }; 394 395 i2c1_pins: i2c1 { 396 pins_bus { 397 pinmux = <PINMUX_GPIO81__FUNC_SDA1>, 398 <PINMUX_GPIO84__FUNC_SCL1>; 399 mediatek,pull-up-adv = <3>; 400 mediatek,drive-strength-adv = <00>; 401 }; 402 }; 403 404 i2c2_pins: i2c2 { 405 pins_bus { 406 pinmux = <PINMUX_GPIO103__FUNC_SCL2>, 407 <PINMUX_GPIO104__FUNC_SDA2>; 408 bias-disable; 409 mediatek,drive-strength-adv = <00>; 410 }; 411 }; 412 413 i2c3_pins: i2c3 { 414 pins_bus { 415 pinmux = <PINMUX_GPIO50__FUNC_SCL3>, 416 <PINMUX_GPIO51__FUNC_SDA3>; 417 mediatek,pull-up-adv = <3>; 418 mediatek,drive-strength-adv = <00>; 419 }; 420 }; 421 422 i2c4_pins: i2c4 { 423 pins_bus { 424 pinmux = <PINMUX_GPIO105__FUNC_SCL4>, 425 <PINMUX_GPIO106__FUNC_SDA4>; 426 bias-disable; 427 mediatek,drive-strength-adv = <00>; 428 }; 429 }; 430 431 i2c5_pins: i2c5 { 432 pins_bus { 433 pinmux = <PINMUX_GPIO48__FUNC_SCL5>, 434 <PINMUX_GPIO49__FUNC_SDA5>; 435 mediatek,pull-up-adv = <3>; 436 mediatek,drive-strength-adv = <00>; 437 }; 438 }; 439 440 i2c6_pins: i2c6 { 441 pins_bus { 442 pinmux = <PINMUX_GPIO11__FUNC_SCL6>, 443 <PINMUX_GPIO12__FUNC_SDA6>; 444 bias-disable; 445 }; 446 }; 447 448 mmc0_pins_default: mmc0-pins-default { 449 pins_cmd_dat { 450 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 451 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 452 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 453 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 454 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 455 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 456 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 457 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 458 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 459 input-enable; 460 drive-strength = <MTK_DRIVE_14mA>; 461 mediatek,pull-up-adv = <01>; 462 }; 463 464 pins_clk { 465 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 466 drive-strength = <MTK_DRIVE_14mA>; 467 mediatek,pull-down-adv = <10>; 468 }; 469 470 pins_rst { 471 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 472 drive-strength = <MTK_DRIVE_14mA>; 473 mediatek,pull-down-adv = <01>; 474 }; 475 }; 476 477 mmc0_pins_uhs: mmc0-pins-uhs { 478 pins_cmd_dat { 479 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 480 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 481 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 482 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 483 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 484 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 485 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 486 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 487 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 488 input-enable; 489 drive-strength = <MTK_DRIVE_14mA>; 490 mediatek,pull-up-adv = <01>; 491 }; 492 493 pins_clk { 494 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 495 drive-strength = <MTK_DRIVE_14mA>; 496 mediatek,pull-down-adv = <10>; 497 }; 498 499 pins_ds { 500 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; 501 drive-strength = <MTK_DRIVE_14mA>; 502 mediatek,pull-down-adv = <10>; 503 }; 504 505 pins_rst { 506 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 507 drive-strength = <MTK_DRIVE_14mA>; 508 mediatek,pull-up-adv = <01>; 509 }; 510 }; 511 512 mmc1_pins_default: mmc1-pins-default { 513 pins_cmd_dat { 514 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 515 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 516 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 517 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 518 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 519 input-enable; 520 mediatek,pull-up-adv = <10>; 521 }; 522 523 pins_clk { 524 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 525 input-enable; 526 mediatek,pull-down-adv = <10>; 527 }; 528 }; 529 530 mmc1_pins_uhs: mmc1-pins-uhs { 531 pins_cmd_dat { 532 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 533 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 534 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 535 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 536 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 537 drive-strength = <MTK_DRIVE_6mA>; 538 input-enable; 539 mediatek,pull-up-adv = <10>; 540 }; 541 542 pins_clk { 543 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 544 drive-strength = <MTK_DRIVE_8mA>; 545 mediatek,pull-down-adv = <10>; 546 input-enable; 547 }; 548 }; 549 550 pwm0_pin_default: pwm0_pin_default { 551 pins1 { 552 pinmux = <PINMUX_GPIO176__FUNC_GPIO176>; 553 output-high; 554 bias-pull-up; 555 }; 556 pins2 { 557 pinmux = <PINMUX_GPIO43__FUNC_DISP_PWM>; 558 }; 559 }; 560 561 scp_pins: scp { 562 pins_scp_uart { 563 pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>, 564 <PINMUX_GPIO112__FUNC_TP_UTXD1_AO>; 565 }; 566 }; 567 568 spi0_pins: spi0 { 569 pins_spi{ 570 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, 571 <PINMUX_GPIO86__FUNC_GPIO86>, 572 <PINMUX_GPIO87__FUNC_SPI0_MO>, 573 <PINMUX_GPIO88__FUNC_SPI0_CLK>; 574 bias-disable; 575 }; 576 }; 577 578 spi1_pins: spi1 { 579 pins_spi{ 580 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, 581 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, 582 <PINMUX_GPIO163__FUNC_SPI1_A_MO>, 583 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>; 584 bias-disable; 585 }; 586 }; 587 588 spi2_pins: spi2 { 589 pins_spi{ 590 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, 591 <PINMUX_GPIO1__FUNC_SPI2_MO>, 592 <PINMUX_GPIO2__FUNC_SPI2_CLK>; 593 bias-disable; 594 }; 595 pins_spi_mi { 596 pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>; 597 mediatek,pull-down-adv = <00>; 598 }; 599 }; 600 601 spi3_pins: spi3 { 602 pins_spi{ 603 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, 604 <PINMUX_GPIO22__FUNC_SPI3_CSB>, 605 <PINMUX_GPIO23__FUNC_SPI3_MO>, 606 <PINMUX_GPIO24__FUNC_SPI3_CLK>; 607 bias-disable; 608 }; 609 }; 610 611 spi4_pins: spi4 { 612 pins_spi{ 613 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, 614 <PINMUX_GPIO18__FUNC_SPI4_CSB>, 615 <PINMUX_GPIO19__FUNC_SPI4_MO>, 616 <PINMUX_GPIO20__FUNC_SPI4_CLK>; 617 bias-disable; 618 }; 619 }; 620 621 spi5_pins: spi5 { 622 pins_spi{ 623 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, 624 <PINMUX_GPIO14__FUNC_SPI5_CSB>, 625 <PINMUX_GPIO15__FUNC_SPI5_MO>, 626 <PINMUX_GPIO16__FUNC_SPI5_CLK>; 627 bias-disable; 628 }; 629 }; 630 631 uart0_pins_default: uart0-pins-default { 632 pins_rx { 633 pinmux = <PINMUX_GPIO95__FUNC_URXD0>; 634 input-enable; 635 bias-pull-up; 636 }; 637 pins_tx { 638 pinmux = <PINMUX_GPIO96__FUNC_UTXD0>; 639 }; 640 }; 641 642 uart1_pins_default: uart1-pins-default { 643 pins_rx { 644 pinmux = <PINMUX_GPIO121__FUNC_URXD1>; 645 input-enable; 646 bias-pull-up; 647 }; 648 pins_tx { 649 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 650 }; 651 pins_rts { 652 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 653 output-enable; 654 }; 655 pins_cts { 656 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 657 input-enable; 658 }; 659 }; 660 661 uart1_pins_sleep: uart1-pins-sleep { 662 pins_rx { 663 pinmux = <PINMUX_GPIO121__FUNC_GPIO121>; 664 input-enable; 665 bias-pull-up; 666 }; 667 pins_tx { 668 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 669 }; 670 pins_rts { 671 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 672 output-enable; 673 }; 674 pins_cts { 675 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 676 input-enable; 677 }; 678 }; 679 680 wifi_pins_pwrseq: wifi-pins-pwrseq { 681 pins_wifi_enable { 682 pinmux = <PINMUX_GPIO119__FUNC_GPIO119>; 683 output-low; 684 }; 685 }; 686 687 wifi_pins_wakeup: wifi-pins-wakeup { 688 pins_wifi_wakeup { 689 pinmux = <PINMUX_GPIO113__FUNC_GPIO113>; 690 input-enable; 691 }; 692 }; 693}; 694 695&pwm0 { 696 status = "okay"; 697 pinctrl-names = "default"; 698 pinctrl-0 = <&pwm0_pin_default>; 699}; 700 701&scp { 702 status = "okay"; 703 pinctrl-names = "default"; 704 pinctrl-0 = <&scp_pins>; 705 706 cros_ec { 707 compatible = "google,cros-ec-rpmsg"; 708 mtk,rpmsg-name = "cros-ec-rpmsg"; 709 }; 710}; 711 712&soc_data { 713 status = "okay"; 714}; 715 716&spi0 { 717 pinctrl-names = "default"; 718 pinctrl-0 = <&spi0_pins>; 719 mediatek,pad-select = <0>; 720 status = "okay"; 721 cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>; 722 723 cr50@0 { 724 compatible = "google,cr50"; 725 reg = <0>; 726 spi-max-frequency = <1000000>; 727 pinctrl-names = "default"; 728 pinctrl-0 = <&h1_int_od_l>; 729 interrupt-parent = <&pio>; 730 interrupts = <153 IRQ_TYPE_EDGE_RISING>; 731 }; 732}; 733 734&spi1 { 735 pinctrl-names = "default"; 736 pinctrl-0 = <&spi1_pins>; 737 mediatek,pad-select = <0>; 738 status = "okay"; 739 740 w25q64dw: spi-flash@0 { 741 compatible = "winbond,w25q64dw", "jedec,spi-nor"; 742 reg = <0>; 743 spi-max-frequency = <25000000>; 744 }; 745}; 746 747&spi2 { 748 pinctrl-names = "default"; 749 pinctrl-0 = <&spi2_pins>; 750 mediatek,pad-select = <0>; 751 status = "okay"; 752 753 cros_ec: cros-ec@0 { 754 compatible = "google,cros-ec-spi"; 755 reg = <0>; 756 spi-max-frequency = <3000000>; 757 interrupt-parent = <&pio>; 758 interrupts = <151 IRQ_TYPE_LEVEL_LOW>; 759 pinctrl-names = "default"; 760 pinctrl-0 = <&ec_ap_int_odl>; 761 762 i2c_tunnel: i2c-tunnel { 763 compatible = "google,cros-ec-i2c-tunnel"; 764 google,remote-bus = <1>; 765 #address-cells = <1>; 766 #size-cells = <0>; 767 }; 768 769 usbc_extcon: extcon0 { 770 compatible = "google,extcon-usbc-cros-ec"; 771 google,usb-port-id = <0>; 772 }; 773 }; 774}; 775 776&spi3 { 777 pinctrl-names = "default"; 778 pinctrl-0 = <&spi3_pins>; 779 mediatek,pad-select = <0>; 780 status = "disabled"; 781}; 782 783&spi4 { 784 pinctrl-names = "default"; 785 pinctrl-0 = <&spi4_pins>; 786 mediatek,pad-select = <0>; 787 status = "disabled"; 788}; 789 790&spi5 { 791 pinctrl-names = "default"; 792 pinctrl-0 = <&spi5_pins>; 793 mediatek,pad-select = <0>; 794 status = "disabled"; 795}; 796 797&ssusb { 798 dr_mode = "host"; 799 wakeup-source; 800 vusb33-supply = <&mt6358_vusb_reg>; 801 status = "okay"; 802}; 803 804&u3phy { 805 status = "okay"; 806}; 807 808&uart0 { 809 pinctrl-names = "default"; 810 pinctrl-0 = <&uart0_pins_default>; 811 status = "okay"; 812}; 813 814&uart1 { 815 pinctrl-names = "default", "sleep"; 816 pinctrl-0 = <&uart1_pins_default>; 817 pinctrl-1 = <&uart1_pins_sleep>; 818 status = "okay"; 819 interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>, 820 <&pio 121 IRQ_TYPE_EDGE_FALLING>; 821 822 bluetooth: bluetooth { 823 pinctrl-names = "default"; 824 pinctrl-0 = <&bt_pins>; 825 status = "okay"; 826 compatible = "qcom,qca6174-bt"; 827 enable-gpios = <&pio 120 0>; 828 clocks = <&clk32k>; 829 firmware-name = "nvm_00440302_i2s.bin"; 830 }; 831}; 832 833&usb_host { 834 #address-cells = <1>; 835 #size-cells = <0>; 836 vusb33-supply = <&mt6358_vusb_reg>; 837 status = "okay"; 838 839 hub@1 { 840 compatible = "usb5e3,610"; 841 reg = <1>; 842 }; 843}; 844 845#include <arm/cros-ec-keyboard.dtsi> 846#include <arm/cros-ec-sbs.dtsi> 847