1// SPDX-License-Identifier: (GPL-2.0+ OR X11) 2/* 3 * Copyright (C) 2016 Marvell Technology Group Ltd. 4 */ 5 6/* 7 * Device Tree file for Marvell Armada CP110. 8 */ 9 10#include <dt-bindings/interrupt-controller/mvebu-icu.h> 11 12#include "armada-common.dtsi" 13 14#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000)) 15#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000)) 16#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000) 17 18/ { 19 /* 20 * The contents of the node are defined below, in order to 21 * save one indentation level 22 */ 23 CP110_NAME: CP110_NAME { }; 24}; 25 26&CP110_NAME { 27 #address-cells = <2>; 28 #size-cells = <2>; 29 compatible = "simple-bus"; 30 interrupt-parent = <&CP110_LABEL(icu)>; 31 ranges; 32 33 config-space@CP110_BASE { 34 #address-cells = <1>; 35 #size-cells = <1>; 36 compatible = "simple-bus"; 37 ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>; 38 39 CP110_LABEL(ethernet): ethernet@0 { 40 compatible = "marvell,armada-7k-pp22"; 41 reg = <0x0 0x100000>, <0x129000 0xb000>; 42 clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>, 43 <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 18>; 44 clock-names = "pp_clk", "gop_clk", 45 "mg_clk", "axi_clk"; 46 marvell,system-controller = <&CP110_LABEL(syscon0)>; 47 status = "disabled"; 48 dma-coherent; 49 50 CP110_LABEL(eth0): eth0 { 51 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>, 52 <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>, 53 <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>, 54 <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>, 55 <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>, 56 <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>; 57 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", 58 "tx-cpu3", "rx-shared", "link"; 59 port-id = <0>; 60 gop-port-id = <0>; 61 status = "disabled"; 62 }; 63 64 CP110_LABEL(eth1): eth1 { 65 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>, 66 <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>, 67 <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>, 68 <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>, 69 <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>, 70 <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>; 71 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", 72 "tx-cpu3", "rx-shared", "link"; 73 port-id = <1>; 74 gop-port-id = <2>; 75 status = "disabled"; 76 }; 77 78 CP110_LABEL(eth2): eth2 { 79 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>, 80 <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>, 81 <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>, 82 <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>, 83 <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>, 84 <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>; 85 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", 86 "tx-cpu3", "rx-shared", "link"; 87 port-id = <2>; 88 gop-port-id = <3>; 89 status = "disabled"; 90 }; 91 }; 92 93 CP110_LABEL(comphy): phy@120000 { 94 compatible = "marvell,comphy-cp110"; 95 reg = <0x120000 0x6000>; 96 marvell,system-controller = <&CP110_LABEL(syscon0)>; 97 #address-cells = <1>; 98 #size-cells = <0>; 99 100 CP110_LABEL(comphy0): phy@0 { 101 reg = <0>; 102 #phy-cells = <1>; 103 }; 104 105 CP110_LABEL(comphy1): phy@1 { 106 reg = <1>; 107 #phy-cells = <1>; 108 }; 109 110 CP110_LABEL(comphy2): phy@2 { 111 reg = <2>; 112 #phy-cells = <1>; 113 }; 114 115 CP110_LABEL(comphy3): phy@3 { 116 reg = <3>; 117 #phy-cells = <1>; 118 }; 119 120 CP110_LABEL(comphy4): phy@4 { 121 reg = <4>; 122 #phy-cells = <1>; 123 }; 124 125 CP110_LABEL(comphy5): phy@5 { 126 reg = <5>; 127 #phy-cells = <1>; 128 }; 129 }; 130 131 CP110_LABEL(mdio): mdio@12a200 { 132 #address-cells = <1>; 133 #size-cells = <0>; 134 compatible = "marvell,orion-mdio"; 135 reg = <0x12a200 0x10>; 136 clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>, 137 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>; 138 status = "disabled"; 139 }; 140 141 CP110_LABEL(xmdio): mdio@12a600 { 142 #address-cells = <1>; 143 #size-cells = <0>; 144 compatible = "marvell,xmdio"; 145 reg = <0x12a600 0x10>; 146 status = "disabled"; 147 }; 148 149 CP110_LABEL(icu): interrupt-controller@1e0000 { 150 compatible = "marvell,cp110-icu"; 151 reg = <0x1e0000 0x10>; 152 #interrupt-cells = <3>; 153 interrupt-controller; 154 msi-parent = <&gicp>; 155 }; 156 157 CP110_LABEL(rtc): rtc@284000 { 158 compatible = "marvell,armada-8k-rtc"; 159 reg = <0x284000 0x20>, <0x284080 0x24>; 160 reg-names = "rtc", "rtc-soc"; 161 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>; 162 }; 163 164 CP110_LABEL(thermal): thermal@400078 { 165 compatible = "marvell,armada-cp110-thermal"; 166 reg = <0x400078 0x4>, 167 <0x400070 0x8>; 168 }; 169 170 CP110_LABEL(syscon0): system-controller@440000 { 171 compatible = "syscon", "simple-mfd"; 172 reg = <0x440000 0x2000>; 173 174 CP110_LABEL(clk): clock { 175 compatible = "marvell,cp110-clock"; 176 #clock-cells = <2>; 177 }; 178 179 CP110_LABEL(gpio1): gpio@100 { 180 compatible = "marvell,armada-8k-gpio"; 181 offset = <0x100>; 182 ngpios = <32>; 183 gpio-controller; 184 #gpio-cells = <2>; 185 gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>; 186 interrupt-controller; 187 interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>, 188 <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>, 189 <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>, 190 <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>; 191 status = "disabled"; 192 }; 193 194 CP110_LABEL(gpio2): gpio@140 { 195 compatible = "marvell,armada-8k-gpio"; 196 offset = <0x140>; 197 ngpios = <31>; 198 gpio-controller; 199 #gpio-cells = <2>; 200 gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>; 201 interrupt-controller; 202 interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>, 203 <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>, 204 <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>, 205 <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>; 206 status = "disabled"; 207 }; 208 }; 209 210 CP110_LABEL(usb3_0): usb3@500000 { 211 compatible = "marvell,armada-8k-xhci", 212 "generic-xhci"; 213 reg = <0x500000 0x4000>; 214 dma-coherent; 215 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&CP110_LABEL(clk) 1 22>; 217 status = "disabled"; 218 }; 219 220 CP110_LABEL(usb3_1): usb3@510000 { 221 compatible = "marvell,armada-8k-xhci", 222 "generic-xhci"; 223 reg = <0x510000 0x4000>; 224 dma-coherent; 225 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>; 226 clocks = <&CP110_LABEL(clk) 1 23>; 227 status = "disabled"; 228 }; 229 230 CP110_LABEL(sata0): sata@540000 { 231 compatible = "marvell,armada-8k-ahci", 232 "generic-ahci"; 233 reg = <0x540000 0x30000>; 234 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>; 235 clocks = <&CP110_LABEL(clk) 1 15>; 236 status = "disabled"; 237 }; 238 239 CP110_LABEL(xor0): xor@6a0000 { 240 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 241 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>; 242 dma-coherent; 243 msi-parent = <&gic_v2m0>; 244 clocks = <&CP110_LABEL(clk) 1 8>; 245 }; 246 247 CP110_LABEL(xor1): xor@6c0000 { 248 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 249 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>; 250 dma-coherent; 251 msi-parent = <&gic_v2m0>; 252 clocks = <&CP110_LABEL(clk) 1 7>; 253 }; 254 255 CP110_LABEL(spi0): spi@700600 { 256 compatible = "marvell,armada-380-spi"; 257 reg = <0x700600 0x50>; 258 #address-cells = <0x1>; 259 #size-cells = <0x0>; 260 clock-names = "core", "axi"; 261 clocks = <&CP110_LABEL(clk) 1 21>, 262 <&CP110_LABEL(clk) 1 17>; 263 status = "disabled"; 264 }; 265 266 CP110_LABEL(spi1): spi@700680 { 267 compatible = "marvell,armada-380-spi"; 268 reg = <0x700680 0x50>; 269 #address-cells = <1>; 270 #size-cells = <0>; 271 clock-names = "core", "axi"; 272 clocks = <&CP110_LABEL(clk) 1 21>, 273 <&CP110_LABEL(clk) 1 17>; 274 status = "disabled"; 275 }; 276 277 CP110_LABEL(i2c0): i2c@701000 { 278 compatible = "marvell,mv78230-i2c"; 279 reg = <0x701000 0x20>; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>; 283 clock-names = "core", "reg"; 284 clocks = <&CP110_LABEL(clk) 1 21>, 285 <&CP110_LABEL(clk) 1 17>; 286 status = "disabled"; 287 }; 288 289 CP110_LABEL(i2c1): i2c@701100 { 290 compatible = "marvell,mv78230-i2c"; 291 reg = <0x701100 0x20>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>; 295 clock-names = "core", "reg"; 296 clocks = <&CP110_LABEL(clk) 1 21>, 297 <&CP110_LABEL(clk) 1 17>; 298 status = "disabled"; 299 }; 300 301 CP110_LABEL(nand): nand@720000 { 302 /* 303 * Due to the limitation of the pins available 304 * this controller is only usable on the CPM 305 * for A7K and on the CPS for A8K. 306 */ 307 compatible = "marvell,armada-8k-nand", 308 "marvell,armada370-nand"; 309 reg = <0x720000 0x54>; 310 #address-cells = <1>; 311 #size-cells = <1>; 312 interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&CP110_LABEL(clk) 1 2>; 314 marvell,system-controller = <&CP110_LABEL(syscon0)>; 315 status = "disabled"; 316 }; 317 318 CP110_LABEL(trng): trng@760000 { 319 compatible = "marvell,armada-8k-rng", 320 "inside-secure,safexcel-eip76"; 321 reg = <0x760000 0x7d>; 322 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&CP110_LABEL(clk) 1 25>; 324 status = "okay"; 325 }; 326 327 CP110_LABEL(sdhci0): sdhci@780000 { 328 compatible = "marvell,armada-cp110-sdhci"; 329 reg = <0x780000 0x300>; 330 interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>; 331 clock-names = "core", "axi"; 332 clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>; 333 dma-coherent; 334 status = "disabled"; 335 }; 336 337 CP110_LABEL(crypto): crypto@800000 { 338 compatible = "inside-secure,safexcel-eip197"; 339 reg = <0x800000 0x200000>; 340 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>, 341 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>, 342 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>, 343 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>, 344 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>, 345 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>; 346 interrupt-names = "mem", "ring0", "ring1", 347 "ring2", "ring3", "eip"; 348 clocks = <&CP110_LABEL(clk) 1 26>; 349 dma-coherent; 350 }; 351 }; 352 353 CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE { 354 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 355 reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>, 356 <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>; 357 reg-names = "ctrl", "config"; 358 #address-cells = <3>; 359 #size-cells = <2>; 360 #interrupt-cells = <1>; 361 device_type = "pci"; 362 dma-coherent; 363 msi-parent = <&gic_v2m0>; 364 365 bus-range = <0 0xff>; 366 ranges = 367 /* downstream I/O */ 368 <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000 369 /* non-prefetchable memory */ 370 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>; 371 interrupt-map-mask = <0 0 0 0>; 372 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; 373 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; 374 num-lanes = <1>; 375 clocks = <&CP110_LABEL(clk) 1 13>; 376 status = "disabled"; 377 }; 378 379 CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE { 380 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 381 reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>, 382 <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>; 383 reg-names = "ctrl", "config"; 384 #address-cells = <3>; 385 #size-cells = <2>; 386 #interrupt-cells = <1>; 387 device_type = "pci"; 388 dma-coherent; 389 msi-parent = <&gic_v2m0>; 390 391 bus-range = <0 0xff>; 392 ranges = 393 /* downstream I/O */ 394 <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000 395 /* non-prefetchable memory */ 396 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>; 397 interrupt-map-mask = <0 0 0 0>; 398 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; 399 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; 400 401 num-lanes = <1>; 402 clocks = <&CP110_LABEL(clk) 1 11>; 403 status = "disabled"; 404 }; 405 406 CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE { 407 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 408 reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>, 409 <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>; 410 reg-names = "ctrl", "config"; 411 #address-cells = <3>; 412 #size-cells = <2>; 413 #interrupt-cells = <1>; 414 device_type = "pci"; 415 dma-coherent; 416 msi-parent = <&gic_v2m0>; 417 418 bus-range = <0 0xff>; 419 ranges = 420 /* downstream I/O */ 421 <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000 422 /* non-prefetchable memory */ 423 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>; 424 interrupt-map-mask = <0 0 0 0>; 425 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; 426 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; 427 428 num-lanes = <1>; 429 clocks = <&CP110_LABEL(clk) 1 12>; 430 status = "disabled"; 431 }; 432}; 433