1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 SolidRun ltd.
4 * Based on Marvell MACCHIATOBin board
5 *
6 * Device Tree file for SolidRun's ClearFog GT 8K
7 */
8
9#include "armada-8040.dtsi"
10
11#include <dt-bindings/input/input.h>
12#include <dt-bindings/gpio/gpio.h>
13
14/ {
15	model = "SolidRun ClearFog GT 8K";
16	compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040",
17			"marvell,armada-ap806-quad", "marvell,armada-ap806";
18
19	chosen {
20		stdout-path = "serial0:115200n8";
21	};
22
23	memory@00000000 {
24		device_type = "memory";
25		reg = <0x0 0x0 0x0 0x80000000>;
26	};
27
28	aliases {
29		ethernet0 = &cp1_eth1;
30		ethernet1 = &cp0_eth0;
31		ethernet2 = &cp1_eth2;
32	};
33
34	v_3_3: regulator-3-3v {
35		compatible = "regulator-fixed";
36		regulator-name = "v_3_3";
37		regulator-min-microvolt = <3300000>;
38		regulator-max-microvolt = <3300000>;
39		regulator-always-on;
40		status = "okay";
41	};
42
43	v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
44		compatible = "regulator-fixed";
45		gpio = <&cp0_gpio2 15 GPIO_ACTIVE_LOW>;
46		pinctrl-names = "default";
47		pinctrl-0 = <&cp0_xhci_vbus_pins>;
48		regulator-name = "v_5v0_usb3_hst_vbus";
49		regulator-min-microvolt = <5000000>;
50		regulator-max-microvolt = <5000000>;
51		status = "okay";
52	};
53
54	usb3h0_phy: usb3_phy0 {
55		compatible = "usb-nop-xceiv";
56		vcc-supply = <&v_5v0_usb3_hst_vbus>;
57	};
58
59	sfp_cp0_eth0: sfp-cp0-eth0 {
60		compatible = "sff,sfp";
61		i2c-bus = <&cp0_i2c1>;
62		mod-def0-gpio = <&cp0_gpio2 17 GPIO_ACTIVE_LOW>;
63		tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
64		pinctrl-names = "default";
65		pinctrl-0 = <&cp0_sfp_present_pins &cp1_sfp_tx_disable_pins>;
66		maximum-power-milliwatt = <2000>;
67	};
68
69	leds {
70		compatible = "gpio-leds";
71		pinctrl-0 = <&cp0_led0_pins
72			     &cp0_led1_pins>;
73		pinctrl-names = "default";
74		/* No designated function for these LEDs at the moment */
75		led0 {
76			label = "clearfog-gt-8k:green:led0";
77			gpios = <&cp0_gpio2 8 GPIO_ACTIVE_LOW>;
78			default-state = "on";
79		};
80		led1 {
81			label = "clearfog-gt-8k:green:led1";
82			gpios = <&cp0_gpio2 9 GPIO_ACTIVE_LOW>;
83			default-state = "on";
84		};
85	};
86
87	keys {
88		compatible = "gpio-keys";
89		pinctrl-0 = <&cp0_gpio_reset_pins &cp1_wps_button_pins>;
90		pinctrl-names = "default";
91
92		button_0 {
93			/* The rear button */
94			label = "Rear Button";
95			gpios = <&cp0_gpio2 7 GPIO_ACTIVE_LOW>;
96			linux,can-disable;
97			linux,code = <BTN_0>;
98		};
99
100		button_1 {
101			/* The wps button */
102			label = "WPS Button";
103			gpios = <&cp1_gpio1 30 GPIO_ACTIVE_LOW>;
104			linux,can-disable;
105			linux,code = <KEY_WPS_BUTTON>;
106		};
107	};
108};
109
110&uart0 {
111	status = "okay";
112	pinctrl-0 = <&uart0_pins>;
113	pinctrl-names = "default";
114};
115
116&ap_sdhci0 {
117	bus-width = <8>;
118	no-1-8-v;
119	no-sd;
120	no-sdio;
121	non-removable;
122	status = "okay";
123	vqmmc-supply = <&v_3_3>;
124};
125
126&cp0_i2c0 {
127	clock-frequency = <100000>;
128	pinctrl-names = "default";
129	pinctrl-0 = <&cp0_i2c0_pins>;
130	status = "okay";
131};
132
133&cp0_i2c1 {
134	clock-frequency = <100000>;
135	pinctrl-names = "default";
136	pinctrl-0 = <&cp0_i2c1_pins>;
137	status = "okay";
138};
139
140&cp0_pinctrl {
141	/*
142	 * MPP Bus:
143	 * [0-31] = 0xff: Keep default CP0_shared_pins:
144	 * [11] CLKOUT_MPP_11 (out)
145	 * [23] LINK_RD_IN_CP2CP (in)
146	 * [25] CLKOUT_MPP_25 (out)
147	 * [29] AVS_FB_IN_CP2CP (in)
148	 * [32, 33, 34] pci0/1/2 reset
149	 * [35-38] CP0 I2C1 and I2C0
150	 * [39] GPIO reset button
151	 * [40,41] LED0 and LED1
152	 * [43] 1512 phy reset
153	 * [47] USB VBUS EN (active low)
154	 * [48] FAN PWM
155	 * [49] SFP+ present signal
156	 * [50] TPM interrupt
157	 * [51] WLAN0 disable
158	 * [52] WLAN1 disable
159	 * [53] LTE disable
160	 * [54] NFC reset
161	 * [55] Micro SD card detect
162	 * [56-61] Micro SD
163	 */
164
165	cp0_pci0_reset_pins: pci0-reset-pins {
166		marvell,pins = "mpp32";
167		marvell,function = "gpio";
168	};
169
170	cp0_pci1_reset_pins: pci1-reset-pins {
171		marvell,pins = "mpp33";
172		marvell,function = "gpio";
173	};
174
175	cp0_pci2_reset_pins: pci2-reset-pins {
176		marvell,pins = "mpp34";
177		marvell,function = "gpio";
178	};
179
180	cp0_i2c1_pins: i2c1-pins {
181		marvell,pins = "mpp35", "mpp36";
182		marvell,function = "i2c1";
183	};
184
185	cp0_i2c0_pins: i2c0-pins {
186		marvell,pins = "mpp37", "mpp38";
187		marvell,function = "i2c0";
188	};
189
190	cp0_gpio_reset_pins: gpio-reset-pins {
191		marvell,pins = "mpp39";
192		marvell,function = "gpio";
193	};
194
195	cp0_led0_pins: led0-pins {
196		marvell,pins = "mpp40";
197		marvell,function = "gpio";
198	};
199
200	cp0_led1_pins: led1-pins {
201		marvell,pins = "mpp41";
202		marvell,function = "gpio";
203	};
204
205	cp0_copper_eth_phy_reset: copper-eth-phy-reset {
206		marvell,pins = "mpp43";
207		marvell,function = "gpio";
208	};
209
210	cp0_xhci_vbus_pins: xhci0-vbus-pins {
211		marvell,pins = "mpp47";
212		marvell,function = "gpio";
213	};
214
215	cp0_fan_pwm_pins: fan-pwm-pins {
216		marvell,pins = "mpp48";
217		marvell,function = "gpio";
218	};
219
220	cp0_sfp_present_pins: sfp-present-pins {
221		marvell,pins = "mpp49";
222		marvell,function = "gpio";
223	};
224
225	cp0_tpm_irq_pins: tpm-irq-pins {
226		marvell,pins = "mpp50";
227		marvell,function = "gpio";
228	};
229
230	cp0_wlan_disable_pins: wlan-disable-pins {
231		marvell,pins = "mpp51";
232		marvell,function = "gpio";
233	};
234
235	cp0_sdhci_pins: sdhci-pins {
236		marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
237			       "mpp60", "mpp61";
238		marvell,function = "sdio";
239	};
240};
241
242&cp0_pcie0 {
243	pinctrl-names = "default";
244	pinctrl-0 = <&cp0_pci0_reset_pins &cp0_wlan_disable_pins>;
245	reset-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
246	status = "okay";
247};
248
249&cp0_gpio2 {
250	sata_reset {
251		gpio-hog;
252		gpios = <1 GPIO_ACTIVE_HIGH>;
253		output-high;
254	};
255
256	lte_reset {
257		gpio-hog;
258		gpios = <2 GPIO_ACTIVE_LOW>;
259		output-low;
260	};
261
262	wlan_disable {
263		gpio-hog;
264		gpios = <19 GPIO_ACTIVE_LOW>;
265		output-low;
266	};
267
268	lte_disable {
269		gpio-hog;
270		gpios = <21 GPIO_ACTIVE_LOW>;
271		output-low;
272	};
273};
274
275&cp0_ethernet {
276	status = "okay";
277};
278
279/* SFP */
280&cp0_eth0 {
281	status = "okay";
282	phy-mode = "10gbase-kr";
283	managed = "in-band-status";
284	phys = <&cp0_comphy2 0>;
285	sfp = <&sfp_cp0_eth0>;
286};
287
288&cp0_sdhci0 {
289	broken-cd;
290	bus-width = <4>;
291	pinctrl-names = "default";
292	pinctrl-0 = <&cp0_sdhci_pins>;
293	status = "okay";
294	vqmmc-supply = <&v_3_3>;
295};
296
297&cp0_usb3_1 {
298	status = "okay";
299};
300
301&cp1_pinctrl {
302	/*
303	 * MPP Bus:
304	 * [0-5] TDM
305	 * [6]   VHV Enable
306	 * [7]   CP1 SPI0 CSn1 (FXS)
307	 * [8]   CP1 SPI0 CSn0 (TPM)
308	 * [9.11]CP1 SPI0 MOSI/MISO/CLK
309	 * [13]  CP1 SPI1 MISO (TDM and SPI ROM shared)
310	 * [14]  CP1 SPI1 CS0n (64Mb SPI ROM)
311	 * [15]  CP1 SPI1 MOSI (TDM and SPI ROM shared)
312	 * [16]  CP1 SPI1 CLK (TDM and SPI ROM shared)
313	 * [24]  Topaz switch reset
314	 * [26]  Buzzer
315	 * [27]  CP1 SMI MDIO
316	 * [28]  CP1 SMI MDC
317	 * [29]  CP0 10G SFP TX Disable
318	 * [30]  WPS button
319	 * [31]  Front panel button
320	 */
321
322	cp1_spi1_pins: spi1-pins {
323		marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
324		marvell,function = "spi1";
325	};
326
327	cp1_switch_reset_pins: switch-reset-pins {
328		marvell,pins = "mpp24";
329		marvell,function = "gpio";
330	};
331
332	cp1_ge_mdio_pins: ge-mdio-pins {
333		marvell,pins = "mpp27", "mpp28";
334		marvell,function = "ge";
335	};
336
337	cp1_sfp_tx_disable_pins: sfp-tx-disable-pins {
338		marvell,pins = "mpp29";
339		marvell,function = "gpio";
340	};
341
342	cp1_wps_button_pins: wps-button-pins {
343		marvell,pins = "mpp30";
344		marvell,function = "gpio";
345	};
346};
347
348&cp1_sata0 {
349	pinctrl-0 = <&cp0_pci1_reset_pins>;
350	status = "okay";
351
352	sata-port@1 {
353		phys = <&cp1_comphy0 1>;
354		phy-names = "cp1-sata0-1-phy";
355	};
356};
357
358&cp1_mdio {
359	pinctrl-names = "default";
360	pinctrl-0 = <&cp1_ge_mdio_pins>;
361	status = "okay";
362
363	ge_phy: ethernet-phy@0 {
364		/* LED0 - GB link
365		 * LED1 - on: link, blink: activity
366		 */
367		marvell,reg-init = <3 16 0 0x1017>;
368		reg = <0>;
369		pinctrl-names = "default";
370		pinctrl-0 = <&cp0_copper_eth_phy_reset>;
371		reset-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
372		reset-assert-us = <10000>;
373	};
374
375	switch0: switch0@4 {
376		compatible = "marvell,mv88e6085";
377		reg = <4>;
378		pinctrl-names = "default";
379		pinctrl-0 = <&cp1_switch_reset_pins>;
380		reset-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_LOW>;
381
382		ports {
383			#address-cells = <1>;
384			#size-cells = <0>;
385
386			port@1 {
387				reg = <1>;
388				label = "lan2";
389				phy-handle = <&switch0phy0>;
390			};
391
392			port@2 {
393				reg = <2>;
394				label = "lan1";
395				phy-handle = <&switch0phy1>;
396			};
397
398			port@3 {
399				reg = <3>;
400				label = "lan4";
401				phy-handle = <&switch0phy2>;
402			};
403
404			port@4 {
405				reg = <4>;
406				label = "lan3";
407				phy-handle = <&switch0phy3>;
408			};
409
410			port@5 {
411				reg = <5>;
412				label = "cpu";
413				ethernet = <&cp1_eth2>;
414			};
415		};
416
417		mdio {
418			#address-cells = <1>;
419			#size-cells = <0>;
420
421			switch0phy0: switch0phy0@11 {
422				reg = <0x11>;
423			};
424
425			switch0phy1: switch0phy1@12 {
426				reg = <0x12>;
427			};
428
429			switch0phy2: switch0phy2@13 {
430				reg = <0x13>;
431			};
432
433			switch0phy3: switch0phy3@14 {
434				reg = <0x14>;
435			};
436		};
437	};
438};
439
440&cp1_ethernet {
441	status = "okay";
442};
443
444/* 1G copper */
445&cp1_eth1 {
446	status = "okay";
447	phy-mode = "sgmii";
448	phy = <&ge_phy>;
449	phys = <&cp1_comphy3 1>;
450};
451
452/* Switch uplink */
453&cp1_eth2 {
454	status = "okay";
455	phy-mode = "2500base-x";
456	phys = <&cp1_comphy5 2>;
457	fixed-link {
458		speed = <2500>;
459		full-duplex;
460	};
461};
462
463&cp1_spi1 {
464	pinctrl-names = "default";
465	pinctrl-0 = <&cp1_spi1_pins>;
466	status = "okay";
467
468	spi-flash@0 {
469		compatible = "st,w25q32";
470		spi-max-frequency = <50000000>;
471		reg = <0>;
472	};
473};
474
475&cp1_usb3_0 {
476	usb-phy = <&usb3h0_phy>;
477	status = "okay";
478};
479