1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 SolidRun ltd.
4 * Based on Marvell MACCHIATOBin board
5 *
6 * Device Tree file for SolidRun's ClearFog GT 8K
7 */
8
9#include "armada-8040.dtsi"
10
11#include <dt-bindings/input/input.h>
12#include <dt-bindings/gpio/gpio.h>
13
14/ {
15	model = "SolidRun ClearFog GT 8K";
16	compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040",
17			"marvell,armada-ap806-quad", "marvell,armada-ap806";
18
19	chosen {
20		stdout-path = "serial0:115200n8";
21	};
22
23	memory@00000000 {
24		device_type = "memory";
25		reg = <0x0 0x0 0x0 0x80000000>;
26	};
27
28	aliases {
29		ethernet0 = &cp1_eth1;
30		ethernet1 = &cp0_eth0;
31		ethernet2 = &cp1_eth2;
32	};
33
34	v_3_3: regulator-3-3v {
35		compatible = "regulator-fixed";
36		regulator-name = "v_3_3";
37		regulator-min-microvolt = <3300000>;
38		regulator-max-microvolt = <3300000>;
39		regulator-always-on;
40		status = "okay";
41	};
42
43	v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
44		compatible = "regulator-fixed";
45		gpio = <&cp0_gpio2 15 GPIO_ACTIVE_LOW>;
46		pinctrl-names = "default";
47		pinctrl-0 = <&cp0_xhci_vbus_pins>;
48		regulator-name = "v_5v0_usb3_hst_vbus";
49		regulator-min-microvolt = <5000000>;
50		regulator-max-microvolt = <5000000>;
51		status = "okay";
52	};
53
54	usb3h0_phy: usb3_phy0 {
55		compatible = "usb-nop-xceiv";
56		vcc-supply = <&v_5v0_usb3_hst_vbus>;
57	};
58
59	sfp_cp0_eth0: sfp-cp0-eth0 {
60		compatible = "sff,sfp";
61		i2c-bus = <&cp0_i2c1>;
62		mod-def0-gpio = <&cp0_gpio2 17 GPIO_ACTIVE_LOW>;
63		tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
64		pinctrl-names = "default";
65		pinctrl-0 = <&cp0_sfp_present_pins &cp1_sfp_tx_disable_pins>;
66	};
67
68	leds {
69		compatible = "gpio-leds";
70		pinctrl-0 = <&cp0_led0_pins
71			     &cp0_led1_pins>;
72		pinctrl-names = "default";
73		/* No designated function for these LEDs at the moment */
74		led0 {
75			label = "clearfog-gt-8k:green:led0";
76			gpios = <&cp0_gpio2 8 GPIO_ACTIVE_LOW>;
77			default-state = "on";
78		};
79		led1 {
80			label = "clearfog-gt-8k:green:led1";
81			gpios = <&cp0_gpio2 9 GPIO_ACTIVE_LOW>;
82			default-state = "on";
83		};
84	};
85
86	keys {
87		compatible = "gpio-keys";
88		pinctrl-0 = <&cp0_gpio_reset_pins &cp1_wps_button_pins>;
89		pinctrl-names = "default";
90
91		button_0 {
92			/* The rear button */
93			label = "Rear Button";
94			gpios = <&cp0_gpio2 7 GPIO_ACTIVE_LOW>;
95			linux,can-disable;
96			linux,code = <BTN_0>;
97		};
98
99		button_1 {
100			/* The wps button */
101			label = "WPS Button";
102			gpios = <&cp1_gpio1 30 GPIO_ACTIVE_LOW>;
103			linux,can-disable;
104			linux,code = <KEY_WPS_BUTTON>;
105		};
106	};
107};
108
109&uart0 {
110	status = "okay";
111	pinctrl-0 = <&uart0_pins>;
112	pinctrl-names = "default";
113};
114
115&ap_sdhci0 {
116	bus-width = <8>;
117	no-1-8-v;
118	no-sd;
119	no-sdio;
120	non-removable;
121	status = "okay";
122	vqmmc-supply = <&v_3_3>;
123};
124
125&cp0_i2c0 {
126	clock-frequency = <100000>;
127	pinctrl-names = "default";
128	pinctrl-0 = <&cp0_i2c0_pins>;
129	status = "okay";
130};
131
132&cp0_i2c1 {
133	clock-frequency = <100000>;
134	pinctrl-names = "default";
135	pinctrl-0 = <&cp0_i2c1_pins>;
136	status = "okay";
137};
138
139&cp0_pinctrl {
140	/*
141	 * MPP Bus:
142	 * [0-31] = 0xff: Keep default CP0_shared_pins:
143	 * [11] CLKOUT_MPP_11 (out)
144	 * [23] LINK_RD_IN_CP2CP (in)
145	 * [25] CLKOUT_MPP_25 (out)
146	 * [29] AVS_FB_IN_CP2CP (in)
147	 * [32, 33, 34] pci0/1/2 reset
148	 * [35-38] CP0 I2C1 and I2C0
149	 * [39] GPIO reset button
150	 * [40,41] LED0 and LED1
151	 * [43] 1512 phy reset
152	 * [47] USB VBUS EN (active low)
153	 * [48] FAN PWM
154	 * [49] SFP+ present signal
155	 * [50] TPM interrupt
156	 * [51] WLAN0 disable
157	 * [52] WLAN1 disable
158	 * [53] LTE disable
159	 * [54] NFC reset
160	 * [55] Micro SD card detect
161	 * [56-61] Micro SD
162	 */
163
164	cp0_pci0_reset_pins: pci0-reset-pins {
165		marvell,pins = "mpp32";
166		marvell,function = "gpio";
167	};
168
169	cp0_pci1_reset_pins: pci1-reset-pins {
170		marvell,pins = "mpp33";
171		marvell,function = "gpio";
172	};
173
174	cp0_pci2_reset_pins: pci2-reset-pins {
175		marvell,pins = "mpp34";
176		marvell,function = "gpio";
177	};
178
179	cp0_i2c1_pins: i2c1-pins {
180		marvell,pins = "mpp35", "mpp36";
181		marvell,function = "i2c1";
182	};
183
184	cp0_i2c0_pins: i2c0-pins {
185		marvell,pins = "mpp37", "mpp38";
186		marvell,function = "i2c0";
187	};
188
189	cp0_gpio_reset_pins: gpio-reset-pins {
190		marvell,pins = "mpp39";
191		marvell,function = "gpio";
192	};
193
194	cp0_led0_pins: led0-pins {
195		marvell,pins = "mpp40";
196		marvell,function = "gpio";
197	};
198
199	cp0_led1_pins: led1-pins {
200		marvell,pins = "mpp41";
201		marvell,function = "gpio";
202	};
203
204	cp0_copper_eth_phy_reset: copper-eth-phy-reset {
205		marvell,pins = "mpp43";
206		marvell,function = "gpio";
207	};
208
209	cp0_xhci_vbus_pins: xhci0-vbus-pins {
210		marvell,pins = "mpp47";
211		marvell,function = "gpio";
212	};
213
214	cp0_fan_pwm_pins: fan-pwm-pins {
215		marvell,pins = "mpp48";
216		marvell,function = "gpio";
217	};
218
219	cp0_sfp_present_pins: sfp-present-pins {
220		marvell,pins = "mpp49";
221		marvell,function = "gpio";
222	};
223
224	cp0_tpm_irq_pins: tpm-irq-pins {
225		marvell,pins = "mpp50";
226		marvell,function = "gpio";
227	};
228
229	cp0_wlan_disable_pins: wlan-disable-pins {
230		marvell,pins = "mpp51";
231		marvell,function = "gpio";
232	};
233
234	cp0_sdhci_pins: sdhci-pins {
235		marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
236			       "mpp60", "mpp61";
237		marvell,function = "sdio";
238	};
239};
240
241&cp0_pcie0 {
242	pinctrl-names = "default";
243	pinctrl-0 = <&cp0_pci0_reset_pins &cp0_wlan_disable_pins>;
244	reset-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
245	status = "okay";
246};
247
248&cp0_gpio2 {
249	sata_reset {
250		gpio-hog;
251		gpios = <1 GPIO_ACTIVE_HIGH>;
252		output-high;
253	};
254
255	lte_reset {
256		gpio-hog;
257		gpios = <2 GPIO_ACTIVE_LOW>;
258		output-low;
259	};
260
261	wlan_disable {
262		gpio-hog;
263		gpios = <19 GPIO_ACTIVE_LOW>;
264		output-low;
265	};
266
267	lte_disable {
268		gpio-hog;
269		gpios = <21 GPIO_ACTIVE_LOW>;
270		output-low;
271	};
272};
273
274&cp0_ethernet {
275	status = "okay";
276};
277
278/* SFP */
279&cp0_eth0 {
280	status = "okay";
281	phy-mode = "10gbase-kr";
282	managed = "in-band-status";
283	phys = <&cp0_comphy2 0>;
284	sfp = <&sfp_cp0_eth0>;
285};
286
287&cp0_sdhci0 {
288	broken-cd;
289	bus-width = <4>;
290	pinctrl-names = "default";
291	pinctrl-0 = <&cp0_sdhci_pins>;
292	status = "okay";
293	vqmmc-supply = <&v_3_3>;
294};
295
296&cp0_usb3_1 {
297	status = "okay";
298};
299
300&cp1_pinctrl {
301	/*
302	 * MPP Bus:
303	 * [0-5] TDM
304	 * [6]   VHV Enable
305	 * [7]   CP1 SPI0 CSn1 (FXS)
306	 * [8]   CP1 SPI0 CSn0 (TPM)
307	 * [9.11]CP1 SPI0 MOSI/MISO/CLK
308	 * [13]  CP1 SPI1 MISO (TDM and SPI ROM shared)
309	 * [14]  CP1 SPI1 CS0n (64Mb SPI ROM)
310	 * [15]  CP1 SPI1 MOSI (TDM and SPI ROM shared)
311	 * [16]  CP1 SPI1 CLK (TDM and SPI ROM shared)
312	 * [24]  Topaz switch reset
313	 * [26]  Buzzer
314	 * [27]  CP1 SMI MDIO
315	 * [28]  CP1 SMI MDC
316	 * [29]  CP0 10G SFP TX Disable
317	 * [30]  WPS button
318	 * [31]  Front panel button
319	 */
320
321	cp1_spi1_pins: spi1-pins {
322		marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
323		marvell,function = "spi1";
324	};
325
326	cp1_switch_reset_pins: switch-reset-pins {
327		marvell,pins = "mpp24";
328		marvell,function = "gpio";
329	};
330
331	cp1_ge_mdio_pins: ge-mdio-pins {
332		marvell,pins = "mpp27", "mpp28";
333		marvell,function = "ge";
334	};
335
336	cp1_sfp_tx_disable_pins: sfp-tx-disable-pins {
337		marvell,pins = "mpp29";
338		marvell,function = "gpio";
339	};
340
341	cp1_wps_button_pins: wps-button-pins {
342		marvell,pins = "mpp30";
343		marvell,function = "gpio";
344	};
345};
346
347&cp1_sata0 {
348	pinctrl-0 = <&cp0_pci1_reset_pins>;
349	status = "okay";
350};
351
352&cp1_mdio {
353	pinctrl-names = "default";
354	pinctrl-0 = <&cp1_ge_mdio_pins>;
355	status = "okay";
356
357	ge_phy: ethernet-phy@0 {
358		/* LED0 - GB link
359		 * LED1 - on: link, blink: activity
360		 */
361		marvell,reg-init = <3 16 0 0x1017>;
362		reg = <0>;
363		pinctrl-names = "default";
364		pinctrl-0 = <&cp0_copper_eth_phy_reset>;
365		reset-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
366		reset-assert-us = <10000>;
367	};
368
369	switch0: switch0@4 {
370		compatible = "marvell,mv88e6085";
371		reg = <4>;
372		pinctrl-names = "default";
373		pinctrl-0 = <&cp1_switch_reset_pins>;
374		reset-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_LOW>;
375
376		ports {
377			#address-cells = <1>;
378			#size-cells = <0>;
379
380			port@1 {
381				reg = <1>;
382				label = "lan2";
383				phy-handle = <&switch0phy0>;
384			};
385
386			port@2 {
387				reg = <2>;
388				label = "lan1";
389				phy-handle = <&switch0phy1>;
390			};
391
392			port@3 {
393				reg = <3>;
394				label = "lan4";
395				phy-handle = <&switch0phy2>;
396			};
397
398			port@4 {
399				reg = <4>;
400				label = "lan3";
401				phy-handle = <&switch0phy3>;
402			};
403
404			port@5 {
405				reg = <5>;
406				label = "cpu";
407				ethernet = <&cp1_eth2>;
408			};
409		};
410
411		mdio {
412			#address-cells = <1>;
413			#size-cells = <0>;
414
415			switch0phy0: switch0phy0@11 {
416				reg = <0x11>;
417			};
418
419			switch0phy1: switch0phy1@12 {
420				reg = <0x12>;
421			};
422
423			switch0phy2: switch0phy2@13 {
424				reg = <0x13>;
425			};
426
427			switch0phy3: switch0phy3@14 {
428				reg = <0x14>;
429			};
430		};
431	};
432};
433
434&cp1_ethernet {
435	status = "okay";
436};
437
438/* 1G copper */
439&cp1_eth1 {
440	status = "okay";
441	phy-mode = "sgmii";
442	phy = <&ge_phy>;
443	phys = <&cp1_comphy3 1>;
444};
445
446/* Switch uplink */
447&cp1_eth2 {
448	status = "okay";
449	phy-mode = "2500base-x";
450	phys = <&cp1_comphy5 2>;
451	fixed-link {
452		speed = <2500>;
453		full-duplex;
454	};
455};
456
457&cp1_spi1 {
458	pinctrl-names = "default";
459	pinctrl-0 = <&cp1_spi1_pins>;
460	status = "okay";
461
462	spi-flash@0 {
463		compatible = "st,w25q32";
464		spi-max-frequency = <50000000>;
465		reg = <0>;
466	};
467};
468
469&cp1_usb3_0 {
470	usb-phy = <&usb3h0_phy>;
471	status = "okay";
472};
473