1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2018 SolidRun ltd. 4 * Based on Marvell MACCHIATOBin board 5 * 6 * Device Tree file for SolidRun's ClearFog GT 8K 7 */ 8 9#include "armada-8040.dtsi" 10 11#include <dt-bindings/input/input.h> 12#include <dt-bindings/gpio/gpio.h> 13 14/ { 15 model = "SolidRun ClearFog GT 8K"; 16 compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040", 17 "marvell,armada-ap806-quad", "marvell,armada-ap806"; 18 19 chosen { 20 stdout-path = "serial0:115200n8"; 21 }; 22 23 memory@00000000 { 24 device_type = "memory"; 25 reg = <0x0 0x0 0x0 0x80000000>; 26 }; 27 28 aliases { 29 ethernet0 = &cp1_eth1; 30 ethernet1 = &cp0_eth0; 31 ethernet2 = &cp1_eth2; 32 }; 33 34 v_3_3: regulator-3-3v { 35 compatible = "regulator-fixed"; 36 regulator-name = "v_3_3"; 37 regulator-min-microvolt = <3300000>; 38 regulator-max-microvolt = <3300000>; 39 regulator-always-on; 40 status = "okay"; 41 }; 42 43 v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { 44 compatible = "regulator-fixed"; 45 gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>; 46 pinctrl-names = "default"; 47 pinctrl-0 = <&cp0_xhci_vbus_pins>; 48 regulator-name = "v_5v0_usb3_hst_vbus"; 49 regulator-min-microvolt = <5000000>; 50 regulator-max-microvolt = <5000000>; 51 status = "okay"; 52 }; 53 54 usb3h0_phy: usb3_phy0 { 55 compatible = "usb-nop-xceiv"; 56 vcc-supply = <&v_5v0_usb3_hst_vbus>; 57 }; 58 59 sfp_cp0_eth0: sfp-cp0-eth0 { 60 compatible = "sff,sfp"; 61 i2c-bus = <&cp0_i2c1>; 62 mod-def0-gpio = <&cp0_gpio2 17 GPIO_ACTIVE_LOW>; 63 tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; 64 pinctrl-names = "default"; 65 pinctrl-0 = <&cp0_sfp_present_pins &cp1_sfp_tx_disable_pins>; 66 }; 67 68 leds { 69 compatible = "gpio-leds"; 70 pinctrl-0 = <&cp0_led0_pins 71 &cp0_led1_pins>; 72 pinctrl-names = "default"; 73 /* No designated function for these LEDs at the moment */ 74 led0 { 75 label = "clearfog-gt-8k:green:led0"; 76 gpios = <&cp0_gpio2 8 GPIO_ACTIVE_LOW>; 77 default-state = "on"; 78 }; 79 led1 { 80 label = "clearfog-gt-8k:green:led1"; 81 gpios = <&cp0_gpio2 9 GPIO_ACTIVE_LOW>; 82 default-state = "on"; 83 }; 84 }; 85 86 keys { 87 compatible = "gpio-keys"; 88 pinctrl-0 = <&cp0_gpio_reset_pins &cp1_wps_button_pins>; 89 pinctrl-names = "default"; 90 91 button_0 { 92 /* The rear button */ 93 label = "Rear Button"; 94 gpios = <&cp0_gpio2 7 GPIO_ACTIVE_LOW>; 95 linux,can-disable; 96 linux,code = <BTN_0>; 97 }; 98 99 button_1 { 100 /* The wps button */ 101 label = "WPS Button"; 102 gpios = <&cp1_gpio1 30 GPIO_ACTIVE_LOW>; 103 linux,can-disable; 104 linux,code = <KEY_WPS_BUTTON>; 105 }; 106 }; 107}; 108 109&uart0 { 110 status = "okay"; 111 pinctrl-0 = <&uart0_pins>; 112 pinctrl-names = "default"; 113}; 114 115&ap_sdhci0 { 116 bus-width = <8>; 117 no-1-8-v; 118 no-sd; 119 no-sdio; 120 non-removable; 121 status = "okay"; 122 vqmmc-supply = <&v_3_3>; 123}; 124 125&cp0_i2c0 { 126 clock-frequency = <100000>; 127 pinctrl-names = "default"; 128 pinctrl-0 = <&cp0_i2c0_pins>; 129 status = "okay"; 130}; 131 132&cp0_i2c1 { 133 clock-frequency = <100000>; 134 pinctrl-names = "default"; 135 pinctrl-0 = <&cp0_i2c1_pins>; 136 status = "okay"; 137}; 138 139&cp0_pinctrl { 140 /* 141 * MPP Bus: 142 * [0-31] = 0xff: Keep default CP0_shared_pins: 143 * [11] CLKOUT_MPP_11 (out) 144 * [23] LINK_RD_IN_CP2CP (in) 145 * [25] CLKOUT_MPP_25 (out) 146 * [29] AVS_FB_IN_CP2CP (in) 147 * [32, 33, 34] pci0/1/2 reset 148 * [35-38] CP0 I2C1 and I2C0 149 * [39] GPIO reset button 150 * [40,41] LED0 and LED1 151 * [43] 1512 phy reset 152 * [47] USB VBUS EN (active low) 153 * [48] FAN PWM 154 * [49] SFP+ present signal 155 * [50] TPM interrupt 156 * [51] WLAN0 disable 157 * [52] WLAN1 disable 158 * [53] LTE disable 159 * [54] NFC reset 160 * [55] Micro SD card detect 161 * [56-61] Micro SD 162 */ 163 164 cp0_pci0_reset_pins: pci0-reset-pins { 165 marvell,pins = "mpp32"; 166 marvell,function = "gpio"; 167 }; 168 169 cp0_pci1_reset_pins: pci1-reset-pins { 170 marvell,pins = "mpp33"; 171 marvell,function = "gpio"; 172 }; 173 174 cp0_pci2_reset_pins: pci2-reset-pins { 175 marvell,pins = "mpp34"; 176 marvell,function = "gpio"; 177 }; 178 179 cp0_i2c1_pins: i2c1-pins { 180 marvell,pins = "mpp35", "mpp36"; 181 marvell,function = "i2c1"; 182 }; 183 184 cp0_i2c0_pins: i2c0-pins { 185 marvell,pins = "mpp37", "mpp38"; 186 marvell,function = "i2c0"; 187 }; 188 189 cp0_gpio_reset_pins: gpio-reset-pins { 190 marvell,pins = "mpp39"; 191 marvell,function = "gpio"; 192 }; 193 194 cp0_led0_pins: led0-pins { 195 marvell,pins = "mpp40"; 196 marvell,function = "gpio"; 197 }; 198 199 cp0_led1_pins: led1-pins { 200 marvell,pins = "mpp41"; 201 marvell,function = "gpio"; 202 }; 203 204 cp0_copper_eth_phy_reset: copper-eth-phy-reset { 205 marvell,pins = "mpp43"; 206 marvell,function = "gpio"; 207 }; 208 209 cp0_xhci_vbus_pins: xhci0-vbus-pins { 210 marvell,pins = "mpp47"; 211 marvell,function = "gpio"; 212 }; 213 214 cp0_fan_pwm_pins: fan-pwm-pins { 215 marvell,pins = "mpp48"; 216 marvell,function = "gpio"; 217 }; 218 219 cp0_sfp_present_pins: sfp-present-pins { 220 marvell,pins = "mpp49"; 221 marvell,function = "gpio"; 222 }; 223 224 cp0_tpm_irq_pins: tpm-irq-pins { 225 marvell,pins = "mpp50"; 226 marvell,function = "gpio"; 227 }; 228 229 cp0_sdhci_pins: sdhci-pins { 230 marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59", 231 "mpp60", "mpp61"; 232 marvell,function = "sdio"; 233 }; 234}; 235 236&cp0_pcie0 { 237 pinctrl-names = "default"; 238 pinctrl-0 = <&cp0_pci0_reset_pins>; 239 reset-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>; 240 status = "okay"; 241}; 242 243&cp0_gpio2 { 244 sata_reset { 245 gpio-hog; 246 gpios = <1 GPIO_ACTIVE_HIGH>; 247 output-high; 248 }; 249}; 250 251&cp0_ethernet { 252 status = "okay"; 253}; 254 255/* SFP */ 256&cp0_eth0 { 257 status = "okay"; 258 phy-mode = "10gbase-kr"; 259 managed = "in-band-status"; 260 phys = <&cp0_comphy2 0>; 261 sfp = <&sfp_cp0_eth0>; 262}; 263 264&cp0_sdhci0 { 265 broken-cd; 266 bus-width = <4>; 267 pinctrl-names = "default"; 268 pinctrl-0 = <&cp0_sdhci_pins>; 269 status = "okay"; 270 vqmmc-supply = <&v_3_3>; 271}; 272 273&cp1_pinctrl { 274 /* 275 * MPP Bus: 276 * [0-5] TDM 277 * [6] VHV Enable 278 * [7] CP1 SPI0 CSn1 (FXS) 279 * [8] CP1 SPI0 CSn0 (TPM) 280 * [9.11]CP1 SPI0 MOSI/MISO/CLK 281 * [13] CP1 SPI1 MISO (TDM and SPI ROM shared) 282 * [14] CP1 SPI1 CS0n (64Mb SPI ROM) 283 * [15] CP1 SPI1 MOSI (TDM and SPI ROM shared) 284 * [16] CP1 SPI1 CLK (TDM and SPI ROM shared) 285 * [24] Topaz switch reset 286 * [26] Buzzer 287 * [27] CP1 SMI MDIO 288 * [28] CP1 SMI MDC 289 * [29] CP0 10G SFP TX Disable 290 * [30] WPS button 291 * [31] Front panel button 292 */ 293 294 cp1_spi1_pins: spi1-pins { 295 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; 296 marvell,function = "spi1"; 297 }; 298 299 cp1_switch_reset_pins: switch-reset-pins { 300 marvell,pins = "mpp24"; 301 marvell,function = "gpio"; 302 }; 303 304 cp1_ge_mdio_pins: ge-mdio-pins { 305 marvell,pins = "mpp27", "mpp28"; 306 marvell,function = "ge"; 307 }; 308 309 cp1_sfp_tx_disable_pins: sfp-tx-disable-pins { 310 marvell,pins = "mpp29"; 311 marvell,function = "gpio"; 312 }; 313 314 cp1_wps_button_pins: wps-button-pins { 315 marvell,pins = "mpp30"; 316 marvell,function = "gpio"; 317 }; 318}; 319 320&cp1_sata0 { 321 pinctrl-0 = <&cp0_pci1_reset_pins>; 322 status = "okay"; 323}; 324 325&cp1_mdio { 326 pinctrl-names = "default"; 327 pinctrl-0 = <&cp1_ge_mdio_pins>; 328 status = "okay"; 329 330 ge_phy: ethernet-phy@0 { 331 /* LED0 - GB link 332 * LED1 - on: link, blink: activity 333 */ 334 marvell,reg-init = <3 16 0 0x1017>; 335 reg = <0>; 336 }; 337 338 switch0: switch0@4 { 339 compatible = "marvell,mv88e6085"; 340 reg = <4>; 341 pinctrl-names = "default"; 342 pinctrl-0 = <&cp1_switch_reset_pins>; 343 reset-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_LOW>; 344 345 ports { 346 #address-cells = <1>; 347 #size-cells = <0>; 348 349 port@1 { 350 reg = <1>; 351 label = "lan2"; 352 phy-handle = <&switch0phy0>; 353 }; 354 355 port@2 { 356 reg = <2>; 357 label = "lan1"; 358 phy-handle = <&switch0phy1>; 359 }; 360 361 port@3 { 362 reg = <3>; 363 label = "lan4"; 364 phy-handle = <&switch0phy2>; 365 }; 366 367 port@4 { 368 reg = <4>; 369 label = "lan3"; 370 phy-handle = <&switch0phy3>; 371 }; 372 373 port@5 { 374 reg = <5>; 375 label = "cpu"; 376 ethernet = <&cp1_eth2>; 377 }; 378 }; 379 380 mdio { 381 #address-cells = <1>; 382 #size-cells = <0>; 383 384 switch0phy0: switch0phy0@11 { 385 reg = <0x11>; 386 }; 387 388 switch0phy1: switch0phy1@12 { 389 reg = <0x12>; 390 }; 391 392 switch0phy2: switch0phy2@13 { 393 reg = <0x13>; 394 }; 395 396 switch0phy3: switch0phy3@14 { 397 reg = <0x14>; 398 }; 399 }; 400 }; 401}; 402 403&cp1_ethernet { 404 status = "okay"; 405}; 406 407/* 1G copper */ 408&cp1_eth1 { 409 status = "okay"; 410 phy-mode = "sgmii"; 411 phy = <&ge_phy>; 412 phys = <&cp1_comphy3 1>; 413}; 414 415/* Switch uplink */ 416&cp1_eth2 { 417 status = "okay"; 418 phy-mode = "2500base-x"; 419 phys = <&cp1_comphy5 2>; 420 fixed-link { 421 speed = <2500>; 422 full-duplex; 423 }; 424}; 425 426&cp1_spi1 { 427 pinctrl-names = "default"; 428 pinctrl-0 = <&cp1_spi1_pins>; 429 status = "okay"; 430 431 spi-flash@0 { 432 compatible = "st,w25q32"; 433 spi-max-frequency = <50000000>; 434 reg = <0>; 435 }; 436}; 437 438&cp1_usb3_0 { 439 usb-phy = <&usb3h0_phy>; 440 status = "okay"; 441}; 442